diff options
| author | Guillaume Knispel <gknispel@avencall.com> | 2012-10-25 19:27:14 +0200 |
|---|---|---|
| committer | Guillaume Knispel <gknispel@avencall.com> | 2012-10-25 19:27:14 +0200 |
| commit | 0583b6702c1b83a1bc8eb03082330090ffbaa10d (patch) | |
| tree | 30f105e44d5627da1b336f5f2a090962e6234037 /hardware.h | |
| parent | b9afdb6dadb8462d6f632c09cbe617c5c10634db (diff) | |
output 500Hz square signal on two pins for debugging purposessquare_test
Diffstat (limited to 'hardware.h')
| -rw-r--r-- | hardware.h | 8 |
1 files changed, 5 insertions, 3 deletions
@@ -99,7 +99,7 @@ PxIES_INIT //Interrupt Edge Select (0=pos 1=neg) #define P2OUT_INIT (CK410_PWR_GD_N | CPU_VCCP_EN_N | GREEN_LED_N \ | RED_LED_N | SYS_RESET_N) #define P2DIR_INIT (CPU_VCCP_EN_N | GREEN_LED_N | RED_LED_N \ - | IMCH_RSMRST_N) + | IMCH_RSMRST_N | GP24) #define P2REN_INIT (CK410_PWR_GD_N | SYS_RESET_N) #define P2SEL_INIT 0 #define P2IE_INIT 0 @@ -107,8 +107,10 @@ PxIES_INIT //Interrupt Edge Select (0=pos 1=neg) // PORT3 #define P3OUT_INIT 0 -#define P3DIR_INIT (SYS_PWR_OK | VRMPWRGD) -#define P3SEL_INIT (MSP_BSL_TXD | MSP_BSL_RXD) +// #define P3DIR_INIT (SYS_PWR_OK | VRMPWRGD) +// #define P3SEL_INIT (MSP_BSL_TXD | MSP_BSL_RXD) +#define P3DIR_INIT (SYS_PWR_OK | VRMPWRGD | MSP_BSL_TXD) +#define P3SEL_INIT 0 // PORT4 #define P4OUT_INIT (SLP_S3_N) |