From 0583b6702c1b83a1bc8eb03082330090ffbaa10d Mon Sep 17 00:00:00 2001 From: Guillaume Knispel Date: Thu, 25 Oct 2012 19:27:14 +0200 Subject: output 500Hz square signal on two pins for debugging purposes --- hardware.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'hardware.h') diff --git a/hardware.h b/hardware.h index fad5aca..9fc75d8 100644 --- a/hardware.h +++ b/hardware.h @@ -99,7 +99,7 @@ PxIES_INIT //Interrupt Edge Select (0=pos 1=neg) #define P2OUT_INIT (CK410_PWR_GD_N | CPU_VCCP_EN_N | GREEN_LED_N \ | RED_LED_N | SYS_RESET_N) #define P2DIR_INIT (CPU_VCCP_EN_N | GREEN_LED_N | RED_LED_N \ - | IMCH_RSMRST_N) + | IMCH_RSMRST_N | GP24) #define P2REN_INIT (CK410_PWR_GD_N | SYS_RESET_N) #define P2SEL_INIT 0 #define P2IE_INIT 0 @@ -107,8 +107,10 @@ PxIES_INIT //Interrupt Edge Select (0=pos 1=neg) // PORT3 #define P3OUT_INIT 0 -#define P3DIR_INIT (SYS_PWR_OK | VRMPWRGD) -#define P3SEL_INIT (MSP_BSL_TXD | MSP_BSL_RXD) +// #define P3DIR_INIT (SYS_PWR_OK | VRMPWRGD) +// #define P3SEL_INIT (MSP_BSL_TXD | MSP_BSL_RXD) +#define P3DIR_INIT (SYS_PWR_OK | VRMPWRGD | MSP_BSL_TXD) +#define P3SEL_INIT 0 // PORT4 #define P4OUT_INIT (SLP_S3_N) -- cgit v1.2.3