copy pasted a bunch of code (doesn't work)

1 files changed, 5 insertions, 89 deletions

diff --git a/xhfc/xhfc_leb.h b/xhfc/xhfc_leb.h
index e9ee292..c501229 100644
--- a/xhfc/xhfc_leb.h
+++ b/xhfc/xhfc_leb.h
@@ -26,99 +26,21 @@
 #define _XHFC_LEB_H_
 
 #include <linux/pci.h>
-#include "xhfc.h"
-
-#define DRV_NAME	"tolapai_leb_mode3m"
-
-#define LEB_CSRBAR      0
-#define LEB_MMBAR       1
-
-/* === Registers EXP_TIMING_CSn === */
-
-
-/* Enable CS */
-#define LEB_TCS_CS_EN	   (	1u  << 31)
-
-/* Enable parity */
-#define LEB_TCS_PAR_EN	  (	1u  << 30)
 
-#define LEB_TCS_T1_ADDR_TM(x)   (((x) &  3u) << 28)
-#define LEB_TCS_T2_SU_CS_TM(x)  (((x) &  3u) << 26)
-#define LEB_TCS_T3_STRB_TM(x)   (((x) & 15u) << 22)
-#define LEB_TCS_T4_HOLD_TM(x)   (((x) &  3u) << 20)
-#define LEB_TCS_T5_RCVRY_TM(x)  (((x) & 15u) << 16)
-
-#define LEB_TCS_CYC_TYPE(x)     (((x) &  3u) << 14)
-#define LEB_TCS_CYC_TYPE_INTEL  LEB_TCS_CYC_TYPE(0)
-
-#define LEB_TCS_CNFG_4_0(x)     (((x) & 31u) <<  9)
-#define LEB_TCS_CNFG_512_B      LEB_TCS_CNFG_4_0(0)
-#define LEB_TCS_CNFG_1_KiB      LEB_TCS_CNFG_4_0(2)
-#define LEB_TCS_CNFG_2_KiB      LEB_TCS_CNFG_4_0(4)
-#define LEB_TCS_CNFG_4_KiB      LEB_TCS_CNFG_4_0(6)
-#define LEB_TCS_CNFG_8_KiB      LEB_TCS_CNFG_4_0(8)
-#define LEB_TCS_CNFG_16_KiB     LEB_TCS_CNFG_4_0(10)
-#define LEB_TCS_CNFG_32_KiB     LEB_TCS_CNFG_4_0(12)
-#define LEB_TCS_CNFG_64_KiB     LEB_TCS_CNFG_4_0(14)
-#define LEB_TCS_CNFG_128_KiB    LEB_TCS_CNFG_4_0(16)
-#define LEB_TCS_CNFG_256_KiB    LEB_TCS_CNFG_4_0(18)
-#define LEB_TCS_CNFG_512_KiB    LEB_TCS_CNFG_4_0(20)
-#define LEB_TCS_CNFG_1_MiB      LEB_TCS_CNFG_4_0(22)
-#define LEB_TCS_CNFG_2_MiB      LEB_TCS_CNFG_4_0(24)
-#define LEB_TCS_CNFG_4_MiB      LEB_TCS_CNFG_4_0(26)
-#define LEB_TCS_CNFG_8_MiB      LEB_TCS_CNFG_4_0(28)
-#define LEB_TCS_CNFG_16_MiB     LEB_TCS_CNFG_4_0(30)
-/* Now the weird one (which also changes
- *  the memory map of MMBAR if used at least once): */
-#define LEB_TCS_CNFG_32_MiB     LEB_TCS_CNFG_4_0(1)
-
-/* Synchronous Intel StrataFlash: */
-#define LEB_TCS_SYNC_INTEL      (	1u  <<  8)
-
-/* Target device is an EP80579 (hm, WTF??? TODONE ask Intel <- the conf is correct ) */
-#define LEB_TCS_EXP_CHIP	(	1u  <<  7)
-
-/* Byte read access to half-word device */
-#define LEB_TCS_BYTE_RD16       (	1u  <<  6)
-
-/* For HPI (CS4 to CS7 only)
- * 0 => Polarity low true
- * 1 => Polarity high true
- *
- * Don't set if not HPI
- */
-#define LEB_TCS_HRDY_POL	(	1u  <<  5)
-
-/* Enable address/data multiplexing: */
-#define LEB_TCS_MUX_EN	  (	1u  <<  4)
-
-/* Split transaction on internal bus: */
-#define LEB_TCS_SPLT_EN	 (	1u  <<  3)
-
-/* bit 2 is rsvd, a 0 must be written at this position */
-
-/* Enable writes: */
-#define LEB_TCS_WR_EN	   (	1u  <<  1)
-
-/* 8-bit device:
- * 0 => 16-bit-wide data bus
- * 1 => 8-bit data bus */
-#define LEB_TCS_BYTE_EN	 (	1u  <<  0)
-
-#define IRQ_TLP_GPIO_30		31
+#include "xhfc.h"
 
 extern uint trigger;
 
-static inline __u8
-read_xhfc(struct xhfc * xhfc, __u8 reg_addr)
+void leb_init(struct xhfc_pi *leb);
+
+static inline u8 read_xhfc(struct xhfc * xhfc, u8 reg_addr)
 {
 	u8 __iomem *cs_n0 = xhfc->pi->cs_n0;
 
 	return readb(&cs_n0[(trigger << 8) + reg_addr]);
 }
 
-static inline void
-write_xhfc(struct xhfc * xhfc, __u8 reg_addr, __u8 value)
+static inline void write_xhfc(struct xhfc * xhfc, u8 reg_addr, u8 value)
 {
 	u8 __iomem *cs_n0 = xhfc->pi->cs_n0;
 
@@ -145,10 +67,4 @@ struct tlp_leb_regs {
 	u32     parity_status;
 };
 
-void leb_init(struct xhfc_pi *leb);
-
-int __devinit xhfc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
-void __devexit xhfc_remove_one(struct pci_dev *pdev);
-void xhfc_shutdown(struct pci_dev *pdev);
-
 #endif	/* _XHFC_LEB_H_ */