Convert to CAR and make i3100/{early_smbus.c,smbus.c} compile with host gcc

This patch aims to convert the Truxton dev board to CAR which required the
following changes:
- Remove unused variables (to satisfy no warnings flag)
- Change .c includes to use headers (raminit_ep80579, early_smbus, smbus)
- Remove early_mtrr_init because CAR takes care of this
- Remove cache_lbmem (raminit_ep80579.c) as CAR takes care of this
- Remove debug code (for now, coming soon)

One side effect is that the mtarvon and eagleheights (which are already CAR)
romstage now use the new headers.  These two boards have been build tested.
The truxton platform was boot tested and a full memtest was run.

Signed-off-by: Dustin Harrison <dustin.harrison@sutus.com>
---

3 files changed, 72 insertions, 18 deletions

diff --git a/src/northbridge/intel/i3100/Makefile.inc b/src/northbridge/intel/i3100/Makefile.inc
index c2de0fcb5..07a68294f 100644
--- a/src/northbridge/intel/i3100/Makefile.inc
+++ b/src/northbridge/intel/i3100/Makefile.inc
@@ -1,3 +1,5 @@
 driver-y += northbridge.c
 driver-y += pciexp_porta.c
 driver-y += pciexp_porta_ep80579.c
+
+romstage-$(CONFIG_CPU_INTEL_EP80579) += raminit_ep80579.c
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 8967594b5..d3ee447ff 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -18,14 +18,26 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
+#include <console/console.h>
+#include <delay.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <stdlib.h>
+#include <spd.h>
+#include <cpu/x86/msr.h>
+#include <device/pci_def.h>
+#include "southbridge/intel/i3100/early_smbus.h"
 #include "raminit_ep80579.h"
 #include "ep80579.h"
 
+int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
 #define BAR 0x90000000
 
-static void sdram_set_registers(const struct mem_controller *ctrl)
+void sdram_set_registers(const struct mem_controller *ctrl)
 {
 	static const u32 register_values[] = {
 		PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
@@ -36,7 +48,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 		PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0,
 	};
 	int i;
-	int max;
 
 	for (i = 0; i < ARRAY_SIZE(register_values); i += 3) {
 		device_t dev;
@@ -60,7 +71,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
 {
 	/* Calculate the log base 2 size of a DIMM in bits */
 	struct dimm_size sz;
-	int value, low, ddr2;
+	int value, low;
 	sz.side1 = 0;
 	sz.side2 = 0;
 
@@ -485,10 +496,9 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	return drc;
 }
 
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
 	u8 dimm_mask;
-	int i;
 
 	/* Test if we can read the SPD */
 	dimm_mask = spd_detect_dimms(ctrl);
@@ -502,9 +512,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 {
 	u8 c1,c2;
-        u32 dimm,i;
-        u32 data32;
-	u32 t4;
+	u32 data32;
+	int i;
 
 	/* Set up northbridge values */
 	/* ODT enable */
@@ -541,7 +550,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 }
 
 
-static void dump_dcal_regs(void)
+void dump_dcal_regs(void)
 {
 	int i;
 	for (i = 0x0; i < 0x2a0; i += 4) {
@@ -557,7 +566,7 @@ static void dump_dcal_regs(void)
 }
 
 
-static void sdram_enable(int controllers, const struct mem_controller *ctrl)
+void sdram_enable(int controllers, const struct mem_controller *ctrl)
 {
 	int i;
 	int cs;
@@ -565,8 +574,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	u32 drc;
 	u32 data32;
 	u32 mode_reg;
-	msr_t msr;
-	u16 data16;
 
 	mask = spd_detect_dimms(ctrl);
 	print_debug("Starting SDRAM Enable\n");
@@ -783,11 +790,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	/* Set the ECC mode */
 	pci_write_config32(ctrl->f0, DRC, drc);
 
-	/* The memory is now set up--use it */
-	cache_lbmem(MTRR_TYPE_WRBACK);
 }
 
-static inline int memory_initialized(void)
+inline int memory_initialized(void)
 {
 	return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) & (1 << 29);
 }
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.h b/src/northbridge/intel/i3100/raminit_ep80579.h
index 1f54ef2a0..3fd089f7d 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.h
+++ b/src/northbridge/intel/i3100/raminit_ep80579.h
@@ -21,10 +21,57 @@
 #define NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H
 
 #define DIMM_SOCKETS 2
+
+#define BAR 0x90000000
+
+/* EMR(1) settings:
+	 *    12 11 10 987 6 543 2 1 0 (bit numbers)
+	 * 000 0  1  0 111 0 000 1 0 0 (value)
+	 * [0] DLL - enable
+	 * [1] ODS - full
+	 * [6,2] Rtt - disable
+	 * [5:2] Additive CAS - 0
+	 * [9:7] OCD program: 111 - enable default, 000 - exit (maintain setting)
+	 * [10]  DQS# - Enable
+	 * [11]  RDQS - Disable (only 1 slot, Micron TN-47-12)
+	 * [12]  Outputs - Enabled (req'd by Micron)
+	 * [15:13] Reserved - must be 0
+	 * */
+#define EMR1 0x03800001
+/* EMR(2) settings:
+ *   High temp refresh rate is off
+ */
+#define EMR2 0x00000000
+/* EMR(3) settings:
+ *   All reserved at this time
+ */
+#define EMR3 0x00000000
+
+/* DIOMON offset - DDR I/O monitor register */
+#define DIOMON 0xf0
+/* Bit positions in DIOMON */
+#define DSAMP 24
+#define VRESULT 16
+#define DDRIO_ENABLE 15
+#define BIASSEL 11
+#define DQLEGSELOUT 7
+#define DIOPWR 6
+#define CALEGSELOUT 0
+
+#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
+
 struct mem_controller {
 	u32 node_id;
 	device_t f0;
 	u16 channel0[DIMM_SOCKETS];
 };
 
-#endif
+/* Function prototypes. */
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+void sdram_set_registers(const struct mem_controller *ctrl);
+void sdram_set_spd_registers(const struct mem_controller *ctrl);
+void sdram_enable(int controllers, const struct mem_controller *ctrl);
+int memory_initialized(void);
+int spd_read_byte(unsigned int device, unsigned int address);
+void dump_dcal_regs(void);
+#endif			/* NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H */