Convert to CAR and make i3100/{early_smbus.c,smbus.c} compile with host gcc

This patch aims to convert the Truxton dev board to CAR which required the
following changes:
- Remove unused variables (to satisfy no warnings flag)
- Change .c includes to use headers (raminit_ep80579, early_smbus, smbus)
- Remove early_mtrr_init because CAR takes care of this
- Remove cache_lbmem (raminit_ep80579.c) as CAR takes care of this
- Remove debug code (for now, coming soon)

One side effect is that the mtarvon and eagleheights (which are already CAR)
romstage now use the new headers.  These two boards have been build tested.
The truxton platform was boot tested and a full memtest was run.

Signed-off-by: Dustin Harrison <dustin.harrison@sutus.com>
---

14 files changed, 212 insertions, 125 deletions

diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig
index 025ad3f81..d3089462c 100644
--- a/src/cpu/intel/ep80579/Kconfig
+++ b/src/cpu/intel/ep80579/Kconfig
@@ -1,3 +1,8 @@
 config CPU_INTEL_EP80579
 	bool
 	select SSE
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x4000
+	depends on CPU_INTEL_EP80579
diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc
index 7aaedba7e..06a3b9d86 100644
--- a/src/cpu/intel/ep80579/Makefile.inc
+++ b/src/cpu/intel/ep80579/Makefile.inc
@@ -7,3 +7,4 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index a250c05c6..822333349 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -31,7 +31,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/acpi.h>
-#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_smbus.h"
 #include "southbridge/intel/i3100/early_lpc.c"
 #include "reset.c"
 #include "superio/intel/i3100/early_serial.c"
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index b2bba3a84..6e289a540 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -27,7 +27,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_smbus.h"
 #include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"
 #include "superio/intel/i3100/i3100.h"
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig
index c902f1fa1..d4dc29466 100644
--- a/src/mainboard/intel/truxton/Kconfig
+++ b/src/mainboard/intel/truxton/Kconfig
@@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOUTHBRIDGE_INTEL_I3100
 	select SUPERIO_INTEL_I3100
 	select SUPERIO_SMSC_SMSCSUPERIO
-	select ROMCC
 	select HAVE_HARD_RESET
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_2048
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index c836b9c76..b17ec2fde 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -28,15 +28,15 @@
 #include <pc80/mc146818rtc.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_smbus.h"
 #include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit_ep80579.h"
 #include "superio/intel/i3100/i3100.h"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/intel/i3100/early_serial.c"
 #include "cpu/x86/bist.h"
+#include <lib.h>
 #include <spd.h>
+#include "lib/generic_sdram.c"
 
 /* SATA */
 #define SATA_MODE_IDE  0x00
@@ -55,12 +55,6 @@
 #define RCBA_D29IR 0x3144 /* 16 bit */
 #define RCBA_D28IR 0x3146 /* 16 bit */
 
-#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
-
-static inline int spd_read_byte(u16 device, u8 address)
-{
-	return smbus_read_byte(device, address);
-}
 
 static void early_config(void)
 {
@@ -96,18 +90,12 @@ static void early_config(void)
 	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
 }
 
-#include "northbridge/intel/i3100/raminit_ep80579.c"
-#include "lib/generic_sdram.c"
-#include "../../intel/jarrell/debug.c"
-#include "arch/x86/lib/stages.c"
 
 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-	msr_t msr;
-	u16 perf;
-	static const struct mem_controller mch[] = {
+	const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
 			.f0 = PCI_DEV(0, 0x00, 0),
@@ -117,7 +105,6 @@ static void main(unsigned long bist)
 
 	if (bist == 0) {
 		/* Skip this if there was a built in self test failure */
-		early_mtrr_init();
 		if (memory_initialized()) {
 			/* Reboot doesn't work right now, so if we're rebooting
 			 * force a HARD reboot by using the 0xe into CF9h
@@ -145,18 +132,9 @@ static void main(unsigned long bist)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#ifdef TRUXTON_DEBUG
-	print_pci_devices();
-#endif
 	enable_smbus();
-	dump_spd_registers();
 
 	sdram_initialize(ARRAY_SIZE(mch), mch);
-	dump_pci_devices();
-	dump_pci_device(PCI_DEV(0, 0x00, 0));
-#ifdef TRUXTON_DEBUG
-	dump_bar14(PCI_DEV(0, 0x00, 0));
-#endif
 
 	early_config();
 }
diff --git a/src/northbridge/intel/i3100/Makefile.inc b/src/northbridge/intel/i3100/Makefile.inc
index c2de0fcb5..07a68294f 100644
--- a/src/northbridge/intel/i3100/Makefile.inc
+++ b/src/northbridge/intel/i3100/Makefile.inc
@@ -1,3 +1,5 @@
 driver-y += northbridge.c
 driver-y += pciexp_porta.c
 driver-y += pciexp_porta_ep80579.c
+
+romstage-$(CONFIG_CPU_INTEL_EP80579) += raminit_ep80579.c
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 8967594b5..d3ee447ff 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -18,14 +18,26 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
+#include <console/console.h>
+#include <delay.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <stdlib.h>
+#include <spd.h>
+#include <cpu/x86/msr.h>
+#include <device/pci_def.h>
+#include "southbridge/intel/i3100/early_smbus.h"
 #include "raminit_ep80579.h"
 #include "ep80579.h"
 
+int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
 #define BAR 0x90000000
 
-static void sdram_set_registers(const struct mem_controller *ctrl)
+void sdram_set_registers(const struct mem_controller *ctrl)
 {
 	static const u32 register_values[] = {
 		PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
@@ -36,7 +48,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 		PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0,
 	};
 	int i;
-	int max;
 
 	for (i = 0; i < ARRAY_SIZE(register_values); i += 3) {
 		device_t dev;
@@ -60,7 +71,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
 {
 	/* Calculate the log base 2 size of a DIMM in bits */
 	struct dimm_size sz;
-	int value, low, ddr2;
+	int value, low;
 	sz.side1 = 0;
 	sz.side2 = 0;
 
@@ -485,10 +496,9 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	return drc;
 }
 
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+void sdram_set_spd_registers(const struct mem_controller *ctrl)
 {
 	u8 dimm_mask;
-	int i;
 
 	/* Test if we can read the SPD */
 	dimm_mask = spd_detect_dimms(ctrl);
@@ -502,9 +512,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 {
 	u8 c1,c2;
-        u32 dimm,i;
-        u32 data32;
-	u32 t4;
+	u32 data32;
+	int i;
 
 	/* Set up northbridge values */
 	/* ODT enable */
@@ -541,7 +550,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 }
 
 
-static void dump_dcal_regs(void)
+void dump_dcal_regs(void)
 {
 	int i;
 	for (i = 0x0; i < 0x2a0; i += 4) {
@@ -557,7 +566,7 @@ static void dump_dcal_regs(void)
 }
 
 
-static void sdram_enable(int controllers, const struct mem_controller *ctrl)
+void sdram_enable(int controllers, const struct mem_controller *ctrl)
 {
 	int i;
 	int cs;
@@ -565,8 +574,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	u32 drc;
 	u32 data32;
 	u32 mode_reg;
-	msr_t msr;
-	u16 data16;
 
 	mask = spd_detect_dimms(ctrl);
 	print_debug("Starting SDRAM Enable\n");
@@ -783,11 +790,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	/* Set the ECC mode */
 	pci_write_config32(ctrl->f0, DRC, drc);
 
-	/* The memory is now set up--use it */
-	cache_lbmem(MTRR_TYPE_WRBACK);
 }
 
-static inline int memory_initialized(void)
+inline int memory_initialized(void)
 {
 	return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) & (1 << 29);
 }
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.h b/src/northbridge/intel/i3100/raminit_ep80579.h
index 1f54ef2a0..3fd089f7d 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.h
+++ b/src/northbridge/intel/i3100/raminit_ep80579.h
@@ -21,10 +21,57 @@
 #define NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H
 
 #define DIMM_SOCKETS 2
+
+#define BAR 0x90000000
+
+/* EMR(1) settings:
+	 *    12 11 10 987 6 543 2 1 0 (bit numbers)
+	 * 000 0  1  0 111 0 000 1 0 0 (value)
+	 * [0] DLL - enable
+	 * [1] ODS - full
+	 * [6,2] Rtt - disable
+	 * [5:2] Additive CAS - 0
+	 * [9:7] OCD program: 111 - enable default, 000 - exit (maintain setting)
+	 * [10]  DQS# - Enable
+	 * [11]  RDQS - Disable (only 1 slot, Micron TN-47-12)
+	 * [12]  Outputs - Enabled (req'd by Micron)
+	 * [15:13] Reserved - must be 0
+	 * */
+#define EMR1 0x03800001
+/* EMR(2) settings:
+ *   High temp refresh rate is off
+ */
+#define EMR2 0x00000000
+/* EMR(3) settings:
+ *   All reserved at this time
+ */
+#define EMR3 0x00000000
+
+/* DIOMON offset - DDR I/O monitor register */
+#define DIOMON 0xf0
+/* Bit positions in DIOMON */
+#define DSAMP 24
+#define VRESULT 16
+#define DDRIO_ENABLE 15
+#define BIASSEL 11
+#define DQLEGSELOUT 7
+#define DIOPWR 6
+#define CALEGSELOUT 0
+
+#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
+
 struct mem_controller {
 	u32 node_id;
 	device_t f0;
 	u16 channel0[DIMM_SOCKETS];
 };
 
-#endif
+/* Function prototypes. */
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+void sdram_set_registers(const struct mem_controller *ctrl);
+void sdram_set_spd_registers(const struct mem_controller *ctrl);
+void sdram_enable(int controllers, const struct mem_controller *ctrl);
+int memory_initialized(void);
+int spd_read_byte(unsigned int device, unsigned int address);
+void dump_dcal_regs(void);
+#endif			/* NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H */
diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc
index fa6caf1b5..e9868e305 100644
--- a/src/southbridge/intel/i3100/Makefile.inc
+++ b/src/southbridge/intel/i3100/Makefile.inc
@@ -7,3 +7,6 @@ driver-y += smbus.c
 driver-y += pci.c
 ramstage-y += reset.c
 ramstage-y += pciexp_portb.c
+
+romstage-y += early_smbus.c
+romstage-y += smbus.c
diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c
index f3d4450c5..81921083d 100644
--- a/src/southbridge/intel/i3100/early_smbus.c
+++ b/src/southbridge/intel/i3100/early_smbus.c
@@ -18,15 +18,17 @@
  *
  */
 
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
 #include "smbus.h"
+#include "early_smbus.h"
 
-#define SMBUS_IO_BASE 0x0f00
-
-static void enable_smbus(void)
+void enable_smbus(void)
 {
 	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
-	print_spew("SMBus controller enabled\n");
+	printk(BIOS_SPEW, "SMBus controller enabled\n");
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	pci_write_config8(dev, 0x40, 1);
 	pci_write_config8(dev, 0x4, 1);
@@ -37,7 +39,7 @@ static void enable_smbus(void)
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
 }
 
-static int smbus_read_byte(u32 device, u32 address)
+int smbus_read_byte(u32 device, u32 address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/i3100/early_smbus.h b/src/southbridge/intel/i3100/early_smbus.h
new file mode 100644
index 000000000..ed7feb2f1
--- /dev/null
+++ b/src/southbridge/intel/i3100/early_smbus.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sutus, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#ifndef I3100_EARLY_SMBUS_H
+#define I3100_EARLY_SMBUS_H
+
+#define SMBUS_IO_BASE 0x0f00
+
+void enable_smbus(void);
+int smbus_read_byte(u32 device, u32 address);
+void smbus_send_byte(u8 device, u8 value);
+
+#endif				/* I3100_EARLY_SMBUS_H */
diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c
index 23602acb2..06401137f 100644
--- a/src/southbridge/intel/i3100/smbus.c
+++ b/src/southbridge/intel/i3100/smbus.c
@@ -28,6 +28,7 @@
 #include "i3100.h"
 #include "smbus.h"
 
+#ifndef __PRE_RAM__
 static int lsmbus_read_byte(device_t dev, u8 address)
 {
 	u16 device;
@@ -77,3 +78,79 @@ static const struct pci_driver smbus_driver_ep80579 __pci_driver = {
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.device = PCI_DEVICE_ID_INTEL_EP80579_SMB,
 };
+#endif /* __PRE_RAM__ */
+
+void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+int smbus_wait_until_ready(u32 smbus_io_base)
+{
+	u32 loops = SMBUS_TIMEOUT;
+	u8 byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while (byte & 1);
+	return loops ? 0 : -1;
+}
+
+int smbus_wait_until_done(u32 smbus_io_base)
+{
+	u32 loops = SMBUS_TIMEOUT;
+	u8 byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_io_base + SMBHSTSTAT);
+	} while ((byte & 1) || (byte & ~((1 << 6)|(1 << 0))) == 0);
+	return loops ? 0 : -1;
+}
+
+int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address)
+{
+	u8 global_status_register;
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* setup transaction */
+	/* disable interrupts */
+	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | SMBUS_READ, smbus_io_base + SMBXMITADD);
+	/* set the command/address... */
+	outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
+	/* set up for a byte data read */
+	outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
+
+	/* clear the data byte...*/
+	outb(0, smbus_io_base + SMBHSTDAT0);
+
+	/* start the command */
+	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+
+	/* Ignore the In Use Status... */
+	global_status_register &= ~(3 << 5);
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}
diff --git a/src/southbridge/intel/i3100/smbus.h b/src/southbridge/intel/i3100/smbus.h
index 7023a5b75..814b94764 100644
--- a/src/southbridge/intel/i3100/smbus.h
+++ b/src/southbridge/intel/i3100/smbus.h
@@ -19,6 +19,9 @@
 
 /* This code is based on src/southbridge/intel/esb6300/esb6300_smbus.h */
 
+#ifndef SOUTHBRIDGE_INTEL_I3100_SMBUS_H
+#define SOUTHBRIDGE_INTEL_I3100_SMBUS_H
+
 #include <device/smbus_def.h>
 
 #define SMBHSTSTAT 0x0
@@ -36,77 +39,12 @@
 
 #define SMBUS_TIMEOUT (100*1000*10)
 
-static void smbus_delay(void)
-{
-	outb(0x80, 0x80);
-}
-
-static int smbus_wait_until_ready(u32 smbus_io_base)
-{
-	u32 loops = SMBUS_TIMEOUT;
-	u8 byte;
-	do {
-		smbus_delay();
-		if (--loops == 0)
-			break;
-		byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while (byte & 1);
-	return loops ? 0 : -1;
-}
-
-static int smbus_wait_until_done(u32 smbus_io_base)
-{
-	u32 loops = SMBUS_TIMEOUT;
-	u8 byte;
-	do {
-		smbus_delay();
-		if (--loops == 0)
-			break;
-		byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while ((byte & 1) || (byte & ~((1 << 6)|(1 << 0))) == 0);
-	return loops ? 0 : -1;
-}
-
-static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address)
-{
-	u8 global_status_register;
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-	}
-	/* setup transaction */
-	/* disable interrupts */
-	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
-	/* set the command/address... */
-	outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
-	/* set up for a byte data read */
-	outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
-
-	/* clear the data byte...*/
-	outb(0, smbus_io_base + SMBHSTDAT0);
-
-	/* start the command */
-	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
-	}
-
-	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+#define SMBUS_READ  1
+#define SMBUS_WRITE 0
 
-	/* Ignore the In Use Status... */
-	global_status_register &= ~(3 << 5);
+void smbus_delay(void);
+int smbus_wait_until_ready(u32 smbus_io_base);
+int smbus_wait_until_done(u32 smbus_io_base);
+int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address);
 
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTDAT0);
-	if (global_status_register != (1 << 1)) {
-		return SMBUS_ERROR;
-	}
-	return byte;
-}
+#endif /* SOUTHBRIDGE_INTEL_I3100_SMBUS_H */