diff options
Diffstat (limited to 'src/northbridge/intel/i3100/raminit_ep80579.c')
| -rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.c | 39 |
1 files changed, 22 insertions, 17 deletions
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 8967594b5..d3ee447ff 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -18,14 +18,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> +#include <console/console.h> +#include <delay.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <stdlib.h> +#include <spd.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include "southbridge/intel/i3100/early_smbus.h" #include "raminit_ep80579.h" #include "ep80579.h" +int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + #define BAR 0x90000000 -static void sdram_set_registers(const struct mem_controller *ctrl) +void sdram_set_registers(const struct mem_controller *ctrl) { static const u32 register_values[] = { PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, @@ -36,7 +48,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0, }; int i; - int max; for (i = 0; i < ARRAY_SIZE(register_values); i += 3) { device_t dev; @@ -60,7 +71,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, ddr2; + int value, low; sz.side1 = 0; sz.side2 = 0; @@ -485,10 +496,9 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +void sdram_set_spd_registers(const struct mem_controller *ctrl) { u8 dimm_mask; - int i; /* Test if we can read the SPD */ dimm_mask = spd_detect_dimms(ctrl); @@ -502,9 +512,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) { u8 c1,c2; - u32 dimm,i; - u32 data32; - u32 t4; + u32 data32; + int i; /* Set up northbridge values */ /* ODT enable */ @@ -541,7 +550,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) } -static void dump_dcal_regs(void) +void dump_dcal_regs(void) { int i; for (i = 0x0; i < 0x2a0; i += 4) { @@ -557,7 +566,7 @@ static void dump_dcal_regs(void) } -static void sdram_enable(int controllers, const struct mem_controller *ctrl) +void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; int cs; @@ -565,8 +574,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) u32 drc; u32 data32; u32 mode_reg; - msr_t msr; - u16 data16; mask = spd_detect_dimms(ctrl); print_debug("Starting SDRAM Enable\n"); @@ -783,11 +790,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Set the ECC mode */ pci_write_config32(ctrl->f0, DRC, drc); - /* The memory is now set up--use it */ - cache_lbmem(MTRR_TYPE_WRBACK); } -static inline int memory_initialized(void) +inline int memory_initialized(void) { return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) & (1 << 29); } |