1 files changed, 10 insertions, 72 deletions
diff --git a/src/southbridge/intel/i3100/smbus.h b/src/southbridge/intel/i3100/smbus.h
index 7023a5b75..814b94764 100644
--- a/src/southbridge/intel/i3100/smbus.h
+++ b/src/southbridge/intel/i3100/smbus.h
@@ -19,6 +19,9 @@
 
 /* This code is based on src/southbridge/intel/esb6300/esb6300_smbus.h */
 
+#ifndef SOUTHBRIDGE_INTEL_I3100_SMBUS_H
+#define SOUTHBRIDGE_INTEL_I3100_SMBUS_H
+
 #include <device/smbus_def.h>
 
 #define SMBHSTSTAT 0x0
@@ -36,77 +39,12 @@
 
 #define SMBUS_TIMEOUT (100*1000*10)
 
-static void smbus_delay(void)
-{
-	outb(0x80, 0x80);
-}
-
-static int smbus_wait_until_ready(u32 smbus_io_base)
-{
-	u32 loops = SMBUS_TIMEOUT;
-	u8 byte;
-	do {
-		smbus_delay();
-		if (--loops == 0)
-			break;
-		byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while (byte & 1);
-	return loops ? 0 : -1;
-}
-
-static int smbus_wait_until_done(u32 smbus_io_base)
-{
-	u32 loops = SMBUS_TIMEOUT;
-	u8 byte;
-	do {
-		smbus_delay();
-		if (--loops == 0)
-			break;
-		byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while ((byte & 1) || (byte & ~((1 << 6)|(1 << 0))) == 0);
-	return loops ? 0 : -1;
-}
-
-static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address)
-{
-	u8 global_status_register;
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-	}
-	/* setup transaction */
-	/* disable interrupts */
-	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
-	/* set the command/address... */
-	outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
-	/* set up for a byte data read */
-	outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
-
-	/* clear the data byte...*/
-	outb(0, smbus_io_base + SMBHSTDAT0);
-
-	/* start the command */
-	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
-	}
-
-	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
+#define SMBUS_READ  1
+#define SMBUS_WRITE 0
 
-	/* Ignore the In Use Status... */
-	global_status_register &= ~(3 << 5);
+void smbus_delay(void);
+int smbus_wait_until_ready(u32 smbus_io_base);
+int smbus_wait_until_done(u32 smbus_io_base);
+int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address);
 
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTDAT0);
-	if (global_status_register != (1 << 1)) {
-		return SMBUS_ERROR;
-	}
-	return byte;
-}
+#endif /* SOUTHBRIDGE_INTEL_I3100_SMBUS_H */