Age | Commit message (Collapse) | Author |
|
|
|
|
|
|
|
|
|
Make the lapic_ipi function interrupt-safe.
|
|
This is actually unneeded and dangerous, as it may cause the compiler to
access registers in multiple instructions.
|
|
|
|
Move the page properties into the new x86/page module, and the virtual
memory layout macros into the x86/pmap module.
|
|
|
|
|
|
|
|
This turns assert.h into a standard header.
|
|
|
|
In particular, the pic and ioapic modules register their respective
devices as interrupt controllers. Selection between the legacy XT-PIC
and the modern APIC system is made on the availability of ACPI,
disregarding the multiprocessor specification entirely. The uart
driver is also updated to register devices interrupt handlers.
|
|
Now that cpu_delay uses the timestamp counter, local APIC timer
calibration gets more precise, and doesn't require such a long
interval.
|
|
Make kernel code obtain definitions for the printf family of functions
through the inclusion of the standard stdio.h header.
|
|
The printk functions are close enough to the printf ones to bear the
same names.
|
|
Instead of mixing standard headers and internal redefinitions of standard
types, completely rely on the compiler for what is guaranteed for a free
standing environment. This results in the removal of kern/stddef.h and
kern/stdint.h. The kern/types.h header is reintroduced for the different
(and saner) purpose of defining types not specified in standard C,
namely ssize_t for now.
|
|
This change was done using astyle, with a few manual editing here and
there.
|
|
Interrupt handler functions are suffixed with _intr.
|
|
|
|
Make it clear that destinations are APIC IDs and not kernel-assigned
processor IDs.
|
|
|
|
My AMD Phenom II X4 955 processor suddenly started to trigger local APIC
error interrupts with ESR=0 for some strange reason. Work around the
issue by reporting the error instead of halting. In my case, everything
else worked as expected despite the error interrupt, which is triggered
only once, on cpu0, as soon as the scheduler is started and enables
interrupts.
It's probably worth to note that this particular machine has shown other
weird problems while running up-to-date mainstream operating systems
such as Linux.
|
|
|
|
In practice, this merely means an idle thread now exists for each CPU,
and threads can be preempted and rescheduled on each of them. There is
currently no migration between processors.
|
|
Scheduling is temporarily disabled until the thread module is able to
cope with multiple processors.
|
|
In addition, make lapic_eoi public.
|
|
This change adds periodic timer interrupt reporting to the thread
module, basic thread selection, and context switching. It currently
only applies to the main processor. The x86/tcb module has been
drastically simplified as a side effect.
|
|
There are no precise enough criteria to justify the separation of these
two directories.
|
|
The trap module is responsible for managing low level interrupts and
exceptions.
|
|
Merge 32-bit IA-32 (i386) and 64-bit AMD64 (amd64) code into one common
architecture. The amd64 variant isn't functional yet.
|