diff options
| author | Richard Braun <rbraun@sceen.net> | 2014-05-08 10:54:17 +0200 |
|---|---|---|
| committer | Richard Braun <rbraun@sceen.net> | 2014-05-08 11:21:27 +0200 |
| commit | 2ca8c231bb3b509bb6eb90e2e2065079a78fbd1e (patch) | |
| tree | 5fb6559edd7fe3117eedc3365d1e4e7b1009c1b3 /arch/x86/machine/lapic.c | |
| parent | 162ec40917c5849f23108eb6888c043f7b40b947 (diff) | |
x86/lapic: report internal errors
My AMD Phenom II X4 955 processor suddenly started to trigger local APIC
error interrupts with ESR=0 for some strange reason. Work around the
issue by reporting the error instead of halting. In my case, everything
else worked as expected despite the error interrupt, which is triggered
only once, on cpu0, as soon as the scheduler is started and enables
interrupts.
It's probably worth to note that this particular machine has shown other
weird problems while running up-to-date mainstream operating systems
such as Linux.
Diffstat (limited to 'arch/x86/machine/lapic.c')
| -rw-r--r-- | arch/x86/machine/lapic.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/x86/machine/lapic.c b/arch/x86/machine/lapic.c index 2e879a9..f9da06f 100644 --- a/arch/x86/machine/lapic.c +++ b/arch/x86/machine/lapic.c @@ -347,8 +347,13 @@ lapic_intr_timer(struct trap_frame *frame) void lapic_intr_error(struct trap_frame *frame) { + uint32_t esr; + (void)frame; - panic("lapic: unhandled error interrupt"); + esr = lapic_read(&lapic_map->esr); + printk("lapic: error on cpu%u: esr:%08x\n", cpu_id(), esr); + lapic_write(&lapic_map->esr, 0); + lapic_eoi(); } void |