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2025-02-12KVM: selftests: Print out the actual Top-Down Slots count on failureSean Christopherson
Print out the expected vs. actual count of the Top-Down Slots event on failure in the Intel PMU counters test. GUEST_ASSERT() only expands constants/macros, i.e. only prints the value of the expected count, which makes it difficult to debug and triage failures. Link: https://lore.kernel.org/r/20250117234204.2600624-6-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-02-12KVM: selftests: Drop the "feature event" param from guest test helpersSean Christopherson
Now that validation of event count is tied to hardware support for event, and not to guest support for an event, drop the unused "event" parameter from the various helpers. No functional change intended. Link: https://lore.kernel.org/r/20250117234204.2600624-5-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-02-12KVM: selftests: Remove dead code in Intel PMU counters testSean Christopherson
Drop the local "nr_arch_events" in the Intel PMU counters test as the test asserts that "nr_arch_events <= NR_INTEL_ARCH_EVENTS", and then sets nr_arch_events to the max of the two. I.e. nr_arch_events is guaranteed to be NR_INTEL_ARCH_EVENTS for the meat of the test, just use NR_INTEL_ARCH_EVENTS directly. No functional change intended. Link: https://lore.kernel.org/r/20250117234204.2600624-4-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-02-12KVM: selftests: Only validate counts for hardware-supported arch eventsSean Christopherson
In the Intel PMU counters test, only validate the counts for architectural events that are supported in hardware. If an arch event isn't supported, the event selector may enable a completely different event, and thus the logic for the expected count is bogus. This fixes test failures on pre-Icelake systems due to the encoding for the architectural Top-Down Slots event corresponding to something else (at least on the Skylake family of CPUs). Note, validation relies on *hardware* support, not KVM support and not guest support. Architectural events are all about enumerating the event selector encoding; lack of enumeration for an architectural event doesn't mean the event itself is unsupported, i.e. the event should still count as expected even if KVM and/or guest CPUID doesn't enumerate the event as being "architectural". Note #2, it's desirable to _program_ the architectural event encoding even if hardware doesn't support the event. The count can't be validated when the event is fully enabled, but KVM should still let the guest program the event selector, and the PMC shouldn't count if the event is disabled. Fixes: 4f1bd6b16074 ("KVM: selftests: Test Intel PMU architectural events on gp counters") Reported-by: kernel test robot <oliver.sang@intel.com> Closes: https://lore.kernel.org/oe-lkp/202501141009.30c629b4-lkp@intel.com Debugged-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://lore.kernel.org/r/20250117234204.2600624-3-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-02-12KVM: selftests: Make Intel arch events globally available in PMU counters testSean Christopherson
Wrap PMU counter test's array of Intel architectrual in a helper function so that the events can be queried in multiple locations. Add a comment to explain the need for a wrapper. No functional change intended. Link: https://lore.kernel.org/r/20250117234204.2600624-2-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-01-08KVM: selftests: Use data load to trigger LLC references/misses in Intel PMUSean Christopherson
In the PMU counters test, add a data load in the measured loop and target the data with CLFLUSH{OPT} in order to (try to) guarantee the loop generates LLC misses and fills. Per the SDM, some hardware prefetchers are allowed to omit relevant PMU events, and Emerald Rapids (and possibly Sapphire Rapids) appears to have gained an instruction prefetcher that bypasses event counts. E.g. the test will consistently fail on EMR CPUs, but then pass with seemingly benign changes to the code. The event count includes speculation and cache line fills due to the first-level cache hardware prefetcher, but may exclude cache line fills due to other hardware-prefetchers. Generate a data load as a last ditch effort to preserve the (minimal) test coverage for LLC references and misses. Cc: Maxim Levitsky <mlevitsk@redhat.com> Link: https://lore.kernel.org/r/20241127235627.4049619-1-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
2025-01-08KVM: selftests: Fix typos in x86's PMU counter test's macro variable useColton Lewis
Fix goofs in PMU counter test's assertion macros where the macros unintentionally reference variables in the parent scope. The code "works" as-is purely by accident, as all users define a variable with the correct name (and usage). Fixes: cd34fd8c758e ("KVM: selftests: Test PMC virtualization with forced emulation") Signed-off-by: Colton Lewis <coltonlewis@google.com> Reviewed-by: Mingwei Zhang <mizhang@google.com> Link: https://lore.kernel.org/r/20240918205319.3517569-2-coltonlewis@google.com [sean: massage changelog] Signed-off-by: Sean Christopherson <seanjc@google.com>
2024-12-18KVM: selftests: Use canonical $(ARCH) paths for KVM selftests directoriesSean Christopherson
Use the kernel's canonical $(ARCH) paths instead of the raw target triple for KVM selftests directories. KVM selftests are quite nearly the only place in the entire kernel that using the target triple for directories, tools/testing/selftests/drivers/s390x being the lone holdout. Using the kernel's preferred nomenclature eliminates the minor, but annoying, friction of having to translate to KVM's selftests directories, e.g. for pattern matching, opening files, running selftests, etc. Opportunsitically delete file comments that reference the full path of the file, as they are obviously prone to becoming stale, and serve no known purpose. Reviewed-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Acked-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Acked-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20241128005547.4077116-16-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>