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| author | Guillaume Knispel <gknispel@avencall.com> | 2012-07-17 13:12:42 +0200 |
|---|---|---|
| committer | Guillaume Knispel <gknispel@avencall.com> | 2012-07-17 13:12:42 +0200 |
| commit | 3339f31e6de3397185bde7dfb68bc27eeea263df (patch) | |
| tree | bcc68622c95aa47eb330437c161268a8fd40a7c2 /hardware.h | |
| parent | 87e0a6fbac18d3b0ff771d6ca03720441af245be (diff) | |
| parent | 0c5568616fa054f9859db661a50890890dd5d171 (diff) | |
merge masteradc10
Diffstat (limited to 'hardware.h')
| -rw-r--r--[-rwxr-xr-x] | hardware.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/hardware.h b/hardware.h index 33d4855..74cf357 100755..100644 --- a/hardware.h +++ b/hardware.h @@ -78,9 +78,13 @@ PxIES_INIT //Interrupt Edge Select (0=pos 1=neg) // // ATX specifies that there can be as much as 20 ms between 5V reaching // its 95% level and 3.3V doing likewise. U5H1 (ISL6545) is powered by -// 5V and Q5U1, that disables it, has a pull-up 3.3V on its gate. -// ISL6545 can ramp up its output between ~ 10 and 17 ms (and might -// do it even before) after Power On Reset. +// 5V, and Q5U1 (that disables it) has a pull-up to 3.3V on its gate. +// ISL6545 can ramp up its output between ~ 10 and 17 ms after +// Power On Reset (defined by an high enough voltage on the 5V plane), +// and might do it even before. +// So when only using the pull-up to 3.3V rail and with an ATX +// power supply that has a particular timing, V1P2 would start to +// ramp up too early. // PORT1 |