merge masteradc10

2 files changed, 8 insertions, 6 deletions

diff --git a/hardware.h b/hardware.h
index 33d4855..74cf357 100755..100644
--- a/hardware.h
+++ b/hardware.h
@@ -78,9 +78,13 @@ PxIES_INIT                    //Interrupt Edge Select (0=pos 1=neg)
 //
 // ATX specifies that there can be as much as 20 ms between 5V reaching
 // its 95% level and 3.3V doing likewise. U5H1 (ISL6545) is powered by
-// 5V and Q5U1, that disables it, has a pull-up 3.3V on its gate.
-// ISL6545 can ramp up its output between ~ 10 and 17 ms (and might
-// do it even before) after Power On Reset.
+// 5V, and Q5U1 (that disables it) has a pull-up to 3.3V on its gate.
+// ISL6545 can ramp up its output between ~ 10 and 17 ms after
+// Power On Reset (defined by an high enough voltage on the 5V plane),
+// and might do it even before.
+// So when only using the pull-up to 3.3V rail and with an ATX
+// power supply that has a particular timing, V1P2 would start to
+// ramp up too early.
 
 
 // PORT1
diff --git a/main.c b/main.c
index fe88510..106079d 100755..100644
--- a/main.c
+++ b/main.c
@@ -213,9 +213,7 @@ int main(void)
       if ((P4IN & ATX_PWROK) && TENSION_WAIT(V2P5) && TENSION_WAIT(VCC3)) {
         start_monitoring(V2P5);
         start_monitoring(VCC3);
-        // assertion: V1P2_CORE_EN_N is low but high impedance here
-        // TO CHECK
-        SetBit(P1DIR, V1P2_CORE_EN_N);
+        ClrBit(P1OUT, V1P2_CORE_EN_N);
         Timer1 = 30;
         state = WAIT_V1P2;
       }