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authorGuillaume Knispel <gknispel@avencall.com>2012-07-09 17:37:11 +0200
committerGuillaume Knispel <gknispel@avencall.com>2012-07-09 17:37:11 +0200
commit0c5568616fa054f9859db661a50890890dd5d171 (patch)
treefc56d4d865ba9aa155fa057f6904123643a83442
parent8c92e84498baf42f5d4b63cea0d6fb3f74ffb23c (diff)
better comment about V1P2_CORE_EN_N initial stateplatinium-usine-2012-07
-rw-r--r--[-rwxr-xr-x]hardware.h10
-rw-r--r--[-rwxr-xr-x]main.c0
2 files changed, 7 insertions, 3 deletions
diff --git a/hardware.h b/hardware.h
index 56b8782..38f397b 100755..100644
--- a/hardware.h
+++ b/hardware.h
@@ -78,9 +78,13 @@ PxIES_INIT //Interrupt Edge Select (0=pos 1=neg)
//
// ATX specifies that there can be as much as 20 ms between 5V reaching
// its 95% level and 3.3V doing likewise. U5H1 (ISL6545) is powered by
-// 5V and Q5U1, that disables it, has a pull-up 3.3V on its gate.
-// ISL6545 can ramp up its output between ~ 10 and 17 ms (and might
-// do it even before) after Power On Reset.
+// 5V, and Q5U1 (that disables it) has a pull-up to 3.3V on its gate.
+// ISL6545 can ramp up its output between ~ 10 and 17 ms after
+// Power On Reset (defined by an high enough voltage on the 5V plane),
+// and might do it even before.
+// So when only using the pull-up to 3.3V rail and with an ATX
+// power supply that has a particular timing, V1P2 would start to
+// ramp up too early.
// PORT1
diff --git a/main.c b/main.c
index b3842d3..b3842d3 100755..100644
--- a/main.c
+++ b/main.c