From 0c5568616fa054f9859db661a50890890dd5d171 Mon Sep 17 00:00:00 2001 From: Guillaume Knispel Date: Mon, 9 Jul 2012 17:37:11 +0200 Subject: better comment about V1P2_CORE_EN_N initial state --- hardware.h | 10 +++++++--- main.c | 0 2 files changed, 7 insertions(+), 3 deletions(-) mode change 100755 => 100644 hardware.h mode change 100755 => 100644 main.c diff --git a/hardware.h b/hardware.h old mode 100755 new mode 100644 index 56b8782..38f397b --- a/hardware.h +++ b/hardware.h @@ -78,9 +78,13 @@ PxIES_INIT //Interrupt Edge Select (0=pos 1=neg) // // ATX specifies that there can be as much as 20 ms between 5V reaching // its 95% level and 3.3V doing likewise. U5H1 (ISL6545) is powered by -// 5V and Q5U1, that disables it, has a pull-up 3.3V on its gate. -// ISL6545 can ramp up its output between ~ 10 and 17 ms (and might -// do it even before) after Power On Reset. +// 5V, and Q5U1 (that disables it) has a pull-up to 3.3V on its gate. +// ISL6545 can ramp up its output between ~ 10 and 17 ms after +// Power On Reset (defined by an high enough voltage on the 5V plane), +// and might do it even before. +// So when only using the pull-up to 3.3V rail and with an ATX +// power supply that has a particular timing, V1P2 would start to +// ramp up too early. // PORT1 diff --git a/main.c b/main.c old mode 100755 new mode 100644 -- cgit v1.2.3