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#ifndef XIVO_EP80579_P_H
#define XIVO_EP80579_P_H
#include <linux/kernel.h>
struct hss_queue_entry {
__le32 lsc; /* bytes 0 to 3: len_lsb | len_msb | status | chan_id */
u32 data_ptr;
u32 packet_len;
u32 entry_ptr;
} __attribute__ ((aligned (16)));
static inline __le32 len_status_cid(
unsigned len,
unsigned status,
unsigned chan_id)
{
return cpu_to_le32( (len & 0xffff)
| ((status & 0xff) << 16)
| ((chan_id & 0xff) << 24));
}
static inline unsigned lsc_len(__le32 lsc)
{
return le32_to_cpu(lsc) & 0xffffu;
}
static inline unsigned lsc_status(__le32 lsc)
{
return (le32_to_cpu(lsc) >> 16) & 0xffu;
}
static inline unsigned lsc_cid(__le32 lsc)
{
return (le32_to_cpu(lsc) >> 24) & 0xffu;
}
/* Not sure it's really necessary to allocate that wide npe buffer entries for
* the rx buffers (struct hss_queue_entry might maybe be enough), but we won't
* take the risk of data corruption, and maybe they need to be 32 bytes
* aligned anyway.
* (If this doesn't work we indeed might even try cache line size alignment:
* 64 bytes on EP80579 -- in this case we could put the buffers in the
* 32 bytes gap between entries :)
*/
struct hss_piu_entry {
struct hss_queue_entry q_entry;
u32 next_buf_ptr; /* don't know what it is... */
u32 reserved[3];
} __attribute__ ((aligned (32)));
#define HSS_PIU_ENTRY_CHANNEL_ID(pe_ptr) lsc_cid((pe_ptr)->q_entry.lsc)
#endif /* XIVO_EP80579_P_H */
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