diff options
| author | Dustin Harrison <dustin.harrison@sutus.com> | 2011-05-12 18:31:46 +0200 |
|---|---|---|
| committer | Noe Rubinstein <nrubinstein@proformatique.com> | 2011-06-23 10:38:59 +0200 |
| commit | e48e652c19a0b03cbe7e27deb6a96258d14b00ad (patch) | |
| tree | e4b8df3130f240803741edd974af5488d029b2b4 | |
| parent | 6eac0c533c36dc5fd43ae2351bce486af1b5ff8d (diff) | |
Disable ODT/CS/CKE for second slot if not populated.
Tested with boot and memtest.
Signed-off-by: Dustin Harrison <dustin.harrison@sutus.com>
---
| -rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 878f8abce..1cc84eaa4 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -541,6 +541,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, int i; msr_t msr; u8 cycle = 0x25; + int ranks = 0; for (i = 0; i < DIMM_SOCKETS; i++) { if (!(dimm_mask & (1 << i))) @@ -553,13 +554,23 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, die("ERROR: Only x8 DIMMs supported\n"); value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX); + /* 0 is 1 rank, 1 is 2 rank */ + ranks = (spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS) & 0x07); if (value > cycle) cycle = value; } PRINTK_DEBUG("cycle = %02x\n", cycle); drc |= (1 << ECC); /* enable ECC */ - drc |= ( (1 << CKE0) | (1 << CKE1) ); /* enable CKE on each DIMM */ + /* Only enable CKE for slots with memory */ + drc |= (1 << CKE0); + drc |= (1 << CKE1); + /* Disable CKE[1] ODT[1] cs[1] for one DIMM, one rank */ + if (!ranks && (dimm_mask < 3)) { + drc |= (1 << ODT1DIS); + drc |= (1 << CS1DIS); + drc &= ~(1 << CKE1); + } drc |= (1 << CKEPNM); /* enable CKE globally */ /* TODO check: */ @@ -658,6 +669,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; int cs; + int nr_cs=0; long mask; u32 drc; u32 data32; @@ -678,6 +690,10 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Turn the clocks on */ pci_write_config16(ctrl->f0, CKDIS, 0x0000); + if (drc & (1 << CS1DIS)) + nr_cs = 1; + else + nr_cs = 2; /* Program row size */ spd_set_ram_size(ctrl, mask); @@ -826,7 +842,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, 0x0008000f); /* Clear memory and init ECC */ - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < nr_cs; cs++) { if (!(mask & (1<<cs))) continue; PRINTK_DEBUG("clear memory CS%x\n", cs); @@ -850,7 +866,6 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Set initialization complete */ drc |= (1 << INIT_COMP); - drc |= ( (1 << CKE0) | (1 << CKE1) ); data32 = drc & ~(3 << ECC); /* clear ECC mode */ PRINTK_DEBUG("DRC = %08x\n", data32); pci_write_config32(ctrl->f0, DRC, data32); |