Convert hard-coded numbers to register names and values.

This cleans up the DRC, DRT[0:1], DRA registers with bitfield names.  In
addition, the magic register is set based on DIMM size.

There is no change to registers for 512MB ECC DIMM (boot tested and confirmed
with a MCH register dump).

Signed-off-by: Dustin Harrison <dustin.harrison@sutus.com>
---

2 files changed, 156 insertions, 37 deletions

diff --git a/src/northbridge/intel/i3100/ep80579.h b/src/northbridge/intel/i3100/ep80579.h
index 1f9475e19..e80100027 100644
--- a/src/northbridge/intel/i3100/ep80579.h
+++ b/src/northbridge/intel/i3100/ep80579.h
@@ -20,6 +20,7 @@
 #ifndef NORTHBRIDGE_INTEL_I3100_EP80579_H
 #define NORTHBRIDGE_INTEL_I3100_EP80579_H
 
+/* PCI 0:0:0 registers */
 #define SMRBASE   0x14
 #define MCHCFG0	  0x50
 #define FDHC      0x58
@@ -52,6 +53,7 @@
 #define HECBASE   0xce
 #define DEVPRES1  0xf4
 
+/* SMRBASE registers */
 #define DCALCSR   0x040
 #define DCALADDR  0x044
 #define DCALDATA  0x048
@@ -59,5 +61,77 @@
 #define MBADDR    0x144
 #define MBDATA    0x148
 #define DDRIOMC2  0x268
+#define WL_CNTL0  0x284
+#define WL_CNTL1  0x288
+#define WL_CNTL2  0x28c
+#define WL_CNTL3  0x290
+#define WL_CNTL4  0x294
+#define WDLL_MISC 0x298
+/* 32-bit register */
+#define DQSFAIL0 0xa0
+/* 8-bit register */
+#define DQSFAIL1 0x9c
+
+/* DQSFAIL mask to skip the DQS08 */
+#define DQSFAIL0_ECC_MASK (0x00000000 | (3 << 16))
+#define DQSFAIL1_ECC_MASK (0x00 | (3 << 2))
+
+/* DRT0 Bits */
+#define BTBRWTA		29
+#define BTBRTA		26
+#define BBWRTA		23
+#define Trrd		20
+#define Twr			17
+#define Trc			12
+#define Trcd		 9
+#define Trp			 6
+#define CL			 3
+#define PRGRPD		 0
+
+/* DRT1 Bits */
+#define tRAS		28
+#define tRTP		25
+#define tFAW		20
+#define tCCD		18
+#define tWTR		15
+#define BLEN		13
+#define _2Tor1T		12
+#define NOPCNT		 4
+#define BTBWTA		 0
+
+/* DRC Bits */
+#define DS        0
+#define CKEPNM    4
+#define ODT0DIS   5
+#define ODT1DIS   6
+#define CS0DIS    10
+#define CS1DIS    11
+#define CADIS     12
+#define HLDDIS    13
+#define ECC       20
+#define INIT_COMP 29
+#define CKE0      30
+#define CKE1      31
+
+/* DRA Bits */
+#define NR_ODD	  		29
+#define NC_ODD	  		26
+#define NR_EVEN	  		23
+#define NC_EVEN	  		20
+#define DTYPE_RANK 		17
+#define DTYPE_DDR2 		16
+#define DTYPE_ADRSIZE	15
+#define DTYPE	  		14
+#define DWODD	  		10
+#define DIMMTECH_ODD	 6
+#define DWEVEN			 4
+#define DIMMTECH_EVEN	 0
+
+/* DRA Values */
+#define DTYPE_REGISTERED 1
+#define DTYPE_UNBUFFERED 0
+
+#define DTYPE_DDR2_32    1
+#define DTYPE_DDR2_64    0
 
 #endif
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 9eca4a76e..878f8abce 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -147,6 +147,29 @@ void dump_pci_devices(void)
 	}
 }
 
+static void clear_fifo_pointers(void) {
+	PRINTK_DEBUG("clear read/write fifo pointers\n");
+	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
+	udelay(16);
+	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
+	udelay(16);
+
+	return;
+}
+
+static void clear_dqs_fail(u32 drc) {
+	
+	/* Don't clear the fail bit if ECC is not enabled. */
+	if ( drc & (3 << ECC) ) {
+		write32((BAR + DQSFAIL0), 0x0);
+		write32((BAR + DQSFAIL1), 0x0);
+	}
+	else {
+		write32(BAR + DQSFAIL0, DQSFAIL0_ECC_MASK);
+		write8(BAR + DQSFAIL1, DQSFAIL1_ECC_MASK);
+	}
+}
+
 void sdram_set_registers(const struct mem_controller *ctrl)
 {
 	static const u32 register_values[] = {
@@ -333,15 +356,15 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS);
 		if (value < 0) die("Bad SPD data\n");
 		if ((value & 0xf) == 0) die("Invalid # of rows\n");
-		dra |= (((value-13) & 0x7) << 23);
-		dra |= (((value-13) & 0x7) << 29);
+		dra |= (((value-13) & 0x7) << NR_EVEN);
+		dra |= (((value-13) & 0x7) << NR_ODD);
 		reg += value & 0xf;
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS);
 		if (value < 0) die("Bad SPD data\n");
 		if ((value & 0xf) == 0) die("Invalid # of columns\n");
-		dra |= (((value-10) & 0x7) << 20);
-		dra |= (((value-10) & 0x7) << 26);
+		dra |= (((value-10) & 0x7) << NC_EVEN);
+		dra |= (((value-10) & 0x7) << NC_ODD);
 		reg += value & 0xf;
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM);
@@ -352,19 +375,19 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
 		PRINTK_DEBUG("dimm %02x reg = %02x\n", i, reg);
 
 		/* set device density */
-		dra |= ((31-reg));
-		dra |= ((31-reg) << 6);
+		dra |= ((31-reg) << DIMMTECH_EVEN);
+		dra |= ((31-reg) << DIMMTECH_ODD);
 
-		/* set device width (x8) */
-		dra |= (1 << 4);
-		dra |= (1 << 10);
+		/* set device width (x8, only option supported) */
+		dra |= (1 << DWEVEN);
+		dra |= (1 << DWODD);
 
 		/* set device type (registered) */
-		dra |= (1 << 14);
+		dra |= (DTYPE_REGISTERED << DTYPE);
 
 		/* set number of ranks (0=single, 1=dual) */
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS);
-		dra |= ((value & 0x1) << 17);
+		dra |= ((value & 0x1) << DTYPE_RANK);
 
 		PRINTK_DEBUG("DRA %02x = %08x\n", i, dra);
 
@@ -393,8 +416,12 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
 		0x24240002, 0x24360002, 0x24220002, 0x24360002 };
 	static const u32 drt1[] = { /* 533, 800, 400, 667 */
 		0x00400000, 0x00900000, 0x00200000, 0x00700000 };
-	static const u32 magic[] = { /* 533, 800, 400, 667 */
-		0x007b8221, 0x00b94331, 0x005ca1a1, 0x009a62b1 };
+	/* Write recovery for autoprecharge mrs[27:25]
+	 * 533 - 011 - 4
+	 * 800 - 101 - 6
+	 * 400 - 010 - 3
+	 * 667 - 100 - 5
+	 */
 	static const u32 mrs[] = { /* 533, 800, 400, 667 */
 		0x07020000, 0x0b020000, 0x05020000, 0x09020000 };
 	static const int cycle[] = { /* 533, 800, 400, 667 */
@@ -466,26 +493,46 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
 	PRINTK_DEBUG("trtp = %02x\n", trtp);
 	PRINTK_DEBUG("twtr = %02x\n", twtr);
 
-	val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
-	       | ((cl - 3) << 6) | ((cl - 3) << 3));
+	val = (drt0[index] | ((trc - 11) << Trc) | ((cl - 3) << Trcd)
+	       | ((cl - 3) << Trp) | ((cl - 3) << CL));
 	PRINTK_DEBUG("drt0 = %08x\n", val);
 	pci_write_config32(ctrl->f0, DRT0, val);
 
-	val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
-	       | (twtr << 15));
+	val = (drt1[index] | ((tras - 8) << tRAS) | ((trtp - 2) << tRTP)
+	       | (twtr << tWTR));
 	PRINTK_DEBUG("drt1 = %08x\n", val);
 	pci_write_config32(ctrl->f0, DRT1, val);
 
-	val = (magic[index]);
-	PRINTK_DEBUG("magic = %08x\n", val);
-	pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
-
 	val = (mrs[index] | (cl << 20));
 	PRINTK_DEBUG("mrs = %08x\n", val);
 
 	return val;
 }
 
+static void set_magic(u32 drc) {
+
+	u32 index = (drc & 0x00000003);
+	u32 val;
+
+	static const u32 magic[] = { /* 533, 800, 400, 667 */
+		0x007b8001, 0x00b94001, 0x005ca001, 0x009a6001 };
+
+	/* 533, 800, 400, 667 */
+	static const u8 magic2[4][4] = {
+	/* 256Mb */
+	{ 0x14, 0x1e, 0x0f, 0x18 },
+	/* 512Mb */
+	{ 0x1c, 0x2a, 0x15, 0x22 },
+	/* 1024Mb */
+	{ 0x22, 0x33, 0x1a, 0x29 },
+	/* 2048Mb */
+	{ 0x34, 0x4e, 0x27, 0x2b } };
+
+	val = (magic[drc & 0x00] | (magic2[index][3] << 4));
+	PRINTK_DEBUG("magic = %08x\n", val);
+	pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
+}
+
 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 					u8 dimm_mask)
 {
@@ -511,9 +558,9 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	}
 	PRINTK_DEBUG("cycle = %02x\n", cycle);
 
-	drc |= (1 << 20); /* enable ECC */
-	drc |= (3 << 30); /* enable CKE on each DIMM */
-	drc |= (1 << 4); /* enable CKE globally */
+	drc |= (1 << ECC); /* enable ECC */
+	drc |= ( (1 << CKE0) | (1 << CKE1) ); /* enable CKE on each DIMM */
+	drc |= (1 << CKEPNM); /* enable CKE globally */
 
 	/* TODO check: */
 	/* set front side bus speed */
@@ -624,8 +671,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	if (drc == 0) {
 		die("Error calculating DRC\n");
 	}
-	data32 = drc & ~(3 << 20);  /* clear ECC mode */
-	data32 = data32 | (3 << 5);  /* temp turn off ODT */
+	data32 = drc & ~(3 << ECC);  /* clear ECC mode */
+	data32 = data32 | (1 << ODT0DIS) | (1 << ODT1DIS);  /* temp turn off ODT */
   	/* Set DRAM controller mode */
   	pci_write_config32(ctrl->f0, DRC, data32);
 
@@ -764,6 +811,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	}
 
 	PRINT_DCAL_DUMP();
+	clear_dqs_fail(drc);
 
 	/* Adjust RCOMP */
 	data32 = read32(BAR+DDRIOMC2);
@@ -773,7 +821,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 	PRINT_DCAL_DUMP();
 
-	data32 = drc & ~(3 << 20);  /* clear ECC mode */
+	data32 = drc & ~(3 << ECC);  /* clear ECC mode */
 	pci_write_config32(ctrl->f0, DRC, data32);
 	write32(BAR+DCALCSR, 0x0008000f);
 
@@ -792,21 +840,18 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		}
 	}
 
+	set_magic(drc);
+	
 	/* Clear read/write FIFO pointers */
-	PRINTK_DEBUG("clear read/write fifo pointers\n");
-	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
-	udelay(16);
-	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
-	udelay(16);
-
+	clear_fifo_pointers();
 	PRINT_DCAL_DUMP();
 
 	printk(BIOS_INFO, "Memory init done...\n");
 
 	/* Set initialization complete */
-	drc |= (1 << 29);
-	drc |= (3 << 30);
-	data32 = drc & ~(3 << 20);  /* clear ECC mode */
+	drc |= (1 << INIT_COMP);
+	drc |= ( (1 << CKE0) | (1 << CKE1) );
+	data32 = drc & ~(3 << ECC);  /* clear ECC mode */
 	PRINTK_DEBUG("DRC = %08x\n", data32);
 	pci_write_config32(ctrl->f0, DRC, data32);
 
@@ -821,5 +866,5 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 inline int memory_initialized(void)
 {
-	return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) & (1 << 29);
+	return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) & (1 << INIT_COMP);
 }