diff options
| author | Dustin Harrison <dustin.harrison@sutus.com> | 2011-05-12 18:29:38 +0200 |
|---|---|---|
| committer | Noe Rubinstein <nrubinstein@proformatique.com> | 2011-06-23 10:38:59 +0200 |
| commit | 88aae1ccf13fb79b8aa4b40a4ea3241057ccbe27 (patch) | |
| tree | 8557a4ed7babaff3001eea9e3ef60a71c38b0886 | |
| parent | c2c3993f8044cf8a1efb44c874429186ccad9298 (diff) | |
Fix AHCI SATA support on Truxton (and for all EP80579 chips) and enable AHCI.
Signed-off-by: Dustin Harrison <dustin.harrison@sutus.com>
---
| -rw-r--r-- | src/mainboard/intel/truxton/romstage.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/sata.c | 10 |
2 files changed, 16 insertions, 2 deletions
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 00b49e38d..b13ffc17c 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -38,6 +38,12 @@ #include "cpu/x86/bist.h" #include <spd.h> +/* SATA */ +#define SATA_MODE_IDE 0x00 +#define SATA_MODE_AHCI 0x01 + +#define SATA_MAP 0x90 + /* RCBA registers */ #define RCBA 0xF0 #define DEFAULT_RCBA 0xFEA00000 @@ -86,6 +92,8 @@ static void early_config(void) write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237); write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214); + /* Setup sata mode */ + pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); } #include "northbridge/intel/i3100/raminit_ep80579.c" diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index af22600f9..edc2fe022 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -31,7 +31,7 @@ typedef struct southbridge_intel_i3100_config config_t; static void sata_init(struct device *dev) { - u8 ahci; + u8 ahci; /* Get the chip configuration */ ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03; @@ -43,9 +43,15 @@ static void sata_init(struct device *dev) /* AHCI mode */ pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0)); + pci_write_config8(dev, SATA_CMD, 0x07); /* Enable ports */ - pci_write_config8(dev, SATA_PCS, 0x03); +#ifdef CONFIG_CPU_INTEL_EP80579 + pci_write_config8(dev, SATA_PCS + 1, 0x03); +#else + pci_write_config8(dev, SATA_PCS, 0x03); pci_write_config8(dev, SATA_PCS + 1, 0x0F); +#endif + pci_write_config8(dev, SATA_PCS + 2, 0x00); /* Setup timings */ pci_write_config16(dev, SATA_PTIM, 0x8000); |