Fix IRQs on Truxton by adding ACPI.

Booting Truxton without this patch on a linux 2.6.34 kernel results in no valid
IRQs for GbE, USB and several other PCI devices.  Rather then fix the old
tables, convert to ACPI using the eagleheights code as an example.  After this
patch IRQs work for all devices.

In addition, copy the early_config code from the eagleheights mainboard which
will enable RCBA, enable HPET and disable watchdog.

Signed-off-by: Dustin Harrison <dustin.harrison@sutus.com>
---

8 files changed, 1639 insertions, 194 deletions

diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig
index 5f7de086e..c902f1fa1 100644
--- a/src/mainboard/intel/truxton/Kconfig
+++ b/src/mainboard/intel/truxton/Kconfig
@@ -10,10 +10,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SUPERIO_SMSC_SMSCSUPERIO
 	select ROMCC
 	select HAVE_HARD_RESET
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_2048
+	select HAVE_ACPI_TABLES
+	select BOARD_HAS_FADT
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/intel/truxton/acpi_tables.c b/src/mainboard/intel/truxton/acpi_tables.c
new file mode 100644
index 000000000..fc17abfee
--- /dev/null
+++ b/src/mainboard/intel/truxton/acpi_tables.c
@@ -0,0 +1,225 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Written by Stefan Reinauer <stepan@openbios.org>.
+ * ACPI FADT, FACS, and DSDT table support added by 
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <../../../southbridge/intel/i3100/i3100.h>
+#include <../../../southbridge/intel/i3100/ioapic.h>
+#include <../../../northbridge/intel/i3100/ep80579.h>
+#include <arch/ioapic.h>
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+
+extern const unsigned char AmlCode[];
+
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	/* Not implemented */
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	u64 mmcfg;
+
+	dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_MC, 0);
+	if (!dev) {
+	    printk(BIOS_INFO, "ACPI: Did not find MMCFG capable device.");
+		return current;
+    }
+
+    /* MMCFG not supported or not enabled. */
+    mmcfg = ((u64) pci_read_config16(dev, HECBASE)) << 16;
+    if (!mmcfg) {
+	    printk(BIOS_INFO, "ACPI: Did not find MMCFG capable device (current: %lx).", current);
+        return current;
+    }
+
+    current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+            mmcfg, 0x0, 0x0, 0xff);
+    
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+    unsigned int irq_start = 0;
+
+    /* Local Apic */
+    current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0);
+
+    /* IOAPIC */
+    current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC_ADDR, irq_start);
+
+    /* There are two other memory spaces reserved for I/O APICs that may be 
+	 * present on a PCI card (port A or port B).  These are not detected
+	 * currently.
+	 *
+	 * When (if) this is implemented be sure to read num of interrupts
+	 * because this is controlled via a H/W strapping option.
+	 * irq_start += (io_apic_read(IO_APIC_ADDR, 1) >> 16) & 0xff;
+	 */
+
+    /* Map ISA IRQ 0 to IRQ 2 */
+    current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0);
+
+    /* IRQ9 differs from ISA standard - ours is active high, level-triggered */
+    current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d);
+
+	return current;
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR  0xfed00000ULL
+    acpi_header_t *header = &(hpet->header);
+    acpi_addr_t *addr = &(hpet->addr);
+
+    memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+    /* fill out header fields */
+    memcpy(header->signature, "HPET", 4);
+    memcpy(header->oem_id, OEM_ID, 6);
+    memcpy(header->oem_table_id, "IC      ", 8);
+    memcpy(header->asl_compiler_id, ASLC, 4);
+
+    header->length = sizeof(acpi_hpet_t);
+    header->revision = 1;
+
+    /* fill out HPET address */
+    /* XXX factory bios just puts an address here -- who's right? */
+    addr->space_id = 0; /* Memory */
+    addr->bit_width = 64;
+    addr->bit_offset = 0;
+    addr->addrl = HPET_ADDR & 0xffffffff;
+    addr->addrh = HPET_ADDR >> 32;
+
+    hpet->id = 0x80861234;
+    hpet->number = 0x00;
+    hpet->min_tick = 0x0090;
+
+    header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", current);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_intel_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/intel/truxton/dsdt.asl b/src/mainboard/intel/truxton/dsdt.asl
new file mode 100644
index 000000000..0ed0fd59f
--- /dev/null
+++ b/src/mainboard/intel/truxton/dsdt.asl
@@ -0,0 +1,1179 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT", "DSDT", 1, "TRUXTON", "COREBOOT", 0x0000001)
+{
+    Name (MG1B, 0x00000000)
+    Name (MG1L, 0x00000000)
+    Name (MG2B, 0x80000000)
+    Name (MG2L, 0x80000000)
+
+	Scope (\_PR)
+	{
+		Processor (CPU1, 0x01, 0x00000810, 0x06)
+		{
+			OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
+			Name (NCPU, 0x80)
+			Name (TYPE, 0x80000000)
+			Name (HNDL, 0x80000000)
+			Name (CFGD, 0x80000000)
+			Name (TBLD, 0x80)
+			Method (_PDC, 1, NotSerialized)
+			{
+			}
+		}
+	}
+
+	/* For now only define 2 power states:
+	*  - S0 which is fully on
+	*  - S5 which is soft off
+	* Any others would involve declaring the wake up methods.
+	*/
+	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () { 0x07, 0x07, 0x00, 0x00 })
+
+	Name (PICM, 0x00)
+	Method (_PIC, 1, NotSerialized)
+	{
+		Store (Arg0, PICM)
+	}
+
+	/* System bus */
+	Scope (\_SB)
+	{
+
+		/* Routing PCI0 */
+		Name (PR00, Package (0x12)
+		{
+		Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, /* EDMA INTA# */
+		Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, /* PCIe port A */
+		Package (0x04){0x0002FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0002FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0002FFFF,0x03,LNKD,0x00},
+		Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, /* PCIe port A1 */
+		Package (0x04){0x0003FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0003FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0003FFFF,0x03,LNKD,0x00},
+		Package (0x04){0x0004FFFF,0x00,LNKA,0x00}, /* AOIC */
+		Package (0x04){0x0004FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0004FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0004FFFF,0x03,LNKD,0x00},
+		Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, /* PCIe port B */
+			Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, /* UHCI/EHCI INTA# */
+			/* Legacy: has no entry */
+			Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, /* UHCI INTB# */
+		Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, /* SATA/SMBUS INTB# */
+			/* Legacy: has no entry */
+			Package (0x04){0x001FFFFF,0x03,LNKA,0x00}  /* CHAP INTD# */
+		})
+		Name (AR00, Package (0x12)
+		{
+		Package (0x04){0x0001FFFF,0x00,0x00,0x10}, /* EDMA INTA# */
+		Package (0x04){0x0002FFFF,0x00,0x00,0x10}, /* PCIe port A0 */
+		Package (0x04){0x0002FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0002FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0002FFFF,0x03,0x00,0x13},
+		Package (0x04){0x0003FFFF,0x00,0x00,0x10}, /* PCIe port A1 */
+		Package (0x04){0x0003FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0003FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0003FFFF,0x03,0x00,0x13},
+		Package (0x04){0x0004FFFF,0x00,0x00,0x10}, /* AOIC */
+		Package (0x04){0x0004FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0004FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0004FFFF,0x03,0x00,0x13},
+		/* Legacy: has no entry */
+		Package (0x04){0x001CFFFF,0x00,0x00,0x14}, /* PCIe port B */
+			Package (0x04){0x001DFFFF,0x00,0x00,0x17}, /* UHCI/EHCI INTA# */
+			/* Legacy: has no entry */
+			Package (0x04){0x001DFFFF,0x01,0x00,0x13}, /* UHCI INTB# */
+		Package (0x04){0x001FFFFF,0x01,0x00,0x13}, /* SATA/SMBUS INTB# */
+			/* Legacy: 0x01, 0x00, 0x13 */
+			Package (0x04){0x001FFFFF,0x0D,0x00,0x10}  /* CHAP INTD# */
+		})
+	/* Routing PCIe Port A */
+		Name (PR0A, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,LNKA,0x00},
+			Package (0x04){0xFFFF,0x01,LNKB,0x00},
+			Package (0x04){0xFFFF,0x02,LNKC,0x00},
+			Package (0x04){0xFFFF,0x03,LNKD,0x00}
+		})
+		Name (AR0A, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,0x00,0x10},
+			Package (0x04){0xFFFF,0x01,0x00,0x11},
+			Package (0x04){0xFFFF,0x02,0x00,0x12},
+			Package (0x04){0xFFFF,0x03,0x00,0x13}
+		})
+	/* Routing PCIe Port B */
+		Name (PR0B, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,LNKA,0x00},
+			Package (0x04){0xFFFF,0x01,LNKB,0x00},
+			Package (0x04){0xFFFF,0x02,LNKC,0x00},
+			Package (0x04){0xFFFF,0x03,LNKD,0x00}
+		})
+		Name (AR0B, Package (0x04)
+		{
+			Package (0x04){0xFFFF,0x00,0x00,0x10},
+			Package (0x04){0xFFFF,0x01,0x00,0x11},
+			Package (0x04){0xFFFF,0x02,0x00,0x12},
+			Package (0x04){0xFFFF,0x03,0x00,0x13}
+		})
+	/* Routing Bus PCI */
+	Name (PR01, Package (0x04)
+		{
+		Package (0x04){0x0000FFFF,0x00,LNKA,0x00},
+		Package (0x04){0x0000FFFF,0x01,LNKB,0x00},
+		Package (0x04){0x0000FFFF,0x02,LNKC,0x00},
+		Package (0x04){0x0000FFFF,0x03,LNKD,0x00},
+	})
+	Name (AR01, Package (0x04)
+		{
+		Package (0x04){0x0000FFFF,0x00,0x00,0x10},
+		Package (0x04){0x0000FFFF,0x01,0x00,0x11},
+		Package (0x04){0x0000FFFF,0x02,0x00,0x12},
+		Package (0x04){0x0000FFFF,0x03,0x00,0x13},
+	})
+
+		Name (PRSA, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared, )
+				{3,4,5,6,7,10,11,12,14,15}
+		})
+		Alias (PRSA, PRSB)
+		Alias (PRSA, PRSC)
+		Alias (PRSA, PRSD)
+		Alias (PRSA, PRSE)
+		Alias (PRSA, PRSF)
+		Alias (PRSA, PRSG)
+		Alias (PRSA, PRSH)
+
+	Device (PCI0)
+	{
+		Name (_HID, EisaId ("PNP0A08"))
+		Name (_CID, EisaId ("PNP0A03"))
+		Name (_ADR, 0x00)
+		Name (_SEG, 0x00)
+		Name (_UID, 0x00)
+		Name (_BBN, 0x00)
+
+		Name (SUPP, 0) /* PCI _OSC Support Field Value */
+		Name (CTRL, 0) /* PCI _OSC Control Field Value */
+        Method (_INI, 0, NotSerialized)
+                {
+                }
+
+                Name (CRS, ResourceTemplate ()
+                {
+                    WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                        0x0000,             // Granularity
+                        0x0000,             // Range Minimum
+                        0x00FF,             // Range Maximum
+                        0x0000,             // Translation Offset
+                        0x0100,             // Length
+                        ,, )
+                    IO (Decode16,
+                        0x0CF8,             // Range Minimum
+                        0x0CF8,             // Range Maximum
+                        0x01,               // Alignment
+                        0x08,               // Length
+                        )
+                    WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                        0x0000,             // Granularity
+                        0x0000,             // Range Minimum
+                        0x0CF7,             // Range Maximum
+                        0x0000,             // Translation Offset
+                        0x0CF8,             // Length
+                        ,, , TypeStatic)
+                    WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                        0x0000,             // Granularity
+                        0x0D00,             // Range Minimum
+                        0xFFFF,             // Range Maximum
+                        0x0000,             // Translation Offset
+                        0xF300,             // Length
+                        ,, , TypeStatic)
+                    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+                        0x00000000,         // Granularity
+                        0x000A0000,         // Range Minimum
+                        0x000BFFFF,         // Range Maximum
+                        0x00000000,         // Translation Offset
+                        0x00020000,         // Length
+                        ,, , AddressRangeMemory, TypeStatic)
+                    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+                        0x00000000,         // Granularity
+                        0x00000000,         // Range Minimum
+                        0x00000000,         // Range Maximum
+                        0x00000000,         // Translation Offset
+                        0x00000000,         // Length
+                        ,, _Y1B, AddressRangeMemory, TypeStatic)
+                    DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+                        0x00000000,         // Granularity
+                        0x00000000,         // Range Minimum
+                        0x00000000,         // Range Maximum
+                        0x00000000,         // Translation Offset
+                        0x00000000,         // Length
+                        ,, _Y1C, AddressRangeMemory, TypeStatic)
+                })
+                CreateDWordField (CRS, \_SB.PCI0._Y1B._MIN, MIN5)
+                CreateDWordField (CRS, \_SB.PCI0._Y1B._MAX, MAX5)
+                CreateDWordField (CRS, \_SB.PCI0._Y1B._LEN, LEN5)
+                CreateDWordField (CRS, \_SB.PCI0._Y1C._MIN, MIN6)
+                CreateDWordField (CRS, \_SB.PCI0._Y1C._MAX, MAX6)
+                CreateDWordField (CRS, \_SB.PCI0._Y1C._LEN, LEN6)
+                Method (_CRS, 0, NotSerialized)
+                {
+                    Store (MG1L, Local0)
+                    If (Local0)
+                    {
+                        Store (MG1B, MIN5)
+                        Store (MG1L, LEN5)
+                        Add (MIN5, Decrement (Local0), MAX5)
+                    }
+
+                    Store (MG2B, MIN6)
+                    Store (MG2L, LEN6)
+                    Store (MG2L, Local0)
+                    Add (MIN6, Decrement (Local0), MAX6)
+                    Return (CRS)
+                }
+
+
+		Method (_OSC, 4)
+		{
+			/* Check for proper GUID */
+		If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+		{
+			/* Create DWORD-adressable field from the Capabilities Buffer */
+			CreateDWordField (Arg3, 0, CDW1)
+			CreateDWordField (Arg3, 4, CDW2)
+			CreateDWordField (Arg3, 8, CDW3)
+
+			/* Save Capabilities DWord 2 & 3 */
+			Store (CDW2, SUPP)
+			Store (CDW3, CTRL)
+
+			/* Don't care of OS capabilites */
+			/* We support nothing (maybe we should add PCIe Capability Structure Control) */
+			And (CTRL, 0x00, CTRL)
+
+			/* Query flag clear ? */
+			If (Not (And (CDW1, 1)))
+			{
+				/* Nothing to do */
+			}
+
+			/* Unknown revision ? */
+			If (LNotEqual (Arg1, One))
+			{
+				Or (CDW1, 0x08, CDW1)
+			}
+
+			/* Capabilities bits masked ? */
+			If (LNotEqual (CDW3, CTRL))
+			{
+				Or (CDW1, 0x10, CDW1)
+			}
+
+			/* Update DWORD3 in the buffer */
+			Store (CTRL, CDW3)
+
+			Return (Arg3)
+		}
+		Else
+		{
+			/* Unrecognized UUID */
+			Or (CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+		} /* End _OSC */
+
+			Method (_PRT, 0, NotSerialized)
+			{
+				If (PICM)
+				{
+					Return (AR00)
+				}
+
+				Return (PR00)
+			}
+
+		/* PCI Express Port A */
+		Device (EPA0)
+			{
+				Name (_ADR, 0x00020000)
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR0A)
+					}
+
+					Return (PR0A)
+				}
+			}
+
+		/* PCI Express Port A1 */
+			Device (EPA1)
+			{
+				Name (_ADR, 0x00030000)
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR0A)
+					}
+
+					Return (PR0A)
+				}
+			}
+
+		/* PCI Express Port B0 */
+			Device (EPB0)
+			{
+				Name (_ADR, 0x001C0000)
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR0B)
+					}
+
+					Return (PR0B)
+				}
+			}
+
+		/* PCI Bridge */
+			Device (P0P1)
+			{
+				Name (_ADR, 0x001E0000)
+
+				Method (_PRT, 0, NotSerialized)
+				{
+					If (PICM)
+					{
+						Return (AR01)
+					}
+
+					Return (PR01)
+				}
+			}
+
+		/* LPC I/F Bridge */
+		Device (ISA) {
+			Name (_ADR, 0x001F0000)
+
+				/* MMCONF */
+				Device (^PCIE)
+				{
+					Name (_HID, EisaId ("PNP0C02"))
+					Name (_UID, 0x11)
+					Name (CRS, ResourceTemplate ()
+					{
+						Memory32Fixed (ReadOnly,
+							0xE0000000,         // Address Base
+							0x10000000,         // Address Length
+							_Y10)
+					})
+					Method (_CRS, 0, NotSerialized)
+					{
+						CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._BAS, BAS1)
+						CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._LEN, LEN1)
+						Store (0xE0000000, BAS1)
+						Store (0x10000000, LEN1)
+						Return (CRS)
+					}
+				}
+
+		/* PIC */
+				Device (PIC)
+				{
+			Name (_HID, EisaId ("PNP0000"))
+			Name (_CRS, ResourceTemplate()
+			{
+				IO (Decode16,
+				0x0020,
+				0x0020,
+				0x00,
+				0x02,
+				)
+			IO (Decode16,
+				0x00A0,
+				0x00A0,
+				0x00,
+				0x02,
+				)
+			IRQNoFlags ()
+				{2}
+			})
+				}
+
+        /* HPET */
+        Device (HPET)
+        {
+            Name (_HID, EISAID("PNP0103"))
+            Name (_CID, 0x010CD041)
+
+            Name(BUF0, ResourceTemplate()
+            {
+                Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0)
+            })
+
+            Method (_CRS, 0, Serialized) // Current resources
+            {
+                CreateDWordField(BUF0, \_SB.PCI0.ISA.HPET.FED0._BAS, HPT0)
+                Return (BUF0)
+            }
+        }
+
+
+		/* Real time clock */
+				Device (RTC0)
+				{
+					Name (_HID, EisaId ("PNP0B00"))
+					Name (_CRS, ResourceTemplate ()
+					{
+						IO (Decode16,
+				0x0070,
+				0x0070,
+				0x00,
+				0x02)
+						IRQNoFlags ()
+				{8}
+					})
+				}
+
+				Device (UAR1)
+				{
+					Name (_UID, 0x01)
+					Name (_HID, EisaId ("PNP0501"))
+
+					Method (_PRS, 0, NotSerialized)
+					{
+						Return (CMPR)
+					}
+
+					Name (CMPR, ResourceTemplate ()
+					{
+						StartDependentFn (0x00, 0x00)
+						{
+							IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+							IRQNoFlags () {4}
+							DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+							DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x02F8,0x02F8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+				DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x03E8,0x03E8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+				DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,0x02E8,0x02E8,0x01,0x08)
+							IRQNoFlags () {3,4,5,6,7,10,11,12}
+							DMA (Compatibility, NotBusMaster, Transfer8) {}
+						}
+						EndDependentFn ()
+					})
+				}
+
+		/* PS/2 keyboard (seems to be important for WinXP install) */
+		Device (KBD)
+		{
+			Name (_HID, EisaId ("PNP0303"))
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0f)
+			}
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (TMP, ResourceTemplate () {
+							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+				IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+				IRQNoFlags () {1}
+			})
+			Return (TMP)
+			}
+		}
+
+		/* PS/2 mouse */
+		Device (MOU)
+		{
+			Name (_HID, EisaId ("PNP0F13"))
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (0x0f)
+			}
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (TMP, ResourceTemplate () {
+				IRQNoFlags () {12}
+			})
+			Return (TMP)
+			}
+		}
+
+		/* COM ports of SIO */
+		Device(SIO) {
+				OperationRegion (PT4E, SystemIO, 0x4E, 0x02)
+				Field (PT4E, ByteAcc, NoLock, Preserve)
+				{
+					PO4E,   8,
+					PO4F,   8
+				}
+
+				IndexField (PO4E, PO4F, ByteAcc, NoLock, Preserve)
+				{
+							Offset (0x07),
+					ILDN,   8,
+							Offset (0x28),
+					SIUI,   8,
+					SIUC,   8,
+							Offset (0x30),
+					IACT,   8,
+							Offset (0x60),
+					IIOH,   8,
+					IIOL,   8,
+							Offset (0x70),
+					IINT,   8
+				}
+
+				Method (IENF, 0, NotSerialized)
+				{
+					Store (0x80, PO4E)
+					Store (0x86, PO4E)
+				}
+
+				Method (IEXF, 0, NotSerialized)
+				{
+					Store (0x68, PO4E)
+					Store (0x08, PO4E)
+				}
+
+				Device (COM1)
+				{
+					Name (_UID, 0x03)
+					Name (_HID, EisaId ("PNP0501"))
+					Method (_STA, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x04, ILDN)
+						Store (IACT, Local0)
+						IEXF ()
+						If (LEqual (Local0, 0xFF))
+						{
+							Return (0x00)
+						}
+
+						If (LEqual (Local0, One))
+						{
+							Return (0x0F)
+						}
+						Else
+						{
+							Return (0x0D)
+						}
+					}
+
+					Method (_DIS, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x04, ILDN)
+						Store (Zero, IACT)
+						IEXF ()
+					}
+
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BFU1, ResourceTemplate ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								_Y03)
+							IRQNoFlags (_Y04)
+								{5}
+						})
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MIN, IMIN)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MAX, IMAX)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y04._INT, IRQ0)
+						IENF ()
+						Store (0x04, ILDN)
+						Store (IIOH, Local0)
+						ShiftLeft (Local0, 0x08, Local1)
+						Store (IIOL, Local0)
+						Add (Local1, Local0, Local0)
+						Store (Local0, IMIN)
+						Store (Local0, IMAX)
+						Store (IINT, Local0)
+						IEXF ()
+						Store (0x01, Local1)
+						ShiftLeft (Local1, Local0, IRQ0)
+						Return (BFU1)
+					}
+
+					Name (_PRS, ResourceTemplate ()
+					{
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{5}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x02F8,             // Range Minimum
+								0x02F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{9}
+						}
+				EndDependentFn ()
+					})
+					Method (_SRS, 1, NotSerialized)
+					{
+						CreateByteField (Arg0, 0x02, IOLO)
+						CreateByteField (Arg0, 0x03, IOHI)
+						CreateWordField (Arg0, 0x09, IRQ0)
+						IENF ()
+						Store (0x04, ILDN)
+						Store (Zero, IACT)
+						Store (IOLO, IIOL)
+						Store (IOHI, IIOH)
+						FindSetRightBit (IRQ0, Local0)
+						If (LGreater (Local0, 0x00))
+						{
+							Decrement (Local0)
+						}
+
+						Store (Local0, IINT)
+						Store (One, IACT)
+						IEXF ()
+					}
+				} /* COM1 */
+
+				Device (COM2)
+				{
+					Name (_UID, 0x04)
+					Name (_HID, EisaId ("PNP0501"))
+					Method (_STA, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x05, ILDN)
+						Store (IACT, Local0)
+						IEXF ()
+						If (LEqual (Local0, 0xFF))
+						{
+							Return (0x00)
+						}
+
+						If (LEqual (Local0, One))
+						{
+							Return (0x0F)
+						}
+						Else
+						{
+							Return (0x0D)
+						}
+					}
+
+					Method (_DIS, 0, NotSerialized)
+					{
+						IENF ()
+						Store (0x05, ILDN)
+						Store (Zero, IACT)
+						IEXF ()
+					}
+
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BFU1, ResourceTemplate ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								_Y05)
+							IRQNoFlags (_Y06)
+								{9}
+						})
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MIN, IMIN)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MAX, IMAX)
+						CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y06._INT, IRQ0)
+						IENF ()
+						Store (0x05, ILDN)
+						Store (IIOH, Local0)
+						ShiftLeft (Local0, 0x08, Local1)
+						Store (IIOL, Local0)
+						Add (Local1, Local0, Local0)
+						Store (Local0, IMIN)
+						Store (Local0, IMAX)
+						Store (IINT, Local0)
+						IEXF ()
+						Store (0x01, Local1)
+						ShiftLeft (Local1, Local0, IRQ0)
+						Return (BFU1)
+					}
+
+					Name (_PRS, ResourceTemplate ()
+					{
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x03F8,             // Range Minimum
+								0x03F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{5}
+						}
+						StartDependentFnNoPri ()
+						{
+							IO (Decode16,
+								0x02F8,             // Range Minimum
+								0x02F8,             // Range Maximum
+								0x08,               // Alignment
+								0x08,               // Length
+								)
+							IRQNoFlags ()
+								{9}
+						}
+						EndDependentFn ()
+					})
+					Method (_SRS, 1, NotSerialized)
+					{
+						CreateByteField (Arg0, 0x02, IOLO)
+						CreateByteField (Arg0, 0x03, IOHI)
+						CreateWordField (Arg0, 0x09, IRQ0)
+						IENF ()
+						Store (0x05, ILDN)
+						Store (Zero, IACT)
+						Store (IOLO, IIOL)
+						Store (IOHI, IIOH)
+						FindSetRightBit (IRQ0, Local0)
+						If (LGreater (Local0, 0x00))
+						{
+							Decrement (Local0)
+						}
+
+						Store (Local0, IINT)
+						Store (One, IACT)
+						IEXF ()
+					}
+				} /* COM2 */
+		} /* Device SIO */
+		} /* Device ISA */
+	} /* Device PCI 0*/
+	} /* Scope SB */
+
+	OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C)
+	Field (\_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve)
+	{
+		PIRA,   8,
+		PIRB,   8,
+		PIRC,   8,
+		PIRD,   8,
+				Offset (0x08),
+		PIRE,   8,
+		PIRF,   8,
+		PIRG,   8,
+		PIRH,   8
+	}
+
+	Scope (_SB)
+	{
+		Name (BUFA, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared, _Y1C)
+				{15}
+		})
+		CreateWordField (BUFA, \_SB._Y1C._INT, IRA0)
+		Device (LNKA)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x01)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRA, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSA)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRA, 0x80, PIRA)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRA, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRA)
+			}
+		}
+
+		Device (LNKB)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x02)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRB, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSB)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRB, 0x80, PIRB)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRB, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRB)
+			}
+		}
+
+		Device (LNKC)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x03)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRC, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSC)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRC, 0x80, PIRC)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRC, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRC)
+			}
+		}
+
+		Device (LNKD)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x04)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRD, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSD)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRD, 0x80, PIRD)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRD, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRD)
+			}
+		}
+
+		Device (LNKE)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x05)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRE, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSE)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRE, 0x80, PIRE)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRE, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRE)
+			}
+		}
+
+		Device (LNKF)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x06)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRF, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSF)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRF, 0x80, PIRF)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRF, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRF)
+			}
+		}
+
+		Device (LNKG)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x07)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRG, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSG)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRG, 0x80, PIRG)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRG, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRG)
+			}
+		}
+
+		Device (LNKH)
+		{
+			Name (_HID, EisaId ("PNP0C0F"))
+			Name (_UID, 0x08)
+			Method (_STA, 0, NotSerialized)
+			{
+				And (PIRH, 0x80, Local0)
+				If (Local0)
+				{
+					Return (0x09)
+				}
+				Else
+				{
+					Return (0x0B)
+				}
+			}
+
+			Method (_PRS, 0, NotSerialized)
+			{
+				Return (PRSH)
+			}
+
+			Method (_DIS, 0, NotSerialized)
+			{
+				Or (PIRH, 0x80, PIRH)
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				And (PIRH, 0x0F, Local0)
+				ShiftLeft (0x01, Local0, IRA0)
+				Return (BUFA)
+			}
+
+			Method (_SRS, 1, NotSerialized)
+			{
+				CreateWordField (Arg0, 0x01, IRA)
+				FindSetRightBit (IRA, Local0)
+				Decrement (Local0)
+				Store (Local0, PIRH)
+			}
+		}
+	}
+}
+
+
diff --git a/src/mainboard/intel/truxton/fadt.c b/src/mainboard/intel/truxton/fadt.c
new file mode 100644
index 000000000..8cdc8bb3c
--- /dev/null
+++ b/src/mainboard/intel/truxton/fadt.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+#define ACPI_PM1_STS        (pmbase + 0x00)
+#define ACPI_PM1_EN         (pmbase + 0x02)
+#define ACPI_PM1_CNT        (pmbase + 0x04)
+#define ACPI_PM1_TMR        (pmbase + 0x08)
+#define ACPI_PROC_CNT       (pmbase + 0x10)
+#define ACPI_LV2            (pmbase + 0x14)
+#define ACPI_GPE0_STS       (pmbase + 0x28)
+#define ACPI_GPE0_EN        (pmbase + 0x2C)
+#define ACPI_SMI_EN         (pmbase + 0x30)
+#define ACPI_SMI_STS        (pmbase + 0x34)
+#define ACPI_ALT_GP_SMI_EN  (pmbase + 0x38)
+#define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A)
+#define ACPI_DEVACT_STS     (pmbase + 0x44)
+
+#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS
+#define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT
+#define ACPI_PM_TMR_BLK   ACPI_PM1_TMR
+#define ACPI_P_BLK        ACPI_PROC_CNT
+#define ACPI_GPE0_BLK     ACPI_GPE0_STS
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->preferred_pm_profile = 7; /* Performance Server */
+	fadt->sci_int = 0x9;
+#if CONFIG_HAVE_SMI_HANDLER == 1
+	fadt->smi_cmd = 0xb2;
+#else
+	fadt->smi_cmd = 0x00;
+#endif
+	fadt->acpi_enable = 0xa0;
+	fadt->acpi_disable = 0xa1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xc1;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = 0x0;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x28;
+	fadt->gpe1_blk = 0x0;
+
+	fadt->pm1_evt_len = 0x4;
+	fadt->pm1_cnt_len = 0x2;
+	fadt->pm2_cnt_len = 0x0;
+	fadt->pm_tmr_len = 0x4;
+	fadt->gpe0_blk_len = 0x8;
+	fadt->gpe1_blk_len = 0x0;
+	fadt->gpe1_base = 0x10;
+	fadt->cst_cnt = 0xc0;
+	fadt->p_lvl2_lat = 0x65;
+	fadt->p_lvl3_lat = 0x3e9;
+	fadt->flush_size = 0x400;
+	fadt->flush_stride = 0x10;
+	fadt->duty_offset = 0x1;
+	fadt->duty_width = 0x3;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = 0x03;
+	fadt->flags = 0xa5;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = 0xe;
+	fadt->res3 = 0;
+	fadt->res4 = 0;
+	fadt->res5 = 0;
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = 0x0;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/intel/truxton/irq_tables.c b/src/mainboard/intel/truxton/irq_tables.c
deleted file mode 100644
index f7ed1c59e..000000000
--- a/src/mainboard/intel/truxton/irq_tables.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
- */
-
-#include <arch/pirq_routing.h>
-
-const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE, /* u32 signature */
-	PIRQ_VERSION,   /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices)  */
-	0x00,       /* u8 Bus 0 */
-	(0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */
-	0x0000,     /* u16 reserve IRQ for PCI */
-	0x8086,     /* u16 Vendor */
-	0x5031,     /* Device ID */
-	0x00000000, /* u32 miniport_data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x5e,   /*  u8 checksum - mod 256 checksum must give zero */
-	{  /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  */
-	    {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr);
-}
-
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
deleted file mode 100644
index 67a73338b..000000000
--- a/src/mainboard/intel/truxton/mptable.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-	u8 bus_pea0 = 0;
-	u8 bus_pea1 = 0;
-	u8 bus_aioc;
-	device_t dev;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LAPIC_ADDR);
-
-	smp_write_processors(mc);
-
-	/* AIOC bridge */
-	dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
-	if (dev) {
-		bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-	else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
-		bus_aioc = 0;
-	}
-	/* PCIe A0 */
-	dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
-	if (dev) {
-		bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-	else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
-		bus_pea0 = 0;
-	}
-	/* PCIe A1 */
-	dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
-	if (dev) {
-		bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-	else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
-		bus_pea1 = 0;
-	}
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* IOAPIC handling */
-	smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
-
-	mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
-
-	/* Standard local interrupt assignments */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_isa, 0x00, MP_APIC_ALL, 0x01);
-
-	/* IMCH/IICH PCI devices */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
-
-	if (bus_pea0) {
-		/* PCIe slot 0 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0<<2)|0, 0x8, 0x10);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0<<2)|1, 0x8, 0x11);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0<<2)|2, 0x8, 0x12);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0<<2)|3, 0x8, 0x13);
-	}
-
-	if (bus_pea1) {
-		/* PCIe slots 1-4 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0<<2)|0, 0x8, 0x10);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0<<2)|1, 0x8, 0x11);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0<<2)|2, 0x8, 0x12);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0<<2)|3, 0x8, 0x13);
-	}
-
-	if (bus_aioc) {
-		/* AIOC PCI devices */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
-	}
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr);
-	return (unsigned long)smp_write_config_table(v);
-}
-
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 6672a4095..00b49e38d 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -38,6 +38,17 @@
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
+/* RCBA registers */
+#define RCBA 0xF0
+#define DEFAULT_RCBA 0xFEA00000
+#define RCBA_HPTC  0x3404 /* 32 bit */
+#define RCBA_GCS   0x3410 /* 32 bit */
+
+#define RCBA_D31IR 0x3140 /* 16 bit */
+#define RCBA_D30IR 0x3142 /* 16 bit */
+#define RCBA_D29IR 0x3144 /* 16 bit */
+#define RCBA_D28IR 0x3146 /* 16 bit */
+
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
 
 static inline int spd_read_byte(u16 device, u8 address)
@@ -45,6 +56,38 @@ static inline int spd_read_byte(u16 device, u8 address)
 	return smbus_read_byte(device, address);
 }
 
+static void early_config(void)
+{
+	u32 gcs;
+
+	/* Enable RCBA */
+	pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
+
+	/* Disable watchdog */
+	gcs = read32(DEFAULT_RCBA + RCBA_GCS);
+	gcs |= (1 << 5); /* No reset */
+	write32(DEFAULT_RCBA + RCBA_GCS, gcs);
+
+	/* Enable HPET */
+	write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
+
+	/* Improve interrupt routing
+	 * D31:F2 SATA        INTB# -> PIRQD
+	 * D31:F3 SMBUS       INTB# -> PIRQD
+	 * D31:F4 CHAP        INTD# -> PIRQA
+	 * D29:F0 USB1#1      INTA# -> PIRQH
+	 * D29:F1 USB1#2      INTB# -> PIRQD
+	 * D29:F7 USB2        INTA# -> PIRQH
+	 * D28:F0 PCIe Port 1 INTA# -> PIRQE
+	 */
+
+	write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
+	write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
+	write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
+	write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
+
+}
+
 #include "northbridge/intel/i3100/raminit_ep80579.c"
 #include "lib/generic_sdram.c"
 #include "../../intel/jarrell/debug.c"
@@ -96,4 +139,6 @@ static void main(unsigned long bist)
 #ifdef TRUXTON_DEBUG
 	dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
+
+	early_config();
 }
diff --git a/src/southbridge/intel/i3100/ioapic.h b/src/southbridge/intel/i3100/ioapic.h
new file mode 100644
index 000000000..9b3a54ec0
--- /dev/null
+++ b/src/southbridge/intel/i3100/ioapic.h
@@ -0,0 +1,11 @@
+#define INTEL_IOAPIC_NUM_INTERRUPTS 24
+
+/* North/South Interface APIC */
+#define IO_APIC0 0
+
+/* PEA0 APIC */
+#define IO_APIC2 2
+#define IO_APIC2_ADDR 0xfec80000UL
+/* PEA1 APIC */
+#define IO_APIC3 3
+#define IO_APIC3_ADDR 0xfec81000UL