diff options
author | Richard Braun <rbraun@sceen.net> | 2018-06-25 20:18:15 +0200 |
---|---|---|
committer | Richard Braun <rbraun@sceen.net> | 2018-06-25 20:20:06 +0200 |
commit | 55600b6dd5aacb18a5bc13414048331c985b39d9 (patch) | |
tree | daccf2430aee7e05c394dee2ba449961944e9cbc | |
parent | d6b378604d5545c6ade12a47f1d8c2c7a9267f96 (diff) |
x86/cpu: fix and improve MSR accessors
-rw-r--r-- | arch/x86/machine/cpu.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/x86/machine/cpu.h b/arch/x86/machine/cpu.h index 84e11f47..7b7b0109 100644 --- a/arch/x86/machine/cpu.h +++ b/arch/x86/machine/cpu.h @@ -544,16 +544,19 @@ cpu_cpuid(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, : : "memory"); } -static __always_inline void +static inline void cpu_get_msr(uint32_t msr, uint32_t *high, uint32_t *low) { - asm volatile("rdmsr" : "=a" (*low), "=d" (*high) : "c" (msr)); + asm("rdmsr" : "=a" (*low), "=d" (*high) : "c" (msr)); } -static __always_inline void +/* + * Implies a full memory barrier. + */ +static inline void cpu_set_msr(uint32_t msr, uint32_t high, uint32_t low) { - asm volatile("wrmsr" : : "c" (msr), "a" (low), "d" (high)); + asm volatile("wrmsr" : : "c" (msr), "a" (low), "d" (high) : "memory"); } static __always_inline uint64_t |