diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-14 13:49:00 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-17 20:25:35 +0100 |
| commit | f08407210db921a4c9eaeaa92d0c434858b9c6c4 (patch) | |
| tree | 7b209e523ac57cec93a1fd5800c78cd001adf4af /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | c6b1737f45ca708fee76a30afb4a7b0247455749 (diff) | |
arm64: dts: renesas: r8a779g0: Add L3 cache controller
Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.
Extracted from a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions