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author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-11-10 16:09:31 +0000 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-15 09:40:10 +0100 |
commit | c6b1737f45ca708fee76a30afb4a7b0247455749 (patch) | |
tree | 9dc5e71440e4c2badfc599a9eb7482c6c464c9dc /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 594edf2c61f2eb79234e642e3a82d7ae02e7a241 (diff) |
arm64: dts: renesas: r9a09g011: Add L2 Cache node
The Cortex-A53 processor on RZ/V2M has 512 KB L2 Cache.
Add L2 Cache node to SoC dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221110160931.101539-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions