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| author | Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> | 2023-09-19 12:21:26 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-09-21 08:18:07 -0700 |
| commit | c2d9d8e7ee157f0ef78bcf5c0df149a4a03ae1cd (patch) | |
| tree | 679d8ec36155d9daf1cb6451c1f80b1c987f3feb /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 394b4b7df9f791dc2dcc95f29cda0961900da6e9 (diff) | |
drm/i915/xe2lpd: Add display power well
Add Display Power Well for Xe2_LPD. It's mostly the same as Xe_LPD+,
so reuse the code. PGPICA1 contains type-C capable port slices
which requires the well to power powered up, so add new power well
definition for it.
The DC_OFF fake power well will be added in a follow up commit.
v2: Do not rmw as bit 31 is the only R/W bit in the register (Matt Roper)
BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-20-lucas.demarchi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions