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author | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2023-09-19 12:21:25 -0700 |
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committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-09-21 08:18:07 -0700 |
commit | 394b4b7df9f791dc2dcc95f29cda0961900da6e9 (patch) | |
tree | 2d19c25ffb5b28df886fbcbe79b615a0093121dc /tools/perf/scripts/python/export-to-postgresql.py | |
parent | 9d404dad0bf8c949a2c8dabdf280389c8262ddb9 (diff) |
drm/i915/lnl: Add CDCLK table
Add a new CDCLK table for Lunar Lake.
v2:
- Remove mdclk from the table as it's not needed (Matt Roper)
- Update waveform values to the latest from spec (Matt Roper)
- Rename functions and calculation to match by pixel rate (Lucas)
v3: Keep only the table: as far as intel_pixel_rate_to_cdclk()
is concerned, the minimum cdclk should still be half the pixel
rate on Xe2 (bspec 68858:
"Pipe maximum pixel rate = 2 * CDCLK frequency * Pipe Ratio")
(Matt Roper)
Bspec: 68861, 68858
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-19-lucas.demarchi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions