diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-17 20:07:59 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-23 17:50:07 +0300 |
| commit | cf899c0777b8d780dd6f82317bbe561deb6c7d1c (patch) | |
| tree | d77b2402746a84217f29e85dd5bb1f193c2a6746 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 7a8ccadb5425bc42468d2866c1a5ad273cb2c2c3 (diff) | |
drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible
On TGL/derivatives the pipe DMC state is lost when PG1 is disabled,
and the main DMC does not restore any of it. This means the state will
also be lost during PSR+DC5/6. It seems safest to not even enable the
pipe DMC in that case (the main DMC does restore the pipe DMC enable
bit in PIPEDMC_CONTROL_A for some reason).
Since pipe DMC is only needed for "fast LACE" on these platforms we aren't
actually losing anything here. In the future if we do want to enable
"fast LACE" we'll just have to remember that it won't be compatible with
PSR.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-10-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions