diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-17 20:07:59 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-23 17:50:07 +0300 |
| commit | cf899c0777b8d780dd6f82317bbe561deb6c7d1c (patch) | |
| tree | d77b2402746a84217f29e85dd5bb1f193c2a6746 | |
| parent | 7a8ccadb5425bc42468d2866c1a5ad273cb2c2c3 (diff) | |
drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible
On TGL/derivatives the pipe DMC state is lost when PG1 is disabled,
and the main DMC does not restore any of it. This means the state will
also be lost during PSR+DC5/6. It seems safest to not even enable the
pipe DMC in that case (the main DMC does restore the pipe DMC enable
bit in PIPEDMC_CONTROL_A for some reason).
Since pipe DMC is only needed for "fast LACE" on these platforms we aren't
actually losing anything here. In the future if we do want to enable
"fast LACE" we'll just have to remember that it won't be compatible with
PSR.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-10-ville.syrjala@linux.intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dmc.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 5cd68c2912fe..4572e87d9bfa 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -699,6 +699,21 @@ static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe return false; } +static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + /* + * On TGL/derivatives pipe DMC state is lost when PG1 is disabled. + * Do not even enable the pipe DMC when that can happen outside + * of driver control (PSR+DC5/6). + */ + if (DISPLAY_VER(display) == 12 && crtc_state->has_psr) + return false; + + return true; +} + void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -709,6 +724,11 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state) if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) return; + if (!can_enable_pipedmc(crtc_state)) { + intel_dmc_disable_pipe(crtc_state); + return; + } + if (need_pipedmc_load_program(display)) dmc_load_program(display, dmc_id); else if (need_pipedmc_load_mmio(display, pipe)) |