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| author | Arnd Bergmann <arnd@arndb.de> | 2025-09-24 23:17:20 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-09-24 23:17:23 +0200 |
| commit | c4ebd661282df563a0c83acacbc35cfd4d8da541 (patch) | |
| tree | 1ddc25fbb366a97ed2af9dda908ee7e9bcb51500 /lib/crypto/blake2s-selftest.c | |
| parent | a53811fb37d30622db1fdfc37feb40a3190b9731 (diff) | |
| parent | 941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0 (diff) | |
Merge tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V cache drivers for v6.18
sifive:
Reduce the number of fences issued while flushing. Samuel reports that
this is approximately a 15% speed-up.
ax45mp:
Fix the binding so that it permits the cache-sets setting used by the
recently added QiLai SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
cache: sifive_ccache: Optimize cache flushes
dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value
Link: https://lore.kernel.org/r/20250924-relenting-aqua-a4a93b89809e@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'lib/crypto/blake2s-selftest.c')
0 files changed, 0 insertions, 0 deletions