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| author | Arnd Bergmann <arnd@arndb.de> | 2025-09-24 23:17:20 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-09-24 23:17:23 +0200 |
| commit | c4ebd661282df563a0c83acacbc35cfd4d8da541 (patch) | |
| tree | 1ddc25fbb366a97ed2af9dda908ee7e9bcb51500 | |
| parent | a53811fb37d30622db1fdfc37feb40a3190b9731 (diff) | |
| parent | 941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0 (diff) | |
Merge tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V cache drivers for v6.18
sifive:
Reduce the number of fences issued while flushing. Samuel reports that
this is approximately a 15% speed-up.
ax45mp:
Fix the binding so that it permits the cache-sets setting used by the
recently added QiLai SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
cache: sifive_ccache: Optimize cache flushes
dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value
Link: https://lore.kernel.org/r/20250924-relenting-aqua-a4a93b89809e@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 6 | ||||
| -rw-r--r-- | drivers/cache/sifive_ccache.c | 8 |
2 files changed, 9 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index 4de5bb2e5f24..b135ffa4ab6b 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -47,7 +47,7 @@ properties: const: 2 cache-sets: - const: 1024 + enum: [1024, 2048] cache-size: enum: [131072, 262144, 524288, 1048576, 2097152] @@ -81,6 +81,10 @@ allOf: const: 2048 cache-size: const: 2097152 + else: + properties: + cache-sets: + const: 1024 examples: - | diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index e1a283805ea7..a86800b123b9 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -151,16 +151,16 @@ static void ccache_flush_range(phys_addr_t start, size_t len) if (!len) return; - mb(); + mb(); /* complete earlier memory accesses before the cache flush */ for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end; line += SIFIVE_CCACHE_LINE_SIZE) { #ifdef CONFIG_32BIT - writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); + writel_relaxed(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); #else - writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64); + writeq_relaxed(line, ccache_base + SIFIVE_CCACHE_FLUSH64); #endif - mb(); } + mb(); /* issue later memory accesses after the cache flush */ } static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = { |