diff options
| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2025-05-14 12:04:09 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-06-10 10:20:45 +0200 |
| commit | a68ea80f85bbf7b69f69ef9e17e3e1be14d948c8 (patch) | |
| tree | 4dcc9544eb46ac8945ff2544f35d94e14b9fac3b | |
| parent | 2f96afdffad4ef74e3c511207058c41c54a2d014 (diff) | |
clk: renesas: rzg2l: Move pointers after hw member
Reorder the pointer members in struct mstp_clock so they appear immediately
after the hw member. This helps avoid potential padding and eliminates the
need for any calculations in the to_mod_clock() macro. As struct clk_hw
currently contains only pointers, placing it first also avoids padding.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250514090415.4098534-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index c87ad5a972b7..767da288b0f7 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1185,19 +1185,19 @@ fail: * struct mstp_clock - MSTP gating clock * * @hw: handle between common and hardware-specific interfaces + * @priv: CPG/MSTP private data + * @sibling: pointer to the other coupled clock * @off: register offset * @bit: ON/MON bit * @enabled: soft state of the clock, if it is coupled with another clock - * @priv: CPG/MSTP private data - * @sibling: pointer to the other coupled clock */ struct mstp_clock { struct clk_hw hw; + struct rzg2l_cpg_priv *priv; + struct mstp_clock *sibling; u16 off; u8 bit; bool enabled; - struct rzg2l_cpg_priv *priv; - struct mstp_clock *sibling; }; #define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw) |