diff options
| author | Rob Herring (Arm) <robh@kernel.org> | 2025-06-09 16:57:06 -0500 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-07-03 16:29:45 +0200 |
| commit | 0d495db1b9bd4c3eefc201c5e1c92fd1b96ecf2e (patch) | |
| tree | ccd664e2bea839cab5e6c4a833900b330b29a3f6 | |
| parent | f060fee24a52d6d9d6c0d963c24da7f2b42a3d5d (diff) | |
arm64: dts: cavium: thunder2: Add missing PL011 "uartclk"
The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
Thunder2 SoC is missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250609215706.3009692-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi index 6dfe78a7d4ab..966fb57280f3 100644 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -136,8 +136,8 @@ reg = <0x04 0x02020000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk125mhz>; - clock-names = "apb_pclk"; + clocks = <&clk125mhz>, <&clk125mhz>; + clock-names = "uartclk", "apb_pclk"; }; }; |