diff options
| author | Rob Herring (Arm) <robh@kernel.org> | 2025-06-09 16:54:57 -0500 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-07-03 16:29:28 +0200 |
| commit | f060fee24a52d6d9d6c0d963c24da7f2b42a3d5d (patch) | |
| tree | abdd1cfc4ef07ba693b859dbca1353cacee73133 | |
| parent | caec315724f086c734688bd44f4c3a7a19526731 (diff) | |
arm64: dts: lg: Add missing PL011 "uartclk"
The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
LG131x SoCs are missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Link: https://lore.kernel.org/r/20250609-dt-lg-fixes-v1-2-e210e797c2d7@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm64/boot/dts/lg/lg131x.dtsi | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/lg/lg131x.dtsi b/arch/arm64/boot/dts/lg/lg131x.dtsi index dc4229bd9ebb..4cb1e4510897 100644 --- a/arch/arm64/boot/dts/lg/lg131x.dtsi +++ b/arch/arm64/boot/dts/lg/lg131x.dtsi @@ -128,24 +128,24 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfe000000 0x1000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; + clocks = <&clk_bus>, <&clk_bus>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; uart1: serial@fe100000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfe100000 0x1000>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; + clocks = <&clk_bus>, <&clk_bus>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; uart2: serial@fe200000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfe200000 0x1000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; + clocks = <&clk_bus>, <&clk_bus>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; spi0: spi@fe800000 { |