1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
from datasheet_tables import TE_Id, ProfileBase, register_profile
class SMRBase(ProfileBase):
name = "smrbase"
min_page = 601
max_page = 649
te_table = {
(619, TE_Id(text=u'.', top=374, left=80, width=1, height=2)):
[], # suppress reporting of this spurious TE
(623, TE_Id(text=u'DQLEGSELOUT DQ legsel output of DDR I/O. Sets the driver strength for ', top=530, left=145, width=261, height=8)):
[TE_Id(text=u'DQLEGSELOUT', top=530, left=158, width=25, height=8),
TE_Id(text=u'DQ legsel output of DDR I/O. Sets the driver strength for ', top=527, left=202, width=204, height=8)],
(623, TE_Id(text=u'CALEGSELOUT cmd/addr legsel output of DDR I/O Sets the driver ', top=588, left=145, width=237, height=8)):
[TE_Id(text=u'CALEGSELOUT', top=588, left=158, width=25, height=8),
TE_Id(text=u'cmd/addr legsel output of DDR I/O Sets the driver ', top=585, left=202, width=180, height=8)],
(624, TE_Id(text=u'Reserved Reserved', top=243, left=147, width=79, height=8)):
[TE_Id(text=u'Reserved', top=243, left=145, width=32, height=8),
TE_Id(text=u'Reserved', top=243, left=194, width=32, height=8)],
(624, TE_Id(text=u'Reserved_RW Reserved for future use. These bits are RW but SW should ', top=288, left=138, width=261, height=8)):
[TE_Id(text=u'Reserved_RW', top=288, left=145, width=32, height=8),
TE_Id(text=u'Reserved for future use. These bits are RW but SW should ', top=285, left=194, width=205, height=8)],
(625, TE_Id(text=u'SLVBYP DQS ', top=297, left=158, width=78, height=8)):
[TE_Id(text=u'SLVBYP', top=297, left=158, width=34, height=8),
TE_Id(text=u'DQS ', top=297, left=202, width=34, height=8)],
}
def special_replace(self, ps, te):
return self.special_te_mapper(ps, te, self.te_table)
def table_blacklisted(self, chapter, table_num):
return ((chapter, table_num) in [(16, 289), (16, 290)])
register_profile(SMRBase)
|
