path: root/parse_datasheet/output/gbe.py

{'AIT': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RV',
                     'acronym': 'Rsvd',
                     'description': ['Reserved'],
                     'range': (31, 16),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'AIFS',
                     'description': ['Adaptive IFS Value',
                                     'Adaptive IFS throttles back-to-back transmissions in the transmit packet buffer and delays their transfer to the CSMA/CD transmit function. Normally, this register should be set to 0b. However, if additional delay is desired between back-to-back transmit packets, then this register can be set with a value greater than zero (0). This feature can be helpful in high collision half-duplex environments.',
                                     'In order for AIFS to take effect it should be larger than the minimum IFS value defined in IEEE 802.3 standard. AIFS has no effect on transmissions that occur immediately after receives or transmissions that are not back-to-back. In addition, it has no effect on re-transmission timing (retransmission after collisions).',
                                     'The AIFS value is additive to the TIPG.IPGT value. ',
                                     'This time unit for this value is speed dependent:',
                                     '1000Mbps is 8ns',
                                     '100Mbps is 80ns ',
                                     '10 Mbps is 800ns'],
                     'range': (15, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 1112,
         'offset_end': (1115, None),
         'offset_start': (1112, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'AIT',
         'reg_name': 'AIT',
         'size': 32,
         'table_ref': '37-69',
         'title_desc': 'Adaptive IFS Throttle Register',
         'view': 'PCI 3'},
 'ALGNERRC': {'bar': 'CSRBAR',
              'bus_device_function': 'M:2:0',
              'default': 0,
              'description': None,
              'fields': [{'access': 'RC',
                          'acronym': 'ALGNERRC',
                          'description': ['Alignment error count'],
                          'range': (31, 0),
                          'reset': 0,
                          'sticky': ''}],
              'offset': 16388,
              'offset_end': (16391, None),
              'offset_start': (16388, None),
              'power_well': 'Gbe1/2:',
              'recurring': None,
              'reg_base_name': 'ALGNERRC',
              'reg_name': 'ALGNERRC',
              'size': 32,
              'table_ref': '37-80',
              'title_desc': 'Alignment Error Count Register',
              'view': 'PCI 3'},
 'BPRC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'BPRC',
                      'description': ['Number of broadcast packets received'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16504,
          'offset_end': (16507, None),
          'offset_start': (16504, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'BPRC',
          'reg_name': 'BPRC',
          'size': 32,
          'table_ref': '37-104',
          'title_desc': 'Broadcast Packets Received Count Register',
          'view': 'PCI 3'},
 'BPTC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'BPTC',
                      'description': ['Number of broadcast packets transmitted count'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16628,
          'offset_end': (16631, None),
          'offset_start': (16628, None),
          'power_well': None,
          'recurring': None,
          'reg_base_name': 'BPTC',
          'reg_name': 'BPTC',
          'size': 32,
          'table_ref': '37-128',
          'title_desc': 'Broadcast Packets Transmitted Count Register',
          'view': 'PCI 3'},
 'CEXTERR': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RC',
                         'acronym': 'CEXTERR',
                         'description': ['Number of packets received with a carrier extension error.'],
                         'range': (31, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 16444,
             'offset_end': (16447, None),
             'offset_start': (16444, None),
             'power_well': 'Gbe1/2:',
             'recurring': None,
             'reg_base_name': 'CEXTERR',
             'reg_name': 'CEXTERR',
             'size': 32,
             'table_ref': '37-90',
             'title_desc': 'Carrier Extension Error Count Register',
             'view': 'PCI 3'},
 'COLC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'COLC',
                      'description': ['Total number of collisions experienced by the transmitter'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16424,
          'offset_end': (16427, None),
          'offset_start': (16424, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'COLC',
          'reg_name': 'COLC',
          'size': 32,
          'table_ref': '37-87',
          'title_desc': 'Collision Count Register',
          'view': 'PCI 3'},
 'CRCERRS': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RC',
                         'acronym': 'CRCERRS',
                         'description': ['CRC error count'],
                         'range': (31, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 16384,
             'offset_end': (16387, None),
             'offset_start': (16384, None),
             'power_well': 'Gbe1/2:',
             'recurring': None,
             'reg_base_name': 'CRCERRS',
             'reg_name': 'CRCERRS',
             'size': 32,
             'table_ref': '37-79',
             'title_desc': 'CRC Error Count Register',
             'view': 'PCI 3'},
 'CTRL': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 2569,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 31),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'VME',
                      'description': ['VLAN Mode Enable.',
                                      '0 = VLAN Mode Disabled.1 = VLAN Mode Enabled. All packets transmitted have an 802.1q header added to the packet. The contents of the header come from the transmit descriptor and from the VLAN type register. On receive, VLAN information is stripped from 802.1q packets. See "802.1q VLAN Support" on page 1400 for more details.'],
                      'range': (30, 30),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (29, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TFCE',
                      'description': ['Transmit Flow Control Enable.',
                                      '0 = Transmit Flow Control Disabled.1 = Transmit Flow Control Enabled. Flow control packets (XON & XOFF frames) will be transmitted based on receiver fullness. If Auto-Negotiation is enabled, this bit is set to the negotiated duplex value. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for more information about Auto-Negotiation.'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RFCE',
                      'description': ['Receive Flow Control Enable.',
                                      '0 = Receive Flow Control Disabled.1 = Receive Flow Control Enabled. Indicates the device will respond to the reception of flow control packets. Reception of flow control packets requires the correct loading of the FCAH/FCAL & FCT registers. If Auto-Negotiation is enabled, this bit is set to the negotiated duplex value. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for more information about Auto-Negotiation.'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RST',
                      'description': ['Device Reset, also referred to as a "Soft Reset". Normally 0, writing 1 initiates the reset. This bit is self clearing.',
                                      'CTRL.RST may be used to globally reset the entire GbE hardware. This register is provided primarily as a last-ditch software mechanism to recover from an indeterminate or suspected hung hardware state. Most registers (receive, transmit, interrupt, statistics, etc.), and state machines will be set to their power-on reset values, approximating the state following a power-on or Unit Reset. However, the Packet Buffer Allocation Register (PBA) retains its value through a global reset.Note:Software must first disable both transmit & receive operation using the TCTL.EN and RCTL.EN register bits before asserting CTRL.RST. To ensure that the global device reset has fully completed and that the controller will respond to subsequent accesses, software must wait a minimum of 5 milliseconds after setting CTRL.RST before attempting to check if the bit has cleared or to access any other GbE device register.'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ADVD3WUC',
                      'description': ['D3Cold WakeUp Capability Advertisement Enable. ',
                                      'When set, D3Cold wakeup capability may be advertised based on whether the AUX_PWR pin advertises presence of auxiliary power (see section 2.13.3 for details). When 0, D3Cold wakeup capability will not be advertised even if AUX_PWR presence is indicated. Formerly used as SDP2 pin data value, initial value is EEPROM-configurable',
                                      '*Note that this bit is loaded from the EEPROM, if present'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (19, 13),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'FRCDPLX',
                      'description': ['Force Duplex.',
                                      '0 = Mode is Full-Duplex, regardless of the FD setting.1 =CTRL.FD bit sets duplex mode.'],
                      'range': (12, 12),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'FRCSPD',
                      'description': ['Force Speed.',
                                      '0 = Default of 1Gbps is used to set the MAC speed. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for more details.1 =CTRL.SPEED bits set the MAC speed.Note:This bit is superseded by the CTRL_EXT.SPD_BYPS bit which has a similar function.Note:*Note that this bit is loaded from the EEPROM, if present'],
                      'range': (11, 11),
                      'reset': 1,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (10, 10),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'SPEED',
                      'description': ['Speed selection.',
                                      'These bits are written by software (assuming, after reading the PHY registers through the MDIO interface) to set the MAC speed configuration. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for details.',
                                      '? 00 => 10 Mbps',
                                      '? 01 => 100 Mbps',
                                      '? 10 => 1000 Mbps',
                                      '? 11 => reservedNote:These bits affect the MAC speed setting only if CTRL_EXT.SPD_BYPS or CTRL.FRCSPD are used.'],
                      'range': (9, 8),
                      'reset': 2,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Reserved',
                      'description': ['Reserved'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'SLU',
                      'description': ['Set Link Up.',
                                      "SLU must be set to '1' to enable the MAC. This bit may also be initialized by the APME bit in the EEPROM Initialization Control Word3, if an EEPROM is used."],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'Rsvd',
                      'description': ['Reserved. Must be set to 0.'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (3, 3),
                      'reset': 1,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'Rsvd',
                      'description': ["Reserved. Must write '0' to this bit.1 ="],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'FD',
                      'description': ['Full Duplex. Controls the MAC duplex setting.',
                                      '0 = Half Duplex1 = Full Duplex',
                                      "In half-duplex mode, EP80579's GbE transmits carrier extended packets and can receive both carrier extended packets, and packets transmitted with bursting.",
                                      '*Note that this bit is loaded from the EEPROM, if present'],
                      'range': (0, 0),
                      'reset': 1,
                      'sticky': ''}],
          'offset': 0,
          'offset_end': (3, None),
          'offset_start': (0, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'CTRL',
          'reg_name': 'CTRL',
          'size': 32,
          'table_ref': '37-25',
          'title_desc': 'Device Control Register',
          'view': 'PCI 3'},
 'CTRL_AUX': {'bar': 'CSRBAR',
              'bus_device_function': 'M:2:0',
              'default': 256,
              'description': None,
              'fields': [{'access': 'RO',
                          'acronym': 'RSVD',
                          'description': ['Reserved'],
                          'range': (31, 18),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RW',
                          'acronym': 'RMII_LOG_FIX',
                          'description': ['Enable logic change to fix RMII 100mbps TX dropped packet data.',
                                          "To enable this mode of operation, set this bit to a '1'. When enabled, the fix modifies the legacy new-packet signalling logic in the transmit path to prevent the first 8 bytes of packet data from being dropped when operating in RMII mode and a line speed of 100mbps."],
                          'range': (17, 17),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RW',
                          'acronym': 'RMII_FREQ_FIX',
                          'description': ['Disable DMA frequency change to fix RMII 100mbps TX dropped packet data.',
                                          'This is the default mode of operation. ',
                                          "To disable this mode of operation, set this bit to a '1'. This must be disabled if FIX2 is enabled.",
                                          'When enabled, sets the DMA clock frequency to 50MHz when operating in RMII mode. This produces a favorable frequency ratio between DMA and MAC clocks that prevents the first 8 bytes of transmit packet data from being dropped when operating in RMII mode and a line speed of 100mbps.'],
                          'range': (16, 16),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RO',
                          'acronym': 'RSVD',
                          'description': ['Reserved'],
                          'range': (15, 12),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RW',
                          'acronym': 'END_SEL',
                          'description': ['Selects whether the descriptor or packet data is controlled by endianness configuration.',
                                          '00 - descriptor and packet transfers use CTRL_AUX.ENDIANESS',
                                          '01 - descriptor uses CTL_AUX.ENDIANESS, packet uses default',
                                          '10 - descriptor uses default, packet uses CTRL_AUX.ENDIANESS',
                                          '11 - all transfers use CTRL_AUX.ENDIANESS'],
                          'range': (11, 10),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RW',
                          'acronym': 'ENDIANESS',
                          'description': ['Endianness:',
                                          'These bits control the endianness of the data in memory. These settings apply to all internal bus transactions, including packet data and descriptors',
                                          "'00' - LW Little--Endian, Byte Big-Endian ",
                                          "'01' - LW Little-Endian, Byte Little-Endian (default)",
                                          "'10' - LW Big-Endian, Byte Big-Endian",
                                          "'11' - LW Big-Endian, Byte Little-Endian",
                                          'Refer to Section 37.5.14, "Endianness" for further details.'],
                          'range': (9, 8),
                          'reset': 1,
                          'sticky': ''},
                         {'access': 'RO',
                          'acronym': 'RSVD',
                          'description': ['Reserved'],
                          'range': (7, 1),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RW',
                          'acronym': 'RGMII_RMII',
                          'description': ['RGMII/RMII Translation Gasket Select',
                                          "? '0'  -  RGMII",
                                          "? '1'  -  RMII"],
                          'range': (0, 0),
                          'reset': 0,
                          'sticky': ''}],
              'offset': 224,
              'offset_end': (227, None),
              'offset_start': (224, None),
              'power_well': 'Gbe1/2:',
              'recurring': None,
              'reg_base_name': 'CTRL_AUX',
              'reg_name': 'CTRL_AUX',
              'size': 32,
              'table_ref': '37-28',
              'title_desc': 'Auxiliary Device Control Register',
              'view': 'PCI 3'},
 'CTRL_EXT': {'bar': 'CSRBAR',
              'bus_device_function': 'M:2:0',
              'default': 0,
              'description': None,
              'fields': [{'access': 'RV',
                          'acronym': 'Rsvd',
                          'description': ['Reserved'],
                          'range': (31, 25),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RW',
                          'acronym': 'RMII_RX_MODE',
                          'description': ['RMII gasket receive mode select:',
                                          "0 = For proper 100mbps receive operation, after assertion of the RMII CRS_DV signal on GBEn_RXCTL, the RMII gasket requires that a minimum of two di-bits of '00' appear on GBEn_RXDATA[1:0] before the preamble appears.1 = For proper 100mbps receive operation, the RMII gasket requires that CRS_DV be asserted on GBEn_RXCTL synchronously with GBE_REFCLK_RMII and on the same cycle in which the first di-bit of the preamble appears on GBEn_RXDATA[1:0].",
                                          "0 is the default value of this bit and makes the RMII gasket compatible with RMII PHYs that assert CRS_DV as soon as the receive medium is non-idle, and subsequently drive '00' on RXD[1:0] until proper receive signal decoding has been achieved (per the RMII Specification, Revision 1.2).",
                                          'Setting this bit to a 1 makes the gasket compatible with RMII PHYs that assert CRS_DV simultaneously with the start of the preamble driven on RXD[1:0]. While this CRS_DV signalling mode does not scrictly conform to the RMII specification, it is provided to allow compatibility with PHY devices that use this alternate method of asserting CRS_DV at the start of the packet.',
                                          'This bit must be set to the proper state that corresponds to the CRS_DV behavior of the attached RMII PHY, otherwise 100mbps packets cannot be properly received by the GbE.',
                                          'This bit does not affect transmit operations.'],
                          'range': (24, 24),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RW',
                          'acronym': 'LINK_MODE',
                          'description': ['Link Mode. This controls which interface is used to talk to the link.',
                                          '? 00 => GMII/MII mode',
                                          '? 01 => reserved',
                                          '? 10 => reserved',
                                          '? 11 => reserved',
                                          '? *Note that this bit is loaded from the EEPROM, if present'],
                          'range': (23, 22),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RV',
                          'acronym': 'Rsvd',
                          'description': ['Reserved'],
                          'range': (21, 16),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RW',
                          'acronym': 'SPD_BYPS',
                          'description': ['Speed Select Bypass.',
                                          "0 = Normal speed detection mechanisms are used to determine the speed of the MAC.1 = All speed detection mechanisms are bypassed and the MAC is immediately set to the setting of CTRL.SPEED.Note:CTRL_EXT.SPD_BYPS performs a function similar to CTRL.FRCSPD in that the device's speed settings are determined by the value software writes to the CTRL.SPEED bits. However, when using CTRL_EXT.SPD_BYPS the CTRL.SPEED setting takes effect immediately, when using CTRL.FRCSPD the CTRL.SPEED setting waits until after the device's clock switching circuitry performs the change."],
                          'range': (15, 15),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RV',
                          'acronym': 'Rsvd',
                          'description': ['Reserved'],
                          'range': (14, 14),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RW',
                          'acronym': 'EE_RST',
                          'description': ['EEPROM Reset',
                                          'Initiates a "reset-like" event to the EEPROM function. This causes the EEPROM to be read as if a UNIT_RESET had occurred. All device functions should be disabled prior to setting this bit. This bit is self-clearing.',
                                          'NOTE: this will not cause the controller to detect the EEPROM'],
                          'range': (13, 13),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RV',
                          'acronym': 'Rsvd',
                          'description': ['Reserved'],
                          'range': (12, 12),
                          'reset': 0,
                          'sticky': ''},
                         {'access': 'RV',
                          'acronym': 'Rsvd',
                          'description': ['Reserved'],
                          'range': (11, 0),
                          'reset': 0,
                          'sticky': ''}],
              'offset': 24,
              'offset_end': (27, None),
              'offset_start': (24, None),
              'power_well': 'Gbe1/2:',
              'recurring': None,
              'reg_base_name': 'CTRL_EXT',
              'reg_name': 'CTRL_EXT',
              'size': 32,
              'table_ref': '37-27',
              'title_desc': 'Extended Device Control Register',
              'view': 'PCI 3'},
 'DC': {'bar': 'CSRBAR',
        'bus_device_function': 'M:2:0',
        'default': 0,
        'description': None,
        'fields': [{'access': 'RC',
                    'acronym': 'DC',
                    'description': ['Number of defer events.'],
                    'range': (31, 0),
                    'reset': 0,
                    'sticky': ''}],
        'offset': 16432,
        'offset_end': (16435, None),
        'offset_start': (16432, None),
        'power_well': 'Gbe1/2:',
        'recurring': None,
        'reg_base_name': 'DC',
        'reg_name': 'DC',
        'size': 32,
        'table_ref': '37-88',
        'title_desc': 'Defer Count Register',
        'view': 'PCI 3'},
 'ECOL': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'ECOL',
                      'description': ['Number of packets with more than 16 collisions'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16408,
          'offset_end': (16411, None),
          'offset_start': (16408, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'ECOL',
          'reg_name': 'ECOL',
          'size': 32,
          'table_ref': '37-84',
          'title_desc': 'Excessive Collisions Count Register',
          'view': 'PCI 3'},
 'EEPROM_CTRL': {'bar': 'CSRBAR',
                 'bus_device_function': 'M:2:0',
                 'default': u'00000X1Xh',
                 'description': None,
                 'fields': [{'access': 'RO',
                             'acronym': 'RSVD',
                             'description': ['Reserved'],
                             'range': (31, 10),
                             'reset': 0,
                             'sticky': ''},
                            {'access': 'RO',
                             'acronym': 'EE_SIZE',
                             'description': ['EEPROM Size. ',
                                             '0 Reserved',
                                             '1 4096-bit (256 word) NM93C66 compatible EEPROM',
                                             'If an EEPROM is present, this bit indicates its size, based on acknowledges seen during EEPROM scans of different addresses. ',
                                             'This bit is read-only.',
                                             'NOTE: this bit will not be updated as a result of anything but a power up reset.'],
                             'range': (9, 9),
                             'reset': None,
                             'sticky': ''},
                            {'access': 'RO',
                             'acronym': 'EE_PRES',
                             'description': ['EEPROM Present',
                                             'This bit attempts to indicate if an EEPROM is present by monitoring the EE_DO input for a active-low "acknowledge" by the serial EEPROM during initial EEPROM scan. If no EEPROM is present, the EE_DO line will remain pulled-high and thus no acknowledge will be seen. ',
                                             '1=EEPROM present; ',
                                             '0=no EEPROM.',
                                             'NOTE: this bit will not be set except as a result of EEPROM detection during power up reset.'],
                             'range': (8, 8),
                             'reset': None,
                             'sticky': ''},
                            {'access': 'RO',
                             'acronym': 'EE_GNT',
                             'description': ['Grant EEPROM Access',
                                             'When this bit is 1 the software can access the EEPROM using the SK, CS, DI, and DO bits.'],
                             'range': (7, 7),
                             'reset': 0,
                             'sticky': ''},
                            {'access': 'RW',
                             'acronym': 'EE_REQ',
                             'description': ['Request EEPROM Access',
                                             'The software must write a 1 to this bit to get direct EEPROM access. It has access when EE_GNT is 1. When the software completes the access it must write a 0.'],
                             'range': (6, 6),
                             'reset': 0,
                             'sticky': ''},
                            {'access': 'RO',
                             'acronym': 'RSVD',
                             'description': ['Reserved'],
                             'range': (5, 4),
                             'reset': 1,
                             'sticky': ''},
                            {'access': 'RO',
                             'acronym': 'EE_DO',
                             'description': ['Data Output Bit from the EEPROM. ',
                                             'The EE_DO input signal is mapped directly to this bit in the register and contains the EEPROM data output. This bit is read-only from the software perspective - writes to this bit have no effect.'],
                             'range': (3, 3),
                             'reset': None,
                             'sticky': ''},
                            {'access': 'RW',
                             'acronym': 'EE_DI',
                             'description': ['Data Input to the EEPROM. ',
                                             'When EE_GNT is 1, the EE_DI output signal is mapped directly to this bit. Software provides data input to the EEPROM via writes to this bit.'],
                             'range': (2, 2),
                             'reset': 0,
                             'sticky': ''},
                            {'access': 'RW',
                             'acronym': 'EE_CS',
                             'description': ['Chip Select Input to the EEPROM. ',
                                             'When EE_GNT is 1, the EE_CS output signal is mapped to the chip select of the EEPROM device. Software enables the EEPROM by writing a 1 to this bit.'],
                             'range': (1, 1),
                             'reset': 0,
                             'sticky': ''},
                            {'access': 'RW',
                             'acronym': 'EE_SK',
                             'description': ['Clock Input to the EEPROM. ',
                                             'When EE_GNT is 1, the EE_SK output signal is mapped to this bit and provides the serial clock input to the EEPROM. Software clocks the EEPROM via toggling this bit with successive writes.'],
                             'range': (0, 0),
                             'reset': 0,
                             'sticky': ''}],
                 'offset': 16,
                 'offset_end': (19, None),
                 'offset_start': (16, None),
                 'power_well': 'Gbe1/2:',
                 'recurring': None,
                 'reg_base_name': 'EEPROM_CTRL',
                 'reg_name': 'EEPROM_CTRL',
                 'size': 32,
                 'table_ref': '37-29',
                 'title_desc': 'EEPROM Control Register',
                 'view': 'PCI 3'},
 'EEPROM_RR': {'bar': 'CSRBAR',
               'bus_device_function': 'M:2:0',
               'default': u'XXXXXX00h',
               'description': None,
               'fields': [{'access': 'RO',
                           'acronym': 'DATA',
                           'description': ['Read Data',
                                           'Data returned from the EEPROM read.'],
                           'range': (31, 16),
                           'reset': None,
                           'sticky': ''},
                          {'access': 'RW',
                           'acronym': 'ADDR',
                           'description': ['Read Address',
                                           'This field is written by software along with Start Read to indicate the word to read.'],
                           'range': (15, 8),
                           'reset': None,
                           'sticky': ''},
                          {'access': 'RV',
                           'acronym': 'RSVD',
                           'description': ['Reserved ', 'Reads as 0'],
                           'range': (7, 5),
                           'reset': 0,
                           'sticky': ''},
                          {'access': 'RO',
                           'acronym': 'DONE',
                           'description': ['Read Done',
                                           'Set to 1 when the EEPROM read completes.',
                                           'Set to 0 when the EEPROM read is in progress.',
                                           'Writes by software are ignored.'],
                           'range': (4, 4),
                           'reset': 0,
                           'sticky': ''},
                          {'access': 'RV',
                           'acronym': 'RSVD',
                           'description': ['Reserved ', 'Reads as 0'],
                           'range': (3, 1),
                           'reset': 0,
                           'sticky': ''},
                          {'access': 'RW',
                           'acronym': 'START',
                           'description': ['Start Read',
                                           'Writing a 1 to this bit causes the EEPROM to read a (16-bit) word at the address stored in the EE_ADDR field, storing the result in the EE_DATA field. This bit is self-clearing'],
                           'range': (0, 0),
                           'reset': 0,
                           'sticky': ''}],
               'offset': 20,
               'offset_end': (23, None),
               'offset_start': (20, None),
               'power_well': 'Gbe1/2:',
               'recurring': None,
               'reg_base_name': 'EEPROM_RR',
               'reg_name': 'EEPROM_RR',
               'size': 32,
               'table_ref': '37-30',
               'title_desc': 'EEPROM Read Register',
               'view': 'PCI 3'},
 'FCAH': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 256,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (31, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'FCAH',
                      'description': ['This register must be programmed with 0x00_00_01_00.'],
                      'range': (15, 0),
                      'reset': 256,
                      'sticky': ''}],
          'offset': 44,
          'offset_end': (47, None),
          'offset_start': (44, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'FCAH',
          'reg_name': 'FCAH',
          'size': 32,
          'table_ref': '37-32',
          'title_desc': 'Flow Control Address High Register',
          'view': 'PCI 3'},
 'FCAL': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 12746753,
          'description': None,
          'fields': [{'access': 'RW',
                      'acronym': 'FCAL',
                      'description': ['This register must be programmed with 0x00C2_8001.'],
                      'range': (31, 0),
                      'reset': 12746753,
                      'sticky': ''}],
          'offset': 40,
          'offset_end': (43, None),
          'offset_start': (40, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'FCAL',
          'reg_name': 'FCAL',
          'size': 32,
          'table_ref': '37-31',
          'title_desc': 'Flow Control Address Low Register',
          'view': 'PCI 3'},
 'FCRTH': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RW',
                       'acronym': 'XFCE',
                       'description': ['External Flow Control Enabled',
                                       '0b = Disabled.',
                                       '1b = Enabled.',
                                       'Allows the Ethernet controller to send XOFF and XON frames based on external pins XOFF and XON. The transmission of pause frames must be also enabled through the CTRL.TFCE control bit. When the XOFF signal is asserted high, the Ethernet controller transmits a single XOFF frame. The assertion of XON (after deassertion of XOFF) initiates an XON frame transmission, if enabled by FCRTL.XONE. The assertion/deassertion of XON is required between assertions of XOFF in order to send another XOFF frame.',
                                       'This behavior also provides a built-in hysteresis mechanism.',
                                       'Note:The EP80579 does not have external XON/XOFF pins and therefore does not support external flow control enable. This bit must be set to 0 for correct operation.'],
                       'range': (31, 31),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RV',
                       'acronym': 'Rsvd',
                       'description': ['Reserved'],
                       'range': (30, 16),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RW',
                       'acronym': 'RTH',
                       'description': ['Receive Threshold High. FIFO high water mark for flow control transmission.'],
                       'range': (15, 3),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RV',
                       'acronym': '0',
                       'description': ['Writes are ignored, reads return 0.'],
                       'range': (2, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 8552,
           'offset_end': (8555, None),
           'offset_start': (8552, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'FCRTH',
           'reg_name': 'FCRTH',
           'size': 32,
           'table_ref': '37-52',
           'title_desc': 'Flow Control Receive Threshold High Register',
           'view': 'PCI 3'},
 'FCRTL': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RW',
                       'acronym': 'XONE',
                       'description': ['XON Enable',
                                       '0b = Disabled.',
                                       '1b = Enabled.',
                                       'When set, enables the Ethernet controller to transmit XON packets based on receive FIFO crosses FCRTL.RTL threshold value, or based on external pins XOFF and XON. See Section 37.6.4.3, "FCRTH - Flow Control Receive Threshold High Register" on page 1479'],
                       'range': (31, 31),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RV',
                       'acronym': 'Rsvd',
                       'description': ['Reserved'],
                       'range': (30, 16),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RW',
                       'acronym': 'RTL',
                       'description': ['Receive Threshold Low. FIFO low water mark for flow control transmission.'],
                       'range': (15, 3),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RV',
                       'acronym': '0',
                       'description': ['Writes are ignored, reads return 0.'],
                       'range': (2, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 8544,
           'offset_end': (8547, None),
           'offset_start': (8544, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'FCRTL',
           'reg_name': 'FCRTL',
           'size': 32,
           'table_ref': '37-51',
           'title_desc': 'Flow Control Receive Threshold Low Register',
           'view': 'PCI 3'},
 'FCRUC': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RC',
                       'acronym': 'FCRUC',
                       'description': ['Number of unsupported flow control frames received'],
                       'range': (31, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 16472,
           'offset_end': (16475, None),
           'offset_start': (16472, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'FCRUC',
           'reg_name': 'FCRUC',
           'size': 32,
           'table_ref': '37-96',
           'title_desc': 'FC Received Unsupported Count Register',
           'view': 'PCI 3'},
 'FCT': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 34824,
         'description': 'This register must be programmed with 0x00_00_88_0',
         'fields': [{'access': 'RV',
                     'acronym': 'RSVD',
                     'description': ['Reserved'],
                     'range': (31, 16),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'FCT',
                     'description': ['This register must be programmed with 0x00_00_88_08.'],
                     'range': (15, 0),
                     'reset': 34824,
                     'sticky': ''}],
         'offset': 48,
         'offset_end': (51, None),
         'offset_start': (48, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'FCT',
         'reg_name': 'FCT',
         'size': 32,
         'table_ref': '37-33',
         'title_desc': 'Flow Control Type Register',
         'view': 'PCI 3'},
 'FCTTV': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RV',
                       'acronym': 'Rsvd',
                       'description': ['Reserved'],
                       'range': (31, 16),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RW',
                       'acronym': 'TTV',
                       'description': ['Transmit Timer Value to be included in XOFF frame.'],
                       'range': (15, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 368,
           'offset_end': (371, None),
           'offset_start': (368, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'FCTTV',
           'reg_name': 'FCTTV',
           'size': 32,
           'table_ref': '37-35',
           'title_desc': 'Flow Control Transmit Timer Value Register',
           'view': 'PCI 3'},
 'FFLT[0-3]': {'bar': 'CSRBAR',
               'bus_device_function': 'M:2:0',
               'default': 0,
               'description': None,
               'fields': [{'access': 'RV',
                           'acronym': 'RSVD',
                           'description': ['Reserved'],
                           'range': (31, 11),
                           'reset': 0,
                           'sticky': ''},
                          {'access': 'RW',
                           'acronym': 'FFLT_LENx',
                           'description': ['Flexible Filter Length for FIlter x'],
                           'range': (10, 0),
                           'reset': 0,
                           'sticky': ''}],
               'offset': 24320,
               'offset_end': (24323, 8),
               'offset_start': (24320, 8),
               'power_well': None,
               'recurring': 4,
               'reg_base_name': 'FFLT',
               'reg_name': 'FFLT[0-3]',
               'size': 32,
               'table_ref': '37-140',
               'title_desc': 'Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW)',
               'view': 'PCI 3'},
 'FFMT[0-127]': {'bar': 'CSRBAR',
                 'bus_device_function': 'M:2:0',
                 'default': u'0000000Xh',
                 'description': None,
                 'fields': [{'access': 'RV',
                             'acronym': 'RSVD',
                             'description': ['Reserved'],
                             'range': (31, 4),
                             'reset': 0,
                             'sticky': ''},
                            {'access': 'RW',
                             'acronym': 'Mask_x',
                             'description': ['Byte Mask for Byte xx'],
                             'range': (3, 0),
                             'reset': None,
                             'sticky': ''}],
                 'offset': 36864,
                 'offset_end': (36867, 8),
                 'offset_start': (36864, 8),
                 'power_well': None,
                 'recurring': 128,
                 'reg_base_name': 'FFMT',
                 'reg_name': 'FFMT[0-127]',
                 'size': 32,
                 'table_ref': '37-142',
                 'title_desc': 'Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW)',
                 'view': 'PCI 3'},
 'FFVT[0-127]': {'bar': 'CSRBAR',
                 'bus_device_function': 'M:2:0',
                 'default': u'XXXXXXXXh',
                 'description': None,
                 'fields': [{'access': 'RW',
                             'acronym': 'VAL3',
                             'description': ['Byte x Compare Value 3'],
                             'range': (31, 24),
                             'reset': None,
                             'sticky': ''},
                            {'access': 'RW',
                             'acronym': 'VAL2',
                             'description': ['Byte x Compare Value 2'],
                             'range': (23, 16),
                             'reset': None,
                             'sticky': ''},
                            {'access': 'RW',
                             'acronym': 'VAL1',
                             'description': ['Byte x Compare Value 1'],
                             'range': (15, 8),
                             'reset': None,
                             'sticky': ''},
                            {'access': 'RW',
                             'acronym': 'VAL0',
                             'description': ['Byte x Compare Value 0'],
                             'range': (7, 0),
                             'reset': None,
                             'sticky': ''}],
                 'offset': 38912,
                 'offset_end': (38915, 8),
                 'offset_start': (38912, 8),
                 'power_well': None,
                 'recurring': 128,
                 'reg_base_name': 'FFVT',
                 'reg_name': 'FFVT[0-127]',
                 'size': 32,
                 'table_ref': '37-144',
                 'title_desc': 'Flexible Filter Value Table Registers',
                 'view': 'PCI 3'},
 'GORCH': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RC',
                       'acronym': 'GORCH',
                       'description': ['Number of good octets received - upper 4 bytes'],
                       'range': (31, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 16524,
           'offset_end': (16527, None),
           'offset_start': (16524, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'GORCH',
           'reg_name': 'GORCH',
           'size': 32,
           'table_ref': '37-108',
           'title_desc': 'Good Octets Received Count High Register',
           'view': 'PCI 3'},
 'GORCL': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RC',
                       'acronym': 'GORCL',
                       'description': ['Number of good octets received - lower 4 bytes'],
                       'range': (31, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 16520,
           'offset_end': (16522, None),
           'offset_start': (16520, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'GORCL',
           'reg_name': 'GORCL',
           'size': 32,
           'table_ref': '37-107',
           'title_desc': 'Good Octets Received Count Low Register',
           'view': 'PCI 3'},
 'GOTCH': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RC',
                       'acronym': 'GOTCH',
                       'description': ['Number of good octets transmitted - upper 4 bytes'],
                       'range': (31, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 16532,
           'offset_end': (16535, None),
           'offset_start': (16532, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'GOTCH',
           'reg_name': 'GOTCH',
           'size': 32,
           'table_ref': '37-110',
           'title_desc': 'Good Octets Transmitted Count High Register',
           'view': 'PCI 3'},
 'GOTCL': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RC',
                       'acronym': 'GOTCL',
                       'description': ['Number of good octets transmitted - lower 4 bytes'],
                       'range': (31, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 16528,
           'offset_end': (16531, None),
           'offset_start': (16528, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'GOTCL',
           'reg_name': 'GOTCL',
           'size': 32,
           'table_ref': '37-109',
           'title_desc': 'Good Octets Transmitted Count Low Register',
           'view': 'PCI 3'},
 'GPRC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'GPRC',
                      'description': ['Number of good packets received (total of all lengths)'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16500,
          'offset_end': (16503, None),
          'offset_start': (16500, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'GPRC',
          'reg_name': 'GPRC',
          'size': 32,
          'table_ref': '37-103',
          'title_desc': 'Good Packets Received Count (Total) Register',
          'view': 'PCI 3'},
 'GPTC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'GPTC',
                      'description': ['Number of good packets transmitted'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16512,
          'offset_end': (16515, None),
          'offset_start': (16512, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'GPTC',
          'reg_name': 'GPTC',
          'size': 32,
          'table_ref': '37-106',
          'title_desc': 'Good Packets Transmitted Count Register',
          'view': 'PCI 3'},
 'ICR0': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Internal Bus Error. ',
                                      'This bit indicates that an error occurred during either a Target or Host transaction on the bus. Refer to Section 37.5.12, "Error Handling" for complete details.',
                                      'The details of this error are reported in the INTBUS_ERR_STAT register.'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_STAT',
                      'description': ['Statistic Register ECC Error. The Statistic Registers are implemented using a memory that uses a single-bit correct/multi-bit detect ECC parity algorithm to protect it. This bit indicates that a multi-bit error has occurred on a read from that memory. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['This bit indicates that either a Multicast Filter Parity Error, Special Packet Filter Parity Error or a Flex Filter Parity Error occurred. These filters use parity protected SRAMs for data buffers. This bit indicates that a parity error has occurred on a read from either of these data buffers. This error is considered non-fatal and will clear after a read of the MEM_ERR_STAT register.'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_PB',
                      'description': ['DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for data. This bit indicates that a multi-bit error has occurred on a read from that SRAM. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_TXDS',
                      'description': ['DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_RXDS',
                      'description': ['DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (19, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'SRPD',
                      'description': ['Small Receive Packet Detected.',
                                      'Indicates that a packet of size   RSRPD.SIZE register has been detected and transferred to host memory. The interrupt is only asserted if RSRPD.SIZE register has a non-zero value'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'TXD_LOW',
                      'description': ['Transmit Descriptor Low Threshold hit. Indicates that the descriptor ring has reached the threshold specified in "TXDCTL - Transmit Descriptor Control Register" on page 1500.'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (14, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'RXT0',
                      'description': ['Receiver Timer Interrupt. Set when the timers expire, see "Receive Interrupts" on page 1360 for details.'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'RXO',
                      'description': ['Receiver Overrun. Set on receive data FIFO overrun. Could be caused either because there are no available buffers or because Internal Bus receive bandwidth is inadequate.'],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'RXDMT0',
                      'description': ['Receive Descriptor Minimum Threshold Hit. Indicates that the minimum number of receive descriptors are available and software should load more receive descriptors.'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'TXQE',
                      'description': ['Transmit Queue Empty. Set when the last descriptor block for a transmit queue has been used.'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'TXDW',
                      'description': ['Transmit Descriptor Written Back. Set when hardware processes a descriptor with its RS bit set. If using delayed interrupts (TDESC.IDE is set in the Transmit Descriptor CMD), the interrupt is delayed until after one of the delayed-timers (TIDV or TADV) expires.'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 192,
          'offset_end': (195, None),
          'offset_start': (192, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'ICR0',
          'reg_name': 'ICR0',
          'size': 32,
          'table_ref': '37-37',
          'title_desc': 'Interrupt 0 Cause Read Register',
          'view': 'PCI 3'},
 'ICR1': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Internal Bus Error. ',
                                      'This bit indicates that an error occurred during either a Target or Host transaction on the bus. Refer to Section 37.5.12, "Error Handling" for complete details.',
                                      'The details of this error are reported in the INTBUS_ERR_STAT register.'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_STAT',
                      'description': ['Statistic Register ECC Error. The Statistic Registers are implemented using a memory that uses a single-bit correct/multi-bit detect ECC parity algorithm to protect it. This bit indicates that a multi-bit error has occurred on a read from that memory. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Multicast Filter Parity Error/Special Packet Filter Parity Error. The Multicast Filter and Special Packets Filter use parity protected SRAMs for data buffers. This bit indicates that a parity error has occurred on a read from either of these data buffers. This error is considered non-fatal and will clear after a read of the MEM_ERR_STAT register.'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_PB',
                      'description': ['DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for data. This bit indicates that a multi-bit error has occurred on a read from that SRAM. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_TXDS',
                      'description': ['DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_RXDS',
                      'description': ['DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (19, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'SRPD',
                      'description': ['Small Receive Packet Detected.',
                                      'Indicates that a packet of size   RSRPD.SIZE register has been detected and transferred to host memory. The interrupt is only asserted if RSRPD.SIZE register has a non-zero value'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'TXD_LOW',
                      'description': ['Transmit Descriptor Low Threshold hit. Indicates that the descriptor ring has reached the threshold specified in "TXDCTL - Transmit Descriptor Control Register" on page 1500.'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (14, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'RXT0',
                      'description': ['Receiver Timer Interrupt. Set when the timers expire, see "Receive Interrupts" on page 1360 for details.'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'RXO',
                      'description': ['Receiver Overrun. Set on receive data FIFO overrun. Could be caused either because there are no available buffers or because Internal Bus receive bandwidth is inadequate.'],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'RXDMT0',
                      'description': ['Receive Descriptor Minimum Threshold Hit. Indicates that the minimum number of receive descriptors are available and software should load more receive descriptors.'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'TXQE',
                      'description': ['Transmit Queue Empty. Set when the last descriptor block for a transmit queue has been used.'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'TXDW',
                      'description': ['Transmit Descriptor Written Back. Set when hardware processes a descriptor with its RS bit set. If using delayed interrupts (TDESC.IDE is set in the Transmit Descriptor CMD), the interrupt is delayed until after one of the delayed-timers (TIDV or TADV) expires.'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 2240,
          'offset_end': (2243, None),
          'offset_start': (2240, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'ICR1',
          'reg_name': 'ICR1',
          'size': 32,
          'table_ref': '37-42',
          'title_desc': 'Interrupt 1Cause Read Register',
          'view': 'PCI 3'},
 'ICR2': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Internal Bus Error. ',
                                      'This bit indicates that an error occurred during either a Target or Host transaction on the bus. Refer to Section 37.5.12, "Error Handling" for complete details.',
                                      'The details of this error are reported in the INTBUS_ERR_STAT register.'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_STAT',
                      'description': ['Statistic Register ECC Error. The Statistic Registers are implemented using a memory that uses a single-bit correct/multi-bit detect ECC parity algorithm to protect it. This bit indicates that a multi-bit error has occurred on a read from that memory. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Multicast Filter Parity Error/Special Packet Filter Parity Error. The Multicast Filter and Special Packets Filter use parity protected SRAMs for data buffers. This bit indicates that a parity error has occurred on a read from either of these data buffers. '],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_PB',
                      'description': ['DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for data. This bit indicates that a multi-bit error has occurred on a read from that SRAM. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_TXDS',
                      'description': ['DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RCWC',
                      'acronym': 'ERR_RXDS',
                      'description': ['DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved'],
                      'range': (19, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 2272,
          'offset_end': (2275, None),
          'offset_start': (2272, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'ICR2',
          'reg_name': 'ICR2',
          'size': 32,
          'table_ref': '37-46',
          'title_desc': 'Error Interrupt Cause Read Register',
          'view': 'PCI 3'},
 'ICS0': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Triggers Internal Bus Error'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_STAT',
                      'description': ['Triggers Statistic Register ECC Error'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Triggers Special Packet Filter Parity Error'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_PKBUF',
                      'description': ['Triggers DMA Packet Buffer ECC Error'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_TXDS',
                      'description': ['Triggers DMA Transmit Descriptor Buffer ECC Error'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_RXDS',
                      'description': ['Triggers DMA Receive Descriptor Buffer ECC Error'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (19, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'SRPD',
                      'description': ['Triggers Small Receive Packet Detected and Transferred'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXD_LOW',
                      'description': ['Triggers Transmit Descriptor Low Threshold Hit'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (14, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXT0',
                      'description': ['Triggers Receiver Timer Interrupt'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXO',
                      'description': ['Triggers Receiver Overrun. Set on receive data FIFO overrun'],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXDMT0',
                      'description': ['Triggers Receive Descriptor Minimum Threshold hit'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ["Reserved. Must be written as '0'"],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXQE',
                      'description': ['Triggers Transmit Queue Empty'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXDW',
                      'description': ['Triggers Transmit Descriptor Written Back'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 200,
          'offset_end': (203, None),
          'offset_start': (200, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'ICS0',
          'reg_name': 'ICS0',
          'size': 32,
          'table_ref': '37-39',
          'title_desc': 'Interrupt 0 Cause Set Register',
          'view': 'PCI 3'},
 'ICS1': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Triggers Internal Bus Error'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_STAT',
                      'description': ['Triggers Statistic Register ECC Error'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Triggers Special Packet Filter Parity Error'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_PKBUF',
                      'description': ['Triggers DMA Packet Buffer ECC Error'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_TXDS',
                      'description': ['Triggers DMA Transmit Descriptor Buffer ECC Error'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_RXDS',
                      'description': ['Triggers DMA Receive Descriptor Buffer ECC Error'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (19, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'SRPD',
                      'description': ['Triggers Small Receive Packet Detected and Transferred'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXD_LOW',
                      'description': ['Triggers Transmit Descriptor Low Threshold Hit'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (14, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXT0',
                      'description': ['Triggers Receiver Timer Interrupt'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXO',
                      'description': ['Triggers Receiver Overrun. Set on receive data FIFO overrun'],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXDMT0',
                      'description': ['Triggers Receive Descriptor Minimum Threshold hit'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ["Reserved. Must be written as '0'"],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXQE',
                      'description': ['Triggers Transmit Queue Empty'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXDW',
                      'description': ['Triggers Transmit Descriptor Written Back'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 2248,
          'offset_end': (2251, None),
          'offset_start': (2248, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'ICS1',
          'reg_name': 'ICS1',
          'size': 32,
          'table_ref': '37-43',
          'title_desc': 'Interrupt 0 Cause Set Register',
          'view': 'PCI 3'},
 'ICS2': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Triggers Internal Bus Error'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_STAT',
                      'description': ['Triggers Statistic Register ECC Error'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Triggers Special Packet Filter Parity Error'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_PKBUF',
                      'description': ['Triggers DMA Packet Buffer ECC Error'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_TXDS',
                      'description': ['Triggers DMA Transmit Descriptor Buffer ECC Error'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_RXDS',
                      'description': ['Triggers DMA Receive Descriptor Buffer ECC Error'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (19, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 2280,
          'offset_end': (2283, None),
          'offset_start': (2280, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'ICS2',
          'reg_name': 'ICS2',
          'size': 32,
          'table_ref': '37-47',
          'title_desc': 'Error Interrupt Cause Set Register',
          'view': 'PCI 3'},
 'IMC0': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Clears the mask for Internal Bus Error'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_STAT',
                      'description': ['Clears the mask for Statistic Register ECC Error'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Clears the mask for the Filter Memory Errors'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_PKBUF',
                      'description': ['Clears the mask for DMA Packet Buffer ECC Error'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_TXDS',
                      'description': ['Clears the mask for DMA Transmit Descriptor Buffer ECC Error'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_RXDS',
                      'description': ['Clears the mask for DMA Receive Descriptor Buffer ECC Error'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (19, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'SRPD',
                      'description': ['Clears the mask for Small Receive Packet Detected and Transferred'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'TXD_LOW',
                      'description': ['Clears the mask for Transmit Descriptor Low Threshold Hit'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (14, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'RXT0',
                      'description': ['Clears the mask for Receiver Timer Interrupt'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'RXO',
                      'description': ['Clears the mask for Receiver Overrun. Set on receive data FIFO overrun'],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'RXDMT0',
                      'description': ['Clears the mask for Receive Descriptor Minimum Threshold hit'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ["Reserved. Must be written as '0'"],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'TXQE',
                      'description': ['Clears the mask for Transmit Queue Empty'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'TXDW',
                      'description': ['Clears the mask for Transmit Descriptor Written Back'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 216,
          'offset_end': (219, None),
          'offset_start': (216, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'IMC0',
          'reg_name': 'IMC0',
          'size': 32,
          'table_ref': '37-41',
          'title_desc': 'Interrupt 0 Mask Clear Register',
          'view': 'PCI 3'},
 'IMC1': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Clears the mask for Internal Bus Error'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_STAT',
                      'description': ['Clears the mask for Statistic Register ECC Error'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Clears the mask for the Filter Memory Errors'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_PKBUF',
                      'description': ['Clears the mask for DMA Packet Buffer ECC Error'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_TXDS',
                      'description': ['Clears the mask for DMA Transmit Descriptor Buffer ECC Error'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_RXDS',
                      'description': ['Clears the mask for DMA Receive Descriptor Buffer ECC Error'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (19, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'SRPD',
                      'description': ['Clears the mask for Small Receive Packet Detected and Transferred'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'TXD_LOW',
                      'description': ['Clears the mask for Transmit Descriptor Low Threshold Hit'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (14, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'RXT0',
                      'description': ['Clears the mask for Receiver Timer Interrupt'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'RXO',
                      'description': ['Clears the mask for Receiver Overrun. Set on receive data FIFO overrun'],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'RXDMT0',
                      'description': ['Clears the mask for Receive Descriptor Minimum Threshold hit'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'TXQE',
                      'description': ['Clears the mask for Transmit Queue Empty'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'TXDW',
                      'description': ['Clears the mask for Transmit Descriptor Written Back'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 2264,
          'offset_end': (2267, None),
          'offset_start': (2264, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'IMC1',
          'reg_name': 'IMC1',
          'size': 32,
          'table_ref': '37-45',
          'title_desc': 'Interrupt 1 Mask Clear Register',
          'view': 'PCI 3'},
 'IMC2': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Clears the mask for Internal Bus Error'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_STAT',
                      'description': ['Clears the mask for Statistic Register ECC Error'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_INT',
                      'description': ['Clears the mask for Internal Memory Error'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_PKBUF',
                      'description': ['Clears the mask for DMA Packet Buffer ECC Error'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_TXDS',
                      'description': ['Clears the mask for DMA Transmit Descriptor Buffer ECC Error'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_RXDS',
                      'description': ['Clears the mask for DMA Receive Descriptor Buffer ECC Error'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (19, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 2296,
          'offset_end': (2299, None),
          'offset_start': (2296, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'IMC2',
          'reg_name': 'IMC2',
          'size': 32,
          'table_ref': '37-49',
          'title_desc': 'Error Interrupt Mask Clear Register',
          'view': 'PCI 3'},
 'IMS0': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Enables Internal Bus Error'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_STAT',
                      'description': ['Enables Statistic Register ECC Error'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Enables Special Packet Filter Parity Error'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_PKBUF',
                      'description': ['Enables DMA Packet Buffer ECC Error'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_TXDS',
                      'description': ['Enables DMA Transmit Descriptor Buffer ECC Error'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_RXDS',
                      'description': ['Enables DMA Receive Descriptor Buffer ECC Error'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ["Reserved. Must be written as '0'"],
                      'range': (19, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'SRPD',
                      'description': ['Sets the mask for Small Receive Packet Detected and Transferred'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXD_LOW',
                      'description': ['Sets the mask for Transmit Descriptor Low Threshold Hit'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (14, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXT0',
                      'description': ['Sets the mask for Receiver Timer Interrupt'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXO',
                      'description': ['Sets the mask for Receiver Overrun. Set on receive data FIFO overrun'],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXDMT0',
                      'description': ['Sets the mask for Receive Descriptor Minimum Threshold hit'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ["Reserved. Must be written as '0'"],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXQE',
                      'description': ['Sets the mask for Transmit Queue Empty'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXDW',
                      'description': ['Sets the mask for Transmit Descriptor Written Back'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 208,
          'offset_end': (211, None),
          'offset_start': (208, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'IMS0',
          'reg_name': 'IMS0',
          'size': 32,
          'table_ref': '37-40',
          'title_desc': 'Interrupt 0 Mask Set/Read Register',
          'view': 'PCI 3'},
 'IMS1': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'WO',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Enables Internal Bus Error'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': 'RW'},
                     {'access': 'WO',
                      'acronym': 'ERR_STAT',
                      'description': ['Enables Statistic Register ECC Error'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': 'RW'},
                     {'access': 'WO',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Enables Special Packet Filter Parity Error'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': 'RW'},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': 'RV'},
                     {'access': 'WO',
                      'acronym': 'ERR_PKBUF',
                      'description': ['Enables DMA Packet Buffer ECC Error'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': 'RW'},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': 'RV'},
                     {'access': 'WO',
                      'acronym': 'ERR_TXDS',
                      'description': ['Enables DMA Transmit Descriptor Buffer ECC Error'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': 'RW'},
                     {'access': 'WO',
                      'acronym': 'ERR_RXDS',
                      'description': ['Enables DMA Receive Descriptor Buffer ECC Error'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': 'RW'},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (19, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'SRPD',
                      'description': ['Sets the mask for Small Receive Packet Detected and Transferred'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXD_LOW',
                      'description': ['Sets the mask for Transmit Descriptor Low Threshold Hit'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (14, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXT0',
                      'description': ['Sets the mask for Receiver Timer Interrupt'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXO',
                      'description': ['Sets the mask for Receiver Overrun. Set on receive data FIFO overrun'],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RXDMT0',
                      'description': ['Sets the mask for Receive Descriptor Minimum Threshold hit'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'Rsvd',
                      'description': ["Reserved. Must be written as '0'"],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXQE',
                      'description': ['Sets the mask for Transmit Queue Empty'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'TXDW',
                      'description': ['Sets the mask for Transmit Descriptor Written Back'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 2256,
          'offset_end': (2259, None),
          'offset_start': (2256, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'IMS1',
          'reg_name': 'IMS1',
          'size': 32,
          'table_ref': '37-44',
          'title_desc': 'Interrupt 1 Mask Set/Read Register',
          'view': 'PCI 3'},
 'IMS2': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 29),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_INTBUS',
                      'description': ['Enables Internal Bus Error'],
                      'range': (28, 28),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_STAT',
                      'description': ['Enables Statistic Register ECC Error'],
                      'range': (27, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_MCFSPF',
                      'description': ['Enables Special Packet Filter Parity Error'],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (25, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_PKBUF',
                      'description': ['Enables DMA Packet Buffer ECC Error'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_TXDS',
                      'description': ['Enables DMA Transmit Descriptor Buffer ECC Error'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ERR_RXDS',
                      'description': ['Enables DMA Receive Descriptor Buffer ECC Error'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (19, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 2288,
          'offset_end': (2291, None),
          'offset_start': (2288, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'IMS2',
          'reg_name': 'IMS2',
          'size': 32,
          'table_ref': '37-48',
          'title_desc': 'Error Interrupt Mask Set/Read Register',
          'view': 'PCI 3'},
 'INTBUS_ERR_STAT': {'bar': 'CSRBAR',
                     'bus_device_function': 'M:2:0',
                     'default': 0,
                     'description': None,
                     'fields': [{'access': 'RV',
                                 'acronym': 'Rsvd',
                                 'description': ['Reserved'],
                                 'range': (31, 13),
                                 'reset': 0,
                                 'sticky': ''},
                                {'access': 'RW',
                                 'acronym': 'INTBUS_ERR_H_DIS',
                                 'description': ['0 - Internal Bus errors will halt further GbE transmit/receive operation.',
                                                 '1 - Internal Bus errors will not halt further GbE operation. '],
                                 'range': (12, 12),
                                 'reset': 0,
                                 'sticky': ''},
                                {'access': 'RV',
                                 'acronym': 'Rsvd',
                                 'description': ['Reserved'],
                                 'range': (11, 6),
                                 'reset': 0,
                                 'sticky': ''},
                                {'access': 'RO',
                                 'acronym': 'Type',
                                 'description': ['Internal Bus Error Type:',
                                                 '? 00 = Unsupported internal bus transaction targeted at GbE',
                                                 '? 01 = Pull data error detected during a target write transaction',
                                                 '? 10 = GbE received a Internal Bus Data Error response while mastering a DMA transaction',
                                                 '? 11 = Master Pull data error occurred as a result of an internal memory error'],
                                 'range': (5, 4),
                                 'reset': 0,
                                 'sticky': ''},
                                {'access': 'RV',
                                 'acronym': 'Rsvd',
                                 'description': ['Reserved'],
                                 'range': (3, 2),
                                 'reset': 0,
                                 'sticky': ''},
                                {'access': 'RWC',
                                 'acronym': 'MERR',
                                 'description': ['Indicates whether one or more than one Internal Bus errors have occurred before INTBUS_ERR_STAT.CERR was cleared',
                                                 '0 = One Internal Bus Error1 = More than one Internal Bus Error'],
                                 'range': (1, 1),
                                 'reset': 0,
                                 'sticky': ''},
                                {'access': 'RWC',
                                 'acronym': 'CERR',
                                 'description': ['Internal Bus Error: Asserts when Internal Bus Error status and address registers are valid',
                                                 '0 = no error has been logged1 = Internal Bus Error status and address registers have logged an error',
                                                 'If error handling is enabled (INTBUS_ERR_H_DIS = 0) then this bit can only be cleared by a reset.'],
                                 'range': (0, 0),
                                 'reset': 0,
                                 'sticky': ''}],
                     'offset': 1296,
                     'offset_end': (1299, None),
                     'offset_start': (1296, None),
                     'power_well': None,
                     'recurring': None,
                     'reg_base_name': 'INTBUS_ERR_STAT',
                     'reg_name': 'INTBUS_ERR_STAT',
                     'size': 32,
                     'table_ref': '37-145',
                     'title_desc': 'Internal Bus Error Status Register',
                     'view': 'PCI 3'},
 'IPAV': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved. Should be set to 0.'],
                      'range': (31, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'V60',
                      'description': ['IPv6 Address 0 Valid'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved. Should be set to 0.'],
                      'range': (15, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'V43',
                      'description': ['IPv4 Address 3 Valid'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'V42',
                      'description': ['IPv4 Address 2 Valid'],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'V41',
                      'description': ['IPv4 Address 1 Valid'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'V40',
                      'description': ['IPv4 Address 0 Valid',
                                      "The initial value is loaded from the IP Address Valid bit of the EEPROM's Management Control Register"],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 22584,
          'offset_end': (22587, None),
          'offset_start': (22584, None),
          'power_well': None,
          'recurring': None,
          'reg_base_name': 'IPAV',
          'reg_name': 'IPAV',
          'size': 32,
          'table_ref': '37-134',
          'title_desc': 'IP Address Valid Register (0x05838; RW)',
          'view': 'PCI 3'},
 'IPV6_ADDR0BYTES_13_16': {'bar': 'CSRBAR',
                           'bus_device_function': 'M:2:0',
                           'default': u'XXXXXXXXh',
                           'description': None,
                           'fields': [{'access': 'RW',
                                       'acronym': 'IPV6DDR3',
                                       'description': ['IPV6 Address, bytes 13 - 16'],
                                       'range': (31, 0),
                                       'reset': None,
                                       'sticky': ''}],
                           'offset': 22668,
                           'offset_end': (22671, None),
                           'offset_start': (22668, None),
                           'power_well': None,
                           'recurring': None,
                           'reg_base_name': 'IPV6_ADDR0BYTES_13_16',
                           'reg_name': 'IPV6_ADDR0BYTES_13_16',
                           'size': 32,
                           'table_ref': '37-139',
                           'title_desc': 'IPv6 Address Table Register, Bytes 13 - 16',
                           'view': 'PCI 3'},
 'IPV6_ADDR0BYTES_1_4': {'bar': 'CSRBAR',
                         'bus_device_function': 'M:2:0',
                         'default': u'XXXXXXXXh',
                         'description': None,
                         'fields': [{'access': 'RW',
                                     'acronym': 'IPV6ADDR0',
                                     'description': ['IPV6 Address0, bytes 1 - 4'],
                                     'range': (31, 0),
                                     'reset': None,
                                     'sticky': ''}],
                         'offset': 22656,
                         'offset_end': (22659, None),
                         'offset_start': (22656, None),
                         'power_well': None,
                         'recurring': None,
                         'reg_base_name': 'IPV6_ADDR0BYTES_1_4',
                         'reg_name': 'IPV6_ADDR0BYTES_1_4',
                         'size': 32,
                         'table_ref': '37-136',
                         'title_desc': 'IPv6 Address Table Register (0x5880), Bytes 1 - 4',
                         'view': 'PCI 3'},
 'IPV6_ADDR0BYTES_5_8': {'bar': 'CSRBAR',
                         'bus_device_function': 'M:2:0',
                         'default': u'XXXXXXXXh',
                         'description': None,
                         'fields': [{'access': 'RW',
                                     'acronym': 'IPV6ADDR1',
                                     'description': ['IPV6 Address, bytes 5 - 8'],
                                     'range': (31, 0),
                                     'reset': None,
                                     'sticky': ''}],
                         'offset': 22660,
                         'offset_end': (22671, None),
                         'offset_start': (22660, None),
                         'power_well': None,
                         'recurring': None,
                         'reg_base_name': 'IPV6_ADDR0BYTES_5_8',
                         'reg_name': 'IPV6_ADDR0BYTES_5_8',
                         'size': 32,
                         'table_ref': '37-137',
                         'title_desc': 'IPv6 Address Table Register, Bytes 5 - 8',
                         'view': 'PCI 3'},
 'IPV6_ADDR0BYTES_9_12': {'bar': 'CSRBAR',
                          'bus_device_function': 'M:2:0',
                          'default': u'XXXXXXXXh',
                          'description': None,
                          'fields': [{'access': 'RW',
                                      'acronym': 'IPV6ADDR2',
                                      'description': ['IPV6 Address, bytes 9 - 12'],
                                      'range': (31, 0),
                                      'reset': None,
                                      'sticky': ''}],
                          'offset': 22664,
                          'offset_end': (22667, None),
                          'offset_start': (22664, None),
                          'power_well': None,
                          'recurring': None,
                          'reg_base_name': 'IPV6_ADDR0BYTES_9_12',
                          'reg_name': 'IPV6_ADDR0BYTES_9_12',
                          'size': 32,
                          'table_ref': '37-138',
                          'title_desc': 'IPv6 Address Table Register, Bytes 9 - 12',
                          'view': 'PCI 3'},
 'ITR0': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'MIII',
                      'description': ['Minimum Inter-interrupt Interval. ',
                                      '? In RGMII mode, the interval is specified in 256ns increments. ',
                                      '? In RMII mode, the interval is specified in 320ns increments',
                                      '? Zero disables interrupt throttling logic',
                                      '(The following example applies to RGMII mode)',
                                      "To independently validate configuration settings, software can use the following formula to convert the inter-interrupt interval value to the common 'interrupts/sec' performance metric:-9-interrupts/sec = (256 x 10 sec x inter-interrupt interval)1",
                                      'Inversely, inter-interrupt interval value can be calculated as:-9-inter-interrupt interval = (256 x 10 sec x interrupts/sec)1',
                                      'For example, if the interval is programmed to 500d, the network controller guarantees the CPU will not be interrupted by the network controller for 128 usec from the last interrupt. The maximum observable interrupt rate from the adapter should never exceed 7813 interrupts/sec.',
                                      'The optimal performance setting for this register is system/configuration specific. A initial suggested range is 651-5580 (28Bh - 15CCh), or, more generally, between 700 and 6000 interrupts per second.'],
                      'range': (15, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 196,
          'offset_end': (199, None),
          'offset_start': (196, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'ITR0',
          'reg_name': 'ITR0',
          'size': 32,
          'table_ref': '37-38',
          'title_desc': 'Interrupt 0 Throttling Register',
          'view': 'PCI 3'},
 'LATECOL': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RC',
                         'acronym': 'LATECOL',
                         'description': ['Number of packets with late collisions'],
                         'range': (31, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 16416,
             'offset_end': (16419, None),
             'offset_start': (16416, None),
             'power_well': 'Gbe1/2:',
             'recurring': None,
             'reg_base_name': 'LATECOL',
             'reg_name': 'LATECOL',
             'size': 32,
             'table_ref': '37-86',
             'title_desc': 'Late Collisions Count Register',
             'view': 'PCI 3'},
 'MCC': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RC',
                     'acronym': 'MCC',
                     'description': ['Number of times a successful transmit encountered multiple collisions.'],
                     'range': (31, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 16412,
         'offset_end': (16415, None),
         'offset_start': (16412, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'MCC',
         'reg_name': 'MCC',
         'size': 32,
         'table_ref': '37-85',
         'title_desc': 'Multiple Collision Count Register',
         'view': 'PCI 3'},
 'MEM_STS': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 8323072,
             'description': None,
             'fields': [{'access': 'RV',
                         'acronym': 'Rsvd',
                         'description': ['Reserved.'],
                         'range': (31, 23),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'ERR_FLEX_DIS',
                         'description': ['Flex Filter Parity Error Disable',
                                         '0: Error trapping enabled',
                                         '1: Error trapping disabled'],
                         'range': (22, 22),
                         'reset': 1,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'ERR_STAT_DIS',
                         'description': ['Statistics Register ECC Error Disable',
                                         '0: Error trapping enabled',
                                         '1: Error trapping disabled'],
                         'range': (21, 21),
                         'reset': 1,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'ERR_PKBUF_DIS',
                         'description': ['Packet Buffer ECC Error Disable',
                                         '0: Error trapping enabled',
                                         '1: Error trapping disabled'],
                         'range': (20, 20),
                         'reset': 1,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'ERR_TXDS_DIS',
                         'description': ['Transmit Descriptor ECC Error Disable',
                                         '0: Error trapping enabled',
                                         '1: Error trapping disabled'],
                         'range': (19, 19),
                         'reset': 1,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'ERR_RXDS_DIS',
                         'description': ['Receive Descriptor ECC Error Disable',
                                         '0: Error trapping enabled',
                                         '1: Error trapping disabled'],
                         'range': (18, 18),
                         'reset': 1,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'ERR_SPF_DIS',
                         'description': ['Special Packets Filter Parity Error Disable',
                                         '0: Error trapping enabled',
                                         '1: Error trapping disabled'],
                         'range': (17, 17),
                         'reset': 1,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'ERR_MF_DIS',
                         'description': ['Multicast Filter Parity Error Disable',
                                         '0: Error trapping enabled',
                                         '1: Error trapping disabled'],
                         'range': (16, 16),
                         'reset': 1,
                         'sticky': ''},
                        {'access': 'RV',
                         'acronym': 'Rsvd',
                         'description': ['Reserved'],
                         'range': (15, 13),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'MEM_ERRH_DIS',
                         'description': ['Memory Error Handling Disable: ',
                                         'Indicates, for the following error types, whether GbE Tx/Rx operation will be halted:',
                                         'ERR_STAT',
                                         'ERR_PKBUF',
                                         'ERR_RXDS',
                                         'ERR_TXDS',
                                         '0: Memory Errors will halt further GbE Tx/Rx operation and a soft-reset is required to restore operation',
                                         '1: Memory Errors will be logged, but will not halt further GbE Tx/Rx operation'],
                         'range': (12, 12),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RV',
                         'acronym': 'Rsvd',
                         'description': ['Reserved.'],
                         'range': (11, 7),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RO/RWC',
                         'acronym': 'ERR_FLEX',
                         'description': ['Flex filter Parity Error',
                                         '0: No error occurred',
                                         '1: Error occurred',
                                         'When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC.'],
                         'range': (6, 6),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RO/RWC',
                         'acronym': 'ERR_STAT',
                         'description': ['Statistics Register ECC Error',
                                         '0: No error occurred',
                                         '1: Error occurred',
                                         'When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC'],
                         'range': (5, 5),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RO/RWC',
                         'acronym': 'ERR_PKBUF',
                         'description': ['Packet Buffer ECC 2-bit Error',
                                         '0: No error occurred',
                                         '1: Error occurred',
                                         'When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC.'],
                         'range': (4, 4),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RO/RWC',
                         'acronym': 'ERR_TXDS',
                         'description': ['Transmit Descriptor ECC 2-bit Error',
                                         '0: No error occurred',
                                         '1: Error occurred',
                                         'When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC.'],
                         'range': (3, 3),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RO/RWC',
                         'acronym': 'ERR_RXDS',
                         'description': ['Receive Descriptor ECC 2-bit Error',
                                         '0: No error occurred',
                                         '1: Error occurred',
                                         'When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC.'],
                         'range': (2, 2),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RO/RWC',
                         'acronym': 'ERR_SPF',
                         'description': ['Special Packets Filter Parity Error',
                                         '0: No error occurred',
                                         '1: Error occurred',
                                         'When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC'],
                         'range': (1, 1),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RO/RWC',
                         'acronym': 'ERR_MF',
                         'description': ['Multicast Filter Parity Error',
                                         '0: No error occurred',
                                         '1: Error occurred',
                                         'When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC'],
                         'range': (0, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 2308,
             'offset_end': (2311, None),
             'offset_start': (2308, None),
             'power_well': None,
             'recurring': None,
             'reg_base_name': 'MEM_STS',
             'reg_name': 'MEM_STS',
             'size': 32,
             'table_ref': '37-147',
             'title_desc': 'Memory Error Status Register',
             'view': 'PCI 3'},
 'MEM_TST': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RV',
                         'acronym': 'Rsvd',
                         'description': ['Reserved'],
                         'range': (31, 19),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'Select',
                         'description': ['Selects the memory where the error mask is applied:',
                                         '000 : None - no errors injected',
                                         '001 : Statistics Registers',
                                         '010 : Multicast Filter Memory',
                                         '011 : Special Packet Filter Memory',
                                         '100 : TX Descriptor Buffer',
                                         '101 : RX Descriptor Buffer',
                                         '110 : Packet Buffer',
                                         '111 : Flexible Filter Memory'],
                         'range': (18, 16),
                         'reset': 0,
                         'sticky': ''},
                        {'access': 'RW',
                         'acronym': 'Mask',
                         'description': ['ECC/Parity check bit XOR mask',
                                         'The Valid Mask bits are selected according to the Select field, as follows:',
                                         '001 : 15:8 Reserved; 7:0 ECC Mask',
                                         '010 : 15:4 Reserved; 3:0 Parity bit Mask',
                                         '011 : 15:4 Reserved; 3:0 Parity bit Mask',
                                         '100 : 15:0 ECC Mask',
                                         '101 : 15:0 ECC Mask',
                                         '110 : 15:0 ECC Mask',
                                         '111 : 15:0 Reserved; 3:0 Parity bit Mask'],
                         'range': (15, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 2304,
             'offset_end': (2307, None),
             'offset_start': (2304, None),
             'power_well': None,
             'recurring': None,
             'reg_base_name': 'MEM_TST',
             'reg_name': 'MEM_TST',
             'size': 32,
             'table_ref': '37-146',
             'title_desc': 'Memory Error Test Register',
             'view': 'PCI 3'},
 'MPC': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RC',
                     'acronym': 'MPC',
                     'description': ['Missed Packets Count'],
                     'range': (31, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 16400,
         'offset_end': (16403, None),
         'offset_start': (16400, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'MPC',
         'reg_name': 'MPC',
         'size': 32,
         'table_ref': '37-82',
         'title_desc': 'Missed Packet Count Register',
         'view': 'PCI 3'},
 'MPRC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'MPRC',
                      'description': ['Number of multicast packets received'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16508,
          'offset_end': (16511, None),
          'offset_start': (16508, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'MPRC',
          'reg_name': 'MPRC',
          'size': 32,
          'table_ref': '37-105',
          'title_desc': 'Multicast Packets Received Count Register',
          'view': 'PCI 3'},
 'MPTC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'MPTC',
                      'description': ['Number of multicast packets transmitted'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16624,
          'offset_end': (16627, None),
          'offset_start': (16624, None),
          'power_well': None,
          'recurring': None,
          'reg_base_name': 'MPTC',
          'reg_name': 'MPTC',
          'size': 32,
          'table_ref': '37-127',
          'title_desc': 'Multicast Packets Transmitted Count Register',
          'view': 'PCI 3'},
 'MTA[0-127]': {'bar': 'CSRBAR',
                'bus_device_function': 'M:2:0',
                'default': u'XXXX_XXXXh',
                'description': None,
                'fields': [{'access': 'RW',
                            'acronym': 'Vector',
                            'description': ['32b vector of multicast address filter table information.'],
                            'range': (31, 0),
                            'reset': None,
                            'sticky': ''}],
                'offset': 20992,
                'offset_end': (20995, 4),
                'offset_start': (20992, 4),
                'power_well': 'Gbe1/2:',
                'recurring': 128,
                'reg_base_name': 'MTA',
                'reg_name': 'MTA[0-127]',
                'size': 32,
                'table_ref': '37-63',
                'title_desc': '128 Multicast Table Array Registers',
                'view': 'PCI 3'},
 'PBA': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 1048624,
         'description': None,
         'fields': [{'access': 'RO',
                     'acronym': 'RSVD',
                     'description': ['Reserved'],
                     'range': (31, 22),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RO',
                     'acronym': 'TXA',
                     'description': ['Transmit Packet Buffer Allocation in K bytes. PBA.TXA is read only and calculated based on PBA.RXA.',
                                     '0010h =>16KB'],
                     'range': (21, 16),
                     'reset': 16,
                     'sticky': ''},
                    {'access': 'RO',
                     'acronym': 'RSVD',
                     'description': ['Reserved'],
                     'range': (15, 6),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'RXA',
                     'description': ['Receive Packet Buffer Allocation in K bytes. PBA.RXA legal values must be 8K aligned.',
                                     'Valid values are (decimal) 8, 16, 24, 32, 40, 48, 56.',
                                     '0030h => 48KBh'],
                     'range': (5, 0),
                     'reset': 48,
                     'sticky': ''}],
         'offset': 4096,
         'offset_end': (4099, None),
         'offset_start': (4096, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'PBA',
         'reg_name': 'PBA',
         'size': 32,
         'table_ref': '37-36',
         'title_desc': 'Packet Buffer Allocation Register',
         'view': 'PCI 3'},
 'PRC1023': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RC',
                         'acronym': 'PRC1023',
                         'description': ['Number of good packets received, (512-1023) bytes in length'],
                         'range': (31, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 16492,
             'offset_end': (16495, None),
             'offset_start': (16492, None),
             'power_well': 'Gbe1/2:',
             'recurring': None,
             'reg_base_name': 'PRC1023',
             'reg_name': 'PRC1023',
             'size': 32,
             'table_ref': '37-101',
             'title_desc': 'Good Packets Received Count (512-1023 Bytes) Register',
             'view': 'PCI 3'},
 'PRC127': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RC',
                        'acronym': 'PRC127',
                        'description': ['Number of good packets received, (65-127) bytes in length'],
                        'range': (31, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 16480,
            'offset_end': (16483, None),
            'offset_start': (16480, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'PRC127',
            'reg_name': 'PRC127',
            'size': 32,
            'table_ref': '37-98',
            'title_desc': 'Good Packets Received Count (65-127 Bytes) Register',
            'view': 'PCI 3'},
 'PRC1522': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RC',
                         'acronym': 'PRC1522',
                         'description': ['Number of good packets received, (1024-Max) bytes in length'],
                         'range': (31, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 16496,
             'offset_end': (16499, None),
             'offset_start': (16496, None),
             'power_well': 'Gbe1/2:',
             'recurring': None,
             'reg_base_name': 'PRC1522',
             'reg_name': 'PRC1522',
             'size': 32,
             'table_ref': '37-102',
             'title_desc': 'Good Packets Received Count (1024 to Max Bytes) Register',
             'view': 'PCI 3'},
 'PRC255': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RC',
                        'acronym': 'PRC255',
                        'description': ['Number of good packets received, (128-255) bytes in length.'],
                        'range': (31, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 16484,
            'offset_end': (16487, None),
            'offset_start': (16484, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'PRC255',
            'reg_name': 'PRC255',
            'size': 32,
            'table_ref': '37-99',
            'title_desc': 'Good Packets Received Count (128-255 Bytes) Register',
            'view': 'PCI 3'},
 'PRC511': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RC',
                        'acronym': 'PRC511',
                        'description': ['Number of good packets received, (256-511) bytes in length'],
                        'range': (31, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 16488,
            'offset_end': (16491, None),
            'offset_start': (16488, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'PRC511',
            'reg_name': 'PRC511',
            'size': 32,
            'table_ref': '37-100',
            'title_desc': 'Good Packets Received Count (256-511 Bytes) Register',
            'view': 'PCI 3'},
 'PRC64': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RC',
                       'acronym': 'PRC64',
                       'description': ['Number of good packets received exactly 64 bytes in length.'],
                       'range': (31, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 16476,
           'offset_end': (16479, None),
           'offset_start': (16476, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'PRC64',
           'reg_name': 'PRC64',
           'size': 32,
           'table_ref': '37-97',
           'title_desc': 'Good Packets Received Count (64 Bytes) Register',
           'view': 'PCI 3'},
 'PTC1023': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RC',
                         'acronym': 'PTC1023',
                         'description': ['Number of packets transmitted that are 512-1023 bytes in length'],
                         'range': (31, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 16616,
             'offset_end': (16619, None),
             'offset_start': (16616, None),
             'power_well': None,
             'recurring': None,
             'reg_base_name': 'PTC1023',
             'reg_name': 'PTC1023',
             'size': 32,
             'table_ref': '37-125',
             'title_desc': 'Packets Transmitted Count (512-1023 Bytes) Register',
             'view': 'PCI 3'},
 'PTC1522': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RC',
                         'acronym': 'PTC1522',
                         'description': ['Number of packets transmitted that are 1024 or more bytes in length'],
                         'range': (31, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 16620,
             'offset_end': (16623, None),
             'offset_start': (16620, None),
             'power_well': None,
             'recurring': None,
             'reg_base_name': 'PTC1522',
             'reg_name': 'PTC1522',
             'size': 32,
             'table_ref': '37-126',
             'title_desc': 'Packets Transmitted Count (1024-1522 Bytes) Register',
             'view': 'PCI 3'},
 'PTC255': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RC',
                        'acronym': 'PTC255',
                        'description': ['Number of packets transmitted that are 128-255 bytes in length'],
                        'range': (31, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 16608,
            'offset_end': (16611, None),
            'offset_start': (16608, None),
            'power_well': None,
            'recurring': None,
            'reg_base_name': 'PTC255',
            'reg_name': 'PTC255',
            'size': 32,
            'table_ref': '37-123',
            'title_desc': 'Packets Transmitted Count (128-255 Bytes) Register',
            'view': 'PCI 3'},
 'PTC511': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RC',
                        'acronym': 'PTC511',
                        'description': ['Number of packets transmitted that are 256-511 bytes in length'],
                        'range': (31, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 16612,
            'offset_end': (16615, None),
            'offset_start': (16612, None),
            'power_well': None,
            'recurring': None,
            'reg_base_name': 'PTC511',
            'reg_name': 'PTC511',
            'size': 32,
            'table_ref': '37-124',
            'title_desc': 'Packets Transmitted Count (256-511 Bytes) Register',
            'view': 'PCI 3'},
 'PTC64': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RC',
                       'acronym': 'PTC64',
                       'description': ['Number of all packets transmitted that are 64 bytes in length'],
                       'range': (31, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 16600,
           'offset_end': (16603, None),
           'offset_start': (16600, None),
           'power_well': None,
           'recurring': None,
           'reg_base_name': 'PTC64',
           'reg_name': 'PTC64',
           'size': 32,
           'table_ref': '37-122',
           'title_desc': 'Packets Transmitted Count (64 Bytes) Register',
           'view': 'PCI 3'},
 'RADV': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RADT',
                      'description': ['Receive Absolute Delay Timer ',
                                      'Receive Absolute delay timer measured in increments of',
                                      'RMII: 1.28 microseconds',
                                      'RGMII: 1.024 microseconds. ',
                                      '(0b =disabled)',
                                      'If the packet delay timer is used to coalesce receive interrupts, the Ethernet controller ensures that when receive traffic abates, an interrupt is generated within a specified interval of no receives. During times when receive traffic is continuous, it may be necessary to ensure that no receive remains unnoticed for too long an interval. This register can be used to ENSURE that a receive interrupt occurs at some predefined interval after the first packet is received. When this timer is enabled, a separate absolute countdown timer is initiated upon successfully receiving each packet to system memory. When this absolute timer expires, pending receive descriptor writebacks are flushed and a receive timer interrupt is generated. ',
                                      'Setting this register to 0b disables the absolute timer mechanism (the RDTR register should be used with a value of 0b to cause immediate interrupts for all receive packets).',
                                      'Receive interrupts due to a Receive Packet Timer (RDTR) expiration cancels a pending RADV interrupt. If enabled, the RADV countdown timer is reloaded but halted, so as to avoid generation of a spurious second interrupt after the RDTR has been noted.'],
                      'range': (15, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 10284,
          'offset_end': (10287, None),
          'offset_start': (10284, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'RADV',
          'reg_name': 'RADV',
          'size': 32,
          'table_ref': '37-60',
          'title_desc': 'Receive Interrupt Absolute Delay Timer Register',
          'view': 'PCI 3'},
 'RAH[0-15]': {'bar': 'CSRBAR',
               'bus_device_function': 'M:2:0',
               'default': u'000XXXXXh',
               'description': None,
               'fields': [{'access': 'RW',
                           'acronym': 'AV',
                           'description': ['Address valid. This bit determines whether this address is compared against the incoming packet. Cleared after software reset or Unit Reset.',
                                           '0 = No match on this address field ',
                                           '1 = Match on this address field'],
                           'range': (31, 31),
                           'reset': 0,
                           'sticky': ''},
                          {'access': 'RV',
                           'acronym': 'Rsvd',
                           'description': ['Reserved'],
                           'range': (30, 18),
                           'reset': 0,
                           'sticky': ''},
                          {'access': 'RW',
                           'acronym': 'ASEL',
                           'description': ['Address Select. Selects how the address is to be used when performing special filtering on receive packets.',
                                           '? 00: Destination address (must be set to this in normal mode)',
                                           '? 01: Source address',
                                           '? 10: Reserved',
                                           '? 11: Reserved'],
                           'range': (17, 16),
                           'reset': None,
                           'sticky': ''},
                          {'access': 'RW',
                           'acronym': 'RAH',
                           'description': ['Receive Address High. The upper 16 bits of the 48 bit Ethernet address.'],
                           'range': (15, 0),
                           'reset': None,
                           'sticky': ''}],
               'offset': 21508,
               'offset_end': (21511, 8),
               'offset_start': (21508, 8),
               'power_well': None,
               'recurring': 16,
               'reg_base_name': 'RAH',
               'reg_name': 'RAH[0-15]',
               'size': 32,
               'table_ref': '37-65',
               'title_desc': 'Receive Address High Register',
               'view': 'PCI 3'},
 'RAL[0-15]': {'bar': 'CSRBAR',
               'bus_device_function': 'M:2:0',
               'default': u'XXXXXXXXh',
               'description': None,
               'fields': [{'access': 'RW',
                           'acronym': 'RAL',
                           'description': ['Receive Address Low. The lower 32 bits of the 48 bit Ethernet address.'],
                           'range': (31, 0),
                           'reset': None,
                           'sticky': ''}],
               'offset': 21504,
               'offset_end': (21507, 8),
               'offset_start': (21504, 8),
               'power_well': None,
               'recurring': 16,
               'reg_base_name': 'RAL',
               'reg_name': 'RAL[0-15]',
               'size': 32,
               'table_ref': '37-64',
               'title_desc': 'Receive Address Low Register',
               'view': 'PCI 3'},
 'RCTL': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 27),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'SECRC',
                      'description': ["Strip Ethernet CRC. This bit controls whether the hardware strips the Ethernet CRC from the received packet. This stripping occurs prior to any checksum calculations. The stripped CRC is not DMA'd to host memory and is not included in the length reported in the descriptor."],
                      'range': (26, 26),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'BSEX',
                      'description': ['Buffer Size Extension. Combined with RCTL.BSIZE to program the receive buffer size. Control of receive buffer size permits software to trade-off descriptor performance versus required storage space. Buffers that are 2048 bytes require only one descriptor per receive packet maximizing descriptor efficiency. Buffers that are 256 bytes maximize memory efficiency at a cost of multiple descriptors for packets longer than 256 bytes.',
                                      'RCTL.BSEX = 0 / RCTL.BSIZE = 00 -> Receive Buffer Size = 2048B',
                                      'RCTL.BSEX = 0 / RCTL.BSIZE = 01 -> Receive Buffer Size = 1024B',
                                      'RCTL.BSEX = 0 / RCTL.BSIZE = 10 -> Receive Buffer Size = 512B',
                                      'RCTL.BSEX = 0 / RCTL.BSIZE = 11 -> Receive Buffer Size = 256B',
                                      'RCTL.BSEX = 1 / RCTL.BSIZE = 00 -> Reserved',
                                      'RCTL.BSEX = 1 / RCTL.BSIZE = 01 -> Receive Buffer Size = 16384B',
                                      'RCTL.BSEX = 1 / RCTL.BSIZE = 10 -> Receive Buffer Size = 8192B',
                                      'RCTL.BSEX = 1 / RCTL.BSIZE = 11 -> Receive Buffer Size = 4096B'],
                      'range': (25, 25),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (24, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'PMCF',
                      'description': ['Pass MAC Control Frames. This bit controls the DMA function of MAC control frames (other than flow control). A MAC control frame in this context must be addressed to either the MAC control frame multicast address or the station address, it must match the type field and must NOT match the PAUSE opcode of 0x0001.',
                                      '0 = Do not pass MAC control frames1 = Pass any MAC control frame (type field value of 0x8808) that does not contain the pause opcode of 0x0001.'],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'DPF',
                      'description': ["Discard Pause Frames. This bit controls the DMA function of flow control packets addressed to the station address (RAH/RAL[0]). If a packet is a valid flow control packet and is addressed to the station address it will not be DMA'd to host memory if RCTL.DPF=1.",
                                      '0 = Incoming frames are subject to filter comparison1 = Incoming valid PAUSE frames discarded even if they match any of the filter registers'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (21, 21),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'CFI',
                      'description': ['Canonical Form Indicator. One of the three bits that control the VLAN filter table. This bit may be compared to the CFI bit found in the 802.1q packet as part of the acceptance criteria. RCTL.CFIEN and RCTL.VFE determine whether or not this comparison takes place.'],
                      'range': (20, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'CFIEN',
                      'description': ['Canonical Form Indicator Enable. One of the three bits that control the VLAN filter table. This bit enables using the CFI bit found in the 802.1q packet as part of the acceptance criteria.',
                                      'The next two are used to decide whether the CFI bit found in the.1Q packet should be used as part of the acceptance criteria.',
                                      '0 = CFI Disabled: bit not compared to determine packet acceptance1 = CFI from packet must match CFI field for acceptance of 802.1q packet'],
                      'range': (19, 19),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'VFE',
                      'description': ['VLAN Filter Enable. One of the three bits that control the VLAN filter table. This bit determines whether the table participates in the packet acceptance criteria.',
                                      '0 = Disabled, filter table does not decide packet acceptance1 = Enabled, filter table decides acceptance of 802.1q packets'],
                      'range': (18, 18),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'BSIZE',
                      'description': ['Receive Buffer Size. Combined with RCTL.BSEX to program the receive buffer size. Control of receive buffer size permits software to trade-off descriptor performance versus required storage space. Buffers that are 2048 bytes require only one descriptor per receive packet maximizing descriptor efficiency. Buffers that are 256 bytes maximize memory efficiency at a cost of multiple descriptors for packets longer than 256 bytes.',
                                      'RCTL.BSEX = 0 / RCTL.BSIZE = 00 -> Receive Buffer Size = 2048B',
                                      'RCTL.BSEX = 0 / RCTL.BSIZE = 01 -> Receive Buffer Size = 1024B',
                                      'RCTL.BSEX = 0 / RCTL.BSIZE = 10 -> Receive Buffer Size = 512B',
                                      'RCTL.BSEX = 0 / RCTL.BSIZE = 11 -> Receive Buffer Size = 256B',
                                      'RCTL.BSEX = 1 / RCTL.BSIZE = 00 -> Reserved',
                                      'RCTL.BSEX = 1 / RCTL.BSIZE = 01 -> Receive Buffer Size = 16384B',
                                      'RCTL.BSEX = 1 / RCTL.BSIZE = 10 -> Receive Buffer Size = 8192B',
                                      'RCTL.BSEX = 1 / RCTL.BSIZE = 11 -> Receive Buffer Size = 4096B'],
                      'range': (17, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'BAM',
                      'description': ['Broadcast Accept Mode.',
                                      '0 = Ignore broadcast (unless it matches exact or imperfect filters)1 = Accept broadcast packets'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (14, 14),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'MO',
                      'description': ['Multicast Offset. This determines which bits of the incoming multicast address are used in looking up the bit vector.',
                                      '? 00 = [47:36]',
                                      '? 01 = [46:35]',
                                      '? 10 = [45:34]',
                                      '? 11 = [43:32]'],
                      'range': (13, 12),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (11, 10),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RDMTS',
                      'description': ['Receive Descriptor Minimum Threshold Size. These bits determines the threshold value for free receive descriptors. The corresponding interrupt is set whenever the fractional number of free descriptors becomes equal to RCTL.RDMTS. Refer to "RDLEN - Receive Descriptor Length Register" on page 1481 for further information.',
                                      '? 00 = 1/2',
                                      '? 01 = 1/4',
                                      '? 10 = 1/8',
                                      '? 11 = Reserved'],
                      'range': (9, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'LBM',
                      'description': ['Loopback mode. These bits enable the loopback function.When using a PHY, a value of 00 should be used and the PHY is configured for loopback through the MDIO interface.',
                                      '? 00 = Normal operation (or PHY loopback in GMII/MII mode) ',
                                      '? 01 = MAC Loopback enable (only supported for GMII/MII mode)',
                                      '? 10 = Reserved',
                                      '? 11 = Reserved',
                                      '? 11 = ReservedNote:PHY devices require programming for loopback operation using MDIO accesses.Note:The GbE must be configured for Full-Duplex operation if Mac Loopback mode is enabled.'],
                      'range': (7, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'LPE',
                      'description': ['Long packet enable. This bit controls whether long packet reception is permitted.',
                                      '0 = Disabled, hardware discards packets longer than 1522B1 = Enabled, 16384B is the maximum packet size that the GbE can receive'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'MPE',
                      'description': ['Multicast promiscuous enable.',
                                      '0 = Disabled1 = Enabled'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'UPE',
                      'description': ['Unicast promiscuous enable.',
                                      '0 = Disabled1 = Enabled'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'SBP',
                      'description': ['Store bad packets.',
                                      '0 = Disabled1 = Enabled'],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'EN',
                      'description': ['Receiver Enable.',
                                      '0 = All incoming packets are immediately dropped and are not stored in the receive FIFO. If a packet is already in-progress when disabled it will be finished.1 = Incoming packet reception is enabled.'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 256,
          'offset_end': (259, None),
          'offset_start': (256, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'RCTL',
          'reg_name': 'RCTL',
          'size': 32,
          'table_ref': '37-50',
          'title_desc': 'Receive Control Register',
          'view': 'PCI 3'},
 'RDBAH': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': u'XXXXXXXXh',
           'description': None,
           'fields': [{'access': 'RW',
                       'acronym': 'RDBAH',
                       'description': ['Receive Descriptor Base Address.Note:RDBAH[31:0] must be set to 0.'],
                       'range': (31, 0),
                       'reset': None,
                       'sticky': ''}],
           'offset': 10244,
           'offset_end': (10247, None),
           'offset_start': (10244, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'RDBAH',
           'reg_name': 'RDBAH',
           'size': 32,
           'table_ref': '37-54',
           'title_desc': 'Receive Descriptor Base Address High Register',
           'view': 'PCI 3'},
 'RDBAL': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': u'XXXXXXX0h',
           'description': None,
           'fields': [{'access': 'RW',
                       'acronym': 'RDBAL',
                       'description': ['Receive Descriptor Base Address Low'],
                       'range': (31, 4),
                       'reset': None,
                       'sticky': ''},
                      {'access': 'RV',
                       'acronym': '0',
                       'description': ['Writes are ignored, reads return 0.'],
                       'range': (3, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 10240,
           'offset_end': (10243, None),
           'offset_start': (10240, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'RDBAL',
           'reg_name': 'RDBAL',
           'size': 32,
           'table_ref': '37-53',
           'title_desc': 'Receive Descriptor Base Address Low Register',
           'view': 'PCI 3'},
 'RDH': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RV',
                     'acronym': 'Rsvd',
                     'description': ['Reserved'],
                     'range': (31, 16),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'RDH',
                     'description': ['Receive Descriptor Head'],
                     'range': (15, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 10256,
         'offset_end': (10259, None),
         'offset_start': (10256, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'RDH',
         'reg_name': 'RDH',
         'size': 32,
         'table_ref': '37-56',
         'title_desc': 'Receive Descriptor Head Register',
         'view': 'PCI 3'},
 'RDLEN': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RV',
                       'acronym': 'Rsvd',
                       'description': ['Reserved'],
                       'range': (31, 20),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RW',
                       'acronym': 'LEN',
                       'description': ['Descriptor Length'],
                       'range': (19, 7),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RV',
                       'acronym': '0',
                       'description': ['Writes are ignored, reads return 0.'],
                       'range': (6, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 10248,
           'offset_end': (10251, None),
           'offset_start': (10248, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'RDLEN',
           'reg_name': 'RDLEN',
           'size': 32,
           'table_ref': '37-55',
           'title_desc': 'Receive Descriptor Length Register',
           'view': 'PCI 3'},
 'RDT': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RV',
                     'acronym': 'Rsvd',
                     'description': ['Reserved'],
                     'range': (31, 16),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'RDT',
                     'description': ['Receive Descriptor Tail'],
                     'range': (15, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 10264,
         'offset_end': (10267, None),
         'offset_start': (10264, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'RDT',
         'reg_name': 'RDT',
         'size': 32,
         'table_ref': '37-57',
         'title_desc': 'Receive Descriptor Tail Register',
         'view': 'PCI 3'},
 'RDTR': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'WO',
                      'acronym': 'FPD',
                      'description': ['Flush Partial Descriptor. Writing this bit with 1 initiates an immediate expiration of the timer, causing a writeback of any consumed receive descriptors pending writeback, and results in a receive timer interrupt in the ICR register. This bit is self clearing and always reads 0.'],
                      'range': (31, 31),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (30, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RPDT',
                      'description': ['Receive Packet Delay Timer ',
                                      'Timer increments are ',
                                      'RMII: 1.28 microseconds',
                                      'RGMII: 1.024 microseconds. ',
                                      'See register description above'],
                      'range': (15, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 10272,
          'offset_end': (10275, None),
          'offset_start': (10272, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'RDTR',
          'reg_name': 'RDTR',
          'size': 32,
          'table_ref': '37-58',
          'title_desc': 'RX Interrupt Delay Timer (Packet Timer) Register',
          'view': 'PCI 3'},
 'RFC': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RC',
                     'acronym': 'RFC',
                     'description': ['Number of receive fragment errors'],
                     'range': (31, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 16552,
         'offset_end': (16555, None),
         'offset_start': (16552, None),
         'power_well': None,
         'recurring': None,
         'reg_base_name': 'RFC',
         'reg_name': 'RFC',
         'size': 32,
         'table_ref': '37-113',
         'title_desc': 'Receive Fragment Count Register',
         'view': 'PCI 3'},
 'RJC': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RC',
                     'acronym': 'RJC',
                     'description': ['Number of receive jabber errors'],
                     'range': (31, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 16560,
         'offset_end': (16563, None),
         'offset_start': (16560, None),
         'power_well': None,
         'recurring': None,
         'reg_base_name': 'RJC',
         'reg_name': 'RJC',
         'size': 32,
         'table_ref': '37-115',
         'title_desc': 'Receive Jabber Count Register',
         'view': 'PCI 3'},
 'RLEC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'RLEC',
                      'description': ['Number of packets with receive length errors.'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16448,
          'offset_end': (16451, None),
          'offset_start': (16448, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'RLEC',
          'reg_name': 'RLEC',
          'size': 32,
          'table_ref': '37-91',
          'title_desc': 'Receive Length Error Count Register',
          'view': 'PCI 3'},
 'RNBC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'RNBC',
                      'description': ['Number of receive no buffer conditions'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16544,
          'offset_end': (16547, None),
          'offset_start': (16544, None),
          'power_well': None,
          'recurring': None,
          'reg_base_name': 'RNBC',
          'reg_name': 'RNBC',
          'size': 32,
          'table_ref': '37-111',
          'title_desc': 'Receive No Buffers Count Register',
          'view': 'PCI 3'},
 'ROC': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RC',
                     'acronym': 'ROC',
                     'description': ['Number of receive oversize errors'],
                     'range': (31, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 16556,
         'offset_end': (16559, None),
         'offset_start': (16556, None),
         'power_well': None,
         'recurring': None,
         'reg_base_name': 'ROC',
         'reg_name': 'ROC',
         'size': 32,
         'table_ref': '37-114',
         'title_desc': 'Receive Oversize Count Register',
         'view': 'PCI 3'},
 'RSRPD': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RV',
                       'acronym': 'Rsvd',
                       'description': ['Reserved'],
                       'range': (31, 12),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RW',
                       'acronym': 'SIZE',
                       'description': ['Any packet received that is <= SIZE will assert an interrupt condition (ICR.SRPD). This field is specified in bytes and includes the headers and the CRC but not the VLAN header in the size calculation.'],
                       'range': (11, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 11264,
           'offset_end': (11267, None),
           'offset_start': (11264, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'RSRPD',
           'reg_name': 'RSRPD',
           'size': 32,
           'table_ref': '37-61',
           'title_desc': 'Receive Small Packet Detect Interrupt Register',
           'view': 'PCI 3'},
 'RUC': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RC',
                     'acronym': 'RUC',
                     'description': ['Number of receive undersize errors'],
                     'range': (31, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 16548,
         'offset_end': (16551, None),
         'offset_start': (16548, None),
         'power_well': None,
         'recurring': None,
         'reg_base_name': 'RUC',
         'reg_name': 'RUC',
         'size': 32,
         'table_ref': '37-112',
         'title_desc': 'Receive Undersize Count Register',
         'view': 'PCI 3'},
 'RXCSUM': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (31, 10),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'TUOFL',
                        'description': ['TCP/UDP Checksum Off load Enable. This bit is used to enable the TCP/UDP Checksum off-loading feature.',
                                        '0 = TCP/UDP Checksum Off load Disabled1 = Hardware will calculate the TCP or UDP checksum and indicate a pass/fail indication to software via the TCP/UDP Checksum Error bit (TCPE).'],
                        'range': (9, 9),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'IPOFL',
                        'description': ['IP Checksum Off load Enable. This bit is used to enable the IP Checksum off-loading feature.',
                                        '0 = IP Checksum Off load Disabled1 = Hardware will calculate the IP checksum and indicate a pass/fail indication to software via the IP Checksum Error bit (IPE) in the ERROR field of the receive descriptor.'],
                        'range': (8, 8),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'PCSS',
                        'description': ["Packet Checksum Start. This field controls the starting byte for the Packet Checksum calculation. The Packet Checksum is the one's complement over the receive packet, starting from the byte indicated by PCSS (0 corresponds to the first byte of the packet), after stripping.",
                                        'For example, for an Ethernet II frame encapsulated as an 802.3ac VLAN packet and with PCSS set to 14, the packet checksum would include the entire encapsulated frame, excluding the 14-byte Ethernet header (DA, SA, Type and Length) and the 4-byte VLAN tag. The Packet Checksum will not include the Ethernet CRC if the RCTL.SECRC bit is set. Software must make the required offsetting computation (to back out the bytes that should not have been included and to include the pseudo-header) prior to comparing the Packet Checksum against the TCP checksum stored in the packet. '],
                        'range': (7, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 20480,
            'offset_end': (20483, None),
            'offset_start': (20480, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'RXCSUM',
            'reg_name': 'RXCSUM',
            'size': 32,
            'table_ref': '37-62',
            'title_desc': 'Receive Checksum Control Register',
            'view': 'PCI 3'},
 'RXDCTL': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 65536,
            'description': None,
            'fields': [{'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (31, 25),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'GRAN',
                        'description': ['Granularity of the thresholds in this register.',
                                        '0 = Threshold values are in units of Cache Lines, thresholds specified must not be greater than 31 descriptors (496B) or 15 32B cache lines.1 = Threshold values are in units of Descriptors (16B each)'],
                        'range': (24, 24),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (23, 22),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'WTHRESH',
                        'description': ["Write-back Threshold. This field controls the write-back of processed receive descriptors. This threshold refers to the number of receive descriptors in the GbE hardware buffer which are ready to be written back to host memory. In the absence of external events (explicit flushes), the write-back will occur only after more than WTHRESH descriptors are available for write-back.Note:Since the default value for this field is 1, the descriptors are normally written back as soon as one cache line is available. This field must contain a non-zero value to take advantage of the write-back bursting capabilities of the EP80579's GbE."],
                        'range': (21, 16),
                        'reset': 1,
                        'sticky': ''},
                       {'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (15, 14),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'HTHRESH',
                        'description': ['Host Threshold. This field is used to control the fetching of descriptors from host memory. This threshold refers to the number of valid, unprocessed receive descriptors that must exist in host memory before they will be fetched.'],
                        'range': (13, 8),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (7, 6),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'PTHRESH',
                        'description': ['Prefetch Threshold. This field is used to control when a prefetch of descriptors will be considered. This threshold refers to the number of valid, unprocessed receive descriptors the chip has in its GbE hardware buffer. If this number drops below PTHRESH, the algorithm will consider pre-fetching descriptors from host memory. This fetch will not happen however unless there are at least HTHRESH valid descriptors in host memory to fetch.'],
                        'range': (5, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 10280,
            'offset_end': (10283, None),
            'offset_start': (10280, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'RXDCTL',
            'reg_name': 'RXDCTL',
            'size': 32,
            'table_ref': '37-59',
            'title_desc': 'Receive Descriptor Control Register',
            'view': 'PCI 3'},
 'RXERRC': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RC',
                        'acronym': 'RXERRC',
                        'description': ['RX Error Count'],
                        'range': (31, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 16396,
            'offset_end': (16399, None),
            'offset_start': (16396, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'RXERRC',
            'reg_name': 'RXERRC',
            'size': 32,
            'table_ref': '37-81',
            'title_desc': 'Receive Error Count Register',
            'view': 'PCI 3'},
 'SCC': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RC',
                     'acronym': 'SCC',
                     'description': ['Number of times a transmit encountered a single collision.'],
                     'range': (31, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 16404,
         'offset_end': (16407, None),
         'offset_start': (16404, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'SCC',
         'reg_name': 'SCC',
         'size': 32,
         'table_ref': '37-83',
         'title_desc': 'Single Collision Count Register',
         'view': 'PCI 3'},
 'STATUS': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': u'0000XXXXh',
            'description': None,
            'fields': [{'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (31, 10),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RO',
                        'acronym': 'Reserved',
                        'description': ['Reserved'],
                        'range': (9, 8),
                        'reset': None,
                        'sticky': ''},
                       {'access': 'RO',
                        'acronym': 'SPEED',
                        'description': ['Link Speed Setting: Reflects speed setting of the MAC.',
                                        'In GMII/MII mode, these bits reflect the software CTRL.SPEED setting ',
                                        '? 00 => 10 Mbps',
                                        '? 01 => 100 Mbps',
                                        '? 10 => 1000 Mbps',
                                        '? 11 => 1000 Mbps'],
                        'range': (7, 6),
                        'reset': None,
                        'sticky': ''},
                       {'access': 'RO',
                        'acronym': 'LINKMODE',
                        'description': ['Mode. Based on CTRL_EXT. LINK_MODE.',
                                        '0 = MAC is operating in GMII/MII mode1 = Reserved'],
                        'range': (5, 5),
                        'reset': None,
                        'sticky': ''},
                       {'access': 'RO',
                        'acronym': 'TXOFF',
                        'description': ['Transmission Off. This bit indicates the state of the transmit function when symmetrical flow control has been enabled and negotiated with the link partner.',
                                        '0 = Symmetrical flow control is disabled, or transmission is not paused.1 = Symmetrical flow control is enabled, and the transmit function is paused due to the reception of an XOFF frame. It is cleared upon expiration of the pause timer or the receipt of an XON frame.'],
                        'range': (4, 4),
                        'reset': None,
                        'sticky': ''},
                       {'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (3, 2),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RO',
                        'acronym': 'RSVD',
                        'description': ['Reserved'],
                        'range': (1, 1),
                        'reset': None,
                        'sticky': ''},
                       {'access': 'RO',
                        'acronym': 'FD',
                        'description': ['Full Duplex. This bit reflects the MAC duplex configuration. Normally, the duplex setting for the link, as it should reflect the duplex configuration negotiated between the PHY and link partner (copper link) or MAC and link partner (fiber link).',
                                        '0 = Half Duplex mode1 = Full Duplex mode'],
                        'range': (0, 0),
                        'reset': None,
                        'sticky': ''}],
            'offset': 8,
            'offset_end': (11, None),
            'offset_start': (8, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'STATUS',
            'reg_name': 'STATUS',
            'size': 32,
            'table_ref': '37-26',
            'title_desc': 'Device Status Register',
            'view': 'PCI 3'},
 'TADV': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'IDV',
                      'description': ['Interrupt Delay Value. ',
                                      'Timer increments are',
                                      'RMII: 1.28 microseconds',
                                      'RGMII: 1.024 microseconds. ',
                                      'The transmit interrupt delay timer (TIDV) can be used to coalesce transmit interrupts. However, it might be necessary to ensure that no completed transmit remains unnoticed for too long an interval in order ensure timely release of transmit buffers. This register can be used to ENSURE that a transmit interrupt occurs at some predefined interval after a transmit is completed. Like the delayed-transmit timer, the absolute transmit timer ONLY applies to transmit descriptor operations where (a) interrupt-based reporting is requested (RS set) and (b) the use of the timer function is requested (IDE is set).',
                                      'This feature operates by initiating a countdown timer upon successfully transmitting the buffer. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated. The occurrence of either an immediate (non-scheduled) or delayed transmit timer (TIDV) expiration interrupt halts the TADV timer and eliminates any spurious second interrupts.',
                                      'Setting the value to 0b disables the transmit absolute delay function. If an immediate (nonscheduled) interrupt is desired for any transmit descriptor, the descriptor IDE should be set to 0b.Note:This timer ONLY causes an interrupt. It does NOT cause a writeback'],
                      'range': (15, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 14380,
          'offset_end': (14383, None),
          'offset_start': (14380, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'TADV',
          'reg_name': 'TADV',
          'size': 32,
          'table_ref': '37-77',
          'title_desc': 'Transmit Absolute Interrupt Delay Value Register',
          'view': 'PCI 3'},
 'TCTL': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 8,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 25),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RTLC',
                      'description': ['Re-Transmit on Late Collision. This bit configures the hardware to perform retransmission of packets when a late collision is detected. Note that the collision window is speed dependent: 64B for 10/100 Mbps and 512B for 1Gbps operation. If a late collision is detected when this bit is clear, the transmit function assumes the packet is successfully transmitted.Note:This bit is ignored in full-duplex mode.'],
                      'range': (24, 24),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'PBE',
                      'description': ["Packet Burst Enable. The EP80579's GbE does not support Packet Bursting for 1Gbps half-duplex transmit operation. This bit must be set to 0."],
                      'range': (23, 23),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'SWXOFF',
                      'description': ['Software XOFF Transmission. When set to a 1 the device will schedule the transmission of an XOFF (PAUSE) frame using the current value of the PAUSE timer. This bit clears itself upon transmission of the XOFF frame.Note:While 802.3x flow control is only defined during full duplex operation, the sending of PAUSE frames via the SWXOFF bit is not gated by the duplex settings within the device. Software should not write a 1 to this bit while the device is configured for half duplex operation.'],
                      'range': (22, 22),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'COLD',
                      'description': ['Collision Distance. Wire speeds of 1Gbps result in a very short collision radius with traditional minimum packet sizes. This bit specifies the minimum number of bytes in the packet to satisfy the desired collision distance for proper CSMA/CD operation. It is important to note that the resulting packet has special characters appended to the end, not regular data characters. Hardware strips special characters for packets that go from 1 Gbps environments to 100 Mbps environments.Note:The hardware checks and pads to this value even in full-duplex operation.'],
                      'range': (21, 12),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'CT',
                      'description': ['Collision Threshold. Software may choose to abort packet transmission in less than the Ethernet mandated 16 collisions. This field determines the number of attempts at retransmission prior to giving up on the packet (not including the first transmission attempt). The Ethernet back-off algorithm is implemented and clamps to the maximum number of slot-times after 10 retries. This field only has meaning when in half-duplex operation.Note:While this field can be varied, it should be set to a value of 15 in order to comply with the IEEE specification requiring a total of 16 attempts.'],
                      'range': (11, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'PSP',
                      'description': ['Pad Short Packets to 64B with valid data characters, NOT padding symbols.',
                                      '0 = Do not pad short packets1 = Pad short packetsNote:This is not the same as the mini-mum collision distance.'],
                      'range': (3, 3),
                      'reset': 1,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved. '],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'EN',
                      'description': ['Enable.',
                                      '0 = Writing this bit to 0 will stop transmission after any in progress packets are sent. Data remains in the transmit FIFO until the device is re-enabled. Software should combine this with reset if the packets in the FIFO should be flushed.1 = The transmitter is enabled.'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved. '],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 1024,
          'offset_end': (1027, None),
          'offset_start': (1024, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'TCTL',
          'reg_name': 'TCTL',
          'size': 32,
          'table_ref': '37-67',
          'title_desc': 'Transmit Control Register',
          'view': 'PCI 3'},
 'TDBAH': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': u'XXXXXXXXh',
           'description': None,
           'fields': [{'access': 'RW',
                       'acronym': 'TDBAH',
                       'description': ['Transmit Descriptor Base AddressNote:TDBAH[31:0] must be set to 0.'],
                       'range': (31, 0),
                       'reset': None,
                       'sticky': ''}],
           'offset': 14340,
           'offset_end': (14343, None),
           'offset_start': (14340, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'TDBAH',
           'reg_name': 'TDBAH',
           'size': 32,
           'table_ref': '37-71',
           'title_desc': 'Transmit Descriptor Base Address High Register',
           'view': 'PCI 3'},
 'TDBAL': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': u'XXXXXXX0h',
           'description': None,
           'fields': [{'access': 'RW',
                       'acronym': 'TDBAL',
                       'description': ['Transmit Descriptor Base Address Low'],
                       'range': (31, 4),
                       'reset': None,
                       'sticky': ''},
                      {'access': 'RV',
                       'acronym': '0',
                       'description': ['Writes are ignored, reads return 0.'],
                       'range': (3, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 14336,
           'offset_end': (14339, None),
           'offset_start': (14336, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'TDBAL',
           'reg_name': 'TDBAL',
           'size': 32,
           'table_ref': '37-70',
           'title_desc': 'Transmit Descriptor Base Address Low Register',
           'view': 'PCI 3'},
 'TDH': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RV',
                     'acronym': 'Rsvd',
                     'description': ['Reserved'],
                     'range': (31, 16),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'TDH',
                     'description': ['Transmit Descriptor Head'],
                     'range': (15, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 14352,
         'offset_end': (14355, None),
         'offset_start': (14352, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'TDH',
         'reg_name': 'TDH',
         'size': 32,
         'table_ref': '37-73',
         'title_desc': 'Transmit Descriptor Head Register',
         'view': 'PCI 3'},
 'TDLEN': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RV',
                       'acronym': 'Rsvd',
                       'description': ['Reserved'],
                       'range': (31, 20),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RW',
                       'acronym': 'LEN',
                       'description': ['Descriptor Length'],
                       'range': (19, 7),
                       'reset': 0,
                       'sticky': ''},
                      {'access': 'RV',
                       'acronym': '0',
                       'description': ['Writes are ignored, reads return 0.'],
                       'range': (6, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 14344,
           'offset_end': (14347, None),
           'offset_start': (14344, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'TDLEN',
           'reg_name': 'TDLEN',
           'size': 32,
           'table_ref': '37-72',
           'title_desc': 'Transmit Descriptor Length Register',
           'view': 'PCI 3'},
 'TDT': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RV',
                     'acronym': 'Rsvd',
                     'description': ['Reserved'],
                     'range': (31, 16),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'TDT',
                     'description': ['Transmit Descriptor Tail'],
                     'range': (15, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 14360,
         'offset_end': (14363, None),
         'offset_start': (14360, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'TDT',
         'reg_name': 'TDT',
         'size': 32,
         'table_ref': '37-74',
         'title_desc': 'Transmit Descriptor Tail Register',
         'view': 'PCI 3'},
 'TIDV': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'IDV',
                      'description': ['Interrupt Delay Value. ',
                                      'Timer increments are',
                                      'RMII: 1.28 microseconds',
                                      'RGMII: 1.024 microseconds. ',
                                      '? This register is used to delay interrupt notification for transmit operations by coalescing interrupts for multiple transmitted buffers. Delaying interrupt notification helps maximize the amount of transmit buffers reclaimed by a single interrupt. This feature only applies to transmit descriptor operations where (a) interrupt-based reporting is requested (RS set) and (b) the use of the timer function is requested (IDE is set).',
                                      '? This feature operates by initiating a countdown timer upon successfully transmitting the buffer. If a subsequent transmit delayed-interrupt is scheduled before the timer expires, the timer is re-initialized to the programmed value and re-starts its countdown. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated.',
                                      '? Hardware always loads the transmit interrupt counter whenever it processes a descriptor with IDE set even if it is already counting down due to a previous descriptor.',
                                      '? Setting the value to 0 is not allowed. If an immediate (non-scheduled) interrupt is desired for any transmit descriptor, the descriptor IDE should be set to 0.',
                                      '? The occurrence of either an immediate (non-scheduled) or absolute transmit timer interrupt will halt the TIDV timer and eliminate any spurious second interrupts.',
                                      '? Transmit interrupts due to a Transmit Absolute Timer (TADV) expiration or an immediate interrupt (RS =1, IDE=0) will cancel a pending TIDV interrupt. The TIDV countdown timer is reloaded but halted, though it may be restarted by a processing a subsequent transmit descriptor.'],
                      'range': (15, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 14368,
          'offset_end': (14371, None),
          'offset_start': (14368, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'TIDV',
          'reg_name': 'TIDV',
          'size': 32,
          'table_ref': '37-75',
          'title_desc': 'Transmit Interrupt Delay Value Register',
          'view': 'PCI 3'},
 'TIPG': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 6299656,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (31, 30),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'IPGR2',
                      'description': ['IPG Receive Time 2. ',
                                      'Specifies the total length of the IPG time for non back-to-back transmissions. Measured in increments of the MAC clock: ',
                                      '? 8 ns MAC clock when operating @ 1 Gbps (82544GC/EI only).',
                                      '? 80 ns MAC clock when operating @ 100 Mbps ',
                                      '? 800 ns MAC clock when operating @ 10 Mbps. ',
                                      'In order to calculate the actual IPG value, a value of six should be added to the IPGR2 value as six MAC clocks are used by the MAC for synchronization and internal engines. ',
                                      'For the IEEE 802.3 standard IPG value of 96-bit time, the value that should be programmed into IPGR2 is six (total IPG delay of 12 MAC clock cycles) ',
                                      'According to the IEEE802.3 standard, IPGR1 should be 2/3 of IPGR2 value.IPGR2 is significant only in half-duplex mode of operation. '],
                      'range': (29, 20),
                      'reset': 6,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'IPGR1',
                      'description': ['IPG Receive Time 1. ',
                                      'Specifies the length of the first part of the IPG time for non back-to- back transmissions. During this time, the internal IPG counter restarts if any carrier event occurs. Once the time specified in IPGR1 has elapsed, carrier sense does not affect the IPG counter. According to the IEEE802.3 standard, IPGR1 should be 2/3 of IPGR2 value. Measured in increments of the MAC clock:',
                                      '? 8 ns MAC clock when operating @ 1 Gbps ',
                                      '? 80 ns MAC clock when operating @ 100 Mbps ',
                                      '? 800 ns MAC clock when operating @ 10 Mbps. ',
                                      'For IEEE 802.3 minimum IPG value of 96-bit time, the value that should be programmed into IPGR1 is eight. IPGR1 is significant only in half-duplex mode of operation. '],
                      'range': (19, 10),
                      'reset': 8,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'IPGT',
                      'description': ['IPG Transmit Time ',
                                      'Specifies the IPG time for back-to-back packet transmissions',
                                      'Measured in increments of the MAC clock: ',
                                      '? 8 ns MAC clock when operating @ 1 Gbps.',
                                      '? 80 ns MAC clock when operating @ 100 Mbps. ',
                                      '? 800 ns MAC clock when operating @ 10 Mbps. ',
                                      'To calculate the IPG value for 10/100/1000BASE-T applications, a value of four should be added to the IPGT value as four clocks are used by the MAC as internal overhead. The value that should be programmed into IPGT is 8. These values are recommended to assure that the minimum IPG gap is met under all synchronization conditions. '],
                      'range': (9, 0),
                      'reset': 8,
                      'sticky': ''}],
          'offset': 1040,
          'offset_end': (1043, None),
          'offset_start': (1040, None),
          'power_well': 'Gbe1/2:',
          'recurring': None,
          'reg_base_name': 'TIPG',
          'reg_name': 'TIPG',
          'size': 32,
          'table_ref': '37-68',
          'title_desc': 'Transmit IPG Register',
          'view': 'PCI 3'},
 'TNCRS': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RC',
                       'acronym': 'TNCRS',
                       'description': ['Number of transmissions without a CRS assertion from the PHY.'],
                       'range': (31, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 16436,
           'offset_end': (16439, None),
           'offset_start': (16436, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'TNCRS',
           'reg_name': 'TNCRS',
           'size': 32,
           'table_ref': '37-89',
           'title_desc': 'Transmit with No CRS Count Register',
           'view': 'PCI 3'},
 'TORH': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'TORH',
                      'description': ['Number of total octets received - upper 4 bytes'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16580,
          'offset_end': (16583, None),
          'offset_start': (16580, None),
          'power_well': None,
          'recurring': None,
          'reg_base_name': 'TORH',
          'reg_name': 'TORH',
          'size': 32,
          'table_ref': '37-117',
          'title_desc': 'Total Octets Received High Register',
          'view': 'PCI 3'},
 'TORL': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'TORL',
                      'description': ['Number of total octets received - lower 4 bytes'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16576,
          'offset_end': (16579, None),
          'offset_start': (16576, None),
          'power_well': None,
          'recurring': None,
          'reg_base_name': 'TORL',
          'reg_name': 'TORL',
          'size': 32,
          'table_ref': '37-116',
          'title_desc': 'Total Octets Received Low Register',
          'view': 'PCI 3'},
 'TOTH': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'TOTH',
                      'description': ['Number of total octets transmitted - upper 4 bytes'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16588,
          'offset_end': (16591, None),
          'offset_start': (16588, None),
          'power_well': None,
          'recurring': None,
          'reg_base_name': 'TOTH',
          'reg_name': 'TOTH',
          'size': 32,
          'table_ref': '37-119',
          'title_desc': 'Total Octets Transmitted High Register',
          'view': 'PCI 3'},
 'TOTL': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RC',
                      'acronym': 'TOTL',
                      'description': ['Number of total octets transmitted - lower 4 bytes'],
                      'range': (31, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 16584,
          'offset_end': (16591, None),
          'offset_start': (16584, None),
          'power_well': None,
          'recurring': None,
          'reg_base_name': 'TOTL',
          'reg_name': 'TOTL',
          'size': 32,
          'table_ref': '37-118',
          'title_desc': 'Total Octets Transmitted Low Register',
          'view': 'PCI 3'},
 'TPR': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RC',
                     'acronym': 'TPR',
                     'description': ['Total of all packets received'],
                     'range': (31, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 16592,
         'offset_end': (16595, None),
         'offset_start': (16592, None),
         'power_well': None,
         'recurring': None,
         'reg_base_name': 'TPR',
         'reg_name': 'TPR',
         'size': 32,
         'table_ref': '37-120',
         'title_desc': 'Total Packets Received Register',
         'view': 'PCI 3'},
 'TPT': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RC',
                     'acronym': 'TPT',
                     'description': ['Number of all packets transmitted'],
                     'range': (31, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 16596,
         'offset_end': (16599, None),
         'offset_start': (16596, None),
         'power_well': None,
         'recurring': None,
         'reg_base_name': 'TPT',
         'reg_name': 'TPT',
         'size': 32,
         'table_ref': '37-121',
         'title_desc': 'Total Packets Transmitted Register',
         'view': 'PCI 3'},
 'TSCTC': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 0,
           'description': None,
           'fields': [{'access': 'RC',
                       'acronym': 'TSCTC',
                       'description': ['Number of TCP Segmentation contexts transmitted count'],
                       'range': (31, 0),
                       'reset': 0,
                       'sticky': ''}],
           'offset': 16632,
           'offset_end': (16635, None),
           'offset_start': (16632, None),
           'power_well': None,
           'recurring': None,
           'reg_base_name': 'TSCTC',
           'reg_name': 'TSCTC',
           'size': 32,
           'table_ref': '37-129',
           'title_desc': 'TCP Segmentation Context Transmitted Count Register',
           'view': 'PCI 3'},
 'TSCTFC': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RC',
                        'acronym': 'TSCTFC',
                        'description': ['Number of TCP Segmentation contexts where the device failed to transmit the entire data payload'],
                        'range': (31, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 16636,
            'offset_end': (16639, None),
            'offset_start': (16636, None),
            'power_well': None,
            'recurring': None,
            'reg_base_name': 'TSCTFC',
            'reg_name': 'TSCTFC',
            'size': 32,
            'table_ref': '37-130',
            'title_desc': 'TCP Segmentation Context Transmit Fail Count Register',
            'view': 'PCI 3'},
 'TSPMT': {'bar': 'CSRBAR',
           'bus_device_function': 'M:2:0',
           'default': 16778240,
           'description': None,
           'fields': [{'access': 'RW',
                       'acronym': 'TSPBP',
                       'description': ['TCP Segmentation Packet Buffer Padding, value is in bytes. This field allows software configuration of packet buffer space which must be reserved as "pad" for worst-case header insertion. To ensure that this value does not prevent descriptors from being serviced at all, it is necessary that the transmit packet buffer allocation should be larger than the sum of (maximum TCP HDRLEN + maximum MSS + TSPMT.TMPBP + 80 bytes).'],
                       'range': (31, 16),
                       'reset': 256,
                       'sticky': ''},
                      {'access': 'RW',
                       'acronym': 'TSMT',
                       'description': ['TCP Segmentation Minimum Transfer, value is in bytes. The DMA will attempt to issue burst fetches for as much data as possible, and it is possible for the transmit DMA to cause the transmit packet buffer to approach fullness (less the pad specified). However, if the packet buffer empties slightly, the transmit DMA could initiate a series of small transfers.',
                                       'To further optimize the efficiency of the transmit DMA during TCP segmentation operation, the this TSPMT.TSMT field allows software configuration of the minimum number of bytes which the DMA should attempt to transfer in a single burst operation. The transmit DMA will use this value to refrain from issuing a burst read until at least TSPMT.TSMT bytes of data from the current data descriptor can be stored in the packet buffer.',
                                       'This check will be ignored if, after a series of DMA operations, the descriptor contains a smaller number of unfetched data bytes. To ensure that this minimum threshold does not prevent descriptors from being serviced at all, it is necessary that the transmit packet buffer allocation should be larger than the sum of (TSPMT.TSMT + TSPMT.TSPBP + 80 bytes).'],
                       'range': (15, 0),
                       'reset': 1024,
                       'sticky': ''}],
           'offset': 14384,
           'offset_end': (14387, None),
           'offset_start': (14384, None),
           'power_well': 'Gbe1/2:',
           'recurring': None,
           'reg_base_name': 'TSPMT',
           'reg_name': 'TSPMT',
           'size': 32,
           'table_ref': '37-78',
           'title_desc': 'TCP Segmentation Pad And Minimum Threshold Register',
           'view': 'PCI 3'},
 'TXDCTL': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RW',
                        'acronym': 'LWTHRESH',
                        'description': ['Transmit Descriptor Low Threshold. This field controls the number of pre-fetched transmit descriptors at which a transmit descriptor-low interrupt is reported. Asserting ICR.TXD_LOW only when the processing distance from the TDT register drops below LWTHRESH may allow software to operate more efficiently by maintaining a continuous addition of transmit work, interrupting only when the hardware nears completion of all submitted work.',
                                        'An interrupt condition is asserted when the number of descriptors available transitions from',
                                        'threshold_level + 1 -> threshold_level',
                                        'where LWTHRESH specifies a multiple of 8 descriptors, (i.e. threshold_level = 8*LWTHRESH).',
                                        'Setting this value to 0 will cause this interrupt to be generated only when the transmit descriptor cache becomes completely empty.'],
                        'range': (31, 25),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'GRAN',
                        'description': ['Granularity of the thresholds in this register.',
                                        '0 = Cache Lines1 = Descriptors (16B each)'],
                        'range': (24, 24),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (23, 22),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'WTHRESH',
                        'description': ['Write-back Threshold. This field controls the write-back of processed transmit descriptors. This threshold refers to the number of transmit descriptors in the GbE hardware buffer which are ready to be written back to host memory. In the absence of external events (explicit flushes), the write-back will occur only after more than WTHRESH descriptors are available for write-back.',
                                        'Since write-back notification of transmit descriptor completion is optional (under the control of the RS bit in the descriptor), not all processed descriptors are counted with respect to WTHRESH (any single transmit descriptor with RS=0 is consumed with no writeback notification performed). When WTHRESH is non-zero, processing a descriptor with RS=1 initiates accumulation of pending writebacks; accumulated writebacks will include even those descriptors with RS=0, in order to optimize writeback bursts.Note:When WTHRESH value is set to 0, transmit descriptor writeback notification will be similar to the 82452 behavior. In accordance with WTHRESH=0, the writeback notification for a descriptor with RS=1 will occur as soon as the descriptor is processed. In addition, processed transmit descriptors are not written-back in entirety; only the descriptor status field is written back/ updated. This 82542-compatible mode is the default HW behavior.'],
                        'range': (21, 16),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (15, 14),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'HTHRESH',
                        'description': ['Host Threshold. This field is used to control the fetching of descriptors from host memory. This threshold refers to the number of valid, unprocessed receive descriptors that must exist in host memory before they will be fetched.'],
                        'range': (13, 8),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RV',
                        'acronym': 'Rsvd',
                        'description': ['Reserved'],
                        'range': (7, 6),
                        'reset': 0,
                        'sticky': ''},
                       {'access': 'RW',
                        'acronym': 'PTHRESH',
                        'description': ['Prefetch Threshold. This field is used to control when a prefetch of descriptors will be considered. This threshold refers to the number of valid, unprocessed transmit descriptors the chip has in its GbE hardware buffer. If this number drops below PTHRESH, the algorithm will consider pre-fetching descriptors from host memory. This fetch will not happen however unless there are at least HTHRESH valid descriptors in host memory to fetch.'],
                        'range': (5, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 14376,
            'offset_end': (14379, None),
            'offset_start': (14376, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'TXDCTL',
            'reg_name': 'TXDCTL',
            'size': 32,
            'table_ref': '37-76',
            'title_desc': 'Transmit Descriptor Control Register',
            'view': 'PCI 3'},
 'VET': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 33024,
         'description': 'To be compliant with the 802.3ac standard, this register must be programmed with the value 0x00_00_81_00',
         'fields': [{'access': 'RV',
                     'acronym': 'RSVD',
                     'description': ['Reserved'],
                     'range': (31, 16),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'VET',
                     'description': ['To be compliant with the 802.3ac standard, this register must be programmed with the value 0x00_00_81_00.'],
                     'range': (15, 0),
                     'reset': 33024,
                     'sticky': ''}],
         'offset': 56,
         'offset_end': (59, None),
         'offset_start': (56, None),
         'power_well': 'Gbe1/2:',
         'recurring': None,
         'reg_base_name': 'VET',
         'reg_name': 'VET',
         'size': 32,
         'table_ref': '37-34',
         'title_desc': 'VLAN EtherType Register',
         'view': 'PCI 3'},
 'VFTA[0-127]': {'bar': 'CSRBAR',
                 'bus_device_function': 'M:2:0',
                 'default': u'XXXXXXXXh',
                 'description': None,
                 'fields': [{'access': 'RW',
                             'acronym': 'VLAN_Vector',
                             'description': ['VLAN_Vector 32b vector of VLAN filter table information.'],
                             'range': (31, 0),
                             'reset': None,
                             'sticky': ''}],
                 'offset': 22016,
                 'offset_end': (22019, 4),
                 'offset_start': (22016, 4),
                 'power_well': 'Gbe1/2:',
                 'recurring': 128,
                 'reg_base_name': 'VFTA',
                 'reg_name': 'VFTA[0-127]',
                 'size': 32,
                 'table_ref': '37-66',
                 'title_desc': '128 VLAN Filter Table Array Registers',
                 'view': 'PCI 3'},
 'WUC': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RO',
                     'acronym': 'RSVD',
                     'description': ['Reserved'],
                     'range': (31, 4),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'APMPME',
                     'description': ['Assert PME On APM Wakeup - ',
                                     'If it is 1, the GbE will set the PME_Status bit in the Power Management Control / Status Register (PMCSR) and assert GBE_PME_WAKE when APM Wakeup is enabled and the GbE receives a matching magic packet.',
                                     '*Note that this bit is loaded from the EEPROM, if present'],
                     'range': (3, 3),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'PME_Status',
                     'description': ['PME_Status',
                                     'This bit is set when the GbE receives a wakeup event. It is the same as the PME_Status bit in the Power Management Control / Status Register (PMCSR). Writing a "1" to this bit will clear it and clear the PME_Status bit in the PMCSR.'],
                     'range': (2, 2),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'PME_EN',
                     'description': ['PME_En',
                                     'This read/write bit is used by the driver to access the PME_En bit of the Power Management Control / Status Register (PMCSR) without writing to PCI configuration space.'],
                     'range': (1, 1),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RW',
                     'acronym': 'APME',
                     'description': ['Advance Power Management Enable - ',
                                     'If "1", APM Wakeup is enabled.',
                                     '*Note that this bit is loaded from the EEPROM, if present'],
                     'range': (0, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 22528,
         'offset_end': (22531, None),
         'offset_start': (22528, None),
         'power_well': None,
         'recurring': None,
         'reg_base_name': 'WUC',
         'reg_name': 'WUC',
         'size': 32,
         'table_ref': '37-131',
         'title_desc': 'Wake Up Control Register (0x05800; RW)',
         'view': 'PCI 3'},
 'WUFC': {'bar': 'CSRBAR',
          'bus_device_function': 'M:2:0',
          'default': 0,
          'description': None,
          'fields': [{'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved. Should be set to 0.'],
                      'range': (31, 20),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'FLX3',
                      'description': ['Flexible Filter 3 Enable'],
                      'range': (19, 19),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'FLX2',
                      'description': ['Flexible Filter 2 Enable'],
                      'range': (18, 18),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'FLX1',
                      'description': ['Flexible Filter 1 Enable'],
                      'range': (17, 17),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'FLX0',
                      'description': ['Flexible Filter 0 Enable'],
                      'range': (16, 16),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'RSVD',
                      'description': ['Reserved. Should be set to 0.'],
                      'range': (15, 15),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'RSVD',
                      'description': ['Reserved. Should be set to 0.'],
                      'range': (14, 8),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'IPV6',
                      'description': ['Directed IPv6 Packet Wake Up Enable'],
                      'range': (7, 7),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'IPV4',
                      'description': ['Directed IPv4 Packet Wake Up Enable'],
                      'range': (6, 6),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'ARP',
                      'description': ['ARP/IPv4 Request Packet Wake Up Enable'],
                      'range': (5, 5),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'BC',
                      'description': ['Broadcast Wake Up Enable'],
                      'range': (4, 4),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'MC',
                      'description': ['Directed Multicast Wake Up Enable'],
                      'range': (3, 3),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'EX',
                      'description': ['Directed Exact Wake Up Enable'],
                      'range': (2, 2),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RW',
                      'acronym': 'MAG',
                      'description': ['Magic Packet Wake Up Enable'],
                      'range': (1, 1),
                      'reset': 0,
                      'sticky': ''},
                     {'access': 'RV',
                      'acronym': 'Rsvd',
                      'description': ['Reserved'],
                      'range': (0, 0),
                      'reset': 0,
                      'sticky': ''}],
          'offset': 22536,
          'offset_end': (22539, None),
          'offset_start': (22536, None),
          'power_well': None,
          'recurring': None,
          'reg_base_name': 'WUFC',
          'reg_name': 'WUFC',
          'size': 32,
          'table_ref': '37-132',
          'title_desc': 'Wake Up Filter Control Register (0x05808; RW)',
          'view': 'PCI 3'},
 'WUS': {'bar': 'CSRBAR',
         'bus_device_function': 'M:2:0',
         'default': 0,
         'description': None,
         'fields': [{'access': 'RV',
                     'acronym': 'RSVD',
                     'description': ['Reserved. Should be set to 0.'],
                     'range': (31, 20),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'FLX3',
                     'description': ['Flexible Filter 3 Match'],
                     'range': (19, 19),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'FLX2',
                     'description': ['Flexible Filter 2 Match'],
                     'range': (18, 18),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'FLX1',
                     'description': ['Flexible Filter 1 Match'],
                     'range': (17, 17),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'FLX0',
                     'description': ['Flexible Filter 0 Match'],
                     'range': (16, 16),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RV',
                     'acronym': 'Reserved',
                     'description': ['Reserved. '],
                     'range': (15, 8),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'IPV6',
                     'description': ['Directed IPv6 Packet Wake Up Packet Received'],
                     'range': (7, 7),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'IPV4',
                     'description': ['Directed IPv4 Packet Wake Up Packet Received'],
                     'range': (6, 6),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'ARP',
                     'description': ['ARP/IPv4 Request Packet Wake Up Packet Received'],
                     'range': (5, 5),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'BC',
                     'description': ['Broadcast Wake Up Packet Received'],
                     'range': (4, 4),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'MC',
                     'description': ['Directed Multicast Wake Up Packet Received ',
                                     'The packet was a multicast packet whose hashed to a value that corresponded to a 1 bit in the Multicast Table ArrayNote:If the MAC has been configured for promiscuous mode, a multicast wakeup will occur if a broadcast packet is received. This is because a broadcast message is a special type of multicast message. Refer to 802.3.'],
                     'range': (3, 3),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'EX',
                     'description': ['Directed Exact Wake Up Packet Received',
                                     "The packet's address matched one of the 16 pre-programmed exact values in the Receive Address registers"],
                     'range': (2, 2),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RWC',
                     'acronym': 'MAG',
                     'description': ['Magic Packet Wake Up Packet Received'],
                     'range': (1, 1),
                     'reset': 0,
                     'sticky': ''},
                    {'access': 'RV',
                     'acronym': 'Rsvd',
                     'description': ["Reserved. Must be written as '0'"],
                     'range': (0, 0),
                     'reset': 0,
                     'sticky': ''}],
         'offset': 22544,
         'offset_end': (22547, None),
         'offset_start': (22544, None),
         'power_well': None,
         'recurring': None,
         'reg_base_name': 'WUS',
         'reg_name': 'WUS',
         'size': 32,
         'table_ref': '37-133',
         'title_desc': 'Wake Up Status Register (0x05810; RW)',
         'view': 'PCI 3'},
 'XOFFRXC': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RC',
                         'acronym': 'XOFFRXC',
                         'description': ['Number of XOFF packets received.'],
                         'range': (31, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 16464,
             'offset_end': (16467, None),
             'offset_start': (16464, None),
             'power_well': 'Gbe1/2:',
             'recurring': None,
             'reg_base_name': 'XOFFRXC',
             'reg_name': 'XOFFRXC',
             'size': 32,
             'table_ref': '37-94',
             'title_desc': 'XOFF Received Count Register',
             'view': 'PCI 3'},
 'XOFFTXC': {'bar': 'CSRBAR',
             'bus_device_function': 'M:2:0',
             'default': 0,
             'description': None,
             'fields': [{'access': 'RC',
                         'acronym': 'XOFFTXC',
                         'description': ['Number of XOFF packets transmitted.'],
                         'range': (31, 0),
                         'reset': 0,
                         'sticky': ''}],
             'offset': 16468,
             'offset_end': (16471, None),
             'offset_start': (16468, None),
             'power_well': 'Gbe1/2:',
             'recurring': None,
             'reg_base_name': 'XOFFTXC',
             'reg_name': 'XOFFTXC',
             'size': 32,
             'table_ref': '37-95',
             'title_desc': 'XOFF Transmitted Count Register',
             'view': 'PCI 3'},
 'XONRXC': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RC',
                        'acronym': 'XONRXC',
                        'description': ['Number of XON packets received.'],
                        'range': (31, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 16456,
            'offset_end': (16459, None),
            'offset_start': (16456, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'XONRXC',
            'reg_name': 'XONRXC',
            'size': 32,
            'table_ref': '37-92',
            'title_desc': 'XON Received Count Register',
            'view': 'PCI 3'},
 'XONTXC': {'bar': 'CSRBAR',
            'bus_device_function': 'M:2:0',
            'default': 0,
            'description': None,
            'fields': [{'access': 'RC',
                        'acronym': 'XONTXC',
                        'description': ['Number of XON packets transmitted.'],
                        'range': (31, 0),
                        'reset': 0,
                        'sticky': ''}],
            'offset': 16460,
            'offset_end': (16463, None),
            'offset_start': (16460, None),
            'power_well': 'Gbe1/2:',
            'recurring': None,
            'reg_base_name': 'XONTXC',
            'reg_name': 'XONTXC',
            'size': 32,
            'table_ref': '37-93',
            'title_desc': 'XON Transmitted Count Register',
            'view': 'PCI 3'}}