Merge branch 'master' of alcor:git/misc

26 files changed, 819 insertions, 4 deletions

diff --git a/400.dat b/400.dat
new file mode 100644
index 0000000..1c56567
--- /dev/null
+++ b/400.dat
@@ -0,0 +1,28 @@
+0 0.000000
+1 0.000000
+2 0.000000
+3 663.461538
+4 796.153846
+5 928.846154
+6 1061.538462
+7 1382.692308
+8 1515.384615
+9 1648.076923
+10 1780.769231
+11 1913.461538
+12 2046.153846
+13 2178.846154
+14 2311.538462
+15 2632.692308
+16 2765.384615
+17 2898.076923
+18 3030.769231
+19 3163.461538
+20 3296.153846
+21 3428.846154
+22 3561.538462
+23 3882.692308
+24 4015.384615
+25 4148.076923
+26 4280.769231
+27 4413.461538
diff --git a/533.dat b/533.dat
new file mode 100644
index 0000000..bf3035f
--- /dev/null
+++ b/533.dat
@@ -0,0 +1,28 @@
+0 0.000000
+1 0.000000
+2 0.000000
+3 465.277778
+4 558.333333
+5 651.388889
+6 744.444444
+7 1030.555556
+8 1123.611111
+9 1216.666667
+10 1309.722222
+11 1402.777778
+12 1495.833333
+13 1588.888889
+14 1681.944444
+15 1968.055556
+16 2061.111111
+17 2154.166667
+18 2247.222222
+19 2340.277778
+20 2433.333333
+21 2526.388889
+22 2619.444444
+23 2905.555556
+24 2998.611111
+25 3091.666667
+26 3184.722222
+27 3277.777778
diff --git a/667.dat b/667.dat
new file mode 100644
index 0000000..8e6c106
--- /dev/null
+++ b/667.dat
@@ -0,0 +1,28 @@
+0 0.000000
+1 0.000000
+2 0.000000
+3 361.111111
+4 433.333333
+5 505.555556
+6 577.777778
+7 822.222222
+8 894.444444
+9 966.666667
+10 1038.888889
+11 1111.111111
+12 1183.333333
+13 1255.555556
+14 1327.777778
+15 1572.222222
+16 1644.444444
+17 1716.666667
+18 1788.888889
+19 1861.111111
+20 1933.333333
+21 2005.555556
+22 2077.777778
+23 2322.222222
+24 2394.444444
+25 2466.666667
+26 2538.888889
+27 2611.111111
diff --git a/800.dat b/800.dat
new file mode 100644
index 0000000..2c83b7e
--- /dev/null
+++ b/800.dat
@@ -0,0 +1,28 @@
+0 0.000000
+1 0.000000
+2 0.000000
+3 281.250000
+4 337.500000
+5 393.750000
+6 450.000000
+7 681.250000
+8 737.500000
+9 793.750000
+10 850.000000
+11 906.250000
+12 962.500000
+13 1018.750000
+14 1075.000000
+15 1306.250000
+16 1362.500000
+17 1418.750000
+18 1475.000000
+19 1531.250000
+20 1587.500000
+21 1643.750000
+22 1700.000000
+23 1931.250000
+24 1987.500000
+25 2043.750000
+26 2100.000000
+27 2156.250000
diff --git a/bin.c b/bin.c
index dca7f5e..565b1bb 100644
--- a/bin.c
+++ b/bin.c
@@ -12,8 +12,8 @@ printu32(unsigned int n) {
 printu32_long(unsigned int n) {
 	int i;
 	printf("%u = 0x%08x\n", n, n);
-	printf("|31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15"
-			"|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0\n");
+	printf("|31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16"
+	       "|15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0\n");
 	for(i = 31; i>=0; i--) printf("| %d", !!(n&(1<<i)));
 	printf("\n");
 }
diff --git a/cbfs_poc/Makefile b/cbfs_poc/Makefile
new file mode 100644
index 0000000..73856a8
--- /dev/null
+++ b/cbfs_poc/Makefile
@@ -0,0 +1,24 @@
+PWD := $(shell pwd)
+
+KSRC ?= /bad__ksrc__not_set
+COREBOOT ?= /bad__coreboot__not_set
+LIBPAYLOAD ?= $(COREBOOT)/payloads/libpayload
+CBFS_A ?= $(LIBPAYLOAD)/build/libcbfs.a
+CBFS_INCLUDES ?= -I$(readlink -f .) -I$(LIBPAYLOAD)/include -I$(LIBPAYLOAD)/include/i386
+
+EXTRA_CFLAGS += -D_ARCH_TYPES_H -I$(LIBPAYLOAD)/include -I$(LIBPAYLOAD)/include/i386
+
+obj-m := module_lol.o
+module_lol-y += libcbfs.a
+
+modules:
+
+libcbfs.a:
+	cp $(CBFS_A) $@
+
+modules modules_install clean:
+	$(MAKE) -C $(KSRC) M=$(PWD) $@
+
+distclean: clean
+	rm -f Module.symvers modules.order
+
diff --git a/cbfs_poc/module_lol.c b/cbfs_poc/module_lol.c
new file mode 100644
index 0000000..80dc000
--- /dev/null
+++ b/cbfs_poc/module_lol.c
@@ -0,0 +1,25 @@
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <cbfs.h>
+
+#define DRIVER_NAME "cbfs_poc"
+
+static int init_cbfs_poc(void)
+{
+	struct cbfs_header* header;
+	setup_cbfs_from_flash();
+	header = get_cbfs_header();
+	if (header == (void*)0xffffffff)
+		printk("Header not found!\n");
+	else
+		printk("Header found at address %p\n", header);
+	return 0;
+}
+module_init(init_cbfs_poc);
+
+static void exit_cbfs_poc(void)
+{
+}
+module_exit(exit_cbfs_poc);
+
diff --git a/convert2.rb b/convert2.rb
index 85a047c..94e296f 100755
--- a/convert2.rb
+++ b/convert2.rb
@@ -1,5 +1,6 @@
 #!/usr/bin/ruby1.9.1
-$spaces_in_acronym = " "
+$acronym_regex = "."
+#$acronym_regex = "[\w\d_]"
 class Reg
     private
     def valid_bitnumber(current, new)
@@ -33,7 +34,7 @@ class Reg
                     (?'something'\d{1,4})
                 )?
                 \s+
-                (?'acronym'[\w\d_#{$spaces_in_acronym}]+?)
+                (?'acronym'#{$acronym_regex}+?)
                 \s*
                 $
             >
@@ -139,6 +140,7 @@ class Reg
         end
     end
 
+    # FVS = return a table of values
     def fvs value
         @fields.map do |f|
             width = f.start - f.stop + 1
@@ -153,6 +155,22 @@ class Reg
         [longest, longest_name]
     end
 
+    def analyze_and_or andv, orv, stream=$stdout
+        longest, longest_name = find_longest
+        value = orv # yo, lol
+        bits_changed = 0 | ~andv | orv
+
+        for f, fv in @fields.zip fvs(value)
+            width = f.start - f.stop + 1
+            if 0 != (bits_changed >> f.stop) & ((1 << width) - 1)
+                if 0 != ~(bits_changed >> f.stop) & ((1 << width) - 1)
+                  stream << "WARNING: some bits not changed in following field!\n"
+                end
+                analyze_one f, fv, longest, longest_name, stream
+            end
+        end
+    end
+
     def analyze value, stream=$stdout
         longest, longest_name = find_longest
 
@@ -200,6 +218,7 @@ require 'trollop'
 
 usage = <<END
 Usage: #{$PROGRAM_NAME} <register dump> <register name or address> <value>
+       #{$PROGRAM_NAME} <register dump> <register name or address> <AND-ed value> <OR-ed value>
        #{$PROGRAM_NAME} <value> < <copy-paste from Xpdf>
 END
 opts = Trollop::options do
@@ -337,5 +356,15 @@ when 3
   end
   value = ARGV[2].to_i 0
   reg.analyze(value)
+when 4
+  data = load_data ARGV[0]
+  reg = reg_from_str(data, ARGV[1], $stdout)
+  unless reg
+    puts
+    exit
+  end
+  andv = ARGV[2].to_i 0
+  orv = ARGV[3].to_i 0
+  reg.analyze_and_or(andv, orv)
 end
 
diff --git a/ddr_plot.c b/ddr_plot.c
new file mode 100644
index 0000000..c41754b
--- /dev/null
+++ b/ddr_plot.c
@@ -0,0 +1,474 @@
+#include <stdint.h>
+#include <stdio.h>
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+#define WL_CALIB_SIZE   28
+enum ddr_speed { DDR_400, DDR_533, DDR_667, DDR_800, DDR_1066 };
+
+static const u16 wl_cntl_calib[4][WL_CALIB_SIZE] = {
+	[DDR_533] = {		// same as 667
+                0x80,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0x80,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0x80,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0x850,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  010100b 14h 24o */
+
+                0x860,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0x870,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  011100b 1ch 34o */
+
+                0x880,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0x910,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  000100b  4h  4o */
+
+                0x920,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  001000b  8h 10o */
+
+                0x930,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xB40,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  010000b 10h 20o */
+
+                0xB50,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  010100b 14h 24o */
+
+                0xB60,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0xB70,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  011100b 1ch 34o */
+
+                0xB80,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0xA10,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  000100b  4h  4o */
+
+                0xA20,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  001000b  8h 10o */
+
+                0xA30,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xC40,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  010000b 10h 20o */
+
+                0xC50,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  010100b 14h 24o */
+
+                0xC60,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0xC70,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  011100b 1ch 34o */
+
+                0xC80,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0xD10,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  000100b  4h  4o */
+
+                0xD20,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  001000b  8h 10o */
+
+                0xD30,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xD40,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  010000b 10h 20o */
+
+                0xD50,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  010100b 14h 24o */
+	},
+	[DDR_800] = {
+                0x60,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0x60,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0x60,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0x83C,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  001111b  fh 17o */
+
+                0x848,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  010010b 12h 22o */
+
+                0x854,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  010101b 15h 25o */
+
+                0x860,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0x90C,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  000011b  3h  3o */
+
+                0x918,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  000110b  6h  6o */
+
+                0x924,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  001001b  9h 11o */
+
+                0xB30,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xB3C,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  001111b  fh 17o */
+
+                0xB48,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  010010b 12h 22o */
+
+                0xB54,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  010101b 15h 25o */
+
+                0xB60,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0xA0C,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  000011b  3h  3o */
+
+                0xA18,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  000110b  6h  6o */
+
+                0xA24,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  001001b  9h 11o */
+
+                0xC30,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xC3C,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  001111b  fh 17o */
+
+                0xC48,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  010010b 12h 22o */
+
+                0xC54,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  010101b 15h 25o */
+
+                0xC60,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0xD0C,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  000011b  3h  3o */
+
+                0xD18,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  000110b  6h  6o */
+
+                0xD24,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  001001b  9h 11o */
+
+                0xD30,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xD3C,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  001111b  fh 17o */
+
+	},
+	[DDR_400] = {
+                0xC0,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  110000b 30h 60o */
+
+                0xC0,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  110000b 30h 60o */
+
+                0xC0,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  110000b 30h 60o */
+
+                0x878,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  011110b 1eh 36o */
+
+                0x890,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  100100b 24h 44o */
+
+                0x8A8,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  101010b 2ah 52o */
+
+                0x8C0,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  110000b 30h 60o */
+
+                0x918,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  000110b  6h  6o */
+
+                0x930,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0x948,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  010010b 12h 22o */
+
+                0xB60,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0xB78,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  011110b 1eh 36o */
+
+                0xB90,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  100100b 24h 44o */
+
+                0xBA8,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  101010b 2ah 52o */
+
+                0xBC0,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  110000b 30h 60o */
+
+                0xA18,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  000110b  6h  6o */
+
+                0xA30,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xA48,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  010010b 12h 22o */
+
+                0xC60,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0xC78,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  011110b 1eh 36o */
+
+                0xC90,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  100100b 24h 44o */
+
+                0xCA8,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  101010b 2ah 52o */
+
+                0xCC0,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  110000b 30h 60o */
+
+                0xD18,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  000110b  6h  6o */
+
+                0xD30,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xD48,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  010010b 12h 22o */
+
+                0xD60,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0xD78,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  011110b 1eh 36o */
+
+	},
+	[DDR_667] = {		// same as 533
+                0x80,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0x80,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0x80,   /* 11:8   WL_CNTRL     0000b  0h  0o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0x850,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  010100b 14h 24o */
+
+                0x860,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0x870,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  011100b 1ch 34o */
+
+                0x880,  /* 11:8   WL_CNTRL     1000b  8h 10o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0x910,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  000100b  4h  4o */
+
+                0x920,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  001000b  8h 10o */
+
+                0x930,  /* 11:8   WL_CNTRL     1001b  9h 11o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xB40,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  010000b 10h 20o */
+
+                0xB50,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  010100b 14h 24o */
+
+                0xB60,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0xB70,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  011100b 1ch 34o */
+
+                0xB80,  /* 11:8   WL_CNTRL     1011b  bh 13o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0xA10,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  000100b  4h  4o */
+
+                0xA20,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  001000b  8h 10o */
+
+                0xA30,  /* 11:8   WL_CNTRL     1010b  ah 12o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xC40,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  010000b 10h 20o */
+
+                0xC50,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  010100b 14h 24o */
+
+                0xC60,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  011000b 18h 30o */
+
+                0xC70,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  011100b 1ch 34o */
+
+                0xC80,  /* 11:8   WL_CNTRL     1100b  ch 14o
+                         *  7:2   WDLL_CNTL  100000b 20h 40o */
+
+                0xD10,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  000100b  4h  4o */
+
+                0xD20,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  001000b  8h 10o */
+
+                0xD30,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  001100b  ch 14o */
+
+                0xD40,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  010000b 10h 20o */
+
+                0xD50,  /* 11:8   WL_CNTRL     1101b  dh 15o
+                         *  7:2   WDLL_CNTL  010100b 14h 24o */
+
+	},
+};
+
+static const u32 wdll_misc_calib[WL_CALIB_SIZE] = {
+
+							// Delay CK[5:3]
+							//       CK_L[5:3]
+/*0*/	0x1200002, 0x1200002, 0x1200002,
+	// 24:24  WLCKDLY              1b  1h   1o
+	// 22:16  WL_PHSEL_MODE  0100000b 20h  40o
+	// 11:8   WL_CNTRL          0000b  0h   0o		0
+	//  7:4   WL_CNTRL_A        0000b  0h   0o
+	//  2:0   WL_CMD_DLY         010b  2h   2o
+
+/*3*/	0x1200902, 0x1200902, 0x1200902, 0x1200902,
+	0x1200902, 0x1200902, 0x1200902,
+	// 24:24  WLCKDLY              1b  1h   1o
+	// 22:16  WL_PHSEL_MODE  0100000b 20h  40o
+	// 11:8   WL_CNTRL          1001b  9h  11o		1/4 CLK
+	//  7:4   WL_CNTRL_A        0000b  0h   0o
+	//  2:0   WL_CMD_DLY         010b  2h   2o
+
+/*10*/	0x1200802, 0x1200802, 0x1200802, 0x1200802,
+	0x1200802, 0x1200802, 0x1200802, 0x1200802,
+	// 24:24  WLCKDLY              1b  1h   1o
+	// 22:16  WL_PHSEL_MODE  0100000b 20h  40o
+	// 11:8   WL_CNTRL          1000b  8h  10o		1/2 CLK
+	//  7:4   WL_CNTRL_A        0000b  0h   0o
+	//  2:0   WL_CMD_DLY         010b  2h   2o
+
+/*18*/	0x1200B02, 0x1200B02, 0x1200B02, 0x1200B02,
+	0x1200B02, 0x1200B02, 0x1200B02, 0x1200B02,
+	// 24:24  WLCKDLY              1b  1h   1o
+	// 22:16  WL_PHSEL_MODE  0100000b 20h  40o
+	// 11:8   WL_CNTRL          1011b  bh  13o		3/4 CLK
+	//  7:4   WL_CNTRL_A        0000b  0h   0o
+	//  2:0   WL_CMD_DLY         010b  2h   2o
+
+/*26*/	0x1200C02, 0x1200C02,
+	// 24:24  WLCKDLY              1b  1h   1o
+	// 22:16  WL_PHSEL_MODE  0100000b 20h  40o
+	// 11:8   WL_CNTRL          1100b  ch  14o		1 CLK
+	//  7:4   WL_CNTRL_A        0000b  0h   0o
+	//  2:0   WL_CMD_DLY         010b  2h   2o
+
+};
+
+static const int freq_to_int[] = {
+	[DDR_800] = 800,
+	[DDR_667] = 667,
+	[DDR_533] = 533,
+	[DDR_400] = 400,
+};
+
+static const int ck_period[] = { /* clock period in 10*picoseconds */
+	[DDR_800] = 250, /* 2.5ns  */
+	[DDR_667] = 300, /* 3ns    */
+	[DDR_533] = 375, /* 3.75ns */
+	[DDR_400] = 500, /* 5ns    */
+};
+
+#define WL_CNTRL(a) (((a)>>8)&0xf)
+#define WDLL_CNTRL(a) (((a)>>2)&0x3f)
+#define debug printf
+
+static double delay(u8 wl_cntrl, double wdll_dly, double clk)
+{
+	if (((wl_cntrl >> 3) & 1) == 0) return 0;
+
+	switch (wl_cntrl) {
+	case 8:    return wdll_dly;
+	case 0x9:  debug("WILD GUESS... "); return 0.25*clk+wdll_dly;
+	case 0xb:  return 0.25*clk+wdll_dly;
+	case 0xa:  debug("WILD GUESS... "); return 0.5*clk+wdll_dly;
+	case 0xc:  return 0.5*clk+wdll_dly;
+	case 0xd:  return 0.75*clk+wdll_dly;
+	case 0x19: return 0.25*clk;
+	case 0x18: return 0.5*clk;
+	case 0x1b: return 0.75*clk;
+	case 0x1c: return clk;
+	}
+
+	return 42424242;
+}
+
+#define MASTCNTL(speed) ((speed) == DDR_400 ? 6 : (speed) == DDR_533 ? 4 : (speed) == DDR_667 ? 4 : /* DDR_800 */ 3 )
+static double wdll_dly(u8 wdll_cntrl, double clk, int mastcntl)
+{
+	double delay_uncomp = 100;
+	double delay_element = (0.25*clk - delay_uncomp) / (mastcntl + 0.5);
+	return (delay_element * wdll_cntrl) / 8;
+}
+
+int main(void)
+{
+	int i;
+	int f;
+	FILE *fi;
+	char fname[10];
+
+	for (f = 0; f < 4; f++) {
+		sprintf(fname, "%d.dat", freq_to_int[f]);
+		fi = fopen(fname, "w");
+		for (i = 0; i < WL_CALIB_SIZE; i++) {
+			u32 wl_cntl = wl_cntl_calib[f][i];
+			u32 wdll_misc = wdll_misc_calib[i];
+			u8 wdll_misc_wl_cntrl = (wdll_misc >> 8) & 0xf;
+			u8 wl_cntrl = WL_CNTRL(wl_cntl);
+			u8 wdll_cntrl = WDLL_CNTRL(wl_cntl);
+			int clk = ck_period[f]*10;
+			double dly = wdll_dly(wdll_cntrl, clk, MASTCNTL(f));
+			printf("%d WL_CNTRL=%x WDLL_CNTRL=%02x CLK=%d WDLL_DLY=%lf delay=%lf\n", i,
+					wl_cntrl, wdll_cntrl, clk, dly,
+					delay(wl_cntrl, dly, clk));
+			if (wl_cntrl != wdll_misc_wl_cntrl)
+				printf("WARNING: WDLL_MISC.WL_CNTRL=%x\n", wdll_misc_wl_cntrl);
+			fprintf(fi, "%d %lf\n", i, delay(wl_cntrl, dly, clk));
+		}
+		fclose(fi);
+	}
+}
diff --git a/extract.rb b/extract.rb
new file mode 100644
index 0000000..bc89c35
--- /dev/null
+++ b/extract.rb
@@ -0,0 +1,19 @@
+$begin = /BEGIN MAC REGISTER DUMP/
+$end = /END MAC REGISTER DUMP/
+def name
+  base = ARGF.path
+  i = 0
+  loop do
+    name = "#{base}.#{i}"
+    return name unless File.exists? name
+    i += 1
+  end
+end
+
+f = nil
+while gets
+  (f.close; f = nil) if ~$end
+  f << $_ if f
+  f = File.open name, 'w' if ~$begin
+end
+
diff --git a/power_sequence_state_diagram.dia b/power_sequence_state_diagram.dia
index 7fcc8fb..16ab5a0 100644
--- a/power_sequence_state_diagram.dia
+++ b/power_sequence_state_diagram.dia
diff --git a/regs/PHY_00 b/regs/PHY_00
new file mode 100644
index 0000000..0fc239e
--- /dev/null
+++ b/regs/PHY_00
@@ -0,0 +1,12 @@
+ 15         Reset
+ 14         Loopback
+13 Speed Select (LSB)
+12 Auto-Negotia- tion Enable
+ 11         Power Down
+ 10         Isolate
+   9         Restart Copper Auto-Negotiation
+   8         Copper Duplex Mode
+   7         Collision Test
+6          Speed Selec- tion (MSB)
+5:0        Reserved
+
diff --git a/regs/PHY_01 b/regs/PHY_01
new file mode 100644
index 0000000..585dd2c
--- /dev/null
+++ b/regs/PHY_01
@@ -0,0 +1,17 @@
+ 15         100BASE-T4
+ 14         100BASE-X Full-duplex
+ 13         100BASE-X Half-duplex
+   12        10 Mbps Full- duplex
+   11        10 Mbps Half- duplex
+   10        100BASE-T2 Full-duplex
+   9         100BASE-T2 Half-duplex
+   8         Extended Sta- tus
+   7         Reserved
+   6         MF Preamble Suppression
+5          Copper Auto- Negotiation Complete
+4          Copper Remote Fault
+3          Auto- Negotiation Ability
+2          Copper Link Status
+1          Jabber Detect
+0          Extended Capability
+
diff --git a/regs/PHY_04 b/regs/PHY_04
new file mode 100644
index 0000000..ac05cbf
--- /dev/null
+++ b/regs/PHY_04
@@ -0,0 +1,13 @@
+   15        Next Page
+   14        Ack
+   13        Remote Fault
+   12        Reserved
+ 11         Asymmetric Pause
+ 10         Pause
+ 9          100BASE-T4
+8 100BASE-TX Full-duplex
+7 100BASE-TX Half-duplex
+6 10BASE-TX Full-duplex
+ 5          10BASE-TX Half-duplex
+ 4:0        Selector Field
+
diff --git a/regs/PHY_05 b/regs/PHY_05
new file mode 100644
index 0000000..069d90d
--- /dev/null
+++ b/regs/PHY_05
@@ -0,0 +1,14 @@
+  15        Next Page
+  14        Acknowledge
+  13        Remote Fault
+  12        Technology Ability Field
+  11        Asymetric Pause
+  10        Pause Capable
+  9         100BASE-T4 Capability
+  8         100BASE-TX Full-duplex Capability
+7          100BASE-TX Half-duplex Capability
+6          10BASE-T Full-duplex Capability
+5          10BASE-T Half-duplex Capability
+4:0        Selector Field
+
+
diff --git a/regs/PHY_06 b/regs/PHY_06
new file mode 100644
index 0000000..1904ba0
--- /dev/null
+++ b/regs/PHY_06
@@ -0,0 +1,6 @@
+   15:5      Reserved
+   4         Parallel Detection Fault
+   3         Link Partner Next page Able
+   2         Local Next Page Able
+   1         Page Received
+   0         Link Partner Auto-Negotiation Able
diff --git a/regs/PHY_07 b/regs/PHY_07
new file mode 100644
index 0000000..3de09e7
--- /dev/null
+++ b/regs/PHY_07
@@ -0,0 +1,7 @@
+15   Next Page
+14   Reserved
+13   Message Page Mode
+12   Acknowledge2
+11   Toggle
+10:0 Message/ Unformatted Field
+
diff --git a/regs/PHY_08 b/regs/PHY_08
new file mode 100644
index 0000000..f974a43
--- /dev/null
+++ b/regs/PHY_08
@@ -0,0 +1,7 @@
+15   Next Page
+14   Acknowledge
+13   Message Page
+12   Acknowledge2
+11   Toggle
+10:0 Message/ Unformatted Field
+
diff --git a/regs/PHY_09 b/regs/PHY_09
new file mode 100644
index 0000000..4e6a2a9
--- /dev/null
+++ b/regs/PHY_09
@@ -0,0 +1,8 @@
+   15:13     Test Mode
+   12        MASTER/ SLAVE Manual Config- uration Enable
+   11        MASTER/ SLAVE Configuration Value
+ 10         Port Type
+ 9          1000BASE-T Full-duplex
+ 8          1000BASE-T Half-duplex
+ 7:0        Reserved
+
diff --git a/regs/PHY_10 b/regs/PHY_10
new file mode 100644
index 0000000..6c1c4c9
--- /dev/null
+++ b/regs/PHY_10
@@ -0,0 +1,9 @@
+  15        MASTER/ SLAVE Configuration Fault
+  14        MASTER/ SLAVE Configuration Resolution
+  13        Local Receiver Status
+  12        Remote Receiver Status
+  11        Link Partner 1000BASE-T Full-Duplex Capability
+  10        Link Partner 1000BASE-T Half-Duplex Capability
+  9:8       Reserved
+  7:0       Idle Error Count
+
diff --git a/regs/PHY_15 b/regs/PHY_15
new file mode 100644
index 0000000..9f0b878
--- /dev/null
+++ b/regs/PHY_15
@@ -0,0 +1,6 @@
+   15        1000BASE-X Full-duplex
+   14        1000BASE-X Half-duplex
+   13        1000BASE-T Full-duplex
+   12        1000BASE-T Half-duplex
+   11:0      Reserved
+
diff --git a/regs/PHY_specific_control_reg b/regs/PHY_16_PHY_specific_control_reg
index 776e502..776e502 100644
--- a/regs/PHY_specific_control_reg
+++ b/regs/PHY_16_PHY_specific_control_reg
diff --git a/regs/PHY_specific_status_reg b/regs/PHY_17_specific_status_reg
index c061bb3..c061bb3 100644
--- a/regs/PHY_specific_status_reg
+++ b/regs/PHY_17_specific_status_reg
diff --git a/regs/PHY_18 b/regs/PHY_18
new file mode 100644
index 0000000..85174d1
--- /dev/null
+++ b/regs/PHY_18
@@ -0,0 +1,17 @@
+ 15         Auto-Negotia- tion Error Inter- rupt Enable
+ 14         Speed Changed Interrupt Enable
+ 13         Duplex Changed Interrupt Enable
+ 12         Page Received Interrupt Enable
+ 11         Auto-Negotia- tion Completed Interrupt Enable
+ 10         Link Status Changed Interrupt Enable
+ 9          Symbol Error Interrupt Enable
+   8          False Carrier Interrupt Enable
+   7          FIFO Over/ Underflow Interrupt Enable
+   6          MDI Crossover Changed Interrupt Enable
+   5          Downshift Inter- rupt Enable
+   4          Energy Detect Interrupt Enable
+   3          Reserved
+   2          DTE power detection sta- tus changed interrupt enable
+   1          Polarity Changed Interrupt Enable
+   0          Jabber Interrupt Enable
+
diff --git a/regs/PHY_19 b/regs/PHY_19
new file mode 100644
index 0000000..57ae3e0
--- /dev/null
+++ b/regs/PHY_19
@@ -0,0 +1,16 @@
+  15        Auto- Negotiation Error
+  14        Speed Changed
+  13        Duplex Changed
+  12        Page Received
+  11        Auto- Negotiation Completed
+  10        Link Status Changed
+  9         Symbol Error
+  8         False Carrier
+  7         FIFO Over/ Underflow
+  6         MDI Crossover Changed
+  5         Downshift Inter rupt
+  4         Energy Detect Changed
+  3         Reserved
+  2         DTE power detection sta- tus changed interrupt
+  1         Polarity Changed
+  0         Jabber
diff --git a/regs/Ext_PHY_specific_control_reg b/regs/PHY_20_Ext_PHY_specific_control_reg
index a13fb8e..a13fb8e 100644
--- a/regs/Ext_PHY_specific_control_reg
+++ b/regs/PHY_20_Ext_PHY_specific_control_reg