diff options
| author | Noe Rubinstein <nrubinstein@avencall.com> | 2012-04-02 11:30:19 +0200 |
|---|---|---|
| committer | Noe Rubinstein <nrubinstein@avencall.com> | 2012-04-02 11:30:19 +0200 |
| commit | 9fa99a6f9e885c4e618f68a4498eccc6a91ba29a (patch) | |
| tree | 1ea25cc05e74610bc42f1f0c05a6b60b99295c20 | |
| parent | 2d87b59fdded1589ba0372abb147673f05bd65f6 (diff) | |
parse datasheets: YAML support
| -rw-r--r-- | parse_datasheet/output/gbe.yaml | 5820 | ||||
| -rw-r--r-- | parse_datasheet/output/smrbase.yaml | 2609 | ||||
| -rwxr-xr-x | parse_datasheet/parse_320066.py | 13 |
3 files changed, 8440 insertions, 2 deletions
diff --git a/parse_datasheet/output/gbe.yaml b/parse_datasheet/output/gbe.yaml new file mode 100644 index 0000000..9f411dc --- /dev/null +++ b/parse_datasheet/output/gbe.yaml @@ -0,0 +1,5820 @@ +AIT: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: AIFS + description: [Adaptive IFS Value, 'Adaptive IFS throttles back-to-back transmissions + in the transmit packet buffer and delays their transfer to the CSMA/CD transmit + function. Normally, this register should be set to 0b. However, if additional + delay is desired between back-to-back transmit packets, then this register + can be set with a value greater than zero (0). This feature can be helpful + in high collision half-duplex environments.', 'In order for AIFS to take effect + it should be larger than the minimum IFS value defined in IEEE 802.3 standard. + AIFS has no effect on transmissions that occur immediately after receives + or transmissions that are not back-to-back. In addition, it has no effect + on re-transmission timing (retransmission after collisions).', 'The AIFS value + is additive to the TIPG.IPGT value. ', 'This time unit for this value is speed + dependent:', 1000Mbps is 8ns, '100Mbps is 80ns ', 10 Mbps is 800ns] + range: [15, 0] + reset: 0 + sticky: '' + offset: 1112 + offset_end: [1115, null] + offset_start: [1112, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: AIT + reg_name: AIT + size: 32 + table_ref: 37-69 + title_desc: Adaptive IFS Throttle Register + view: PCI 3 +ALGNERRC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: ALGNERRC + description: [Alignment error count] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16388 + offset_end: [16391, null] + offset_start: [16388, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: ALGNERRC + reg_name: ALGNERRC + size: 32 + table_ref: 37-80 + title_desc: Alignment Error Count Register + view: PCI 3 +BPRC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: BPRC + description: [Number of broadcast packets received] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16504 + offset_end: [16507, null] + offset_start: [16504, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: BPRC + reg_name: BPRC + size: 32 + table_ref: 37-104 + title_desc: Broadcast Packets Received Count Register + view: PCI 3 +BPTC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: BPTC + description: [Number of broadcast packets transmitted count] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16628 + offset_end: [16631, null] + offset_start: [16628, null] + power_well: null + recurring: null + reg_base_name: BPTC + reg_name: BPTC + size: 32 + table_ref: 37-128 + title_desc: Broadcast Packets Transmitted Count Register + view: PCI 3 +CEXTERR: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: CEXTERR + description: [Number of packets received with a carrier extension error.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16444 + offset_end: [16447, null] + offset_start: [16444, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: CEXTERR + reg_name: CEXTERR + size: 32 + table_ref: 37-90 + title_desc: Carrier Extension Error Count Register + view: PCI 3 +COLC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: COLC + description: [Total number of collisions experienced by the transmitter] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16424 + offset_end: [16427, null] + offset_start: [16424, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: COLC + reg_name: COLC + size: 32 + table_ref: 37-87 + title_desc: Collision Count Register + view: PCI 3 +CRCERRS: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: CRCERRS + description: [CRC error count] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16384 + offset_end: [16387, null] + offset_start: [16384, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: CRCERRS + reg_name: CRCERRS + size: 32 + table_ref: 37-79 + title_desc: CRC Error Count Register + view: PCI 3 +CTRL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 2569 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 31] + reset: 0 + sticky: '' + - access: RW + acronym: VME + description: [VLAN Mode Enable., '0 = VLAN Mode Disabled.1 = VLAN Mode Enabled. + All packets transmitted have an 802.1q header added to the packet. The contents + of the header come from the transmit descriptor and from the VLAN type register. + On receive, VLAN information is stripped from 802.1q packets. See "802.1q + VLAN Support" on page 1400 for more details.'] + range: [30, 30] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [29, 29] + reset: 0 + sticky: '' + - access: RW + acronym: TFCE + description: [Transmit Flow Control Enable., '0 = Transmit Flow Control Disabled.1 + = Transmit Flow Control Enabled. Flow control packets (XON & XOFF frames) + will be transmitted based on receiver fullness. If Auto-Negotiation is enabled, + this bit is set to the negotiated duplex value. See "Physical Layer Auto-Negotiation + & Link Setup Features" on page 1394 for more information about Auto-Negotiation.'] + range: [28, 28] + reset: 0 + sticky: '' + - access: RW + acronym: RFCE + description: [Receive Flow Control Enable., '0 = Receive Flow Control Disabled.1 + = Receive Flow Control Enabled. Indicates the device will respond to the reception + of flow control packets. Reception of flow control packets requires the correct + loading of the FCAH/FCAL & FCT registers. If Auto-Negotiation is enabled, + this bit is set to the negotiated duplex value. See "Physical Layer Auto-Negotiation + & Link Setup Features" on page 1394 for more information about Auto-Negotiation.'] + range: [27, 27] + reset: 0 + sticky: '' + - access: RW + acronym: RST + description: ['Device Reset, also referred to as a "Soft Reset". Normally 0, writing + 1 initiates the reset. This bit is self clearing.', 'CTRL.RST may be used + to globally reset the entire GbE hardware. This register is provided primarily + as a last-ditch software mechanism to recover from an indeterminate or suspected + hung hardware state. Most registers (receive, transmit, interrupt, statistics, + etc.), and state machines will be set to their power-on reset values, approximating + the state following a power-on or Unit Reset. However, the Packet Buffer Allocation + Register (PBA) retains its value through a global reset.Note:Software must + first disable both transmit & receive operation using the TCTL.EN and RCTL.EN + register bits before asserting CTRL.RST. To ensure that the global device + reset has fully completed and that the controller will respond to subsequent + accesses, software must wait a minimum of 5 milliseconds after setting CTRL.RST + before attempting to check if the bit has cleared or to access any other GbE + device register.'] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 21] + reset: 0 + sticky: '' + - access: RW + acronym: ADVD3WUC + description: ['D3Cold WakeUp Capability Advertisement Enable. ', 'When set, D3Cold + wakeup capability may be advertised based on whether the AUX_PWR pin advertises + presence of auxiliary power (see section 2.13.3 for details). When 0, D3Cold + wakeup capability will not be advertised even if AUX_PWR presence is indicated. + Formerly used as SDP2 pin data value, initial value is EEPROM-configurable', + '*Note that this bit is loaded from the EEPROM, if present'] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [19, 13] + reset: 0 + sticky: '' + - access: RW + acronym: FRCDPLX + description: [Force Duplex., '0 = Mode is Full-Duplex, regardless of the FD setting.1 + =CTRL.FD bit sets duplex mode.'] + range: [12, 12] + reset: 0 + sticky: '' + - access: RW + acronym: FRCSPD + description: [Force Speed., '0 = Default of 1Gbps is used to set the MAC speed. + See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for + more details.1 =CTRL.SPEED bits set the MAC speed.Note:This bit is superseded + by the CTRL_EXT.SPD_BYPS bit which has a similar function.Note:*Note that + this bit is loaded from the EEPROM, if present'] + range: [11, 11] + reset: 1 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [10, 10] + reset: 0 + sticky: '' + - access: RW + acronym: SPEED + description: [Speed selection., 'These bits are written by software (assuming, + after reading the PHY registers through the MDIO interface) to set the MAC + speed configuration. See "Physical Layer Auto-Negotiation & Link Setup Features" + on page 1394 for details.', '? 00 => 10 Mbps', '? 01 => 100 Mbps', '? 10 => + 1000 Mbps', '? 11 => reservedNote:These bits affect the MAC speed setting + only if CTRL_EXT.SPD_BYPS or CTRL.FRCSPD are used.'] + range: [9, 8] + reset: 2 + sticky: '' + - access: RV + acronym: Reserved + description: [Reserved] + range: [7, 7] + reset: 0 + sticky: '' + - access: RW + acronym: SLU + description: [Set Link Up., 'SLU must be set to ''1'' to enable the MAC. This + bit may also be initialized by the APME bit in the EEPROM Initialization Control + Word3, if an EEPROM is used.'] + range: [6, 6] + reset: 0 + sticky: '' + - access: RW + acronym: Rsvd + description: [Reserved. Must be set to 0.] + range: [5, 5] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [4, 4] + reset: 0 + sticky: '' + - access: RW + acronym: Rsvd + description: [Reserved] + range: [3, 3] + reset: 1 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: Rsvd + description: [Reserved. Must write '0' to this bit.1 =] + range: [1, 1] + reset: 0 + sticky: '' + - access: RW + acronym: FD + description: [Full Duplex. Controls the MAC duplex setting., 0 = Half Duplex1 + = Full Duplex, 'In half-duplex mode, EP80579''s GbE transmits carrier extended + packets and can receive both carrier extended packets, and packets transmitted + with bursting.', '*Note that this bit is loaded from the EEPROM, if present'] + range: [0, 0] + reset: 1 + sticky: '' + offset: 0 + offset_end: [3, null] + offset_start: [0, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: CTRL + reg_name: CTRL + size: 32 + table_ref: 37-25 + title_desc: Device Control Register + view: PCI 3 +CTRL_AUX: + bar: CSRBAR + bus_device_function: M:2:0 + default: 256 + description: null + fields: + - access: RO + acronym: RSVD + description: [Reserved] + range: [31, 18] + reset: 0 + sticky: '' + - access: RW + acronym: RMII_LOG_FIX + description: [Enable logic change to fix RMII 100mbps TX dropped packet data., + 'To enable this mode of operation, set this bit to a ''1''. When enabled, the + fix modifies the legacy new-packet signalling logic in the transmit path to + prevent the first 8 bytes of packet data from being dropped when operating + in RMII mode and a line speed of 100mbps.'] + range: [17, 17] + reset: 0 + sticky: '' + - access: RW + acronym: RMII_FREQ_FIX + description: [Disable DMA frequency change to fix RMII 100mbps TX dropped packet + data., 'This is the default mode of operation. ', 'To disable this mode of + operation, set this bit to a ''1''. This must be disabled if FIX2 is enabled.', + 'When enabled, sets the DMA clock frequency to 50MHz when operating in RMII + mode. This produces a favorable frequency ratio between DMA and MAC clocks + that prevents the first 8 bytes of transmit packet data from being dropped + when operating in RMII mode and a line speed of 100mbps.'] + range: [16, 16] + reset: 0 + sticky: '' + - access: RO + acronym: RSVD + description: [Reserved] + range: [15, 12] + reset: 0 + sticky: '' + - access: RW + acronym: END_SEL + description: [Selects whether the descriptor or packet data is controlled by endianness + configuration., 00 - descriptor and packet transfers use CTRL_AUX.ENDIANESS, + '01 - descriptor uses CTL_AUX.ENDIANESS, packet uses default', '10 - descriptor + uses default, packet uses CTRL_AUX.ENDIANESS', 11 - all transfers use CTRL_AUX.ENDIANESS] + range: [11, 10] + reset: 0 + sticky: '' + - access: RW + acronym: ENDIANESS + description: ['Endianness:', 'These bits control the endianness of the data in + memory. These settings apply to all internal bus transactions, including packet + data and descriptors', '''00'' - LW Little--Endian, Byte Big-Endian ', '''01'' + - LW Little-Endian, Byte Little-Endian (default)', '''10'' - LW Big-Endian, + Byte Big-Endian', '''11'' - LW Big-Endian, Byte Little-Endian', 'Refer to + Section 37.5.14, "Endianness" for further details.'] + range: [9, 8] + reset: 1 + sticky: '' + - access: RO + acronym: RSVD + description: [Reserved] + range: [7, 1] + reset: 0 + sticky: '' + - access: RW + acronym: RGMII_RMII + description: [RGMII/RMII Translation Gasket Select, '? ''0'' - RGMII', '? ''1'' - RMII'] + range: [0, 0] + reset: 0 + sticky: '' + offset: 224 + offset_end: [227, null] + offset_start: [224, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: CTRL_AUX + reg_name: CTRL_AUX + size: 32 + table_ref: 37-28 + title_desc: Auxiliary Device Control Register + view: PCI 3 +CTRL_EXT: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 25] + reset: 0 + sticky: '' + - access: RW + acronym: RMII_RX_MODE + description: ['RMII gasket receive mode select:', '0 = For proper 100mbps receive + operation, after assertion of the RMII CRS_DV signal on GBEn_RXCTL, the RMII + gasket requires that a minimum of two di-bits of ''00'' appear on GBEn_RXDATA[1:0] + before the preamble appears.1 = For proper 100mbps receive operation, the + RMII gasket requires that CRS_DV be asserted on GBEn_RXCTL synchronously with + GBE_REFCLK_RMII and on the same cycle in which the first di-bit of the preamble + appears on GBEn_RXDATA[1:0].', '0 is the default value of this bit and makes + the RMII gasket compatible with RMII PHYs that assert CRS_DV as soon as the + receive medium is non-idle, and subsequently drive ''00'' on RXD[1:0] until + proper receive signal decoding has been achieved (per the RMII Specification, + Revision 1.2).', 'Setting this bit to a 1 makes the gasket compatible with + RMII PHYs that assert CRS_DV simultaneously with the start of the preamble + driven on RXD[1:0]. While this CRS_DV signalling mode does not scrictly conform + to the RMII specification, it is provided to allow compatibility with PHY + devices that use this alternate method of asserting CRS_DV at the start of + the packet.', 'This bit must be set to the proper state that corresponds to + the CRS_DV behavior of the attached RMII PHY, otherwise 100mbps packets cannot + be properly received by the GbE.', This bit does not affect transmit operations.] + range: [24, 24] + reset: 0 + sticky: '' + - access: RW + acronym: LINK_MODE + description: [Link Mode. This controls which interface is used to talk to the + link., '? 00 => GMII/MII mode', '? 01 => reserved', '? 10 => reserved', '? + 11 => reserved', '? *Note that this bit is loaded from the EEPROM, if present'] + range: [23, 22] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [21, 16] + reset: 0 + sticky: '' + - access: RW + acronym: SPD_BYPS + description: [Speed Select Bypass., '0 = Normal speed detection mechanisms are + used to determine the speed of the MAC.1 = All speed detection mechanisms + are bypassed and the MAC is immediately set to the setting of CTRL.SPEED.Note:CTRL_EXT.SPD_BYPS + performs a function similar to CTRL.FRCSPD in that the device''s speed settings + are determined by the value software writes to the CTRL.SPEED bits. However, + when using CTRL_EXT.SPD_BYPS the CTRL.SPEED setting takes effect immediately, + when using CTRL.FRCSPD the CTRL.SPEED setting waits until after the device''s + clock switching circuitry performs the change.'] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 14] + reset: 0 + sticky: '' + - access: RW + acronym: EE_RST + description: [EEPROM Reset, Initiates a "reset-like" event to the EEPROM function. + This causes the EEPROM to be read as if a UNIT_RESET had occurred. All device + functions should be disabled prior to setting this bit. This bit is self-clearing., + 'NOTE: this will not cause the controller to detect the EEPROM'] + range: [13, 13] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [12, 12] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [11, 0] + reset: 0 + sticky: '' + offset: 24 + offset_end: [27, null] + offset_start: [24, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: CTRL_EXT + reg_name: CTRL_EXT + size: 32 + table_ref: 37-27 + title_desc: Extended Device Control Register + view: PCI 3 +DC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: DC + description: [Number of defer events.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16432 + offset_end: [16435, null] + offset_start: [16432, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: DC + reg_name: DC + size: 32 + table_ref: 37-88 + title_desc: Defer Count Register + view: PCI 3 +ECOL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: ECOL + description: [Number of packets with more than 16 collisions] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16408 + offset_end: [16411, null] + offset_start: [16408, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: ECOL + reg_name: ECOL + size: 32 + table_ref: 37-84 + title_desc: Excessive Collisions Count Register + view: PCI 3 +EEPROM_CTRL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 00000X1Xh + description: null + fields: + - access: RO + acronym: RSVD + description: [Reserved] + range: [31, 10] + reset: 0 + sticky: '' + - access: RO + acronym: EE_SIZE + description: ['EEPROM Size. ', 0 Reserved, 1 4096-bit (256 word) NM93C66 compatible + EEPROM, 'If an EEPROM is present, this bit indicates its size, based on acknowledges + seen during EEPROM scans of different addresses. ', This bit is read-only., + 'NOTE: this bit will not be updated as a result of anything but a power up reset.'] + range: [9, 9] + reset: null + sticky: '' + - access: RO + acronym: EE_PRES + description: [EEPROM Present, 'This bit attempts to indicate if an EEPROM is present + by monitoring the EE_DO input for a active-low "acknowledge" by the serial + EEPROM during initial EEPROM scan. If no EEPROM is present, the EE_DO line + will remain pulled-high and thus no acknowledge will be seen. ', '1=EEPROM + present; ', 0=no EEPROM., 'NOTE: this bit will not be set except as a result + of EEPROM detection during power up reset.'] + range: [8, 8] + reset: null + sticky: '' + - access: RO + acronym: EE_GNT + description: [Grant EEPROM Access, 'When this bit is 1 the software can access + the EEPROM using the SK, CS, DI, and DO bits.'] + range: [7, 7] + reset: 0 + sticky: '' + - access: RW + acronym: EE_REQ + description: [Request EEPROM Access, The software must write a 1 to this bit to + get direct EEPROM access. It has access when EE_GNT is 1. When the software + completes the access it must write a 0.] + range: [6, 6] + reset: 0 + sticky: '' + - access: RO + acronym: RSVD + description: [Reserved] + range: [5, 4] + reset: 1 + sticky: '' + - access: RO + acronym: EE_DO + description: ['Data Output Bit from the EEPROM. ', The EE_DO input signal is mapped + directly to this bit in the register and contains the EEPROM data output. + This bit is read-only from the software perspective - writes to this bit have + no effect.] + range: [3, 3] + reset: null + sticky: '' + - access: RW + acronym: EE_DI + description: ['Data Input to the EEPROM. ', 'When EE_GNT is 1, the EE_DI output + signal is mapped directly to this bit. Software provides data input to the + EEPROM via writes to this bit.'] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: EE_CS + description: ['Chip Select Input to the EEPROM. ', 'When EE_GNT is 1, the EE_CS + output signal is mapped to the chip select of the EEPROM device. Software + enables the EEPROM by writing a 1 to this bit.'] + range: [1, 1] + reset: 0 + sticky: '' + - access: RW + acronym: EE_SK + description: ['Clock Input to the EEPROM. ', 'When EE_GNT is 1, the EE_SK output + signal is mapped to this bit and provides the serial clock input to the EEPROM. + Software clocks the EEPROM via toggling this bit with successive writes.'] + range: [0, 0] + reset: 0 + sticky: '' + offset: 16 + offset_end: [19, null] + offset_start: [16, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: EEPROM_CTRL + reg_name: EEPROM_CTRL + size: 32 + table_ref: 37-29 + title_desc: EEPROM Control Register + view: PCI 3 +EEPROM_RR: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXX00h + description: null + fields: + - access: RO + acronym: DATA + description: [Read Data, Data returned from the EEPROM read.] + range: [31, 16] + reset: null + sticky: '' + - access: RW + acronym: ADDR + description: [Read Address, This field is written by software along with Start + Read to indicate the word to read.] + range: [15, 8] + reset: null + sticky: '' + - access: RV + acronym: RSVD + description: ['Reserved ', Reads as 0] + range: [7, 5] + reset: 0 + sticky: '' + - access: RO + acronym: DONE + description: [Read Done, Set to 1 when the EEPROM read completes., Set to 0 when + the EEPROM read is in progress., Writes by software are ignored.] + range: [4, 4] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: ['Reserved ', Reads as 0] + range: [3, 1] + reset: 0 + sticky: '' + - access: RW + acronym: START + description: [Start Read, 'Writing a 1 to this bit causes the EEPROM to read a + (16-bit) word at the address stored in the EE_ADDR field, storing the result + in the EE_DATA field. This bit is self-clearing'] + range: [0, 0] + reset: 0 + sticky: '' + offset: 20 + offset_end: [23, null] + offset_start: [20, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: EEPROM_RR + reg_name: EEPROM_RR + size: 32 + table_ref: 37-30 + title_desc: EEPROM Read Register + view: PCI 3 +FCAH: + bar: CSRBAR + bus_device_function: M:2:0 + default: 256 + description: null + fields: + - access: RV + acronym: RSVD + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: FCAH + description: [This register must be programmed with 0x00_00_01_00.] + range: [15, 0] + reset: 256 + sticky: '' + offset: 44 + offset_end: [47, null] + offset_start: [44, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: FCAH + reg_name: FCAH + size: 32 + table_ref: 37-32 + title_desc: Flow Control Address High Register + view: PCI 3 +FCAL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 12746753 + description: null + fields: + - access: RW + acronym: FCAL + description: [This register must be programmed with 0x00C2_8001.] + range: [31, 0] + reset: 12746753 + sticky: '' + offset: 40 + offset_end: [43, null] + offset_start: [40, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: FCAL + reg_name: FCAL + size: 32 + table_ref: 37-31 + title_desc: Flow Control Address Low Register + view: PCI 3 +FCRTH: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RW + acronym: XFCE + description: [External Flow Control Enabled, 0b = Disabled., 1b = Enabled., 'Allows + the Ethernet controller to send XOFF and XON frames based on external pins + XOFF and XON. The transmission of pause frames must be also enabled through + the CTRL.TFCE control bit. When the XOFF signal is asserted high, the Ethernet + controller transmits a single XOFF frame. The assertion of XON (after deassertion + of XOFF) initiates an XON frame transmission, if enabled by FCRTL.XONE. The + assertion/deassertion of XON is required between assertions of XOFF in order + to send another XOFF frame.', This behavior also provides a built-in hysteresis + mechanism., 'Note:The EP80579 does not have external XON/XOFF pins and therefore + does not support external flow control enable. This bit must be set to 0 for + correct operation.'] + range: [31, 31] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [30, 16] + reset: 0 + sticky: '' + - access: RW + acronym: RTH + description: [Receive Threshold High. FIFO high water mark for flow control transmission.] + range: [15, 3] + reset: 0 + sticky: '' + - access: RV + acronym: '0' + description: ['Writes are ignored, reads return 0.'] + range: [2, 0] + reset: 0 + sticky: '' + offset: 8552 + offset_end: [8555, null] + offset_start: [8552, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: FCRTH + reg_name: FCRTH + size: 32 + table_ref: 37-52 + title_desc: Flow Control Receive Threshold High Register + view: PCI 3 +FCRTL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RW + acronym: XONE + description: [XON Enable, 0b = Disabled., 1b = Enabled., 'When set, enables the + Ethernet controller to transmit XON packets based on receive FIFO crosses + FCRTL.RTL threshold value, or based on external pins XOFF and XON. See Section + 37.6.4.3, "FCRTH - Flow Control Receive Threshold High Register" on page 1479'] + range: [31, 31] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [30, 16] + reset: 0 + sticky: '' + - access: RW + acronym: RTL + description: [Receive Threshold Low. FIFO low water mark for flow control transmission.] + range: [15, 3] + reset: 0 + sticky: '' + - access: RV + acronym: '0' + description: ['Writes are ignored, reads return 0.'] + range: [2, 0] + reset: 0 + sticky: '' + offset: 8544 + offset_end: [8547, null] + offset_start: [8544, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: FCRTL + reg_name: FCRTL + size: 32 + table_ref: 37-51 + title_desc: Flow Control Receive Threshold Low Register + view: PCI 3 +FCRUC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: FCRUC + description: [Number of unsupported flow control frames received] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16472 + offset_end: [16475, null] + offset_start: [16472, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: FCRUC + reg_name: FCRUC + size: 32 + table_ref: 37-96 + title_desc: FC Received Unsupported Count Register + view: PCI 3 +FCT: + bar: CSRBAR + bus_device_function: M:2:0 + default: 34824 + description: This register must be programmed with 0x00_00_88_0 + fields: + - access: RV + acronym: RSVD + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: FCT + description: [This register must be programmed with 0x00_00_88_08.] + range: [15, 0] + reset: 34824 + sticky: '' + offset: 48 + offset_end: [51, null] + offset_start: [48, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: FCT + reg_name: FCT + size: 32 + table_ref: 37-33 + title_desc: Flow Control Type Register + view: PCI 3 +FCTTV: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: TTV + description: [Transmit Timer Value to be included in XOFF frame.] + range: [15, 0] + reset: 0 + sticky: '' + offset: 368 + offset_end: [371, null] + offset_start: [368, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: FCTTV + reg_name: FCTTV + size: 32 + table_ref: 37-35 + title_desc: Flow Control Transmit Timer Value Register + view: PCI 3 +FFLT[0-3]: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: RSVD + description: [Reserved] + range: [31, 11] + reset: 0 + sticky: '' + - access: RW + acronym: FFLT_LENx + description: [Flexible Filter Length for FIlter x] + range: [10, 0] + reset: 0 + sticky: '' + offset: 24320 + offset_end: [24323, 8] + offset_start: [24320, 8] + power_well: null + recurring: 4 + reg_base_name: FFLT + reg_name: FFLT[0-3] + size: 32 + table_ref: 37-140 + title_desc: Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW) + view: PCI 3 +FFMT[0-127]: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0000000Xh + description: null + fields: + - access: RV + acronym: RSVD + description: [Reserved] + range: [31, 4] + reset: 0 + sticky: '' + - access: RW + acronym: Mask_x + description: [Byte Mask for Byte xx] + range: [3, 0] + reset: null + sticky: '' + offset: 36864 + offset_end: [36867, 8] + offset_start: [36864, 8] + power_well: null + recurring: 128 + reg_base_name: FFMT + reg_name: FFMT[0-127] + size: 32 + table_ref: 37-142 + title_desc: Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW) + view: PCI 3 +FFVT[0-127]: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXXXh + description: null + fields: + - access: RW + acronym: VAL3 + description: [Byte x Compare Value 3] + range: [31, 24] + reset: null + sticky: '' + - access: RW + acronym: VAL2 + description: [Byte x Compare Value 2] + range: [23, 16] + reset: null + sticky: '' + - access: RW + acronym: VAL1 + description: [Byte x Compare Value 1] + range: [15, 8] + reset: null + sticky: '' + - access: RW + acronym: VAL0 + description: [Byte x Compare Value 0] + range: [7, 0] + reset: null + sticky: '' + offset: 38912 + offset_end: [38915, 8] + offset_start: [38912, 8] + power_well: null + recurring: 128 + reg_base_name: FFVT + reg_name: FFVT[0-127] + size: 32 + table_ref: 37-144 + title_desc: Flexible Filter Value Table Registers + view: PCI 3 +GORCH: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: GORCH + description: [Number of good octets received - upper 4 bytes] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16524 + offset_end: [16527, null] + offset_start: [16524, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: GORCH + reg_name: GORCH + size: 32 + table_ref: 37-108 + title_desc: Good Octets Received Count High Register + view: PCI 3 +GORCL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: GORCL + description: [Number of good octets received - lower 4 bytes] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16520 + offset_end: [16522, null] + offset_start: [16520, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: GORCL + reg_name: GORCL + size: 32 + table_ref: 37-107 + title_desc: Good Octets Received Count Low Register + view: PCI 3 +GOTCH: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: GOTCH + description: [Number of good octets transmitted - upper 4 bytes] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16532 + offset_end: [16535, null] + offset_start: [16532, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: GOTCH + reg_name: GOTCH + size: 32 + table_ref: 37-110 + title_desc: Good Octets Transmitted Count High Register + view: PCI 3 +GOTCL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: GOTCL + description: [Number of good octets transmitted - lower 4 bytes] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16528 + offset_end: [16531, null] + offset_start: [16528, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: GOTCL + reg_name: GOTCL + size: 32 + table_ref: 37-109 + title_desc: Good Octets Transmitted Count Low Register + view: PCI 3 +GPRC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: GPRC + description: [Number of good packets received (total of all lengths)] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16500 + offset_end: [16503, null] + offset_start: [16500, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: GPRC + reg_name: GPRC + size: 32 + table_ref: 37-103 + title_desc: Good Packets Received Count (Total) Register + view: PCI 3 +GPTC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: GPTC + description: [Number of good packets transmitted] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16512 + offset_end: [16515, null] + offset_start: [16512, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: GPTC + reg_name: GPTC + size: 32 + table_ref: 37-106 + title_desc: Good Packets Transmitted Count Register + view: PCI 3 +ICR0: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: RSVD + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_INTBUS + description: ['Internal Bus Error. ', 'This bit indicates that an error occurred + during either a Target or Host transaction on the bus. Refer to Section 37.5.12, + "Error Handling" for complete details.', The details of this error are reported + in the INTBUS_ERR_STAT register.] + range: [28, 28] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_STAT + description: ['Statistic Register ECC Error. The Statistic Registers are implemented + using a memory that uses a single-bit correct/multi-bit detect ECC parity + algorithm to protect it. This bit indicates that a multi-bit error has occurred + on a read from that memory. No indication of a single-bit error correction + will be given by hardware.Note:If this interrupt asserts, further GbE DMA + Reads and Writes are blocked until software issues a soft reset to the GbE + by writing the Device Control Register (CTRL.RST)'] + range: [27, 27] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_MCFSPF + description: ['This bit indicates that either a Multicast Filter Parity Error, + Special Packet Filter Parity Error or a Flex Filter Parity Error occurred. + These filters use parity protected SRAMs for data buffers. This bit indicates + that a parity error has occurred on a read from either of these data buffers. + This error is considered non-fatal and will clear after a read of the MEM_ERR_STAT + register.'] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_PB + description: ['DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses + a single-bit correct/multi-bit detect ECC parity algorithm to protect the + SRAM it uses for data. This bit indicates that a multi-bit error has occurred + on a read from that SRAM. No indication of a single-bit error correction will + be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads + and Writes are blocked until software issues a soft reset to the GbE by writing + the Device Control Register (CTRL.RST)'] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_TXDS + description: ['DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor + Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to + protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit + error has occurred on a read from that data buffer. No indication of a single-bit + error correction will be given by hardware. Note:If this interrupt asserts, + further GbE DMA Reads and Writes are blocked until software issues a soft + reset to the GbE by writing the Device Control Register (CTRL.RST)'] + range: [21, 21] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_RXDS + description: ['DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor + Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to + protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit + error has occurred on a read from that data buffer. No indication of a single-bit + error correction will be given by hardware. Note:If this interrupt asserts, + further GbE DMA Reads and Writes are blocked until software issues a soft + reset to the GbE by writing the Device Control Register (CTRL.RST)'] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [19, 17] + reset: 0 + sticky: '' + - access: RCWC + acronym: SRPD + description: [Small Receive Packet Detected., Indicates that a packet of size RSRPD.SIZE + register has been detected and transferred to host memory. The interrupt is + only asserted if RSRPD.SIZE register has a non-zero value] + range: [16, 16] + reset: 0 + sticky: '' + - access: RCWC + acronym: TXD_LOW + description: [Transmit Descriptor Low Threshold hit. Indicates that the descriptor + ring has reached the threshold specified in "TXDCTL - Transmit Descriptor + Control Register" on page 1500.] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 8] + reset: 0 + sticky: '' + - access: RCWC + acronym: RXT0 + description: ['Receiver Timer Interrupt. Set when the timers expire, see "Receive + Interrupts" on page 1360 for details.'] + range: [7, 7] + reset: 0 + sticky: '' + - access: RCWC + acronym: RXO + description: [Receiver Overrun. Set on receive data FIFO overrun. Could be caused + either because there are no available buffers or because Internal Bus receive + bandwidth is inadequate.] + range: [6, 6] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [5, 5] + reset: 0 + sticky: '' + - access: RCWC + acronym: RXDMT0 + description: [Receive Descriptor Minimum Threshold Hit. Indicates that the minimum + number of receive descriptors are available and software should load more + receive descriptors.] + range: [4, 4] + reset: 0 + sticky: '' + - access: RCWC + acronym: Rsvd + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [2, 2] + reset: 0 + sticky: '' + - access: RCWC + acronym: TXQE + description: [Transmit Queue Empty. Set when the last descriptor block for a transmit + queue has been used.] + range: [1, 1] + reset: 0 + sticky: '' + - access: RCWC + acronym: TXDW + description: ['Transmit Descriptor Written Back. Set when hardware processes a + descriptor with its RS bit set. If using delayed interrupts (TDESC.IDE is + set in the Transmit Descriptor CMD), the interrupt is delayed until after + one of the delayed-timers (TIDV or TADV) expires.'] + range: [0, 0] + reset: 0 + sticky: '' + offset: 192 + offset_end: [195, null] + offset_start: [192, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: ICR0 + reg_name: ICR0 + size: 32 + table_ref: 37-37 + title_desc: Interrupt 0 Cause Read Register + view: PCI 3 +ICR1: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: RSVD + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_INTBUS + description: ['Internal Bus Error. ', 'This bit indicates that an error occurred + during either a Target or Host transaction on the bus. Refer to Section 37.5.12, + "Error Handling" for complete details.', The details of this error are reported + in the INTBUS_ERR_STAT register.] + range: [28, 28] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_STAT + description: ['Statistic Register ECC Error. The Statistic Registers are implemented + using a memory that uses a single-bit correct/multi-bit detect ECC parity + algorithm to protect it. This bit indicates that a multi-bit error has occurred + on a read from that memory. No indication of a single-bit error correction + will be given by hardware.Note:If this interrupt asserts, further GbE DMA + Reads and Writes are blocked until software issues a soft reset to the GbE + by writing the Device Control Register (CTRL.RST)'] + range: [27, 27] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_MCFSPF + description: [Multicast Filter Parity Error/Special Packet Filter Parity Error. + The Multicast Filter and Special Packets Filter use parity protected SRAMs + for data buffers. This bit indicates that a parity error has occurred on a + read from either of these data buffers. This error is considered non-fatal + and will clear after a read of the MEM_ERR_STAT register.] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_PB + description: ['DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses + a single-bit correct/multi-bit detect ECC parity algorithm to protect the + SRAM it uses for data. This bit indicates that a multi-bit error has occurred + on a read from that SRAM. No indication of a single-bit error correction will + be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads + and Writes are blocked until software issues a soft reset to the GbE by writing + the Device Control Register (CTRL.RST).'] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_TXDS + description: ['DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor + Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to + protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit + error has occurred on a read from that data buffer. No indication of a single-bit + error correction will be given by hardware. Note:If this interrupt asserts, + further GbE DMA Reads and Writes are blocked until software issues a soft + reset to the GbE by writing the Device Control Register (CTRL.RST).'] + range: [21, 21] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_RXDS + description: ['DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor + Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to + protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit + error has occurred on a read from that data buffer. No indication of a single-bit + error correction will be given by hardware. Note:If this interrupt asserts, + further GbE DMA Reads and Writes are blocked until software issues a soft + reset to the GbE by writing the Device Control Register (CTRL.RST).'] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [19, 17] + reset: 0 + sticky: '' + - access: RCWC + acronym: SRPD + description: [Small Receive Packet Detected., Indicates that a packet of size RSRPD.SIZE + register has been detected and transferred to host memory. The interrupt is + only asserted if RSRPD.SIZE register has a non-zero value] + range: [16, 16] + reset: 0 + sticky: '' + - access: RCWC + acronym: TXD_LOW + description: [Transmit Descriptor Low Threshold hit. Indicates that the descriptor + ring has reached the threshold specified in "TXDCTL - Transmit Descriptor + Control Register" on page 1500.] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 8] + reset: 0 + sticky: '' + - access: RCWC + acronym: RXT0 + description: ['Receiver Timer Interrupt. Set when the timers expire, see "Receive + Interrupts" on page 1360 for details.'] + range: [7, 7] + reset: 0 + sticky: '' + - access: RCWC + acronym: RXO + description: [Receiver Overrun. Set on receive data FIFO overrun. Could be caused + either because there are no available buffers or because Internal Bus receive + bandwidth is inadequate.] + range: [6, 6] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [5, 5] + reset: 0 + sticky: '' + - access: RCWC + acronym: RXDMT0 + description: [Receive Descriptor Minimum Threshold Hit. Indicates that the minimum + number of receive descriptors are available and software should load more + receive descriptors.] + range: [4, 4] + reset: 0 + sticky: '' + - access: RCWC + acronym: Rsvd + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [2, 2] + reset: 0 + sticky: '' + - access: RCWC + acronym: TXQE + description: [Transmit Queue Empty. Set when the last descriptor block for a transmit + queue has been used.] + range: [1, 1] + reset: 0 + sticky: '' + - access: RCWC + acronym: TXDW + description: ['Transmit Descriptor Written Back. Set when hardware processes a + descriptor with its RS bit set. If using delayed interrupts (TDESC.IDE is + set in the Transmit Descriptor CMD), the interrupt is delayed until after + one of the delayed-timers (TIDV or TADV) expires.'] + range: [0, 0] + reset: 0 + sticky: '' + offset: 2240 + offset_end: [2243, null] + offset_start: [2240, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: ICR1 + reg_name: ICR1 + size: 32 + table_ref: 37-42 + title_desc: Interrupt 1Cause Read Register + view: PCI 3 +ICR2: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: RSVD + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_INTBUS + description: ['Internal Bus Error. ', 'This bit indicates that an error occurred + during either a Target or Host transaction on the bus. Refer to Section 37.5.12, + "Error Handling" for complete details.', The details of this error are reported + in the INTBUS_ERR_STAT register.] + range: [28, 28] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_STAT + description: ['Statistic Register ECC Error. The Statistic Registers are implemented + using a memory that uses a single-bit correct/multi-bit detect ECC parity + algorithm to protect it. This bit indicates that a multi-bit error has occurred + on a read from that memory. No indication of a single-bit error correction + will be given by hardware.Note:If this interrupt asserts, further GbE DMA + Reads and Writes are blocked until software issues a soft reset to the GbE + by writing the Device Control Register (CTRL.RST)'] + range: [27, 27] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_MCFSPF + description: ['Multicast Filter Parity Error/Special Packet Filter Parity Error. + The Multicast Filter and Special Packets Filter use parity protected SRAMs + for data buffers. This bit indicates that a parity error has occurred on a + read from either of these data buffers. '] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_PB + description: ['DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses + a single-bit correct/multi-bit detect ECC parity algorithm to protect the + SRAM it uses for data. This bit indicates that a multi-bit error has occurred + on a read from that SRAM. No indication of a single-bit error correction will + be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads + and Writes are blocked until software issues a soft reset to the GbE by writing + the Device Control Register (CTRL.RST).'] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_TXDS + description: ['DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor + Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to + protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit + error has occurred on a read from that data buffer. No indication of a single-bit + error correction will be given by hardware. Note:If this interrupt asserts, + further GbE DMA Reads and Writes are blocked until software issues a soft + reset to the GbE by writing the Device Control Register (CTRL.RST).'] + range: [21, 21] + reset: 0 + sticky: '' + - access: RCWC + acronym: ERR_RXDS + description: ['DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor + Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to + protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit + error has occurred on a read from that data buffer. No indication of a single-bit + error correction will be given by hardware.Note:If this interrupt asserts, + further GbE DMA Reads and Writes are blocked until software issues a soft + reset to the GbE by writing the Device Control Register (CTRL.RST).'] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved] + range: [19, 0] + reset: 0 + sticky: '' + offset: 2272 + offset_end: [2275, null] + offset_start: [2272, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: ICR2 + reg_name: ICR2 + size: 32 + table_ref: 37-46 + title_desc: Error Interrupt Cause Read Register + view: PCI 3 +ICS0: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_INTBUS + description: [Triggers Internal Bus Error] + range: [28, 28] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_STAT + description: [Triggers Statistic Register ECC Error] + range: [27, 27] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_MCFSPF + description: [Triggers Special Packet Filter Parity Error] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_PKBUF + description: [Triggers DMA Packet Buffer ECC Error] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_TXDS + description: [Triggers DMA Transmit Descriptor Buffer ECC Error] + range: [21, 21] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_RXDS + description: [Triggers DMA Receive Descriptor Buffer ECC Error] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [19, 17] + reset: 0 + sticky: '' + - access: RW + acronym: SRPD + description: [Triggers Small Receive Packet Detected and Transferred] + range: [16, 16] + reset: 0 + sticky: '' + - access: RW + acronym: TXD_LOW + description: [Triggers Transmit Descriptor Low Threshold Hit] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 8] + reset: 0 + sticky: '' + - access: RW + acronym: RXT0 + description: [Triggers Receiver Timer Interrupt] + range: [7, 7] + reset: 0 + sticky: '' + - access: RW + acronym: RXO + description: [Triggers Receiver Overrun. Set on receive data FIFO overrun] + range: [6, 6] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [5, 5] + reset: 0 + sticky: '' + - access: RW + acronym: RXDMT0 + description: [Triggers Receive Descriptor Minimum Threshold hit] + range: [4, 4] + reset: 0 + sticky: '' + - access: RW + acronym: Rsvd + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved. Must be written as '0'] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: TXQE + description: [Triggers Transmit Queue Empty] + range: [1, 1] + reset: 0 + sticky: '' + - access: RW + acronym: TXDW + description: [Triggers Transmit Descriptor Written Back] + range: [0, 0] + reset: 0 + sticky: '' + offset: 200 + offset_end: [203, null] + offset_start: [200, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: ICS0 + reg_name: ICS0 + size: 32 + table_ref: 37-39 + title_desc: Interrupt 0 Cause Set Register + view: PCI 3 +ICS1: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_INTBUS + description: [Triggers Internal Bus Error] + range: [28, 28] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_STAT + description: [Triggers Statistic Register ECC Error] + range: [27, 27] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_MCFSPF + description: [Triggers Special Packet Filter Parity Error] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_PKBUF + description: [Triggers DMA Packet Buffer ECC Error] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_TXDS + description: [Triggers DMA Transmit Descriptor Buffer ECC Error] + range: [21, 21] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_RXDS + description: [Triggers DMA Receive Descriptor Buffer ECC Error] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [19, 17] + reset: 0 + sticky: '' + - access: RW + acronym: SRPD + description: [Triggers Small Receive Packet Detected and Transferred] + range: [16, 16] + reset: 0 + sticky: '' + - access: RW + acronym: TXD_LOW + description: [Triggers Transmit Descriptor Low Threshold Hit] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 8] + reset: 0 + sticky: '' + - access: RW + acronym: RXT0 + description: [Triggers Receiver Timer Interrupt] + range: [7, 7] + reset: 0 + sticky: '' + - access: RW + acronym: RXO + description: [Triggers Receiver Overrun. Set on receive data FIFO overrun] + range: [6, 6] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [5, 5] + reset: 0 + sticky: '' + - access: RW + acronym: RXDMT0 + description: [Triggers Receive Descriptor Minimum Threshold hit] + range: [4, 4] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved. Must be written as '0'] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: TXQE + description: [Triggers Transmit Queue Empty] + range: [1, 1] + reset: 0 + sticky: '' + - access: RW + acronym: TXDW + description: [Triggers Transmit Descriptor Written Back] + range: [0, 0] + reset: 0 + sticky: '' + offset: 2248 + offset_end: [2251, null] + offset_start: [2248, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: ICS1 + reg_name: ICS1 + size: 32 + table_ref: 37-43 + title_desc: Interrupt 0 Cause Set Register + view: PCI 3 +ICS2: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_INTBUS + description: [Triggers Internal Bus Error] + range: [28, 28] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_STAT + description: [Triggers Statistic Register ECC Error] + range: [27, 27] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_MCFSPF + description: [Triggers Special Packet Filter Parity Error] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_PKBUF + description: [Triggers DMA Packet Buffer ECC Error] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_TXDS + description: [Triggers DMA Transmit Descriptor Buffer ECC Error] + range: [21, 21] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_RXDS + description: [Triggers DMA Receive Descriptor Buffer ECC Error] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [19, 0] + reset: 0 + sticky: '' + offset: 2280 + offset_end: [2283, null] + offset_start: [2280, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: ICS2 + reg_name: ICS2 + size: 32 + table_ref: 37-47 + title_desc: Error Interrupt Cause Set Register + view: PCI 3 +IMC0: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_INTBUS + description: [Clears the mask for Internal Bus Error] + range: [28, 28] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_STAT + description: [Clears the mask for Statistic Register ECC Error] + range: [27, 27] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_MCFSPF + description: [Clears the mask for the Filter Memory Errors] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_PKBUF + description: [Clears the mask for DMA Packet Buffer ECC Error] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_TXDS + description: [Clears the mask for DMA Transmit Descriptor Buffer ECC Error] + range: [21, 21] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_RXDS + description: [Clears the mask for DMA Receive Descriptor Buffer ECC Error] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [19, 17] + reset: 0 + sticky: '' + - access: WO + acronym: SRPD + description: [Clears the mask for Small Receive Packet Detected and Transferred] + range: [16, 16] + reset: 0 + sticky: '' + - access: WO + acronym: TXD_LOW + description: [Clears the mask for Transmit Descriptor Low Threshold Hit] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 8] + reset: 0 + sticky: '' + - access: WO + acronym: RXT0 + description: [Clears the mask for Receiver Timer Interrupt] + range: [7, 7] + reset: 0 + sticky: '' + - access: WO + acronym: RXO + description: [Clears the mask for Receiver Overrun. Set on receive data FIFO overrun] + range: [6, 6] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [5, 5] + reset: 0 + sticky: '' + - access: WO + acronym: RXDMT0 + description: [Clears the mask for Receive Descriptor Minimum Threshold hit] + range: [4, 4] + reset: 0 + sticky: '' + - access: WO + acronym: Rsvd + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved. Must be written as '0'] + range: [2, 2] + reset: 0 + sticky: '' + - access: WO + acronym: TXQE + description: [Clears the mask for Transmit Queue Empty] + range: [1, 1] + reset: 0 + sticky: '' + - access: WO + acronym: TXDW + description: [Clears the mask for Transmit Descriptor Written Back] + range: [0, 0] + reset: 0 + sticky: '' + offset: 216 + offset_end: [219, null] + offset_start: [216, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: IMC0 + reg_name: IMC0 + size: 32 + table_ref: 37-41 + title_desc: Interrupt 0 Mask Clear Register + view: PCI 3 +IMC1: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_INTBUS + description: [Clears the mask for Internal Bus Error] + range: [28, 28] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_STAT + description: [Clears the mask for Statistic Register ECC Error] + range: [27, 27] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_MCFSPF + description: [Clears the mask for the Filter Memory Errors] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_PKBUF + description: [Clears the mask for DMA Packet Buffer ECC Error] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_TXDS + description: [Clears the mask for DMA Transmit Descriptor Buffer ECC Error] + range: [21, 21] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_RXDS + description: [Clears the mask for DMA Receive Descriptor Buffer ECC Error] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [19, 17] + reset: 0 + sticky: '' + - access: WO + acronym: SRPD + description: [Clears the mask for Small Receive Packet Detected and Transferred] + range: [16, 16] + reset: 0 + sticky: '' + - access: WO + acronym: TXD_LOW + description: [Clears the mask for Transmit Descriptor Low Threshold Hit] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 8] + reset: 0 + sticky: '' + - access: WO + acronym: RXT0 + description: [Clears the mask for Receiver Timer Interrupt] + range: [7, 7] + reset: 0 + sticky: '' + - access: WO + acronym: RXO + description: [Clears the mask for Receiver Overrun. Set on receive data FIFO overrun] + range: [6, 6] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [5, 5] + reset: 0 + sticky: '' + - access: WO + acronym: RXDMT0 + description: [Clears the mask for Receive Descriptor Minimum Threshold hit] + range: [4, 4] + reset: 0 + sticky: '' + - access: WO + acronym: Rsvd + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [2, 2] + reset: 0 + sticky: '' + - access: WO + acronym: TXQE + description: [Clears the mask for Transmit Queue Empty] + range: [1, 1] + reset: 0 + sticky: '' + - access: WO + acronym: TXDW + description: [Clears the mask for Transmit Descriptor Written Back] + range: [0, 0] + reset: 0 + sticky: '' + offset: 2264 + offset_end: [2267, null] + offset_start: [2264, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: IMC1 + reg_name: IMC1 + size: 32 + table_ref: 37-45 + title_desc: Interrupt 1 Mask Clear Register + view: PCI 3 +IMC2: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_INTBUS + description: [Clears the mask for Internal Bus Error] + range: [28, 28] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_STAT + description: [Clears the mask for Statistic Register ECC Error] + range: [27, 27] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_INT + description: [Clears the mask for Internal Memory Error] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_PKBUF + description: [Clears the mask for DMA Packet Buffer ECC Error] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_TXDS + description: [Clears the mask for DMA Transmit Descriptor Buffer ECC Error] + range: [21, 21] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_RXDS + description: [Clears the mask for DMA Receive Descriptor Buffer ECC Error] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [19, 0] + reset: 0 + sticky: '' + offset: 2296 + offset_end: [2299, null] + offset_start: [2296, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: IMC2 + reg_name: IMC2 + size: 32 + table_ref: 37-49 + title_desc: Error Interrupt Mask Clear Register + view: PCI 3 +IMS0: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_INTBUS + description: [Enables Internal Bus Error] + range: [28, 28] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_STAT + description: [Enables Statistic Register ECC Error] + range: [27, 27] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_MCFSPF + description: [Enables Special Packet Filter Parity Error] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_PKBUF + description: [Enables DMA Packet Buffer ECC Error] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_TXDS + description: [Enables DMA Transmit Descriptor Buffer ECC Error] + range: [21, 21] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_RXDS + description: [Enables DMA Receive Descriptor Buffer ECC Error] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved. Must be written as '0'] + range: [19, 17] + reset: 0 + sticky: '' + - access: RW + acronym: SRPD + description: [Sets the mask for Small Receive Packet Detected and Transferred] + range: [16, 16] + reset: 0 + sticky: '' + - access: RW + acronym: TXD_LOW + description: [Sets the mask for Transmit Descriptor Low Threshold Hit] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 8] + reset: 0 + sticky: '' + - access: RW + acronym: RXT0 + description: [Sets the mask for Receiver Timer Interrupt] + range: [7, 7] + reset: 0 + sticky: '' + - access: RW + acronym: RXO + description: [Sets the mask for Receiver Overrun. Set on receive data FIFO overrun] + range: [6, 6] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [5, 5] + reset: 0 + sticky: '' + - access: RW + acronym: RXDMT0 + description: [Sets the mask for Receive Descriptor Minimum Threshold hit] + range: [4, 4] + reset: 0 + sticky: '' + - access: RW + acronym: Rsvd + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved. Must be written as '0'] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: TXQE + description: [Sets the mask for Transmit Queue Empty] + range: [1, 1] + reset: 0 + sticky: '' + - access: RW + acronym: TXDW + description: [Sets the mask for Transmit Descriptor Written Back] + range: [0, 0] + reset: 0 + sticky: '' + offset: 208 + offset_end: [211, null] + offset_start: [208, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: IMS0 + reg_name: IMS0 + size: 32 + table_ref: 37-40 + title_desc: Interrupt 0 Mask Set/Read Register + view: PCI 3 +IMS1: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: WO + acronym: ERR_INTBUS + description: [Enables Internal Bus Error] + range: [28, 28] + reset: 0 + sticky: RW + - access: WO + acronym: ERR_STAT + description: [Enables Statistic Register ECC Error] + range: [27, 27] + reset: 0 + sticky: RW + - access: WO + acronym: ERR_MCFSPF + description: [Enables Special Packet Filter Parity Error] + range: [26, 26] + reset: 0 + sticky: RW + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: RV + - access: WO + acronym: ERR_PKBUF + description: [Enables DMA Packet Buffer ECC Error] + range: [23, 23] + reset: 0 + sticky: RW + - access: RV + acronym: Rsvd + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: RV + - access: WO + acronym: ERR_TXDS + description: [Enables DMA Transmit Descriptor Buffer ECC Error] + range: [21, 21] + reset: 0 + sticky: RW + - access: WO + acronym: ERR_RXDS + description: [Enables DMA Receive Descriptor Buffer ECC Error] + range: [20, 20] + reset: 0 + sticky: RW + - access: RV + acronym: Rsvd + description: [Reserved] + range: [19, 17] + reset: 0 + sticky: '' + - access: RW + acronym: SRPD + description: [Sets the mask for Small Receive Packet Detected and Transferred] + range: [16, 16] + reset: 0 + sticky: '' + - access: RW + acronym: TXD_LOW + description: [Sets the mask for Transmit Descriptor Low Threshold Hit] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 8] + reset: 0 + sticky: '' + - access: RW + acronym: RXT0 + description: [Sets the mask for Receiver Timer Interrupt] + range: [7, 7] + reset: 0 + sticky: '' + - access: RW + acronym: RXO + description: [Sets the mask for Receiver Overrun. Set on receive data FIFO overrun] + range: [6, 6] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [5, 5] + reset: 0 + sticky: '' + - access: RW + acronym: RXDMT0 + description: [Sets the mask for Receive Descriptor Minimum Threshold hit] + range: [4, 4] + reset: 0 + sticky: '' + - access: RW + acronym: Rsvd + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: '' + - access: RW + acronym: Rsvd + description: [Reserved. Must be written as '0'] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: TXQE + description: [Sets the mask for Transmit Queue Empty] + range: [1, 1] + reset: 0 + sticky: '' + - access: RW + acronym: TXDW + description: [Sets the mask for Transmit Descriptor Written Back] + range: [0, 0] + reset: 0 + sticky: '' + offset: 2256 + offset_end: [2259, null] + offset_start: [2256, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: IMS1 + reg_name: IMS1 + size: 32 + table_ref: 37-44 + title_desc: Interrupt 1 Mask Set/Read Register + view: PCI 3 +IMS2: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 29] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_INTBUS + description: [Enables Internal Bus Error] + range: [28, 28] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_STAT + description: [Enables Statistic Register ECC Error] + range: [27, 27] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_MCFSPF + description: [Enables Special Packet Filter Parity Error] + range: [26, 26] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_PKBUF + description: [Enables DMA Packet Buffer ECC Error] + range: [23, 23] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [22, 22] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_TXDS + description: [Enables DMA Transmit Descriptor Buffer ECC Error] + range: [21, 21] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_RXDS + description: [Enables DMA Receive Descriptor Buffer ECC Error] + range: [20, 20] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [19, 0] + reset: 0 + sticky: '' + offset: 2288 + offset_end: [2291, null] + offset_start: [2288, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: IMS2 + reg_name: IMS2 + size: 32 + table_ref: 37-48 + title_desc: Error Interrupt Mask Set/Read Register + view: PCI 3 +INTBUS_ERR_STAT: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 13] + reset: 0 + sticky: '' + - access: RW + acronym: INTBUS_ERR_H_DIS + description: [0 - Internal Bus errors will halt further GbE transmit/receive operation., + '1 - Internal Bus errors will not halt further GbE operation. '] + range: [12, 12] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [11, 6] + reset: 0 + sticky: '' + - access: RO + acronym: Type + description: ['Internal Bus Error Type:', '? 00 = Unsupported internal bus transaction + targeted at GbE', '? 01 = Pull data error detected during a target write transaction', + '? 10 = GbE received a Internal Bus Data Error response while mastering a DMA + transaction', '? 11 = Master Pull data error occurred as a result of an internal + memory error'] + range: [5, 4] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [3, 2] + reset: 0 + sticky: '' + - access: RWC + acronym: MERR + description: [Indicates whether one or more than one Internal Bus errors have + occurred before INTBUS_ERR_STAT.CERR was cleared, 0 = One Internal Bus Error1 + = More than one Internal Bus Error] + range: [1, 1] + reset: 0 + sticky: '' + - access: RWC + acronym: CERR + description: ['Internal Bus Error: Asserts when Internal Bus Error status and + address registers are valid', 0 = no error has been logged1 = Internal Bus + Error status and address registers have logged an error, If error handling + is enabled (INTBUS_ERR_H_DIS = 0) then this bit can only be cleared by a reset.] + range: [0, 0] + reset: 0 + sticky: '' + offset: 1296 + offset_end: [1299, null] + offset_start: [1296, null] + power_well: null + recurring: null + reg_base_name: INTBUS_ERR_STAT + reg_name: INTBUS_ERR_STAT + size: 32 + table_ref: 37-145 + title_desc: Internal Bus Error Status Register + view: PCI 3 +IPAV: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: RSVD + description: [Reserved. Should be set to 0.] + range: [31, 17] + reset: 0 + sticky: '' + - access: RW + acronym: V60 + description: [IPv6 Address 0 Valid] + range: [16, 16] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved. Should be set to 0.] + range: [15, 4] + reset: 0 + sticky: '' + - access: RW + acronym: V43 + description: [IPv4 Address 3 Valid] + range: [3, 3] + reset: 0 + sticky: '' + - access: RW + acronym: V42 + description: [IPv4 Address 2 Valid] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: V41 + description: [IPv4 Address 1 Valid] + range: [1, 1] + reset: 0 + sticky: '' + - access: RW + acronym: V40 + description: [IPv4 Address 0 Valid, The initial value is loaded from the IP Address + Valid bit of the EEPROM's Management Control Register] + range: [0, 0] + reset: 0 + sticky: '' + offset: 22584 + offset_end: [22587, null] + offset_start: [22584, null] + power_well: null + recurring: null + reg_base_name: IPAV + reg_name: IPAV + size: 32 + table_ref: 37-134 + title_desc: IP Address Valid Register (0x05838; RW) + view: PCI 3 +IPV6_ADDR0BYTES_13_16: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXXXh + description: null + fields: + - access: RW + acronym: IPV6DDR3 + description: ['IPV6 Address, bytes 13 - 16'] + range: [31, 0] + reset: null + sticky: '' + offset: 22668 + offset_end: [22671, null] + offset_start: [22668, null] + power_well: null + recurring: null + reg_base_name: IPV6_ADDR0BYTES_13_16 + reg_name: IPV6_ADDR0BYTES_13_16 + size: 32 + table_ref: 37-139 + title_desc: IPv6 Address Table Register, Bytes 13 - 16 + view: PCI 3 +IPV6_ADDR0BYTES_1_4: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXXXh + description: null + fields: + - access: RW + acronym: IPV6ADDR0 + description: ['IPV6 Address0, bytes 1 - 4'] + range: [31, 0] + reset: null + sticky: '' + offset: 22656 + offset_end: [22659, null] + offset_start: [22656, null] + power_well: null + recurring: null + reg_base_name: IPV6_ADDR0BYTES_1_4 + reg_name: IPV6_ADDR0BYTES_1_4 + size: 32 + table_ref: 37-136 + title_desc: IPv6 Address Table Register (0x5880), Bytes 1 - 4 + view: PCI 3 +IPV6_ADDR0BYTES_5_8: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXXXh + description: null + fields: + - access: RW + acronym: IPV6ADDR1 + description: ['IPV6 Address, bytes 5 - 8'] + range: [31, 0] + reset: null + sticky: '' + offset: 22660 + offset_end: [22671, null] + offset_start: [22660, null] + power_well: null + recurring: null + reg_base_name: IPV6_ADDR0BYTES_5_8 + reg_name: IPV6_ADDR0BYTES_5_8 + size: 32 + table_ref: 37-137 + title_desc: IPv6 Address Table Register, Bytes 5 - 8 + view: PCI 3 +IPV6_ADDR0BYTES_9_12: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXXXh + description: null + fields: + - access: RW + acronym: IPV6ADDR2 + description: ['IPV6 Address, bytes 9 - 12'] + range: [31, 0] + reset: null + sticky: '' + offset: 22664 + offset_end: [22667, null] + offset_start: [22664, null] + power_well: null + recurring: null + reg_base_name: IPV6_ADDR0BYTES_9_12 + reg_name: IPV6_ADDR0BYTES_9_12 + size: 32 + table_ref: 37-138 + title_desc: IPv6 Address Table Register, Bytes 9 - 12 + view: PCI 3 +ITR0: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: MIII + description: ['Minimum Inter-interrupt Interval. ', '? In RGMII mode, the interval + is specified in 256ns increments. ', '? In RMII mode, the interval is specified + in 320ns increments', '? Zero disables interrupt throttling logic', (The following + example applies to RGMII mode), 'To independently validate configuration settings, + software can use the following formula to convert the inter-interrupt interval + value to the common ''interrupts/sec'' performance metric:-9-interrupts/sec + = (256 x 10 sec x inter-interrupt interval)1', 'Inversely, inter-interrupt + interval value can be calculated as:-9-inter-interrupt interval = (256 x 10 + sec x interrupts/sec)1', 'For example, if the interval is programmed to 500d, + the network controller guarantees the CPU will not be interrupted by the network + controller for 128 usec from the last interrupt. The maximum observable interrupt + rate from the adapter should never exceed 7813 interrupts/sec.', 'The optimal + performance setting for this register is system/configuration specific. A + initial suggested range is 651-5580 (28Bh - 15CCh), or, more generally, between + 700 and 6000 interrupts per second.'] + range: [15, 0] + reset: 0 + sticky: '' + offset: 196 + offset_end: [199, null] + offset_start: [196, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: ITR0 + reg_name: ITR0 + size: 32 + table_ref: 37-38 + title_desc: Interrupt 0 Throttling Register + view: PCI 3 +LATECOL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: LATECOL + description: [Number of packets with late collisions] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16416 + offset_end: [16419, null] + offset_start: [16416, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: LATECOL + reg_name: LATECOL + size: 32 + table_ref: 37-86 + title_desc: Late Collisions Count Register + view: PCI 3 +MCC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: MCC + description: [Number of times a successful transmit encountered multiple collisions.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16412 + offset_end: [16415, null] + offset_start: [16412, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: MCC + reg_name: MCC + size: 32 + table_ref: 37-85 + title_desc: Multiple Collision Count Register + view: PCI 3 +MEM_STS: + bar: CSRBAR + bus_device_function: M:2:0 + default: 8323072 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved.] + range: [31, 23] + reset: 0 + sticky: '' + - access: RW + acronym: ERR_FLEX_DIS + description: [Flex Filter Parity Error Disable, '0: Error trapping enabled', '1: + Error trapping disabled'] + range: [22, 22] + reset: 1 + sticky: '' + - access: RW + acronym: ERR_STAT_DIS + description: [Statistics Register ECC Error Disable, '0: Error trapping enabled', + '1: Error trapping disabled'] + range: [21, 21] + reset: 1 + sticky: '' + - access: RW + acronym: ERR_PKBUF_DIS + description: [Packet Buffer ECC Error Disable, '0: Error trapping enabled', '1: + Error trapping disabled'] + range: [20, 20] + reset: 1 + sticky: '' + - access: RW + acronym: ERR_TXDS_DIS + description: [Transmit Descriptor ECC Error Disable, '0: Error trapping enabled', + '1: Error trapping disabled'] + range: [19, 19] + reset: 1 + sticky: '' + - access: RW + acronym: ERR_RXDS_DIS + description: [Receive Descriptor ECC Error Disable, '0: Error trapping enabled', + '1: Error trapping disabled'] + range: [18, 18] + reset: 1 + sticky: '' + - access: RW + acronym: ERR_SPF_DIS + description: [Special Packets Filter Parity Error Disable, '0: Error trapping + enabled', '1: Error trapping disabled'] + range: [17, 17] + reset: 1 + sticky: '' + - access: RW + acronym: ERR_MF_DIS + description: [Multicast Filter Parity Error Disable, '0: Error trapping enabled', + '1: Error trapping disabled'] + range: [16, 16] + reset: 1 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [15, 13] + reset: 0 + sticky: '' + - access: RW + acronym: MEM_ERRH_DIS + description: ['Memory Error Handling Disable: ', 'Indicates, for the following + error types, whether GbE Tx/Rx operation will be halted:', ERR_STAT, ERR_PKBUF, + ERR_RXDS, ERR_TXDS, '0: Memory Errors will halt further GbE Tx/Rx operation + and a soft-reset is required to restore operation', '1: Memory Errors will + be logged, but will not halt further GbE Tx/Rx operation'] + range: [12, 12] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved.] + range: [11, 7] + reset: 0 + sticky: '' + - access: RO/RWC + acronym: ERR_FLEX + description: [Flex filter Parity Error, '0: No error occurred', '1: Error occurred', + When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then + this bit is RWC.] + range: [6, 6] + reset: 0 + sticky: '' + - access: RO/RWC + acronym: ERR_STAT + description: [Statistics Register ECC Error, '0: No error occurred', '1: Error + occurred', When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS + is set then this bit is RWC] + range: [5, 5] + reset: 0 + sticky: '' + - access: RO/RWC + acronym: ERR_PKBUF + description: [Packet Buffer ECC 2-bit Error, '0: No error occurred', '1: Error + occurred', When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS + is set then this bit is RWC.] + range: [4, 4] + reset: 0 + sticky: '' + - access: RO/RWC + acronym: ERR_TXDS + description: [Transmit Descriptor ECC 2-bit Error, '0: No error occurred', '1: + Error occurred', When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS + is set then this bit is RWC.] + range: [3, 3] + reset: 0 + sticky: '' + - access: RO/RWC + acronym: ERR_RXDS + description: [Receive Descriptor ECC 2-bit Error, '0: No error occurred', '1: + Error occurred', When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS + is set then this bit is RWC.] + range: [2, 2] + reset: 0 + sticky: '' + - access: RO/RWC + acronym: ERR_SPF + description: [Special Packets Filter Parity Error, '0: No error occurred', '1: + Error occurred', When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS + is set then this bit is RWC] + range: [1, 1] + reset: 0 + sticky: '' + - access: RO/RWC + acronym: ERR_MF + description: [Multicast Filter Parity Error, '0: No error occurred', '1: Error + occurred', When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS + is set then this bit is RWC] + range: [0, 0] + reset: 0 + sticky: '' + offset: 2308 + offset_end: [2311, null] + offset_start: [2308, null] + power_well: null + recurring: null + reg_base_name: MEM_STS + reg_name: MEM_STS + size: 32 + table_ref: 37-147 + title_desc: Memory Error Status Register + view: PCI 3 +MEM_TST: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 19] + reset: 0 + sticky: '' + - access: RW + acronym: Select + description: ['Selects the memory where the error mask is applied:', '000 : None + - no errors injected', '001 : Statistics Registers', '010 : Multicast Filter + Memory', '011 : Special Packet Filter Memory', '100 : TX Descriptor Buffer', + '101 : RX Descriptor Buffer', '110 : Packet Buffer', '111 : Flexible Filter + Memory'] + range: [18, 16] + reset: 0 + sticky: '' + - access: RW + acronym: Mask + description: [ECC/Parity check bit XOR mask, 'The Valid Mask bits are selected + according to the Select field, as follows:', '001 : 15:8 Reserved; 7:0 ECC + Mask', '010 : 15:4 Reserved; 3:0 Parity bit Mask', '011 : 15:4 Reserved; 3:0 + Parity bit Mask', '100 : 15:0 ECC Mask', '101 : 15:0 ECC Mask', '110 : 15:0 + ECC Mask', '111 : 15:0 Reserved; 3:0 Parity bit Mask'] + range: [15, 0] + reset: 0 + sticky: '' + offset: 2304 + offset_end: [2307, null] + offset_start: [2304, null] + power_well: null + recurring: null + reg_base_name: MEM_TST + reg_name: MEM_TST + size: 32 + table_ref: 37-146 + title_desc: Memory Error Test Register + view: PCI 3 +MPC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: MPC + description: [Missed Packets Count] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16400 + offset_end: [16403, null] + offset_start: [16400, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: MPC + reg_name: MPC + size: 32 + table_ref: 37-82 + title_desc: Missed Packet Count Register + view: PCI 3 +MPRC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: MPRC + description: [Number of multicast packets received] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16508 + offset_end: [16511, null] + offset_start: [16508, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: MPRC + reg_name: MPRC + size: 32 + table_ref: 37-105 + title_desc: Multicast Packets Received Count Register + view: PCI 3 +MPTC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: MPTC + description: [Number of multicast packets transmitted] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16624 + offset_end: [16627, null] + offset_start: [16624, null] + power_well: null + recurring: null + reg_base_name: MPTC + reg_name: MPTC + size: 32 + table_ref: 37-127 + title_desc: Multicast Packets Transmitted Count Register + view: PCI 3 +MTA[0-127]: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXX_XXXXh + description: null + fields: + - access: RW + acronym: Vector + description: [32b vector of multicast address filter table information.] + range: [31, 0] + reset: null + sticky: '' + offset: 20992 + offset_end: [20995, 4] + offset_start: [20992, 4] + power_well: 'Gbe1/2:' + recurring: 128 + reg_base_name: MTA + reg_name: MTA[0-127] + size: 32 + table_ref: 37-63 + title_desc: 128 Multicast Table Array Registers + view: PCI 3 +PBA: + bar: CSRBAR + bus_device_function: M:2:0 + default: 1048624 + description: null + fields: + - access: RO + acronym: RSVD + description: [Reserved] + range: [31, 22] + reset: 0 + sticky: '' + - access: RO + acronym: TXA + description: [Transmit Packet Buffer Allocation in K bytes. PBA.TXA is read only + and calculated based on PBA.RXA., 0010h =>16KB] + range: [21, 16] + reset: 16 + sticky: '' + - access: RO + acronym: RSVD + description: [Reserved] + range: [15, 6] + reset: 0 + sticky: '' + - access: RW + acronym: RXA + description: [Receive Packet Buffer Allocation in K bytes. PBA.RXA legal values + must be 8K aligned., 'Valid values are (decimal) 8, 16, 24, 32, 40, 48, 56.', + 0030h => 48KBh] + range: [5, 0] + reset: 48 + sticky: '' + offset: 4096 + offset_end: [4099, null] + offset_start: [4096, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: PBA + reg_name: PBA + size: 32 + table_ref: 37-36 + title_desc: Packet Buffer Allocation Register + view: PCI 3 +PRC1023: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PRC1023 + description: ['Number of good packets received, (512-1023) bytes in length'] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16492 + offset_end: [16495, null] + offset_start: [16492, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: PRC1023 + reg_name: PRC1023 + size: 32 + table_ref: 37-101 + title_desc: Good Packets Received Count (512-1023 Bytes) Register + view: PCI 3 +PRC127: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PRC127 + description: ['Number of good packets received, (65-127) bytes in length'] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16480 + offset_end: [16483, null] + offset_start: [16480, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: PRC127 + reg_name: PRC127 + size: 32 + table_ref: 37-98 + title_desc: Good Packets Received Count (65-127 Bytes) Register + view: PCI 3 +PRC1522: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PRC1522 + description: ['Number of good packets received, (1024-Max) bytes in length'] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16496 + offset_end: [16499, null] + offset_start: [16496, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: PRC1522 + reg_name: PRC1522 + size: 32 + table_ref: 37-102 + title_desc: Good Packets Received Count (1024 to Max Bytes) Register + view: PCI 3 +PRC255: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PRC255 + description: ['Number of good packets received, (128-255) bytes in length.'] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16484 + offset_end: [16487, null] + offset_start: [16484, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: PRC255 + reg_name: PRC255 + size: 32 + table_ref: 37-99 + title_desc: Good Packets Received Count (128-255 Bytes) Register + view: PCI 3 +PRC511: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PRC511 + description: ['Number of good packets received, (256-511) bytes in length'] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16488 + offset_end: [16491, null] + offset_start: [16488, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: PRC511 + reg_name: PRC511 + size: 32 + table_ref: 37-100 + title_desc: Good Packets Received Count (256-511 Bytes) Register + view: PCI 3 +PRC64: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PRC64 + description: [Number of good packets received exactly 64 bytes in length.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16476 + offset_end: [16479, null] + offset_start: [16476, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: PRC64 + reg_name: PRC64 + size: 32 + table_ref: 37-97 + title_desc: Good Packets Received Count (64 Bytes) Register + view: PCI 3 +PTC1023: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PTC1023 + description: [Number of packets transmitted that are 512-1023 bytes in length] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16616 + offset_end: [16619, null] + offset_start: [16616, null] + power_well: null + recurring: null + reg_base_name: PTC1023 + reg_name: PTC1023 + size: 32 + table_ref: 37-125 + title_desc: Packets Transmitted Count (512-1023 Bytes) Register + view: PCI 3 +PTC1522: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PTC1522 + description: [Number of packets transmitted that are 1024 or more bytes in length] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16620 + offset_end: [16623, null] + offset_start: [16620, null] + power_well: null + recurring: null + reg_base_name: PTC1522 + reg_name: PTC1522 + size: 32 + table_ref: 37-126 + title_desc: Packets Transmitted Count (1024-1522 Bytes) Register + view: PCI 3 +PTC255: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PTC255 + description: [Number of packets transmitted that are 128-255 bytes in length] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16608 + offset_end: [16611, null] + offset_start: [16608, null] + power_well: null + recurring: null + reg_base_name: PTC255 + reg_name: PTC255 + size: 32 + table_ref: 37-123 + title_desc: Packets Transmitted Count (128-255 Bytes) Register + view: PCI 3 +PTC511: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PTC511 + description: [Number of packets transmitted that are 256-511 bytes in length] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16612 + offset_end: [16615, null] + offset_start: [16612, null] + power_well: null + recurring: null + reg_base_name: PTC511 + reg_name: PTC511 + size: 32 + table_ref: 37-124 + title_desc: Packets Transmitted Count (256-511 Bytes) Register + view: PCI 3 +PTC64: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: PTC64 + description: [Number of all packets transmitted that are 64 bytes in length] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16600 + offset_end: [16603, null] + offset_start: [16600, null] + power_well: null + recurring: null + reg_base_name: PTC64 + reg_name: PTC64 + size: 32 + table_ref: 37-122 + title_desc: Packets Transmitted Count (64 Bytes) Register + view: PCI 3 +RADV: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: RADT + description: ['Receive Absolute Delay Timer ', Receive Absolute delay timer measured + in increments of, 'RMII: 1.28 microseconds', 'RGMII: 1.024 microseconds. ', + (0b =disabled), 'If the packet delay timer is used to coalesce receive interrupts, + the Ethernet controller ensures that when receive traffic abates, an interrupt + is generated within a specified interval of no receives. During times when + receive traffic is continuous, it may be necessary to ensure that no receive + remains unnoticed for too long an interval. This register can be used to ENSURE + that a receive interrupt occurs at some predefined interval after the first + packet is received. When this timer is enabled, a separate absolute countdown + timer is initiated upon successfully receiving each packet to system memory. + When this absolute timer expires, pending receive descriptor writebacks are + flushed and a receive timer interrupt is generated. ', Setting this register + to 0b disables the absolute timer mechanism (the RDTR register should be used + with a value of 0b to cause immediate interrupts for all receive packets)., + 'Receive interrupts due to a Receive Packet Timer (RDTR) expiration cancels + a pending RADV interrupt. If enabled, the RADV countdown timer is reloaded + but halted, so as to avoid generation of a spurious second interrupt after + the RDTR has been noted.'] + range: [15, 0] + reset: 0 + sticky: '' + offset: 10284 + offset_end: [10287, null] + offset_start: [10284, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RADV + reg_name: RADV + size: 32 + table_ref: 37-60 + title_desc: Receive Interrupt Absolute Delay Timer Register + view: PCI 3 +RAH[0-15]: + bar: CSRBAR + bus_device_function: M:2:0 + default: 000XXXXXh + description: null + fields: + - access: RW + acronym: AV + description: [Address valid. This bit determines whether this address is compared + against the incoming packet. Cleared after software reset or Unit Reset., + '0 = No match on this address field ', 1 = Match on this address field] + range: [31, 31] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [30, 18] + reset: 0 + sticky: '' + - access: RW + acronym: ASEL + description: [Address Select. Selects how the address is to be used when performing + special filtering on receive packets., '? 00: Destination address (must be + set to this in normal mode)', '? 01: Source address', '? 10: Reserved', '? + 11: Reserved'] + range: [17, 16] + reset: null + sticky: '' + - access: RW + acronym: RAH + description: [Receive Address High. The upper 16 bits of the 48 bit Ethernet address.] + range: [15, 0] + reset: null + sticky: '' + offset: 21508 + offset_end: [21511, 8] + offset_start: [21508, 8] + power_well: null + recurring: 16 + reg_base_name: RAH + reg_name: RAH[0-15] + size: 32 + table_ref: 37-65 + title_desc: Receive Address High Register + view: PCI 3 +RAL[0-15]: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXXXh + description: null + fields: + - access: RW + acronym: RAL + description: [Receive Address Low. The lower 32 bits of the 48 bit Ethernet address.] + range: [31, 0] + reset: null + sticky: '' + offset: 21504 + offset_end: [21507, 8] + offset_start: [21504, 8] + power_well: null + recurring: 16 + reg_base_name: RAL + reg_name: RAL[0-15] + size: 32 + table_ref: 37-64 + title_desc: Receive Address Low Register + view: PCI 3 +RCTL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 27] + reset: 0 + sticky: '' + - access: RW + acronym: SECRC + description: [Strip Ethernet CRC. This bit controls whether the hardware strips + the Ethernet CRC from the received packet. This stripping occurs prior to + any checksum calculations. The stripped CRC is not DMA'd to host memory and + is not included in the length reported in the descriptor.] + range: [26, 26] + reset: 0 + sticky: '' + - access: RW + acronym: BSEX + description: [Buffer Size Extension. Combined with RCTL.BSIZE to program the receive + buffer size. Control of receive buffer size permits software to trade-off + descriptor performance versus required storage space. Buffers that are 2048 + bytes require only one descriptor per receive packet maximizing descriptor + efficiency. Buffers that are 256 bytes maximize memory efficiency at a cost + of multiple descriptors for packets longer than 256 bytes., RCTL.BSEX = 0 + / RCTL.BSIZE = 00 -> Receive Buffer Size = 2048B, RCTL.BSEX = 0 / RCTL.BSIZE + = 01 -> Receive Buffer Size = 1024B, RCTL.BSEX = 0 / RCTL.BSIZE = 10 -> Receive + Buffer Size = 512B, RCTL.BSEX = 0 / RCTL.BSIZE = 11 -> Receive Buffer Size + = 256B, RCTL.BSEX = 1 / RCTL.BSIZE = 00 -> Reserved, RCTL.BSEX = 1 / RCTL.BSIZE + = 01 -> Receive Buffer Size = 16384B, RCTL.BSEX = 1 / RCTL.BSIZE = 10 -> Receive + Buffer Size = 8192B, RCTL.BSEX = 1 / RCTL.BSIZE = 11 -> Receive Buffer Size + = 4096B] + range: [25, 25] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [24, 24] + reset: 0 + sticky: '' + - access: RW + acronym: PMCF + description: ['Pass MAC Control Frames. This bit controls the DMA function of + MAC control frames (other than flow control). A MAC control frame in this + context must be addressed to either the MAC control frame multicast address + or the station address, it must match the type field and must NOT match the + PAUSE opcode of 0x0001.', 0 = Do not pass MAC control frames1 = Pass any MAC + control frame (type field value of 0x8808) that does not contain the pause + opcode of 0x0001.] + range: [23, 23] + reset: 0 + sticky: '' + - access: RW + acronym: DPF + description: ['Discard Pause Frames. This bit controls the DMA function of flow + control packets addressed to the station address (RAH/RAL[0]). If a packet + is a valid flow control packet and is addressed to the station address it + will not be DMA''d to host memory if RCTL.DPF=1.', 0 = Incoming frames are + subject to filter comparison1 = Incoming valid PAUSE frames discarded even + if they match any of the filter registers] + range: [22, 22] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [21, 21] + reset: 0 + sticky: '' + - access: RW + acronym: CFI + description: [Canonical Form Indicator. One of the three bits that control the + VLAN filter table. This bit may be compared to the CFI bit found in the 802.1q + packet as part of the acceptance criteria. RCTL.CFIEN and RCTL.VFE determine + whether or not this comparison takes place.] + range: [20, 20] + reset: 0 + sticky: '' + - access: RW + acronym: CFIEN + description: [Canonical Form Indicator Enable. One of the three bits that control + the VLAN filter table. This bit enables using the CFI bit found in the 802.1q + packet as part of the acceptance criteria., The next two are used to decide + whether the CFI bit found in the.1Q packet should be used as part of the acceptance + criteria., '0 = CFI Disabled: bit not compared to determine packet acceptance1 + = CFI from packet must match CFI field for acceptance of 802.1q packet'] + range: [19, 19] + reset: 0 + sticky: '' + - access: RW + acronym: VFE + description: [VLAN Filter Enable. One of the three bits that control the VLAN + filter table. This bit determines whether the table participates in the packet + acceptance criteria., '0 = Disabled, filter table does not decide packet acceptance1 + = Enabled, filter table decides acceptance of 802.1q packets'] + range: [18, 18] + reset: 0 + sticky: '' + - access: RW + acronym: BSIZE + description: [Receive Buffer Size. Combined with RCTL.BSEX to program the receive + buffer size. Control of receive buffer size permits software to trade-off + descriptor performance versus required storage space. Buffers that are 2048 + bytes require only one descriptor per receive packet maximizing descriptor + efficiency. Buffers that are 256 bytes maximize memory efficiency at a cost + of multiple descriptors for packets longer than 256 bytes., RCTL.BSEX = 0 + / RCTL.BSIZE = 00 -> Receive Buffer Size = 2048B, RCTL.BSEX = 0 / RCTL.BSIZE + = 01 -> Receive Buffer Size = 1024B, RCTL.BSEX = 0 / RCTL.BSIZE = 10 -> Receive + Buffer Size = 512B, RCTL.BSEX = 0 / RCTL.BSIZE = 11 -> Receive Buffer Size + = 256B, RCTL.BSEX = 1 / RCTL.BSIZE = 00 -> Reserved, RCTL.BSEX = 1 / RCTL.BSIZE + = 01 -> Receive Buffer Size = 16384B, RCTL.BSEX = 1 / RCTL.BSIZE = 10 -> Receive + Buffer Size = 8192B, RCTL.BSEX = 1 / RCTL.BSIZE = 11 -> Receive Buffer Size + = 4096B] + range: [17, 16] + reset: 0 + sticky: '' + - access: RW + acronym: BAM + description: [Broadcast Accept Mode., 0 = Ignore broadcast (unless it matches + exact or imperfect filters)1 = Accept broadcast packets] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [14, 14] + reset: 0 + sticky: '' + - access: RW + acronym: MO + description: [Multicast Offset. This determines which bits of the incoming multicast + address are used in looking up the bit vector., '? 00 = [47:36]', '? 01 = + [46:35]', '? 10 = [45:34]', '? 11 = [43:32]'] + range: [13, 12] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [11, 10] + reset: 0 + sticky: '' + - access: RW + acronym: RDMTS + description: [Receive Descriptor Minimum Threshold Size. These bits determines + the threshold value for free receive descriptors. The corresponding interrupt + is set whenever the fractional number of free descriptors becomes equal to + RCTL.RDMTS. Refer to "RDLEN - Receive Descriptor Length Register" on page + 1481 for further information., '? 00 = 1/2', '? 01 = 1/4', '? 10 = 1/8', '? + 11 = Reserved'] + range: [9, 8] + reset: 0 + sticky: '' + - access: RW + acronym: LBM + description: ['Loopback mode. These bits enable the loopback function.When using + a PHY, a value of 00 should be used and the PHY is configured for loopback + through the MDIO interface.', '? 00 = Normal operation (or PHY loopback in + GMII/MII mode) ', '? 01 = MAC Loopback enable (only supported for GMII/MII + mode)', '? 10 = Reserved', '? 11 = Reserved', '? 11 = ReservedNote:PHY devices + require programming for loopback operation using MDIO accesses.Note:The GbE + must be configured for Full-Duplex operation if Mac Loopback mode is enabled.'] + range: [7, 6] + reset: 0 + sticky: '' + - access: RW + acronym: LPE + description: [Long packet enable. This bit controls whether long packet reception + is permitted., '0 = Disabled, hardware discards packets longer than 1522B1 + = Enabled, 16384B is the maximum packet size that the GbE can receive'] + range: [5, 5] + reset: 0 + sticky: '' + - access: RW + acronym: MPE + description: [Multicast promiscuous enable., 0 = Disabled1 = Enabled] + range: [4, 4] + reset: 0 + sticky: '' + - access: RW + acronym: UPE + description: [Unicast promiscuous enable., 0 = Disabled1 = Enabled] + range: [3, 3] + reset: 0 + sticky: '' + - access: RW + acronym: SBP + description: [Store bad packets., 0 = Disabled1 = Enabled] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: EN + description: [Receiver Enable., 0 = All incoming packets are immediately dropped + and are not stored in the receive FIFO. If a packet is already in-progress + when disabled it will be finished.1 = Incoming packet reception is enabled.] + range: [1, 1] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [0, 0] + reset: 0 + sticky: '' + offset: 256 + offset_end: [259, null] + offset_start: [256, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RCTL + reg_name: RCTL + size: 32 + table_ref: 37-50 + title_desc: Receive Control Register + view: PCI 3 +RDBAH: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXXXh + description: null + fields: + - access: RW + acronym: RDBAH + description: ['Receive Descriptor Base Address.Note:RDBAH[31:0] must be set to + 0.'] + range: [31, 0] + reset: null + sticky: '' + offset: 10244 + offset_end: [10247, null] + offset_start: [10244, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RDBAH + reg_name: RDBAH + size: 32 + table_ref: 37-54 + title_desc: Receive Descriptor Base Address High Register + view: PCI 3 +RDBAL: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXX0h + description: null + fields: + - access: RW + acronym: RDBAL + description: [Receive Descriptor Base Address Low] + range: [31, 4] + reset: null + sticky: '' + - access: RV + acronym: '0' + description: ['Writes are ignored, reads return 0.'] + range: [3, 0] + reset: 0 + sticky: '' + offset: 10240 + offset_end: [10243, null] + offset_start: [10240, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RDBAL + reg_name: RDBAL + size: 32 + table_ref: 37-53 + title_desc: Receive Descriptor Base Address Low Register + view: PCI 3 +RDH: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: RDH + description: [Receive Descriptor Head] + range: [15, 0] + reset: 0 + sticky: '' + offset: 10256 + offset_end: [10259, null] + offset_start: [10256, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RDH + reg_name: RDH + size: 32 + table_ref: 37-56 + title_desc: Receive Descriptor Head Register + view: PCI 3 +RDLEN: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 20] + reset: 0 + sticky: '' + - access: RW + acronym: LEN + description: [Descriptor Length] + range: [19, 7] + reset: 0 + sticky: '' + - access: RV + acronym: '0' + description: ['Writes are ignored, reads return 0.'] + range: [6, 0] + reset: 0 + sticky: '' + offset: 10248 + offset_end: [10251, null] + offset_start: [10248, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RDLEN + reg_name: RDLEN + size: 32 + table_ref: 37-55 + title_desc: Receive Descriptor Length Register + view: PCI 3 +RDT: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: RDT + description: [Receive Descriptor Tail] + range: [15, 0] + reset: 0 + sticky: '' + offset: 10264 + offset_end: [10267, null] + offset_start: [10264, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RDT + reg_name: RDT + size: 32 + table_ref: 37-57 + title_desc: Receive Descriptor Tail Register + view: PCI 3 +RDTR: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: WO + acronym: FPD + description: ['Flush Partial Descriptor. Writing this bit with 1 initiates an + immediate expiration of the timer, causing a writeback of any consumed receive + descriptors pending writeback, and results in a receive timer interrupt in + the ICR register. This bit is self clearing and always reads 0.'] + range: [31, 31] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [30, 16] + reset: 0 + sticky: '' + - access: RW + acronym: RPDT + description: ['Receive Packet Delay Timer ', 'Timer increments are ', 'RMII: 1.28 + microseconds', 'RGMII: 1.024 microseconds. ', See register description above] + range: [15, 0] + reset: 0 + sticky: '' + offset: 10272 + offset_end: [10275, null] + offset_start: [10272, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RDTR + reg_name: RDTR + size: 32 + table_ref: 37-58 + title_desc: RX Interrupt Delay Timer (Packet Timer) Register + view: PCI 3 +RFC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: RFC + description: [Number of receive fragment errors] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16552 + offset_end: [16555, null] + offset_start: [16552, null] + power_well: null + recurring: null + reg_base_name: RFC + reg_name: RFC + size: 32 + table_ref: 37-113 + title_desc: Receive Fragment Count Register + view: PCI 3 +RJC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: RJC + description: [Number of receive jabber errors] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16560 + offset_end: [16563, null] + offset_start: [16560, null] + power_well: null + recurring: null + reg_base_name: RJC + reg_name: RJC + size: 32 + table_ref: 37-115 + title_desc: Receive Jabber Count Register + view: PCI 3 +RLEC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: RLEC + description: [Number of packets with receive length errors.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16448 + offset_end: [16451, null] + offset_start: [16448, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RLEC + reg_name: RLEC + size: 32 + table_ref: 37-91 + title_desc: Receive Length Error Count Register + view: PCI 3 +RNBC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: RNBC + description: [Number of receive no buffer conditions] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16544 + offset_end: [16547, null] + offset_start: [16544, null] + power_well: null + recurring: null + reg_base_name: RNBC + reg_name: RNBC + size: 32 + table_ref: 37-111 + title_desc: Receive No Buffers Count Register + view: PCI 3 +ROC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: ROC + description: [Number of receive oversize errors] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16556 + offset_end: [16559, null] + offset_start: [16556, null] + power_well: null + recurring: null + reg_base_name: ROC + reg_name: ROC + size: 32 + table_ref: 37-114 + title_desc: Receive Oversize Count Register + view: PCI 3 +RSRPD: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 12] + reset: 0 + sticky: '' + - access: RW + acronym: SIZE + description: [Any packet received that is <= SIZE will assert an interrupt condition + (ICR.SRPD). This field is specified in bytes and includes the headers and + the CRC but not the VLAN header in the size calculation.] + range: [11, 0] + reset: 0 + sticky: '' + offset: 11264 + offset_end: [11267, null] + offset_start: [11264, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RSRPD + reg_name: RSRPD + size: 32 + table_ref: 37-61 + title_desc: Receive Small Packet Detect Interrupt Register + view: PCI 3 +RUC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: RUC + description: [Number of receive undersize errors] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16548 + offset_end: [16551, null] + offset_start: [16548, null] + power_well: null + recurring: null + reg_base_name: RUC + reg_name: RUC + size: 32 + table_ref: 37-112 + title_desc: Receive Undersize Count Register + view: PCI 3 +RXCSUM: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 10] + reset: 0 + sticky: '' + - access: RW + acronym: TUOFL + description: [TCP/UDP Checksum Off load Enable. This bit is used to enable the + TCP/UDP Checksum off-loading feature., 0 = TCP/UDP Checksum Off load Disabled1 + = Hardware will calculate the TCP or UDP checksum and indicate a pass/fail + indication to software via the TCP/UDP Checksum Error bit (TCPE).] + range: [9, 9] + reset: 0 + sticky: '' + - access: RW + acronym: IPOFL + description: [IP Checksum Off load Enable. This bit is used to enable the IP Checksum + off-loading feature., 0 = IP Checksum Off load Disabled1 = Hardware will calculate + the IP checksum and indicate a pass/fail indication to software via the IP + Checksum Error bit (IPE) in the ERROR field of the receive descriptor.] + range: [8, 8] + reset: 0 + sticky: '' + - access: RW + acronym: PCSS + description: ['Packet Checksum Start. This field controls the starting byte for + the Packet Checksum calculation. The Packet Checksum is the one''s complement + over the receive packet, starting from the byte indicated by PCSS (0 corresponds + to the first byte of the packet), after stripping.', 'For example, for an + Ethernet II frame encapsulated as an 802.3ac VLAN packet and with PCSS set + to 14, the packet checksum would include the entire encapsulated frame, excluding + the 14-byte Ethernet header (DA, SA, Type and Length) and the 4-byte VLAN + tag. The Packet Checksum will not include the Ethernet CRC if the RCTL.SECRC + bit is set. Software must make the required offsetting computation (to back + out the bytes that should not have been included and to include the pseudo-header) + prior to comparing the Packet Checksum against the TCP checksum stored in + the packet. '] + range: [7, 0] + reset: 0 + sticky: '' + offset: 20480 + offset_end: [20483, null] + offset_start: [20480, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RXCSUM + reg_name: RXCSUM + size: 32 + table_ref: 37-62 + title_desc: Receive Checksum Control Register + view: PCI 3 +RXDCTL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 65536 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 25] + reset: 0 + sticky: '' + - access: RW + acronym: GRAN + description: [Granularity of the thresholds in this register., '0 = Threshold + values are in units of Cache Lines, thresholds specified must not be greater + than 31 descriptors (496B) or 15 32B cache lines.1 = Threshold values are + in units of Descriptors (16B each)'] + range: [24, 24] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [23, 22] + reset: 0 + sticky: '' + - access: RW + acronym: WTHRESH + description: ['Write-back Threshold. This field controls the write-back of processed + receive descriptors. This threshold refers to the number of receive descriptors + in the GbE hardware buffer which are ready to be written back to host memory. + In the absence of external events (explicit flushes), the write-back will + occur only after more than WTHRESH descriptors are available for write-back.Note:Since + the default value for this field is 1, the descriptors are normally written + back as soon as one cache line is available. This field must contain a non-zero + value to take advantage of the write-back bursting capabilities of the EP80579''s + GbE.'] + range: [21, 16] + reset: 1 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [15, 14] + reset: 0 + sticky: '' + - access: RW + acronym: HTHRESH + description: ['Host Threshold. This field is used to control the fetching of descriptors + from host memory. This threshold refers to the number of valid, unprocessed + receive descriptors that must exist in host memory before they will be fetched.'] + range: [13, 8] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [7, 6] + reset: 0 + sticky: '' + - access: RW + acronym: PTHRESH + description: ['Prefetch Threshold. This field is used to control when a prefetch + of descriptors will be considered. This threshold refers to the number of + valid, unprocessed receive descriptors the chip has in its GbE hardware buffer. + If this number drops below PTHRESH, the algorithm will consider pre-fetching + descriptors from host memory. This fetch will not happen however unless there + are at least HTHRESH valid descriptors in host memory to fetch.'] + range: [5, 0] + reset: 0 + sticky: '' + offset: 10280 + offset_end: [10283, null] + offset_start: [10280, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RXDCTL + reg_name: RXDCTL + size: 32 + table_ref: 37-59 + title_desc: Receive Descriptor Control Register + view: PCI 3 +RXERRC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: RXERRC + description: [RX Error Count] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16396 + offset_end: [16399, null] + offset_start: [16396, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: RXERRC + reg_name: RXERRC + size: 32 + table_ref: 37-81 + title_desc: Receive Error Count Register + view: PCI 3 +SCC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: SCC + description: [Number of times a transmit encountered a single collision.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16404 + offset_end: [16407, null] + offset_start: [16404, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: SCC + reg_name: SCC + size: 32 + table_ref: 37-83 + title_desc: Single Collision Count Register + view: PCI 3 +STATUS: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0000XXXXh + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 10] + reset: 0 + sticky: '' + - access: RO + acronym: Reserved + description: [Reserved] + range: [9, 8] + reset: null + sticky: '' + - access: RO + acronym: SPEED + description: ['Link Speed Setting: Reflects speed setting of the MAC.', 'In GMII/MII + mode, these bits reflect the software CTRL.SPEED setting ', '? 00 => 10 Mbps', + '? 01 => 100 Mbps', '? 10 => 1000 Mbps', '? 11 => 1000 Mbps'] + range: [7, 6] + reset: null + sticky: '' + - access: RO + acronym: LINKMODE + description: [Mode. Based on CTRL_EXT. LINK_MODE., 0 = MAC is operating in GMII/MII + mode1 = Reserved] + range: [5, 5] + reset: null + sticky: '' + - access: RO + acronym: TXOFF + description: [Transmission Off. This bit indicates the state of the transmit function + when symmetrical flow control has been enabled and negotiated with the link + partner., '0 = Symmetrical flow control is disabled, or transmission is not + paused.1 = Symmetrical flow control is enabled, and the transmit function + is paused due to the reception of an XOFF frame. It is cleared upon expiration + of the pause timer or the receipt of an XON frame.'] + range: [4, 4] + reset: null + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [3, 2] + reset: 0 + sticky: '' + - access: RO + acronym: RSVD + description: [Reserved] + range: [1, 1] + reset: null + sticky: '' + - access: RO + acronym: FD + description: ['Full Duplex. This bit reflects the MAC duplex configuration. Normally, + the duplex setting for the link, as it should reflect the duplex configuration + negotiated between the PHY and link partner (copper link) or MAC and link + partner (fiber link).', 0 = Half Duplex mode1 = Full Duplex mode] + range: [0, 0] + reset: null + sticky: '' + offset: 8 + offset_end: [11, null] + offset_start: [8, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: STATUS + reg_name: STATUS + size: 32 + table_ref: 37-26 + title_desc: Device Status Register + view: PCI 3 +TADV: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: IDV + description: ['Interrupt Delay Value. ', Timer increments are, 'RMII: 1.28 microseconds', + 'RGMII: 1.024 microseconds. ', 'The transmit interrupt delay timer (TIDV) can + be used to coalesce transmit interrupts. However, it might be necessary to + ensure that no completed transmit remains unnoticed for too long an interval + in order ensure timely release of transmit buffers. This register can be used + to ENSURE that a transmit interrupt occurs at some predefined interval after + a transmit is completed. Like the delayed-transmit timer, the absolute transmit + timer ONLY applies to transmit descriptor operations where (a) interrupt-based + reporting is requested (RS set) and (b) the use of the timer function is requested + (IDE is set).', 'This feature operates by initiating a countdown timer upon + successfully transmitting the buffer. When the timer expires, a transmit-complete + interrupt (ICR.TXDW) is generated. The occurrence of either an immediate (non-scheduled) + or delayed transmit timer (TIDV) expiration interrupt halts the TADV timer + and eliminates any spurious second interrupts.', 'Setting the value to 0b + disables the transmit absolute delay function. If an immediate (nonscheduled) + interrupt is desired for any transmit descriptor, the descriptor IDE should + be set to 0b.Note:This timer ONLY causes an interrupt. It does NOT cause a + writeback'] + range: [15, 0] + reset: 0 + sticky: '' + offset: 14380 + offset_end: [14383, null] + offset_start: [14380, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TADV + reg_name: TADV + size: 32 + table_ref: 37-77 + title_desc: Transmit Absolute Interrupt Delay Value Register + view: PCI 3 +TCTL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 8 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 25] + reset: 0 + sticky: '' + - access: RW + acronym: RTLC + description: ['Re-Transmit on Late Collision. This bit configures the hardware + to perform retransmission of packets when a late collision is detected. Note + that the collision window is speed dependent: 64B for 10/100 Mbps and 512B + for 1Gbps operation. If a late collision is detected when this bit is clear, + the transmit function assumes the packet is successfully transmitted.Note:This + bit is ignored in full-duplex mode.'] + range: [24, 24] + reset: 0 + sticky: '' + - access: RV + acronym: PBE + description: [Packet Burst Enable. The EP80579's GbE does not support Packet Bursting + for 1Gbps half-duplex transmit operation. This bit must be set to 0.] + range: [23, 23] + reset: 0 + sticky: '' + - access: RW + acronym: SWXOFF + description: ['Software XOFF Transmission. When set to a 1 the device will schedule + the transmission of an XOFF (PAUSE) frame using the current value of the PAUSE + timer. This bit clears itself upon transmission of the XOFF frame.Note:While + 802.3x flow control is only defined during full duplex operation, the sending + of PAUSE frames via the SWXOFF bit is not gated by the duplex settings within + the device. Software should not write a 1 to this bit while the device is + configured for half duplex operation.'] + range: [22, 22] + reset: 0 + sticky: '' + - access: RW + acronym: COLD + description: ['Collision Distance. Wire speeds of 1Gbps result in a very short + collision radius with traditional minimum packet sizes. This bit specifies + the minimum number of bytes in the packet to satisfy the desired collision + distance for proper CSMA/CD operation. It is important to note that the resulting + packet has special characters appended to the end, not regular data characters. + Hardware strips special characters for packets that go from 1 Gbps environments + to 100 Mbps environments.Note:The hardware checks and pads to this value even + in full-duplex operation.'] + range: [21, 12] + reset: 0 + sticky: '' + - access: RW + acronym: CT + description: ['Collision Threshold. Software may choose to abort packet transmission + in less than the Ethernet mandated 16 collisions. This field determines the + number of attempts at retransmission prior to giving up on the packet (not + including the first transmission attempt). The Ethernet back-off algorithm + is implemented and clamps to the maximum number of slot-times after 10 retries. + This field only has meaning when in half-duplex operation.Note:While this + field can be varied, it should be set to a value of 15 in order to comply + with the IEEE specification requiring a total of 16 attempts.'] + range: [11, 4] + reset: 0 + sticky: '' + - access: RW + acronym: PSP + description: ['Pad Short Packets to 64B with valid data characters, NOT padding + symbols.', '0 = Do not pad short packets1 = Pad short packetsNote:This is + not the same as the mini-mum collision distance.'] + range: [3, 3] + reset: 1 + sticky: '' + - access: RV + acronym: Rsvd + description: ['Reserved. '] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: EN + description: [Enable., 0 = Writing this bit to 0 will stop transmission after + any in progress packets are sent. Data remains in the transmit FIFO until + the device is re-enabled. Software should combine this with reset if the packets + in the FIFO should be flushed.1 = The transmitter is enabled.] + range: [1, 1] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: ['Reserved. '] + range: [0, 0] + reset: 0 + sticky: '' + offset: 1024 + offset_end: [1027, null] + offset_start: [1024, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TCTL + reg_name: TCTL + size: 32 + table_ref: 37-67 + title_desc: Transmit Control Register + view: PCI 3 +TDBAH: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXXXh + description: null + fields: + - access: RW + acronym: TDBAH + description: ['Transmit Descriptor Base AddressNote:TDBAH[31:0] must be set to + 0.'] + range: [31, 0] + reset: null + sticky: '' + offset: 14340 + offset_end: [14343, null] + offset_start: [14340, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TDBAH + reg_name: TDBAH + size: 32 + table_ref: 37-71 + title_desc: Transmit Descriptor Base Address High Register + view: PCI 3 +TDBAL: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXX0h + description: null + fields: + - access: RW + acronym: TDBAL + description: [Transmit Descriptor Base Address Low] + range: [31, 4] + reset: null + sticky: '' + - access: RV + acronym: '0' + description: ['Writes are ignored, reads return 0.'] + range: [3, 0] + reset: 0 + sticky: '' + offset: 14336 + offset_end: [14339, null] + offset_start: [14336, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TDBAL + reg_name: TDBAL + size: 32 + table_ref: 37-70 + title_desc: Transmit Descriptor Base Address Low Register + view: PCI 3 +TDH: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: TDH + description: [Transmit Descriptor Head] + range: [15, 0] + reset: 0 + sticky: '' + offset: 14352 + offset_end: [14355, null] + offset_start: [14352, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TDH + reg_name: TDH + size: 32 + table_ref: 37-73 + title_desc: Transmit Descriptor Head Register + view: PCI 3 +TDLEN: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 20] + reset: 0 + sticky: '' + - access: RW + acronym: LEN + description: [Descriptor Length] + range: [19, 7] + reset: 0 + sticky: '' + - access: RV + acronym: '0' + description: ['Writes are ignored, reads return 0.'] + range: [6, 0] + reset: 0 + sticky: '' + offset: 14344 + offset_end: [14347, null] + offset_start: [14344, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TDLEN + reg_name: TDLEN + size: 32 + table_ref: 37-72 + title_desc: Transmit Descriptor Length Register + view: PCI 3 +TDT: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: TDT + description: [Transmit Descriptor Tail] + range: [15, 0] + reset: 0 + sticky: '' + offset: 14360 + offset_end: [14363, null] + offset_start: [14360, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TDT + reg_name: TDT + size: 32 + table_ref: 37-74 + title_desc: Transmit Descriptor Tail Register + view: PCI 3 +TIDV: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: IDV + description: ['Interrupt Delay Value. ', Timer increments are, 'RMII: 1.28 microseconds', + 'RGMII: 1.024 microseconds. ', '? This register is used to delay interrupt notification + for transmit operations by coalescing interrupts for multiple transmitted + buffers. Delaying interrupt notification helps maximize the amount of transmit + buffers reclaimed by a single interrupt. This feature only applies to transmit + descriptor operations where (a) interrupt-based reporting is requested (RS + set) and (b) the use of the timer function is requested (IDE is set).', '? + This feature operates by initiating a countdown timer upon successfully transmitting + the buffer. If a subsequent transmit delayed-interrupt is scheduled before + the timer expires, the timer is re-initialized to the programmed value and + re-starts its countdown. When the timer expires, a transmit-complete interrupt + (ICR.TXDW) is generated.', '? Hardware always loads the transmit interrupt + counter whenever it processes a descriptor with IDE set even if it is already + counting down due to a previous descriptor.', '? Setting the value to 0 is + not allowed. If an immediate (non-scheduled) interrupt is desired for any + transmit descriptor, the descriptor IDE should be set to 0.', '? The occurrence + of either an immediate (non-scheduled) or absolute transmit timer interrupt + will halt the TIDV timer and eliminate any spurious second interrupts.', '? + Transmit interrupts due to a Transmit Absolute Timer (TADV) expiration or + an immediate interrupt (RS =1, IDE=0) will cancel a pending TIDV interrupt. + The TIDV countdown timer is reloaded but halted, though it may be restarted + by a processing a subsequent transmit descriptor.'] + range: [15, 0] + reset: 0 + sticky: '' + offset: 14368 + offset_end: [14371, null] + offset_start: [14368, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TIDV + reg_name: TIDV + size: 32 + table_ref: 37-75 + title_desc: Transmit Interrupt Delay Value Register + view: PCI 3 +TIPG: + bar: CSRBAR + bus_device_function: M:2:0 + default: 6299656 + description: null + fields: + - access: RV + acronym: Rsvd + description: [Reserved] + range: [31, 30] + reset: 0 + sticky: '' + - access: RW + acronym: IPGR2 + description: ['IPG Receive Time 2. ', 'Specifies the total length of the IPG time + for non back-to-back transmissions. Measured in increments of the MAC clock: ', + '? 8 ns MAC clock when operating @ 1 Gbps (82544GC/EI only).', '? 80 ns MAC + clock when operating @ 100 Mbps ', '? 800 ns MAC clock when operating @ 10 + Mbps. ', 'In order to calculate the actual IPG value, a value of six should + be added to the IPGR2 value as six MAC clocks are used by the MAC for synchronization + and internal engines. ', 'For the IEEE 802.3 standard IPG value of 96-bit + time, the value that should be programmed into IPGR2 is six (total IPG delay + of 12 MAC clock cycles) ', 'According to the IEEE802.3 standard, IPGR1 should + be 2/3 of IPGR2 value.IPGR2 is significant only in half-duplex mode of operation. '] + range: [29, 20] + reset: 6 + sticky: '' + - access: RW + acronym: IPGR1 + description: ['IPG Receive Time 1. ', 'Specifies the length of the first part + of the IPG time for non back-to- back transmissions. During this time, the + internal IPG counter restarts if any carrier event occurs. Once the time specified + in IPGR1 has elapsed, carrier sense does not affect the IPG counter. According + to the IEEE802.3 standard, IPGR1 should be 2/3 of IPGR2 value. Measured in + increments of the MAC clock:', '? 8 ns MAC clock when operating @ 1 Gbps ', + '? 80 ns MAC clock when operating @ 100 Mbps ', '? 800 ns MAC clock when operating + @ 10 Mbps. ', 'For IEEE 802.3 minimum IPG value of 96-bit time, the value + that should be programmed into IPGR1 is eight. IPGR1 is significant only in + half-duplex mode of operation. '] + range: [19, 10] + reset: 8 + sticky: '' + - access: RW + acronym: IPGT + description: ['IPG Transmit Time ', Specifies the IPG time for back-to-back packet + transmissions, 'Measured in increments of the MAC clock: ', '? 8 ns MAC clock + when operating @ 1 Gbps.', '? 80 ns MAC clock when operating @ 100 Mbps. ', + '? 800 ns MAC clock when operating @ 10 Mbps. ', 'To calculate the IPG value + for 10/100/1000BASE-T applications, a value of four should be added to the + IPGT value as four clocks are used by the MAC as internal overhead. The value + that should be programmed into IPGT is 8. These values are recommended to + assure that the minimum IPG gap is met under all synchronization conditions. '] + range: [9, 0] + reset: 8 + sticky: '' + offset: 1040 + offset_end: [1043, null] + offset_start: [1040, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TIPG + reg_name: TIPG + size: 32 + table_ref: 37-68 + title_desc: Transmit IPG Register + view: PCI 3 +TNCRS: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: TNCRS + description: [Number of transmissions without a CRS assertion from the PHY.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16436 + offset_end: [16439, null] + offset_start: [16436, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TNCRS + reg_name: TNCRS + size: 32 + table_ref: 37-89 + title_desc: Transmit with No CRS Count Register + view: PCI 3 +TORH: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: TORH + description: [Number of total octets received - upper 4 bytes] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16580 + offset_end: [16583, null] + offset_start: [16580, null] + power_well: null + recurring: null + reg_base_name: TORH + reg_name: TORH + size: 32 + table_ref: 37-117 + title_desc: Total Octets Received High Register + view: PCI 3 +TORL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: TORL + description: [Number of total octets received - lower 4 bytes] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16576 + offset_end: [16579, null] + offset_start: [16576, null] + power_well: null + recurring: null + reg_base_name: TORL + reg_name: TORL + size: 32 + table_ref: 37-116 + title_desc: Total Octets Received Low Register + view: PCI 3 +TOTH: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: TOTH + description: [Number of total octets transmitted - upper 4 bytes] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16588 + offset_end: [16591, null] + offset_start: [16588, null] + power_well: null + recurring: null + reg_base_name: TOTH + reg_name: TOTH + size: 32 + table_ref: 37-119 + title_desc: Total Octets Transmitted High Register + view: PCI 3 +TOTL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: TOTL + description: [Number of total octets transmitted - lower 4 bytes] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16584 + offset_end: [16591, null] + offset_start: [16584, null] + power_well: null + recurring: null + reg_base_name: TOTL + reg_name: TOTL + size: 32 + table_ref: 37-118 + title_desc: Total Octets Transmitted Low Register + view: PCI 3 +TPR: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: TPR + description: [Total of all packets received] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16592 + offset_end: [16595, null] + offset_start: [16592, null] + power_well: null + recurring: null + reg_base_name: TPR + reg_name: TPR + size: 32 + table_ref: 37-120 + title_desc: Total Packets Received Register + view: PCI 3 +TPT: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: TPT + description: [Number of all packets transmitted] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16596 + offset_end: [16599, null] + offset_start: [16596, null] + power_well: null + recurring: null + reg_base_name: TPT + reg_name: TPT + size: 32 + table_ref: 37-121 + title_desc: Total Packets Transmitted Register + view: PCI 3 +TSCTC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: TSCTC + description: [Number of TCP Segmentation contexts transmitted count] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16632 + offset_end: [16635, null] + offset_start: [16632, null] + power_well: null + recurring: null + reg_base_name: TSCTC + reg_name: TSCTC + size: 32 + table_ref: 37-129 + title_desc: TCP Segmentation Context Transmitted Count Register + view: PCI 3 +TSCTFC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: TSCTFC + description: [Number of TCP Segmentation contexts where the device failed to transmit + the entire data payload] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16636 + offset_end: [16639, null] + offset_start: [16636, null] + power_well: null + recurring: null + reg_base_name: TSCTFC + reg_name: TSCTFC + size: 32 + table_ref: 37-130 + title_desc: TCP Segmentation Context Transmit Fail Count Register + view: PCI 3 +TSPMT: + bar: CSRBAR + bus_device_function: M:2:0 + default: 16778240 + description: null + fields: + - access: RW + acronym: TSPBP + description: ['TCP Segmentation Packet Buffer Padding, value is in bytes. This + field allows software configuration of packet buffer space which must be reserved + as "pad" for worst-case header insertion. To ensure that this value does not + prevent descriptors from being serviced at all, it is necessary that the transmit + packet buffer allocation should be larger than the sum of (maximum TCP HDRLEN + + maximum MSS + TSPMT.TMPBP + 80 bytes).'] + range: [31, 16] + reset: 256 + sticky: '' + - access: RW + acronym: TSMT + description: ['TCP Segmentation Minimum Transfer, value is in bytes. The DMA will + attempt to issue burst fetches for as much data as possible, and it is possible + for the transmit DMA to cause the transmit packet buffer to approach fullness + (less the pad specified). However, if the packet buffer empties slightly, + the transmit DMA could initiate a series of small transfers.', 'To further + optimize the efficiency of the transmit DMA during TCP segmentation operation, + the this TSPMT.TSMT field allows software configuration of the minimum number + of bytes which the DMA should attempt to transfer in a single burst operation. + The transmit DMA will use this value to refrain from issuing a burst read + until at least TSPMT.TSMT bytes of data from the current data descriptor can + be stored in the packet buffer.', 'This check will be ignored if, after a + series of DMA operations, the descriptor contains a smaller number of unfetched + data bytes. To ensure that this minimum threshold does not prevent descriptors + from being serviced at all, it is necessary that the transmit packet buffer + allocation should be larger than the sum of (TSPMT.TSMT + TSPMT.TSPBP + 80 + bytes).'] + range: [15, 0] + reset: 1024 + sticky: '' + offset: 14384 + offset_end: [14387, null] + offset_start: [14384, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TSPMT + reg_name: TSPMT + size: 32 + table_ref: 37-78 + title_desc: TCP Segmentation Pad And Minimum Threshold Register + view: PCI 3 +TXDCTL: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RW + acronym: LWTHRESH + description: ['Transmit Descriptor Low Threshold. This field controls the number + of pre-fetched transmit descriptors at which a transmit descriptor-low interrupt + is reported. Asserting ICR.TXD_LOW only when the processing distance from + the TDT register drops below LWTHRESH may allow software to operate more efficiently + by maintaining a continuous addition of transmit work, interrupting only when + the hardware nears completion of all submitted work.', An interrupt condition + is asserted when the number of descriptors available transitions from, threshold_level + + 1 -> threshold_level, 'where LWTHRESH specifies a multiple of 8 descriptors, + (i.e. threshold_level = 8*LWTHRESH).', Setting this value to 0 will cause + this interrupt to be generated only when the transmit descriptor cache becomes + completely empty.] + range: [31, 25] + reset: 0 + sticky: '' + - access: RW + acronym: GRAN + description: [Granularity of the thresholds in this register., 0 = Cache Lines1 + = Descriptors (16B each)] + range: [24, 24] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [23, 22] + reset: 0 + sticky: '' + - access: RW + acronym: WTHRESH + description: ['Write-back Threshold. This field controls the write-back of processed + transmit descriptors. This threshold refers to the number of transmit descriptors + in the GbE hardware buffer which are ready to be written back to host memory. + In the absence of external events (explicit flushes), the write-back will + occur only after more than WTHRESH descriptors are available for write-back.', + 'Since write-back notification of transmit descriptor completion is optional + (under the control of the RS bit in the descriptor), not all processed descriptors + are counted with respect to WTHRESH (any single transmit descriptor with RS=0 + is consumed with no writeback notification performed). When WTHRESH is non-zero, + processing a descriptor with RS=1 initiates accumulation of pending writebacks; + accumulated writebacks will include even those descriptors with RS=0, in order + to optimize writeback bursts.Note:When WTHRESH value is set to 0, transmit + descriptor writeback notification will be similar to the 82452 behavior. In + accordance with WTHRESH=0, the writeback notification for a descriptor with + RS=1 will occur as soon as the descriptor is processed. In addition, processed + transmit descriptors are not written-back in entirety; only the descriptor + status field is written back/ updated. This 82542-compatible mode is the default + HW behavior.'] + range: [21, 16] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [15, 14] + reset: 0 + sticky: '' + - access: RW + acronym: HTHRESH + description: ['Host Threshold. This field is used to control the fetching of descriptors + from host memory. This threshold refers to the number of valid, unprocessed + receive descriptors that must exist in host memory before they will be fetched.'] + range: [13, 8] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [7, 6] + reset: 0 + sticky: '' + - access: RW + acronym: PTHRESH + description: ['Prefetch Threshold. This field is used to control when a prefetch + of descriptors will be considered. This threshold refers to the number of + valid, unprocessed transmit descriptors the chip has in its GbE hardware buffer. + If this number drops below PTHRESH, the algorithm will consider pre-fetching + descriptors from host memory. This fetch will not happen however unless there + are at least HTHRESH valid descriptors in host memory to fetch.'] + range: [5, 0] + reset: 0 + sticky: '' + offset: 14376 + offset_end: [14379, null] + offset_start: [14376, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: TXDCTL + reg_name: TXDCTL + size: 32 + table_ref: 37-76 + title_desc: Transmit Descriptor Control Register + view: PCI 3 +VET: + bar: CSRBAR + bus_device_function: M:2:0 + default: 33024 + description: To be compliant with the 802.3ac standard, this register must be programmed + with the value 0x00_00_81_00 + fields: + - access: RV + acronym: RSVD + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: '' + - access: RW + acronym: VET + description: ['To be compliant with the 802.3ac standard, this register must be + programmed with the value 0x00_00_81_00.'] + range: [15, 0] + reset: 33024 + sticky: '' + offset: 56 + offset_end: [59, null] + offset_start: [56, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: VET + reg_name: VET + size: 32 + table_ref: 37-34 + title_desc: VLAN EtherType Register + view: PCI 3 +VFTA[0-127]: + bar: CSRBAR + bus_device_function: M:2:0 + default: XXXXXXXXh + description: null + fields: + - access: RW + acronym: VLAN_Vector + description: [VLAN_Vector 32b vector of VLAN filter table information.] + range: [31, 0] + reset: null + sticky: '' + offset: 22016 + offset_end: [22019, 4] + offset_start: [22016, 4] + power_well: 'Gbe1/2:' + recurring: 128 + reg_base_name: VFTA + reg_name: VFTA[0-127] + size: 32 + table_ref: 37-66 + title_desc: 128 VLAN Filter Table Array Registers + view: PCI 3 +WUC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RO + acronym: RSVD + description: [Reserved] + range: [31, 4] + reset: 0 + sticky: '' + - access: RW + acronym: APMPME + description: ['Assert PME On APM Wakeup - ', 'If it is 1, the GbE will set the + PME_Status bit in the Power Management Control / Status Register (PMCSR) and + assert GBE_PME_WAKE when APM Wakeup is enabled and the GbE receives a matching + magic packet.', '*Note that this bit is loaded from the EEPROM, if present'] + range: [3, 3] + reset: 0 + sticky: '' + - access: RWC + acronym: PME_Status + description: [PME_Status, This bit is set when the GbE receives a wakeup event. + It is the same as the PME_Status bit in the Power Management Control / Status + Register (PMCSR). Writing a "1" to this bit will clear it and clear the PME_Status + bit in the PMCSR.] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: PME_EN + description: [PME_En, This read/write bit is used by the driver to access the + PME_En bit of the Power Management Control / Status Register (PMCSR) without + writing to PCI configuration space.] + range: [1, 1] + reset: 0 + sticky: '' + - access: RW + acronym: APME + description: ['Advance Power Management Enable - ', 'If "1", APM Wakeup is enabled.', + '*Note that this bit is loaded from the EEPROM, if present'] + range: [0, 0] + reset: 0 + sticky: '' + offset: 22528 + offset_end: [22531, null] + offset_start: [22528, null] + power_well: null + recurring: null + reg_base_name: WUC + reg_name: WUC + size: 32 + table_ref: 37-131 + title_desc: Wake Up Control Register (0x05800; RW) + view: PCI 3 +WUFC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: RSVD + description: [Reserved. Should be set to 0.] + range: [31, 20] + reset: 0 + sticky: '' + - access: RW + acronym: FLX3 + description: [Flexible Filter 3 Enable] + range: [19, 19] + reset: 0 + sticky: '' + - access: RW + acronym: FLX2 + description: [Flexible Filter 2 Enable] + range: [18, 18] + reset: 0 + sticky: '' + - access: RW + acronym: FLX1 + description: [Flexible Filter 1 Enable] + range: [17, 17] + reset: 0 + sticky: '' + - access: RW + acronym: FLX0 + description: [Flexible Filter 0 Enable] + range: [16, 16] + reset: 0 + sticky: '' + - access: RW + acronym: RSVD + description: [Reserved. Should be set to 0.] + range: [15, 15] + reset: 0 + sticky: '' + - access: RV + acronym: RSVD + description: [Reserved. Should be set to 0.] + range: [14, 8] + reset: 0 + sticky: '' + - access: RW + acronym: IPV6 + description: [Directed IPv6 Packet Wake Up Enable] + range: [7, 7] + reset: 0 + sticky: '' + - access: RW + acronym: IPV4 + description: [Directed IPv4 Packet Wake Up Enable] + range: [6, 6] + reset: 0 + sticky: '' + - access: RW + acronym: ARP + description: [ARP/IPv4 Request Packet Wake Up Enable] + range: [5, 5] + reset: 0 + sticky: '' + - access: RW + acronym: BC + description: [Broadcast Wake Up Enable] + range: [4, 4] + reset: 0 + sticky: '' + - access: RW + acronym: MC + description: [Directed Multicast Wake Up Enable] + range: [3, 3] + reset: 0 + sticky: '' + - access: RW + acronym: EX + description: [Directed Exact Wake Up Enable] + range: [2, 2] + reset: 0 + sticky: '' + - access: RW + acronym: MAG + description: [Magic Packet Wake Up Enable] + range: [1, 1] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved] + range: [0, 0] + reset: 0 + sticky: '' + offset: 22536 + offset_end: [22539, null] + offset_start: [22536, null] + power_well: null + recurring: null + reg_base_name: WUFC + reg_name: WUFC + size: 32 + table_ref: 37-132 + title_desc: Wake Up Filter Control Register (0x05808; RW) + view: PCI 3 +WUS: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RV + acronym: RSVD + description: [Reserved. Should be set to 0.] + range: [31, 20] + reset: 0 + sticky: '' + - access: RWC + acronym: FLX3 + description: [Flexible Filter 3 Match] + range: [19, 19] + reset: 0 + sticky: '' + - access: RWC + acronym: FLX2 + description: [Flexible Filter 2 Match] + range: [18, 18] + reset: 0 + sticky: '' + - access: RWC + acronym: FLX1 + description: [Flexible Filter 1 Match] + range: [17, 17] + reset: 0 + sticky: '' + - access: RWC + acronym: FLX0 + description: [Flexible Filter 0 Match] + range: [16, 16] + reset: 0 + sticky: '' + - access: RV + acronym: Reserved + description: ['Reserved. '] + range: [15, 8] + reset: 0 + sticky: '' + - access: RWC + acronym: IPV6 + description: [Directed IPv6 Packet Wake Up Packet Received] + range: [7, 7] + reset: 0 + sticky: '' + - access: RWC + acronym: IPV4 + description: [Directed IPv4 Packet Wake Up Packet Received] + range: [6, 6] + reset: 0 + sticky: '' + - access: RWC + acronym: ARP + description: [ARP/IPv4 Request Packet Wake Up Packet Received] + range: [5, 5] + reset: 0 + sticky: '' + - access: RWC + acronym: BC + description: [Broadcast Wake Up Packet Received] + range: [4, 4] + reset: 0 + sticky: '' + - access: RWC + acronym: MC + description: ['Directed Multicast Wake Up Packet Received ', 'The packet was a + multicast packet whose hashed to a value that corresponded to a 1 bit in the + Multicast Table ArrayNote:If the MAC has been configured for promiscuous mode, + a multicast wakeup will occur if a broadcast packet is received. This is because + a broadcast message is a special type of multicast message. Refer to 802.3.'] + range: [3, 3] + reset: 0 + sticky: '' + - access: RWC + acronym: EX + description: [Directed Exact Wake Up Packet Received, The packet's address matched + one of the 16 pre-programmed exact values in the Receive Address registers] + range: [2, 2] + reset: 0 + sticky: '' + - access: RWC + acronym: MAG + description: [Magic Packet Wake Up Packet Received] + range: [1, 1] + reset: 0 + sticky: '' + - access: RV + acronym: Rsvd + description: [Reserved. Must be written as '0'] + range: [0, 0] + reset: 0 + sticky: '' + offset: 22544 + offset_end: [22547, null] + offset_start: [22544, null] + power_well: null + recurring: null + reg_base_name: WUS + reg_name: WUS + size: 32 + table_ref: 37-133 + title_desc: Wake Up Status Register (0x05810; RW) + view: PCI 3 +XOFFRXC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: XOFFRXC + description: [Number of XOFF packets received.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16464 + offset_end: [16467, null] + offset_start: [16464, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: XOFFRXC + reg_name: XOFFRXC + size: 32 + table_ref: 37-94 + title_desc: XOFF Received Count Register + view: PCI 3 +XOFFTXC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: XOFFTXC + description: [Number of XOFF packets transmitted.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16468 + offset_end: [16471, null] + offset_start: [16468, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: XOFFTXC + reg_name: XOFFTXC + size: 32 + table_ref: 37-95 + title_desc: XOFF Transmitted Count Register + view: PCI 3 +XONRXC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: XONRXC + description: [Number of XON packets received.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16456 + offset_end: [16459, null] + offset_start: [16456, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: XONRXC + reg_name: XONRXC + size: 32 + table_ref: 37-92 + title_desc: XON Received Count Register + view: PCI 3 +XONTXC: + bar: CSRBAR + bus_device_function: M:2:0 + default: 0 + description: null + fields: + - access: RC + acronym: XONTXC + description: [Number of XON packets transmitted.] + range: [31, 0] + reset: 0 + sticky: '' + offset: 16460 + offset_end: [16463, null] + offset_start: [16460, null] + power_well: 'Gbe1/2:' + recurring: null + reg_base_name: XONTXC + reg_name: XONTXC + size: 32 + table_ref: 37-93 + title_desc: XON Transmitted Count Register + view: PCI 3 diff --git a/parse_datasheet/output/smrbase.yaml b/parse_datasheet/output/smrbase.yaml new file mode 100644 index 0000000..1aac40f --- /dev/null +++ b/parse_datasheet/output/smrbase.yaml @@ -0,0 +1,2609 @@ +AAAAREG: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 2863311530 + description: 'AAAAREG: Fixed A Pattern' + fields: + - access: RO + acronym: AAAA + description: ['Hardwired to As for read-return '] + range: [31, 0] + reset: 2863311530 + sticky: N + offset: 236 + offset_end: [239, null] + offset_start: [236, null] + power_well: Core + recurring: null + reg_base_name: AAAAREG + reg_name: AAAAREG + size: 32 + table_ref: 16-256 + title_desc: Fixed A Pattern Register + view: PCI +DCALADDR: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: DCALADDR - DCAL Address Register + fields: + - access: RW + acronym: DCALADDR + description: [DCAL Address and Other Information based on DCALCSR.OPCODE. See + Table 16-230.] + range: [31, 0] + reset: 0 + sticky: N + offset: 68 + offset_end: [71, null] + offset_start: [68, null] + power_well: Core + recurring: null + reg_base_name: DCALADDR + reg_name: DCALADDR + size: 32 + table_ref: 16-229 + title_desc: DCAL Address Register + view: PCI +DCALCSR: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: DCALCSR - DCAL Control and Status Register + fields: + - access: RWS + acronym: START + description: [Start Operation, 'When set to 1 by software, the operation selected + by the DCALCSR.OPCODE is initiated. Hardware clears this bit when the operation + is complete.'] + range: [31, 31] + reset: 0 + sticky: N + - access: RW + acronym: FAIL + description: [Completion Status, '1xx = Fail, 0xx = Pass', 'Note: Best practice + is to rely on MemBIST following calibration to confirm a reliable DRAM interface.'] + range: [30, 28] + reset: 0 + sticky: N + - access: RW + acronym: BASPAT + description: ['Basic Data Pattern Enable: This controls which data pattern is + used for the DQS Delay calibration. Setting this field enables the use of + the basic data pattern selected by the DCALCSR.PATTERN bits. When cleared, + the extended data pattern specified in the DDQSCVDP and DDQSCADP registers + is used. Note: extended data pattern mode is not to be used in 2T configurations.'] + range: [27, 27] + reset: 0 + sticky: N + - access: RW + acronym: RSTREGSS + description: ['Reset Registers in Single Step Mode: Reset DCALDATA CSR in single + step calibration mode. This bit should be set during the first step of a single + step calibration. It will enable hardware to clear all registers and status + bits during the calibration step the same way hardware does on the first step + of an automatic "all passes" calibration.'] + range: [26, 26] + reset: 0 + sticky: N + - access: RO + acronym: Reserved + description: [Reserved] + range: [25, 24] + reset: 0 + sticky: N + - access: RW + acronym: SGLSTP + description: ['Single Step Calibration Operation:', Applies only to Receive enable + and DQS cal., '"1" = Single step - a single step of the algorithm selected + by the DCALCSR.OPCODE is run by hardware. No data analysis is run."0" = All + passes - all steps of the algorithm selected by the DACLCSR.OPCODE is run + by hardware including data analysis.'] + range: [23, 23] + reset: 0 + sticky: N + - access: RW + acronym: CS + description: ['Chip select:', 'This field corresponds to the chip select outputs: + CS[1:0]. This field Applies to NOP, Refresh, Precharge all, and MRS/EMRS commands. + It also applies to Receive Enable, and DQS Delay cal in single step mode.', + '01: select Rank 0', '10: select Rank 1', '00: Reserved', '11: ReservedNote:Set + CS to 01 for Self Refresh Entry. Hardware will automatically detect presence + of a second rank/DIMM and sequence Self Refresh Entry via both chip selects + if necessary.'] + range: [22, 21] + reset: 0 + sticky: N + - access: RO + acronym: Reserved + description: [Reserved] + range: [20, 19] + reset: 0 + sticky: N + - access: RW + acronym: PAT + description: ['Data pattern: for DQS cal. This sets the burst length 4 pattern + for a nibble of data. The pattern is repeated for BL8. This pattern is replicated + on all nibbles of the data bus.', '"000" = F > 0 > F > 0"001" = 0 > F > 0 + > F"010" = A > 5 > A > 5"011" = 5 > A > 5 > A"100" = C > 3 > C > 3"101" = + 3 > C > 3 > C"110" = 9 > 6 > 9 > 6"111" = 6 > 9 > 6 > 9'] + range: [18, 16] + reset: 0 + sticky: N + - access: RW + acronym: DARWPR + description: ['Disable FIFO reset: in single pass mode.', Applies only to Receiver + enable and DQS cal., 'When set to 1, this bit inhibits the core to DDR cluster + reset signal generated during the calibration modes. This prevents the DDR + cluster synchronizer FIFO write pointer and data latches from being reset + so that they can be read out of the cluster using the error monitor function. + The reset signal can only be disabled in single step mode. When the DCALCSR.SGLSTP + bit is set to 0, the DARWPR bit has no effect.'] + range: [15, 15] + reset: 0 + sticky: N + - access: RW + acronym: OPMODS + description: ['Operation modifiers: See Table 16-224, Table 16-224, Table 16-227, + and Table 16-235 for details'] + range: [14, 4] + reset: 0 + sticky: N + - access: RW + acronym: OPCODE + description: ['OPCODE:', '"0000" = NOP"0001" = Refresh (SeeTable 16-226) "0010" + = Pre-Charge"0011" = MRS/EMRS', '"0100" = Self-Refresh-Exit (SeeTable 16-226) + "0101" = Automatic DQS Delay Calibration"0110"= Reserved"0111" = DLL BIST', + '"1100" = Automatic Receive Enable Calibration', '"1101" = Self-Refresh Entry + (SeeTable 16-226) ', '"1110" = Error Monitor/Read DDRIO FIFO', '"1111" = ZQ + Calibration', All other settings are reserved] + range: [3, 0] + reset: 0 + sticky: N + offset: 64 + offset_end: [67, null] + offset_start: [64, null] + power_well: Core + recurring: null + reg_base_name: DCALCSR + reg_name: DCALCSR + size: 32 + table_ref: 16-223 + title_desc: DCAL Control and Status Register + view: PCI +DCALDATA[0-71]: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: DCALData - DRAM Calibration Data Registers + fields: + - access: RW + acronym: DCALDATA + description: [DCAL Data and other information based on DCALCSR.OPCODE. See Table + 16-232.] + range: [7, 0] + reset: 0 + sticky: N + offset: 72 + offset_end: [72, 1] + offset_start: [72, 1] + power_well: Core + recurring: 72 + reg_base_name: DCALDATA + reg_name: DCALDATA[0-71] + size: 8 + table_ref: 16-231 + title_desc: DRAM Calibration Data Register + view: PCI +DDQSCADP0: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 2863398911 + description: 'DDQSCADP0: DQS Delay Cal Pattern' + fields: + - access: RW + acronym: AP0 + description: [Aggressor pattern 0] + range: [31, 0] + reset: 2863398911 + sticky: '' + offset: 220 + offset_end: [223, null] + offset_start: [220, null] + power_well: Core + recurring: null + reg_base_name: DDQSCADP0 + reg_name: DDQSCADP0 + size: 32 + table_ref: 16-250 + title_desc: DQS Delay Calibration Aggressor Pattern 0 Register + view: PCI +DDQSCADP1: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 3677592801 + description: 'DDQSCADP1: DQS Delay Cal Pattern' + fields: + - access: RW + acronym: AP1 + description: [Aggressor pattern 1] + range: [31, 0] + reset: 3677592801 + sticky: '' + offset: 224 + offset_end: [227, null] + offset_start: [224, null] + power_well: Core + recurring: null + reg_base_name: DDQSCADP1 + reg_name: DDQSCADP1 + size: 32 + table_ref: 16-251 + title_desc: DQS Delay Calibration Aggressor Pattern 1 Register + view: PCI +DDQSCVDP0: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 2863270405 + description: 'DDQSCVDP0: DQS Delay Cal Pattern' + fields: + - access: RW + acronym: VP0 + description: [Victim pattern 0] + range: [31, 0] + reset: 2863270405 + sticky: '' + offset: 212 + offset_end: [215, null] + offset_start: [212, null] + power_well: Core + recurring: null + reg_base_name: DDQSCVDP0 + reg_name: DDQSCVDP0 + size: 32 + table_ref: 16-248 + title_desc: DQS Delay Calibration Victim Pattern 0 Register + view: PCI +DDQSCVDP1: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 1530109021 + description: 'DDQSCVDP1: DQS Delay Cal Pattern' + fields: + - access: RW + acronym: VP1 + description: [Victim pattern 1] + range: [31, 0] + reset: 1530109021 + sticky: '' + offset: 216 + offset_end: [219, null] + offset_start: [216, null] + power_well: Core + recurring: null + reg_base_name: DDQSCVDP1 + reg_name: DDQSCVDP1 + size: 32 + table_ref: 16-249 + title_desc: DQS Delay Calibration Victim Pattern 1 Register + view: PCI +DDRIOMC0: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 120 + description: null + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 13] + reset: 0 + sticky: N + - access: RW + acronym: DQVOXADJ + description: ['Bits to configure DQ buffer tco balancing '] + range: [12, 9] + reset: 0 + sticky: Y + - access: RW + acronym: DDRVOXCTL1 + description: ['Combine this bit with DDRVOXCTL0 (defined below) Encodings:', '00 + : DQ and CA buffers are in VOX Cross Reference Mode', '01: Bypass DQ and CA + VOX Cross Reference Mode (default)', '10: VOX Bypass Mode', '11: Reset VOX + Mode'] + range: [8, 8] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 7] + reset: 0 + sticky: N + - access: RW + acronym: Reserved + description: [Reserved] + range: [6, 4] + reset: 7 + sticky: N + - access: RW + acronym: DDRVOXCTL0 + description: ['This is the least significant bit of DDRVOXCTL. For encoding details, + see DDRVOXCTL1 above'] + range: [3, 3] + reset: 1 + sticky: Y + - access: RW + acronym: Reserved + description: [Reserved] + range: [2, 0] + reset: 0 + sticky: Y + offset: 608 + offset_end: [611, null] + offset_start: [608, null] + power_well: Core + recurring: null + reg_base_name: DDRIOMC0 + reg_name: DDRIOMC0 + size: 32 + table_ref: 16-287 + title_desc: DDRIO Mode Register Control Register + view: PCI +DDRIOMC1: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 1381105664 + description: 'DDRIOMC1: DDRIO Mode Control Register 1' + fields: + - access: RW + acronym: CASLEW + description: ['CASLEW: The digital slew override 8-bit control allow for balancing + of pull-up and pull-down slew rates T for CA/CLK buffers. The format of these + controls and recommended reset value is given below:', BitsFunction, DDR2Selection., + 7DDR2 = 0, 'Fast Corner falling 6:5slew rate trim', 'Slow Corner falling 4:2slew + rate trim', 'Fast corner rising 1:0slew rate trim'] + range: [31, 24] + reset: 82 + sticky: Y + - access: RW + acronym: DQSLEW + description: ['DQSLEW: The digital slew override 8-bit control allow for balancing + of pull-up and pull-down slew rates T for CA/CLK buffers. The format of these + controls and recommended reset value is given below:', BitsFunction, DDR2 + Selection., 7DDR2 = 0, 'Fast Corner falling 6:5slew rate trim', 'Slow Corner + falling 4:2slew rate trim', 'Fast corner rising 1:0slew rate trim'] + range: [23, 16] + reset: 82 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [15, 7] + reset: 0 + sticky: N + - access: RW + acronym: DEMPDQ + description: ['De-emphasis mode select bit for DQ/DQS pins. This mode can be used + to reduce power and enhance data eyes. When de-emphasis is enable for a given + group of I/Os, subsequent driver values that are the same have their strength + reduced by half ', 'It is recommended that this be controllable by the BIOS + in case there are unwanted side effects of this feature. ', EncodingDescription, + 00Disabled, 01Weakly Enabled, 10Full Enabled, OthersReserved] + range: [6, 5] + reset: 0 + sticky: Y + - access: RW + acronym: DEMPCA + description: ['De-emphasis mode select bit for command/clock pins. This mode can + be used to reduce power and enhance data eyes. When de-emphasis is enable + for a given group of I/Os, subsequent driver values that are the same have + their strength reduced by half.', 'It is recommended that this be controllable + by the BIOS in case there are unwanted side effects of this feature. For instance, + de-emphasis should be off before entering self-refresh mode of the DRAM to + prevent the CKE from exceeding the JEDEC threshold once self-refresh is entered.', + EncodingDescription, 00Disabled, 01Weakly Enabled, 10Full Enabled, OthersReserved] + range: [4, 3] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved + description: [Reserved] + range: [2, 2] + reset: 0 + sticky: Y + - access: RW + acronym: FASTSLEW + description: ['bit[0] controls the control bits', 'bit[1] controls the data bits'] + range: [1, 0] + reset: 0 + sticky: Y + offset: 612 + offset_end: [615, null] + offset_start: [612, null] + power_well: Core + recurring: null + reg_base_name: DDRIOMC1 + reg_name: DDRIOMC1 + size: 32 + table_ref: 16-288 + title_desc: DDRIO Mode Register Control Register 1 + view: PCI +DDRIOMC2: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 60710912 + description: 'DDRIOMC2: DDRIO Mode Control Register 2' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 28] + reset: 0 + sticky: N + - access: RW + acronym: PHSEL + description: ['Core phase to Command/Address relationship. '] + range: [27, 26] + reset: 0 + sticky: Y + - access: RW + acronym: LEGOVERRIDE + description: [Digital Impedance Control for RCOMP of DDR pads. See Legoverride + table above., 'Do not use the Default setting Please refer to Section 11.4.6, + "RCOMP" for more details.'] + range: [25, 16] + reset: 926 + sticky: Y + - access: RW + acronym: FIFOWPTRCLR + description: [This bit clears the DDRIO Receive FIFO read and write pointers. + The write pointer of this FIFO is generated by the DDRIO logic based on DQS + while the read pointer is generated by the memory controller., The DDRIO receive + FIPO read/write pointers need to be cleared after DCAL or Mbist operations + are completed and before issuing any functional DRAM R/W operations., 'Unlike + SDRC.DDRRFRS this register will reset only the read/write pointers of the + DDRIO receive FIFO. It will not reset the DLL''s. Please see Section 16.1.1.45, + "Offset 88h: SDRC - DDR SDRAM Secondary Control Register" for more details.'] + range: [15, 15] + reset: 0 + sticky: N + - access: RW + acronym: MASTCNTL + description: ['Coarse delay of DQS Master DLL '] + range: [14, 12] + reset: 6 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [11, 0] + reset: 0 + sticky: N + offset: 616 + offset_end: [619, null] + offset_start: [616, null] + power_well: Core + recurring: null + reg_base_name: DDRIOMC2 + reg_name: DDRIOMC2 + size: 32 + table_ref: 16-291 + title_desc: DDRIO Mode Control Register 2 + view: PCI +DIOMON: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'DIOMON: DDR I/O Monitor' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 25] + reset: 0 + sticky: N + - access: RW + acronym: DSAMP + description: ['Causes the analog to digital converter to sample the analog input + selected by biasssel '] + range: [24, 24] + reset: 0 + sticky: Y + - access: RO + acronym: VRESULT + description: ['A/D converter output of DDR I/O '] + range: [23, 16] + reset: 0 + sticky: Y + - access: RW + acronym: ENABLE + description: ['Enable A/D converter for the DDR IO Bias logic. Also enables updates + to the following fields of this CSR: VRESULT, DQLEGSELOUT, DIOPWR, CALEGSELOUT'] + range: [15, 15] + reset: 0 + sticky: N + - access: RW + acronym: BIASSEL + description: ['A/D converter input selection '] + range: [14, 11] + reset: 0 + sticky: Y + - access: RO + acronym: DQLEGSELOUT + description: ['DQ legsel output of DDR I/O. Sets the driver strength for DQ IO + buffers. '] + range: [10, 7] + reset: 0 + sticky: Y + - access: RO + acronym: DIOPWR + description: [Nopwr = 0 if Vccddr is off OR in burnin mode., 'During normal operation + it''s set to 1. '] + range: [6, 6] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [5, 4] + reset: 0 + sticky: N + - access: RO + acronym: CALEGSELOUT + description: ['cmd/addr legsel output of DDR I/O Sets the driver strength for + cmd/addr IO buffers. '] + range: [3, 0] + reset: 0 + sticky: Y + offset: 240 + offset_end: [243, null] + offset_start: [240, null] + power_well: Core + recurring: null + reg_base_name: DIOMON + reg_name: DIOMON + size: 32 + table_ref: 16-252 + title_desc: DDR I/O Monitor Register + view: PCI +DQSFAIL0: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'DQSFAIL0: DQS Failure Configuration Register' + fields: + - access: RW + acronym: Reserved_R1DQS15 + description: [Reserved] + range: [31, 31] + reset: 0 + sticky: Y + - access: RW + acronym: R1DQS06 + description: ['Rank 1 DQS06 '] + range: [30, 30] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R1DQS14 + description: [Reserved] + range: [29, 29] + reset: 0 + sticky: Y + - access: RW + acronym: R1DQS05 + description: ['Rank 1 DQS05 '] + range: [28, 28] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R1DQS13 + description: [Reserved] + range: [27, 27] + reset: 0 + sticky: Y + - access: RW + acronym: R1DQS04 + description: ['Rank 1 DQS04 '] + range: [26, 26] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R1DQS12 + description: [Reserved] + range: [25, 25] + reset: 0 + sticky: Y + - access: RW + acronym: R1DQS03 + description: ['Rank 1 DQS03 '] + range: [24, 24] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R1DQS11 + description: [Reserved] + range: [23, 23] + reset: 0 + sticky: Y + - access: RW + acronym: R1DQS02 + description: ['Rank 1 DQS02 '] + range: [22, 22] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R1DQS10 + description: [Reserved] + range: [21, 21] + reset: 0 + sticky: Y + - access: RW + acronym: R1DQS01 + description: ['Rank 1 DQS01 '] + range: [20, 20] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R1DQS09 + description: [Reserved] + range: [19, 19] + reset: 0 + sticky: Y + - access: RW + acronym: R1DQS00 + description: ['Rank 1 DQS00 '] + range: [18, 18] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R0DQS17 + description: [Reserved] + range: [17, 17] + reset: 0 + sticky: Y + - access: RW + acronym: R0DQS08 + description: ['Rank 0 DQS08 '] + range: [16, 16] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R0DQS16 + description: [Reserved] + range: [15, 15] + reset: 0 + sticky: Y + - access: RW + acronym: R0DQS07 + description: ['Rank 0 DQS07 '] + range: [14, 14] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R0DQS15 + description: [Reserved] + range: [13, 13] + reset: 0 + sticky: Y + - access: RW + acronym: R0DQS06 + description: ['Rank 0 DQS06 '] + range: [12, 12] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R0DQS14 + description: [Reserved] + range: [11, 11] + reset: 0 + sticky: Y + - access: RW + acronym: R0DQS05 + description: ['Rank 0 DQS05 '] + range: [10, 10] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R0DQS13 + description: [Reserved] + range: [9, 9] + reset: 0 + sticky: Y + - access: RW + acronym: R0DQS04 + description: ['Rank 0 DQS04 '] + range: [8, 8] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R0DQS12 + description: [Reserved] + range: [7, 7] + reset: 0 + sticky: Y + - access: RW + acronym: R0DQS03 + description: ['Rank 0 DQS03 '] + range: [6, 6] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R0DQS11 + description: [Reserved] + range: [5, 5] + reset: 0 + sticky: Y + - access: RW + acronym: R0DQS02 + description: ['Rank 0 DQS02 '] + range: [4, 4] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R0DQS10 + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: Y + - access: RW + acronym: R0DQS01 + description: ['Rank 0 DQS01 '] + range: [2, 2] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R0DQS09 + description: [Reserved] + range: [1, 1] + reset: 0 + sticky: Y + - access: RW + acronym: R0DQS00 + description: ['Rank 0 DQS00 '] + range: [0, 0] + reset: 0 + sticky: Y + offset: 160 + offset_end: [163, null] + offset_start: [160, null] + power_well: Core + recurring: null + reg_base_name: DQSFAIL0 + reg_name: DQSFAIL0 + size: 32 + table_ref: 16-236 + title_desc: DQS Failure Configuration Register 0 + view: PCI +DQSFAIL1: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'DQSFAIL1: DQS Failure Configuration Register' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 4] + reset: 0 + sticky: N + - access: RW + acronym: Reserved_R1DQS17 + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: Y + - access: RW + acronym: R1DQS08 + description: ['Rank 1 DQS08 '] + range: [2, 2] + reset: 0 + sticky: Y + - access: RW + acronym: Reserved_R1DQS16 + description: [Reserved] + range: [1, 1] + reset: 0 + sticky: Y + - access: RW + acronym: R1DQS07 + description: ['Rank 1 DQS07 '] + range: [0, 0] + reset: 0 + sticky: Y + offset: 156 + offset_end: [156, null] + offset_start: [156, null] + power_well: Core + recurring: null + reg_base_name: DQSFAIL1 + reg_name: DQSFAIL1 + size: 8 + table_ref: 16-235 + title_desc: DQS Failure Configuration Register 1 + view: PCI +DQSOFCS00: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'DQSOFCS00: DQS Calibration Register' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 28] + reset: 0 + sticky: N + - access: RW + acronym: DQS03 + description: ['Rank 0 DQS03: Fine delay '] + range: [27, 24] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [23, 20] + reset: 0 + sticky: N + - access: RW + acronym: DQS02 + description: ['Rank 0 DQS02: Fine delay '] + range: [19, 16] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [15, 12] + reset: 0 + sticky: N + - access: RW + acronym: DQS01 + description: ['Rank 0 DQS01: Fine delay '] + range: [11, 8] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 4] + reset: 0 + sticky: N + - access: RW + acronym: DQS00 + description: ['Rank 0 DQS00: Fine delay '] + range: [3, 0] + reset: 0 + sticky: Y + offset: 180 + offset_end: [183, null] + offset_start: [180, null] + power_well: Core + recurring: null + reg_base_name: DQSOFCS00 + reg_name: DQSOFCS00 + size: 32 + table_ref: 16-240 + title_desc: DQS Calibration Register + view: PCI +DQSOFCS01: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'DQSOFCS01: DQS Calibration Register' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 28] + reset: 0 + sticky: N + - access: RW + acronym: DQS07 + description: ['Rank 0 DQS07: Fine delay '] + range: [27, 24] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [23, 20] + reset: 0 + sticky: N + - access: RW + acronym: DQS06 + description: ['Rank 0 DQS06: Fine delay '] + range: [19, 16] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [15, 12] + reset: 0 + sticky: N + - access: RW + acronym: DQS05 + description: ['Rank 0 DQS05: Fine delay '] + range: [11, 8] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 4] + reset: 0 + sticky: N + - access: RW + acronym: DQS04 + description: ['Rank 0 DQS04: Fine delay '] + range: [3, 0] + reset: 0 + sticky: Y + offset: 184 + offset_end: [187, null] + offset_start: [184, null] + power_well: Core + recurring: null + reg_base_name: DQSOFCS01 + reg_name: DQSOFCS01 + size: 32 + table_ref: 16-241 + title_desc: DQS Calibration Register + view: PCI +DQSOFCS02: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'DQSOFCS02: DQS Calibration Register' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 4] + reset: 0 + sticky: N + - access: RW + acronym: DQS08 + description: ['Rank 0 DQS08: Fine delay '] + range: [3, 0] + reset: 0 + sticky: Y + offset: 198 + offset_end: [198, null] + offset_start: [198, null] + power_well: Core + recurring: null + reg_base_name: DQSOFCS02 + reg_name: DQSOFCS02 + size: 8 + table_ref: 16-242 + title_desc: DQS Calibration Register + view: PCI +DQSOFCS10: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'DQSOFCS10: DQS Calibration Register' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 28] + reset: 0 + sticky: N + - access: RW + acronym: DQS03 + description: ['Rank 1 DQS03: Fine delay '] + range: [27, 24] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [23, 20] + reset: 0 + sticky: N + - access: RW + acronym: DQS02 + description: ['Rank 1 DQS02: Fine delay '] + range: [19, 16] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [15, 12] + reset: 0 + sticky: N + - access: RW + acronym: DQS01 + description: ['Rank 1 DQS01: Fine delay '] + range: [11, 8] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 4] + reset: 0 + sticky: N + - access: RW + acronym: DQS00 + description: ['Rank 1 DQS00: Fine delay '] + range: [3, 0] + reset: 0 + sticky: Y + offset: 188 + offset_end: [191, null] + offset_start: [188, null] + power_well: Core + recurring: null + reg_base_name: DQSOFCS10 + reg_name: DQSOFCS10 + size: 32 + table_ref: 16-243 + title_desc: DQS Calibration Register + view: PCI +DQSOFCS11: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'DQSOFCS11: DQS Calibration Register' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 28] + reset: 0 + sticky: N + - access: RW + acronym: DQS07 + description: ['Rank 1 DQS07: Fine delay '] + range: [27, 24] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [23, 20] + reset: 0 + sticky: N + - access: RW + acronym: DQS06 + description: ['Rank 1 DQS06: Fine delay '] + range: [19, 16] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [15, 12] + reset: 0 + sticky: N + - access: RW + acronym: DQS05 + description: ['Rank 1 DQS05: Fine delay '] + range: [11, 8] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 4] + reset: 0 + sticky: N + - access: RW + acronym: DQS04 + description: ['Rank 1 DQS04: Fine delay '] + range: [3, 0] + reset: 0 + sticky: Y + offset: 192 + offset_end: [195, null] + offset_start: [192, null] + power_well: Core + recurring: null + reg_base_name: DQSOFCS11 + reg_name: DQSOFCS11 + size: 32 + table_ref: 16-244 + title_desc: DQS Calibration Register + view: PCI +DQSOFCS12: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'DQSOFCS12: DQS Calibration Register' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 4] + reset: 0 + sticky: N + - access: RW + acronym: DQS08 + description: ['Rank 1 DQS08: Fine delay '] + range: [3, 0] + reset: 0 + sticky: Y + offset: 199 + offset_end: [199, null] + offset_start: [199, null] + power_well: Core + recurring: null + reg_base_name: DQSOFCS12 + reg_name: DQSOFCS12 + size: 8 + table_ref: 16-245 + title_desc: DQS Calibration Register + view: PCI +DRAMDLLC: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 898752 + description: 'DRAMDLLC: DDR I/O DLL Control' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [23, 22] + reset: 0 + sticky: N + - access: RW + acronym: SLVBYP + description: ['DQS delay bypass '] + range: [21, 21] + reset: 0 + sticky: Y + - access: RW + acronym: SLVLEN4 + description: ['dqs 8 coarse DQS delay '] + range: [20, 18] + reset: 3 + sticky: Y + - access: RW + acronym: SLVLEN3 + description: ['dqs 7 & 6 coarse DQS delay '] + range: [17, 15] + reset: 3 + sticky: Y + - access: RW + acronym: SLVLEN2 + description: ['dqs 5 & 4 coarse DQS delay '] + range: [14, 12] + reset: 3 + sticky: Y + - access: RW + acronym: SLVLEN1 + description: ['dqs 3 & 2 coarse DQS delay '] + range: [11, 9] + reset: 3 + sticky: Y + - access: RW + acronym: SLVLEN0 + description: ['dqs1 & 0 coarse DQS delay '] + range: [8, 6] + reset: 3 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [5, 0] + reset: 0 + sticky: N + offset: 200 + offset_end: [202, null] + offset_start: [200, null] + power_well: Core + recurring: null + reg_base_name: DRAMDLLC + reg_name: DRAMDLLC + size: 24 + table_ref: 16-254 + title_desc: DDR I/O DLL Control Register + view: PCI +DRAMISCTL: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 4113 + description: 'DRAMISCTL: Miscellaneous DRAM DDR Cluster Control Register' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 13] + reset: 0 + sticky: N + - access: RW + acronym: Reserved + description: [Reserved] + range: [12, 12] + reset: 1 + sticky: Y + - access: RW + acronym: Reserved + description: [Reserved] + range: [11, 11] + reset: 0 + sticky: N + - access: RW + acronym: Reserved_RW + description: [Reserved for future use. These bits are RW but SW should not change + the default reset value of these bits.] + range: [10, 8] + reset: 0 + sticky: N + - access: RW + acronym: VREFSEL + description: ['Vref selection: Adjustable VREF voltage at receivers. The threshold + voltage at receiver can be raised or lowered to allow the noise margin on + the data from memory be skewed.', Vref is estimated with the following equation, + Vref = (SQU * VCCDDR + (SQD - SQU) * 0.45) / (SQU + SQD) + VOFF, 'where,', SQU + = SQRT(4*VREFSEL<7> + 2*VREFSEL<6> + VREFSEL<5> + 8*VREFSEL<4>), SQD = SQRT(4*VREFSEL<3> + + 2*VREFSEL<2> + VREFSEL<1> + 8*VREFSEL<0>), 'VOFF = offset, varying for each + chip, nominal value is 0 but can be up to +/- 0.1V', Examples with VCCDDR=1.8V + and VOFF=0, '.VREFSEL. Vref (V) ', 00010001 0.9, 00010011 0.887, 00010101 + 0.875, 00011001 0.855, 11101001 0.840, 11001001 0.823, 10001001 0.779, 00110001 + 0.913, 01010001 0.925, 10010001 0.945, 10011110 0.960, 10011100 0.977, 10011000 + 1.021] + range: [7, 0] + reset: 17 + sticky: Y + offset: 248 + offset_end: [251, null] + offset_start: [248, null] + power_well: Core + recurring: null + reg_base_name: DRAMISCTL + reg_name: DRAMISCTL + size: 32 + table_ref: 16-253 + title_desc: Miscellaneous DRAM DDR Cluster Control Register + view: PCI +DRRTC00: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 101058054 + description: 'DRRTC00: Receive Enable Reference Output Timing Control Register' + fields: + - access: RW + acronym: RCVEN03 + description: ['Receiver enable delay for DQS3 '] + range: [31, 24] + reset: 6 + sticky: Y + - access: RW + acronym: RCVEN02 + description: ['Receiver enable delay for DQS2 '] + range: [23, 16] + reset: 6 + sticky: Y + - access: RW + acronym: RCVEN01 + description: ['Receiver enable delay for DQS1 '] + range: [15, 8] + reset: 6 + sticky: Y + - access: RW + acronym: RCVEN00 + description: ['Receiver enable delay for DQS0 '] + range: [7, 0] + reset: 6 + sticky: Y + offset: 164 + offset_end: [167, null] + offset_start: [164, null] + power_well: Core + recurring: null + reg_base_name: DRRTC00 + reg_name: DRRTC00 + size: 32 + table_ref: 16-237 + title_desc: Receive Enable Reference Output Timing Control Register + view: PCI +DRRTC01: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 101058054 + description: 'DRRTC01: Receive Enable Reference Output Timing Control Register' + fields: + - access: RW + acronym: RCVEN07 + description: ['Receiver enable delay for DQS7 '] + range: [31, 24] + reset: 6 + sticky: Y + - access: RW + acronym: RCVEN06 + description: ['Receiver enable delay for DQS6 '] + range: [23, 16] + reset: 6 + sticky: Y + - access: RW + acronym: RCVEN05 + description: ['Receiver enable delay for DQS5 '] + range: [15, 8] + reset: 6 + sticky: Y + - access: RW + acronym: RCVEN04 + description: ['Receiver enable delay for DQS4 '] + range: [7, 0] + reset: 6 + sticky: Y + offset: 168 + offset_end: [171, null] + offset_start: [168, null] + power_well: Core + recurring: null + reg_base_name: DRRTC01 + reg_name: DRRTC01 + size: 32 + table_ref: 16-238 + title_desc: Receive Enable Reference Output Timing Control Register + view: PCI +DRRTC02: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 6 + description: 'DRRTC02: Receive Enable Reference Output Timing Control Register' + fields: + - access: RW + acronym: RCVEN08 + description: ['Receiver enable delay for DQS8 '] + range: [7, 0] + reset: 6 + sticky: Y + offset: 196 + offset_end: [196, null] + offset_start: [196, null] + power_well: Core + recurring: null + reg_base_name: DRRTC02 + reg_name: DRRTC02 + size: 8 + table_ref: 16-239 + title_desc: Receive Enable Reference Output Timing Control Register + view: PCI +DSRETC: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 1544819712 + description: 'DSRETC: DRAM Self-Refresh (SR) Extended Timing and Control Register' + fields: + - access: RW + acronym: TXSNR + description: ['Exit self-refresh to non-read command timing. Number of Controller + cycles for which accesses to the DIMMs need to be blocked by memory controller. '] + range: [31, 24] + reset: 92 + sticky: Y + - access: RW + acronym: DRSRENT + description: ['Dual rank self-refresh (SR) entry and exit timing - stagger of + self refresh commands between ranks. ', Staggering of the SR commands result + is in the power intensive refresh operations to be staggered between the 2 + ranks.] + range: [23, 16] + reset: 20 + sticky: Y + - access: RW + acronym: DRARTIM + description: ['Dual rank auto-refresh timing - stagger of commands between ranks + prior to self-refresh entry. '] + range: [15, 8] + reset: 20 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 1] + reset: 0 + sticky: N + - access: RW + acronym: ENSREXIT + description: [Enable Self-refresh (SR) exit state machine., 'This bit needs to + be set by BIOS upon power-up from an S3 event. '] + range: [0, 0] + reset: 0 + sticky: N + offset: 152 + offset_end: [155, null] + offset_start: [152, null] + power_well: Core + recurring: null + reg_base_name: DSRETC + reg_name: DSRETC + size: 32 + table_ref: 16-234 + title_desc: DRAM Self-Refresh (SR) Extended Timing and Control Register + view: PCI +FIVESREG: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 1431655765 + description: 'FIVESREG: Fixed 5s Pattern' + fields: + - access: RO + acronym: FIVES + description: ['Hardwired to 5s for read-return '] + range: [31, 0] + reset: 1431655765 + sticky: N + offset: 232 + offset_end: [235, null] + offset_start: [232, null] + power_well: Core + recurring: null + reg_base_name: FIVESREG + reg_name: FIVESREG + size: 32 + table_ref: 16-255 + title_desc: Fixed 5s Pattern Register + view: PCI +MBADDR: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'MBADDR: Memory Test Address' + fields: + - access: RW + acronym: ROW + description: ['Row Address 15:0 '] + range: [31, 16] + reset: 0 + sticky: Y + - access: RW + acronym: SPARE + description: ['Reserved. Must write as ''0'' '] + range: [15, 15] + reset: 0 + sticky: Y + - access: RW + acronym: COL + description: ['Column Address BL8[14:3] <==> DRAM Column Address 15:11,9:3BL4[14:3] + <==> DRAM Column Address 14:11,9:2'] + range: [14, 3] + reset: 0 + sticky: Y + - access: RW + acronym: BA + description: ['Bank Address 2:0 '] + range: [2, 0] + reset: 0 + sticky: Y + offset: 324 + offset_end: [327, null] + offset_start: [324, null] + power_well: Core + recurring: null + reg_base_name: MBADDR + reg_name: MBADDR + size: 32 + table_ref: 16-258 + title_desc: Memory Test Address Register + view: PCI +MBCSR: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'MBCSR: Top level control register for DDR MemBIST.' + fields: + - access: RWS + acronym: START + description: ['Start operation:', 1 => Set this bit to begin MemBIST execution., + 0 => Hardware will clear this bit when MemBIST execution is completed.] + range: [31, 31] + reset: 0 + sticky: N + - access: RW + acronym: PF + description: ['Fail/Pass indicator:', Write to 0 when start MemBIST. Hardware + will set to 1 when a failure is detected., 0 => Pass, 1 => Fail] + range: [30, 30] + reset: 0 + sticky: N + - access: RW + acronym: HALT + description: ['Halt on Error:', 0 => Operation will not halt due to a detected + error., 1 => Operation will halt after read-compare data error is detected., + MemBIST will complete the current transaction before halting. This may result + in multiple errors being logged.] + range: [29, 29] + reset: 0 + sticky: N + - access: RW + acronym: ABORT + description: ['MemBIST test abort. When test abort bit is set, MBCSR bit 31 (Start + operation, RWS) needs to be set to "0" at the same time to avoid restarting + MemBIST. ', 0 => Normal operation., 1 => Need to abort the test during MemBIST + operation., 'If there is any following Membist test after the abort test, + bit [28] needs to be cleared. ', 'The Write to set MBCSR.abort must occur + at least tRFC after the Write to set MBCSR.start. Otherwise subsequent MemBIST + operations may fail. '] + range: [28, 28] + reset: 0 + sticky: N + - access: RO + acronym: SPARE + description: [Reserved] + range: [27, 27] + reset: 0 + sticky: N + - access: RW + acronym: ALGO + description: ['000b: only support setting'] + range: [26, 24] + reset: 0 + sticky: N + - access: RO + acronym: Reserved + description: [Reserved] + range: [23, 22] + reset: 0 + sticky: N + - access: RW + acronym: CS + description: ['Chip Select[1:0] selection in MemBIST mode', '01: select Rank 0', + '10: select Rank 1', '00: Reserved', '11: Reserved'] + range: [21, 20] + reset: 0 + sticky: N + - access: RW + acronym: INV + description: ['0b: only supported setting'] + range: [19, 19] + reset: 0 + sticky: N + - access: RW + acronym: FX + description: ['FIXED: Fixed data pattern selection for MemBIST operation', 000 + => 0, 001 => F, 010 => A, 011 => 5, 100 => C, 101 => 3, 110 => 9, 111 => 6] + range: [18, 16] + reset: 0 + sticky: N + - access: RW + acronym: EN288 + description: ['0b: only supported setting'] + range: [15, 15] + reset: 0 + sticky: N + - access: RW + acronym: MBDATA + description: ['MBDATA: Selects use of MBDATA for error log field for LFSR, Circular + Shift and user defined data modes. This field has no effect on fixed data + patterns.', 0 => use MBDATA0/1/2/3/8 for failure data bit location accumulator., + '1 => use MBDATA0/1/2/3/8 to log 5 failure addresses. '] + range: [14, 14] + reset: 0 + sticky: N + - access: RW + acronym: ABAR + description: ['0: only supported setting'] + range: [13, 13] + reset: 0 + sticky: N + - access: RW + acronym: ADIR + description: ['ADIR: Address decode direction ', 0 => Address increments, 1 => + Address decrements] + range: [12, 12] + reset: 0 + sticky: N + - access: RW + acronym: FAST + description: [FAST Address sequencing, '00: only supported setting'] + range: [11, 10] + reset: 0 + sticky: N + - access: RW + acronym: DTYPE + description: ['Data type selection:', '00 => Fixed data pattern, selected by MBCSR + bits 18:16', 01 => 144 bits user defined data, '10 => Circular shift data + based on Seed in MBLFSRSED ', '11 => LFSR data, seeded from 32 bit LFSR seed + register.', 'Note: Circular shift data and LFSR data type should not be used + for single address operation (ATYPE = 01).', 'Note: Circular shift data and + LFSR data type only for 72-bit mode'] + range: [9, 8] + reset: 0 + sticky: N + - access: RW + acronym: ATYPE + description: ['Address type:', 00 => Reserved, '01 => Single physical address + operation, contained in MBADDR row/column/bank.', '10 => start/end physical + address range defined in MB_START_ADDR & MB_END_ADDR registers. ', '11 => + full address range of the DIMM as defined in DRA/DRB registers which specifies + the number of banks, rows, and columns. ', '?'] + range: [7, 6] + reset: 0 + sticky: N + - access: RW + acronym: CMD + description: ['Command execution:', 00 => Read only without data comparison, '01 + => Write only ', 10 => Read with data comparison, 11 => Write followed by + Read with data comparison] + range: [5, 4] + reset: 0 + sticky: N + - access: RO + acronym: Reserved + description: [Reserved] + range: [3, 0] + reset: 0 + sticky: N + offset: 320 + offset_end: [323, null] + offset_start: [320, null] + power_well: Core + recurring: null + reg_base_name: MBCSR + reg_name: MBCSR + size: 32 + table_ref: 16-257 + title_desc: MemBIST Control Register + view: PCI +MBDATA[0:9]: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'MBADDR[0:9]: Memory Test Data' + fields: + - access: RW + acronym: MBDATA + description: ['Usage varies by mode, refer to table below for details '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 328 + offset_end: [332, 4] + offset_start: [328, 4] + power_well: Core + recurring: 10 + reg_base_name: MBDATA + reg_name: MBDATA[0:9] + size: 32 + table_ref: 16-259 + title_desc: Memory Test Data Register + view: PCI +MBFADDRPTR: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'MBFADDRPTR: Memory Test Failure Address Pointer Register' + fields: + - access: RW + acronym: MBFADDRPTR + description: ['This 32 bit register designates which MemBIST failures to log in + the available failure address locations. ', 'The default value of this register + is zero. It means MemBIST always logs beginning with the first failure. If + it is programmed to hex A (10 in decimal), MemBIST will log failures starting + from the11th failure. ', 'The corresponding MB_ERR_DATA0/1/2/3 registers will + log corrupted data in the first through fourth designated failure addresses. ', + 'Note: this register does not affect the MBDATA failure bit location accumulators. '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 424 + offset_end: [427, null] + offset_start: [424, null] + power_well: Core + recurring: null + reg_base_name: MBFADDRPTR + reg_name: MBFADDRPTR + size: 32 + table_ref: 16-266 + title_desc: Memory Test Failure Address Pointer Register + view: PCI +MBLFSRSED: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'MBLFSRSED: Memory Test Circular Shift and LFSR Seed' + fields: + - access: RW + acronym: MBLFSRSED + description: ['MemBIST LFSR Seed ', This 32 bit register will be used as the initial + data seed for LFSR or Circular shift data pattern.] + range: [31, 0] + reset: 0 + sticky: Y + offset: 420 + offset_end: [423, null] + offset_start: [420, null] + power_well: Core + recurring: null + reg_base_name: MBLFSRSED + reg_name: MBLFSRSED + size: 32 + table_ref: 16-265 + title_desc: Memory Test Circular Shift and LFSR Seed Register + view: PCI +MB_END_ADDR: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'MB_END_ADDR: Memory Test End Address' + fields: + - access: RW + acronym: ROW + description: ['MemBIST End Row Address 15:0 '] + range: [31, 16] + reset: 0 + sticky: Y + - access: RO + acronym: RESERVED + description: [Reserved] + range: [15, 15] + reset: 0 + sticky: N + - access: RW + acronym: COL + description: ['MemBIST End Column Address ', 'BL8[14:3] <==> DRAM Column Address + 15:11,9:3', 'BL4[14:3] <==> DRAM Column Address 14:11,9:2'] + range: [14, 3] + reset: 0 + sticky: Y + - access: RW + acronym: BA + description: ['MemBIST End Bank Address 2:0 '] + range: [2, 0] + reset: 0 + sticky: Y + offset: 416 + offset_end: [419, null] + offset_start: [416, null] + power_well: Core + recurring: null + reg_base_name: MB_END_ADDR + reg_name: MB_END_ADDR + size: 32 + table_ref: 16-264 + title_desc: Memory Test End Address Register + view: PCI +MB_ERR_DATA00: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA00 + fields: + - access: RW + acronym: DATA + description: ['Early failure data [31:0] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 432 + offset_end: [435, null] + offset_start: [432, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA00 + reg_name: MB_ERR_DATA00 + size: 32 + table_ref: 16-267 + title_desc: Memory Test Error Data 0 + view: PCI +MB_ERR_DATA01: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA01 + fields: + - access: RW + acronym: DATA + description: ['Early failure data [63:32] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 436 + offset_end: [439, null] + offset_start: [436, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA01 + reg_name: MB_ERR_DATA01 + size: 32 + table_ref: 16-268 + title_desc: Memory Test Error Data 0 + view: PCI +MB_ERR_DATA02: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA02 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [31:0] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 440 + offset_end: [443, null] + offset_start: [440, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA02 + reg_name: MB_ERR_DATA02 + size: 32 + table_ref: 16-269 + title_desc: Memory Test Error Data 0 + view: PCI +MB_ERR_DATA03: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA03 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [63:32] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 444 + offset_end: [447, null] + offset_start: [444, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA03 + reg_name: MB_ERR_DATA03 + size: 32 + table_ref: 16-270 + title_desc: Memory Test Error Data 0 + view: PCI +MB_ERR_DATA04: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA04 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [71:64] & Early failure data [71:64] '] + range: [15, 0] + reset: 0 + sticky: Y + offset: 448 + offset_end: [449, null] + offset_start: [448, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA04 + reg_name: MB_ERR_DATA04 + size: 16 + table_ref: 16-271 + title_desc: Memory Test Error Data 0 + view: PCI +MB_ERR_DATA10: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA10 + fields: + - access: RW + acronym: DATA + description: ['Early failure data [31:0] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 452 + offset_end: [455, null] + offset_start: [452, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA10 + reg_name: MB_ERR_DATA10 + size: 32 + table_ref: 16-272 + title_desc: Memory Test Error Data 1 + view: PCI +MB_ERR_DATA11: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA11 + fields: + - access: RW + acronym: DATA + description: ['Early failure data [63:32] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 456 + offset_end: [459, null] + offset_start: [456, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA11 + reg_name: MB_ERR_DATA11 + size: 32 + table_ref: 16-273 + title_desc: Memory Test Error Data 1 + view: PCI +MB_ERR_DATA12: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA12 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [31:0] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 460 + offset_end: [463, null] + offset_start: [460, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA12 + reg_name: MB_ERR_DATA12 + size: 32 + table_ref: 16-274 + title_desc: Memory Test Error Data 1 + view: PCI +MB_ERR_DATA13: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA13 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [63:32] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 464 + offset_end: [467, null] + offset_start: [464, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA13 + reg_name: MB_ERR_DATA13 + size: 32 + table_ref: 16-275 + title_desc: Memory Test Error Data 1 + view: PCI +MB_ERR_DATA14: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA14 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [71:64] & Early failure data [71:64] '] + range: [15, 0] + reset: 0 + sticky: Y + offset: 468 + offset_end: [469, null] + offset_start: [468, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA14 + reg_name: MB_ERR_DATA14 + size: 16 + table_ref: 16-276 + title_desc: Memory Test Error Data 1 + view: PCI +MB_ERR_DATA20: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA20 + fields: + - access: RW + acronym: DATA + description: ['Early failure data [31:0] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 472 + offset_end: [475, null] + offset_start: [472, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA20 + reg_name: MB_ERR_DATA20 + size: 32 + table_ref: 16-277 + title_desc: Memory Test Error Data 2 + view: PCI +MB_ERR_DATA21: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA21 + fields: + - access: RW + acronym: DATA + description: ['Early failure data [63:32] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 476 + offset_end: [479, null] + offset_start: [476, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA21 + reg_name: MB_ERR_DATA21 + size: 32 + table_ref: 16-278 + title_desc: Memory Test Error Data 2 + view: PCI +MB_ERR_DATA22: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA22 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [31:0] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 480 + offset_end: [483, null] + offset_start: [480, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA22 + reg_name: MB_ERR_DATA22 + size: 32 + table_ref: 16-279 + title_desc: Memory Test Error Data 2 + view: PCI +MB_ERR_DATA23: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA23 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [63:32] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 484 + offset_end: [487, null] + offset_start: [484, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA23 + reg_name: MB_ERR_DATA23 + size: 32 + table_ref: 16-280 + title_desc: Memory Test Error Data 2 + view: PCI +MB_ERR_DATA24: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA24 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [71:64] & Early failure data [71:64] '] + range: [15, 0] + reset: 0 + sticky: Y + offset: 488 + offset_end: [489, null] + offset_start: [488, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA24 + reg_name: MB_ERR_DATA24 + size: 16 + table_ref: 16-281 + title_desc: Memory Test Error Data 2 + view: PCI +MB_ERR_DATA30: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA30 + fields: + - access: RW + acronym: DATA + description: ['Early failure data [31:0] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 492 + offset_end: [495, null] + offset_start: [492, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA30 + reg_name: MB_ERR_DATA30 + size: 32 + table_ref: 16-282 + title_desc: Memory Test Error Data 3 + view: PCI +MB_ERR_DATA31: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA31 + fields: + - access: RW + acronym: DATA + description: ['Early failure data [63:32] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 496 + offset_end: [500, null] + offset_start: [496, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA31 + reg_name: MB_ERR_DATA31 + size: 32 + table_ref: 16-283 + title_desc: Memory Test Error Data 3 + view: PCI +MB_ERR_DATA32: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA32 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [31:0] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 500 + offset_end: [503, null] + offset_start: [500, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA32 + reg_name: MB_ERR_DATA32 + size: 32 + table_ref: 16-284 + title_desc: Memory Test Error Data 3 + view: PCI +MB_ERR_DATA33: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA33 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [63:32] '] + range: [31, 0] + reset: 0 + sticky: Y + offset: 504 + offset_end: [507, null] + offset_start: [504, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA33 + reg_name: MB_ERR_DATA33 + size: 32 + table_ref: 16-285 + title_desc: Memory Test Error Data 3 + view: PCI +MB_ERR_DATA34: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: MB_ERR_DATA34 + fields: + - access: RW + acronym: DATA + description: ['Late failure data [71:64] & Early failure data [71:64] '] + range: [15, 0] + reset: 0 + sticky: Y + offset: 508 + offset_end: [509, null] + offset_start: [508, null] + power_well: Core + recurring: null + reg_base_name: MB_ERR_DATA34 + reg_name: MB_ERR_DATA34 + size: 16 + table_ref: 16-286 + title_desc: Memory Test Error Data 3 + view: PCI +MB_START_ADDR: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'MB_START_ADDR: Memory Test Start Address' + fields: + - access: RW + acronym: ROW + description: ['MemBIST Start Row Address 15:0 '] + range: [31, 16] + reset: 0 + sticky: Y + - access: RO + acronym: RESERVED + description: [Reserved] + range: [15, 15] + reset: 0 + sticky: '' + - access: RW + acronym: COL + description: ['MemBIST Start Column Address ', 'BL8[14:3] <==> DRAM Column Address + 15:11,9:3', 'BL4[14:3] <==> DRAM Column Address 14:11,9:2'] + range: [14, 3] + reset: 0 + sticky: Y + - access: RW + acronym: BA + description: ['MemBIST Start Bank Address 2:0 '] + range: [2, 0] + reset: 0 + sticky: Y + offset: 412 + offset_end: [415, null] + offset_start: [412, null] + power_well: Core + recurring: null + reg_base_name: MB_START_ADDR + reg_name: MB_START_ADDR + size: 32 + table_ref: 16-263 + title_desc: Memory Test Start Address Register + view: PCI +NOTEPAD: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: null + fields: + - access: RW + acronym: BNSR + description: ['BIOS Register: This register is used by BIOS.'] + range: [15, 0] + reset: 0 + sticky: N + offset: 2 + offset_end: [3, null] + offset_start: [2, null] + power_well: Core + recurring: null + reg_base_name: NOTEPAD + reg_name: NOTEPAD + size: 16 + table_ref: 16-222 + title_desc: Note Pad for BIOS Support Register + view: PCI +NOTESPAD: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: null + fields: + - access: RW + acronym: BSR + description: ['BIOS Sticky Register [STICKY]: This register is used by BIOS. It + is sticky through reset.'] + range: [15, 0] + reset: 0 + sticky: Y + offset: 0 + offset_end: [1, null] + offset_start: [0, null] + power_well: Core + recurring: null + reg_base_name: NOTESPAD + reg_name: NOTESPAD + size: 16 + table_ref: 16-221 + title_desc: Note (Sticky) Pad for BIOS Support Register + view: PCI +RCVENAC: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 1574928 + description: 'RCVENAC: Receiver Enable Algorithm Control' + fields: + - access: RW + acronym: PWIDTH + description: ['Minimum preamble width limit, used to detect if a low pulse in + a DQS waveform is wide enough to be a valid preamble. The default corresponds + to 3/4 of a DRAM clock cycle '] + range: [23, 16] + reset: 24 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [15, 14] + reset: 0 + sticky: '' + - access: RW + acronym: HWIDTH + description: ['Minimum high pulse width limit, used to detect if a high pulse + in a DQS waveform is wide enough to indicate a strobe is toggling in a valid + manner. The default corresponds to 1/4 of a DRAM clock cycle. '] + range: [13, 8] + reset: 8 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 6] + reset: 0 + sticky: '' + - access: RW + acronym: POFFSET + description: ['Preamble center offset from first rising edge, used to position + the DQS receiver enable relative to the preamble edge location recorded in + the DCALDATA registers. The default value corresponds to 1/2 of a DRAM clock + cycle. '] + range: [5, 0] + reset: 16 + sticky: Y + offset: 148 + offset_end: [150, null] + offset_start: [148, null] + power_well: Core + recurring: null + reg_base_name: RCVENAC + reg_name: RCVENAC + size: 24 + table_ref: 16-233 + title_desc: Receiver Enable Algorithm Control Register + view: PCI +WDLL_MISC: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: WDLL_MISC- DLL Miscellaneous Control + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 25] + reset: 0 + sticky: N + - access: RW + acronym: WLCKDLY + description: ['0: delay ECC/DQS[8]/DQS_L[8] only, clocks not delayed', '1: delay + ECC/DQS[8]/DQS_L[8] and CK[2:0]/CK_L[2:0] (Normal setting for DDR2)'] + range: [24, 24] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [23, 23] + reset: 0 + sticky: N + - access: RW + acronym: WL_PHSEL_MODE + description: [See Table 16-294 for DQ/DQS, 'Connectivity:', '[22] CS, ODT, CKE', + '[21] CK[5:3], CK_L[5:3]', '[20] WL_CNTL[0] (DQ[15:0], DQS/DQS_L[1:0])', '[19] + WL_CNTL[1] (DQ[31:16], DQS/DQS_L[3:2])', '[18] WL_CNTL[4] (ECC[7:0], DQS/DQS_L[8],CK[2:0], + CK_L[2:0])', '[17] WL_CNTL[2] (DQ[47:32], DQS/DQS_L[5:4])', '[16] WL_CNTL[3] + (DQ[63:48], DQS/DQS_L[7:6])'] + range: [22, 16] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [15, 12] + reset: 0 + sticky: N + - access: RW + acronym: WL_CNTRL + description: ['Delay select for CK[5:3] and CK_L[5:3]:', '0xxx: no delay', '1001: + delay 1/4 clk1x', '1000: delay 1/2 clk1x', '1011: delay 3/4 clk1x', '1100: + delay 1 clk1x', OthersReserved] + range: [11, 8] + reset: 0 + sticky: Y + - access: RW + acronym: WL_CNTRL_A + description: ['Delay select for CS, ODT and CKE', '0xxx: no delay', '1001: delay + 1/4 clk1x', '1000: delay 1/2 clk1x', '1011: delay 3/4 clk1x', '1100: delay + 1 clk1x', OthersReserved] + range: [7, 4] + reset: 0 + sticky: Y + - access: RO + acronym: Reserved + description: [Reserved] + range: [3, 3] + reset: 0 + sticky: N + - access: RW + acronym: WL_CMD_DLY + description: [Reserved to Intel, 'Encoded additional delay for CS, CKE, ODT', + Delay introduced = (~100ps * WL_CMD_DLY)] + range: [2, 0] + reset: 0 + sticky: Y + offset: 664 + offset_end: [667, null] + offset_start: [664, null] + power_well: Core + recurring: null + reg_base_name: WDLL_MISC + reg_name: WDLL_MISC + size: 32 + table_ref: 16-295 + title_desc: DLL Miscellaneous Control + view: PCI +WL_CNTL[4:0]: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'WL_CNTL[4:0]: Write Levelization Control Register' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [31, 16] + reset: 0 + sticky: N + - access: RW + acronym: Reserved + description: [Reserved] + range: [15, 14] + reset: 0 + sticky: N + - access: RO + acronym: Reserved + description: [Reserved] + range: [13, 12] + reset: 0 + sticky: N + - access: RW + acronym: WL_CNTRL + description: [Delay Select, See Table 16-294] + range: [11, 8] + reset: 0 + sticky: Y + - access: RW + acronym: WDLL_CNTL + description: [Length controls for Slave Write DLL (WDLL). A delay of 0 up to 3/8 + of clk1x can be programmed using this CSR.] + range: [7, 2] + reset: 0 + sticky: Y + - access: RW + acronym: WDLL_CLKG + description: [Control bit for Clock gating of DQ/DQS., 0- Disable clock gating + for DQ/DQS, 1- Enable clock gating for DQ/DQS, 'Note: for WL_CNTL[4], WDLL_CLKG + must be equal to 0'] + range: [1, 1] + reset: 0 + sticky: Y + - access: RW + acronym: BYP_WDLL + description: ['Bypass Write DLL. This bit is used only for centering DQS to the + DQ eye. For write leveling, see Table 16-294.', 0 - Bypass DLL, 1 - Output + with WDLL, 'Before enabling/setting this bit to 1, software needs to first + program the appropriate values in DRAMDLLC.SLVLEN & WL_CNTL[x].WDLL_CNTL.'] + range: [0, 0] + reset: 0 + sticky: Y + offset: 644 + offset_end: [660, 4] + offset_start: [644, 4] + power_well: Core + recurring: 5 + reg_base_name: WL_CNTL + reg_name: WL_CNTL[4:0] + size: 32 + table_ref: 16-293 + title_desc: Write Levelization Control Register + view: PCI +WPTRTC0: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'WPTRTC0: Write pointer timing control' + fields: + - access: RW + acronym: DQS07 + description: ['DQS7 write pointer fine delay '] + range: [31, 28] + reset: 0 + sticky: Y + - access: RW + acronym: DQS06 + description: ['DQS6 write pointer fine delay '] + range: [27, 24] + reset: 0 + sticky: Y + - access: RW + acronym: DQS05 + description: ['DQS5 write pointer fine delay '] + range: [23, 20] + reset: 0 + sticky: Y + - access: RW + acronym: DQS04 + description: [DQS4 write pointer fine delay] + range: [19, 16] + reset: 0 + sticky: Y + - access: RW + acronym: DQS03 + description: ['DQS3 write pointer fine delay '] + range: [15, 12] + reset: 0 + sticky: Y + - access: RW + acronym: DQS02 + description: ['DQS2 write pointer fine delay '] + range: [11, 8] + reset: 0 + sticky: Y + - access: RW + acronym: DQS01 + description: ['DQS1 write pointer fine delay '] + range: [7, 4] + reset: 0 + sticky: Y + - access: RW + acronym: DQS00 + description: ['DQS0 write pointer fine delay '] + range: [3, 0] + reset: 0 + sticky: Y + offset: 204 + offset_end: [207, null] + offset_start: [204, null] + power_well: Core + recurring: null + reg_base_name: WPTRTC0 + reg_name: WPTRTC0 + size: 32 + table_ref: 16-246 + title_desc: Write Pointer Timing Control Register + view: PCI +WPTRTC1: + bar: SMRBASE + bus_device_function: 0:0:0 + default: 0 + description: 'WPTRTC1: Write pointer timing control' + fields: + - access: RO + acronym: Reserved + description: [Reserved] + range: [7, 4] + reset: 0 + sticky: '' + - access: RW + acronym: DQS08 + description: ['DQS8 write pointer fine delay '] + range: [3, 0] + reset: 0 + sticky: Y + offset: 208 + offset_end: [208, null] + offset_start: [208, null] + power_well: Core + recurring: null + reg_base_name: WPTRTC1 + reg_name: WPTRTC1 + size: 8 + table_ref: 16-247 + title_desc: Write Pointer Timing Control 1 Register + view: PCI diff --git a/parse_datasheet/parse_320066.py b/parse_datasheet/parse_320066.py index 75efe14..44fe164 100755 --- a/parse_datasheet/parse_320066.py +++ b/parse_datasheet/parse_320066.py @@ -5,6 +5,12 @@ import sys from pprint import pprint import json +try: + import yaml +except ImportError: + yaml = None + + from datasheet_tables import load_datasheet_pages, \ abs_tables_from_pages, \ profile_factory @@ -48,6 +54,8 @@ def main(): parser.add_option("-H", "--human", action="store_true", dest="human", help="print a human-readable description") parser.add_option("-j", "--json", action="store_true", dest="json", help="save parsed data to JSON") parser.add_option("-P", "--python", action="store_true", dest="python", help="dump datastructure in Python") + if yaml: + parser.add_option("-y", "--yaml", action="store_true", dest="yaml", help="save oarsed data to YAML") parser.add_option("-p", "--pickle", dest="pickle_filename", help="save parsed data to PICKLE", metavar="PICKLE") parser.add_option("-f", "--filename", dest="filename", help="Write data to file instead of stdout") @@ -77,8 +85,9 @@ def main(): elif options.python: pprint(make_stuff(a_t), out) elif options.json: - import json - print json.dump(make_stuff(a_t), out, indent=4) + json.dump(make_stuff(a_t), out, indent=4) + elif yaml and options.yaml: + yaml.safe_dump(make_stuff(a_t), stream=out) if out is not sys.stdout: out.close() |