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-rw-r--r--arch/mips/gt64120/momenco_ocelot/Makefile9
-rw-r--r--arch/mips/gt64120/momenco_ocelot/dbg_io.c126
-rw-r--r--arch/mips/gt64120/momenco_ocelot/int-handler.S131
-rw-r--r--arch/mips/gt64120/momenco_ocelot/irq.c67
-rw-r--r--arch/mips/gt64120/momenco_ocelot/ocelot_pld.h30
-rw-r--r--arch/mips/gt64120/momenco_ocelot/prom.c73
-rw-r--r--arch/mips/gt64120/momenco_ocelot/reset.c47
-rw-r--r--arch/mips/gt64120/momenco_ocelot/setup.c369
8 files changed, 852 insertions, 0 deletions
diff --git a/arch/mips/gt64120/momenco_ocelot/Makefile b/arch/mips/gt64120/momenco_ocelot/Makefile
new file mode 100644
index 00000000000..7b59c6567c7
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for Momentum's Ocelot board.
+#
+
+obj-y += int-handler.o irq.o prom.o reset.o setup.o
+
+obj-$(CONFIG_KGDB) += dbg_io.o
+
+EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/gt64120/momenco_ocelot/dbg_io.c b/arch/mips/gt64120/momenco_ocelot/dbg_io.c
new file mode 100644
index 00000000000..8720bccfdea
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/dbg_io.c
@@ -0,0 +1,126 @@
+#include <linux/config.h>
+
+#ifdef CONFIG_KGDB
+
+#include <asm/serial.h> /* For the serial port location and base baud */
+
+/* --- CONFIG --- */
+
+typedef unsigned char uint8;
+typedef unsigned int uint32;
+
+/* --- END OF CONFIG --- */
+
+#define UART16550_BAUD_2400 2400
+#define UART16550_BAUD_4800 4800
+#define UART16550_BAUD_9600 9600
+#define UART16550_BAUD_19200 19200
+#define UART16550_BAUD_38400 38400
+#define UART16550_BAUD_57600 57600
+#define UART16550_BAUD_115200 115200
+
+#define UART16550_PARITY_NONE 0
+#define UART16550_PARITY_ODD 0x08
+#define UART16550_PARITY_EVEN 0x18
+#define UART16550_PARITY_MARK 0x28
+#define UART16550_PARITY_SPACE 0x38
+
+#define UART16550_DATA_5BIT 0x0
+#define UART16550_DATA_6BIT 0x1
+#define UART16550_DATA_7BIT 0x2
+#define UART16550_DATA_8BIT 0x3
+
+#define UART16550_STOP_1BIT 0x0
+#define UART16550_STOP_2BIT 0x4
+
+/* ----------------------------------------------------- */
+
+/* === CONFIG === */
+
+/* [jsun] we use the second serial port for kdb */
+#define BASE OCELOT_SERIAL1_BASE
+#define MAX_BAUD OCELOT_BASE_BAUD
+
+/* === END OF CONFIG === */
+
+#define REG_OFFSET 4
+
+/* register offset */
+#define OFS_RCV_BUFFER 0
+#define OFS_TRANS_HOLD 0
+#define OFS_SEND_BUFFER 0
+#define OFS_INTR_ENABLE (1*REG_OFFSET)
+#define OFS_INTR_ID (2*REG_OFFSET)
+#define OFS_DATA_FORMAT (3*REG_OFFSET)
+#define OFS_LINE_CONTROL (3*REG_OFFSET)
+#define OFS_MODEM_CONTROL (4*REG_OFFSET)
+#define OFS_RS232_OUTPUT (4*REG_OFFSET)
+#define OFS_LINE_STATUS (5*REG_OFFSET)
+#define OFS_MODEM_STATUS (6*REG_OFFSET)
+#define OFS_RS232_INPUT (6*REG_OFFSET)
+#define OFS_SCRATCH_PAD (7*REG_OFFSET)
+
+#define OFS_DIVISOR_LSB (0*REG_OFFSET)
+#define OFS_DIVISOR_MSB (1*REG_OFFSET)
+
+
+/* memory-mapped read/write of the port */
+#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
+#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
+
+void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+ /* disable interrupts */
+ UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+ /* set up buad rate */
+ {
+ uint32 divisor;
+
+ /* set DIAB bit */
+ UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+ /* set divisor */
+ divisor = MAX_BAUD / baud;
+ UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+ UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
+
+ /* clear DIAB bit */
+ UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+ }
+
+ /* set data format */
+ UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+}
+
+static int remoteDebugInitialized = 0;
+
+uint8 getDebugChar(void)
+{
+ if (!remoteDebugInitialized) {
+ remoteDebugInitialized = 1;
+ debugInit(UART16550_BAUD_38400,
+ UART16550_DATA_8BIT,
+ UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+ }
+
+ while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+ return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+
+int putDebugChar(uint8 byte)
+{
+ if (!remoteDebugInitialized) {
+ remoteDebugInitialized = 1;
+ debugInit(UART16550_BAUD_38400,
+ UART16550_DATA_8BIT,
+ UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+ }
+
+ while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
+ UART16550_WRITE(OFS_SEND_BUFFER, byte);
+ return 1;
+}
+
+#endif
diff --git a/arch/mips/gt64120/momenco_ocelot/int-handler.S b/arch/mips/gt64120/momenco_ocelot/int-handler.S
new file mode 100644
index 00000000000..808acef248c
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/int-handler.S
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * First-level interrupt dispatcher for ocelot board.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+/*
+ * first level interrupt dispatcher for ocelot board -
+ * We check for the timer first, then check PCI ints A and D.
+ * Then check for serial IRQ and fall through.
+ */
+ .align 5
+ NESTED(ocelot_handle_int, PT_SIZE, sp)
+ SAVE_ALL
+ CLI
+ .set at
+ mfc0 t0, CP0_CAUSE
+ mfc0 t2, CP0_STATUS
+
+ and t0, t2
+
+ andi t1, t0, STATUSF_IP2 /* int0 hardware line */
+ bnez t1, ll_pri_enet_irq
+ andi t1, t0, STATUSF_IP3 /* int1 hardware line */
+ bnez t1, ll_sec_enet_irq
+ andi t1, t0, STATUSF_IP4 /* int2 hardware line */
+ bnez t1, ll_uart1_irq
+ andi t1, t0, STATUSF_IP5 /* int3 hardware line */
+ bnez t1, ll_cpci_irq
+ andi t1, t0, STATUSF_IP6 /* int4 hardware line */
+ bnez t1, ll_galileo_irq
+ andi t1, t0, STATUSF_IP7 /* cpu timer */
+ bnez t1, ll_cputimer_irq
+
+ /* now look at the extended interrupts */
+ mfc0 t0, CP0_CAUSE
+ cfc0 t1, CP0_S1_INTCONTROL
+
+ /* shift the mask 8 bits left to line up the bits */
+ sll t2, t1, 8
+
+ and t0, t2
+ srl t0, t0, 16
+
+ andi t1, t0, STATUSF_IP8 /* int6 hardware line */
+ bnez t1, ll_pmc1_irq
+ andi t1, t0, STATUSF_IP9 /* int7 hardware line */
+ bnez t1, ll_pmc2_irq
+ andi t1, t0, STATUSF_IP10 /* int8 hardware line */
+ bnez t1, ll_cpci_abcd_irq
+ andi t1, t0, STATUSF_IP11 /* int9 hardware line */
+ bnez t1, ll_uart2_irq
+
+ .set reorder
+
+ /* wrong alarm or masked ... */
+ j spurious_interrupt
+ nop
+ END(ocelot_handle_int)
+
+ .align 5
+ll_pri_enet_irq:
+ li a0, 2
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_sec_enet_irq:
+ li a0, 3
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_uart1_irq:
+ li a0, 4
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_cpci_irq:
+ li a0, 5
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_galileo_irq:
+ li a0, 6
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_cputimer_irq:
+ li a0, 7
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_pmc1_irq:
+ li a0, 8
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_pmc2_irq:
+ li a0, 9
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_cpci_abcd_irq:
+ li a0, 10
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
+
+ll_uart2_irq:
+ li a0, 11
+ move a1, sp
+ jal do_IRQ
+ j ret_from_irq
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c
new file mode 100644
index 00000000000..4f108da71b2
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/irq.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+
+extern asmlinkage void ocelot_handle_int(void);
+
+void __init arch_init_irq(void)
+{
+ /*
+ * Clear all of the interrupts while we change the able around a bit.
+ * int-handler is not on bootstrap
+ */
+ clear_c0_status(ST0_IM);
+ local_irq_disable();
+
+ /* Sets the first-level interrupt dispatcher. */
+ set_except_vector(0, ocelot_handle_int);
+
+ mips_cpu_irq_init(0);
+ rm7k_cpu_irq_init(8);
+}
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
new file mode 100644
index 00000000000..11f02c402b2
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h
@@ -0,0 +1,30 @@
+/*
+ * Ocelot Board Register Definitions
+ *
+ * (C) 2001 Red Hat, Inc.
+ *
+ * GPL'd
+ */
+#ifndef __MOMENCO_OCELOT_PLD_H__
+#define __MOMENCO_OCELOT_PLD_H__
+
+#define OCELOT_CS0_ADDR (0xe0020000)
+
+#define OCELOT_REG_BOARDREV (0)
+#define OCELOT_REG_PLD1_ID (1)
+#define OCELOT_REG_PLD2_ID (2)
+#define OCELOT_REG_RESET_STATUS (3)
+#define OCELOT_REG_BOARD_STATUS (4)
+#define OCELOT_REG_CPCI_ID (5)
+#define OCELOT_REG_I2C_CTRL (8)
+#define OCELOT_REG_EEPROM_MODE (9)
+#define OCELOT_REG_INTMASK (10)
+#define OCELOT_REG_INTSTATUS (11)
+#define OCELOT_REG_INTSET (12)
+#define OCELOT_REG_INTCLR (13)
+
+#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
+#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
+
+
+#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/gt64120/momenco_ocelot/prom.c b/arch/mips/gt64120/momenco_ocelot/prom.c
new file mode 100644
index 00000000000..8677b6d3ada
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/prom.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <asm/pmon.h>
+
+struct callvectors* debug_vectors;
+
+extern unsigned long gt64120_base;
+
+const char *get_system_type(void)
+{
+ return "Momentum Ocelot";
+}
+
+/* [jsun@junsun.net] PMON passes arguments in C main() style */
+void __init prom_init(void)
+{
+ int argc = fw_arg0;
+ char **arg = (char **) fw_arg1;
+ char **env = (char **) fw_arg2;
+ struct callvectors *cv = (struct callvectors *) fw_arg3;
+ uint32_t tmp;
+ int i;
+
+ /* save the PROM vectors for debugging use */
+ debug_vectors = cv;
+
+ /* arg[0] is "g", the rest is boot parameters */
+ arcs_cmdline[0] = '\0';
+ for (i = 1; i < argc; i++) {
+ if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
+ >= sizeof(arcs_cmdline))
+ break;
+ strcat(arcs_cmdline, arg[i]);
+ strcat(arcs_cmdline, " ");
+ }
+
+ mips_machgroup = MACH_GROUP_MOMENCO;
+ mips_machtype = MACH_MOMENCO_OCELOT;
+
+ while (*env) {
+ if (strncmp("gtbase", *env, 6) == 0) {
+ gt64120_base = simple_strtol(*env + strlen("gtbase="),
+ NULL, 16);
+ break;
+ }
+ *env++;
+ }
+
+ debug_vectors->printf("Booting Linux kernel...\n");
+
+ /* All the boards have at least 64MiB. If there's more, we
+ detect and register it later */
+ add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
+}
+
+unsigned long __init prom_free_prom_memory(void)
+{
+ return 0;
+}
diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c
new file mode 100644
index 00000000000..3fd499adf4c
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/reset.c
@@ -0,0 +1,47 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Copyright (C) 1997, 2001 Ralf Baechle
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <linux/delay.h>
+
+void momenco_ocelot_restart(char *command)
+{
+ void *nvram = ioremap_nocache(0x2c807000, 0x1000);
+
+ if (!nvram) {
+ printk(KERN_NOTICE "ioremap of reset register failed\n");
+ return;
+ }
+ writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
+ assert reset in 1/16 second */
+ mdelay(10+(1000/16));
+ iounmap(nvram);
+ printk(KERN_NOTICE "Watchdog reset failed\n");
+}
+
+void momenco_ocelot_halt(void)
+{
+ printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+ while (1)
+ __asm__(".set\tmips3\n\t"
+ "wait\n\t"
+ ".set\tmips0");
+}
+
+void momenco_ocelot_power_off(void)
+{
+ momenco_ocelot_halt();
+}
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
new file mode 100644
index 00000000000..d610f8c17c8
--- /dev/null
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -0,0 +1,369 @@
+/*
+ * setup.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Momentum Computer Ocelot (CP7000) - board dependent boot routines
+ *
+ * Copyright (C) 1996, 1997, 2001 Ralf Baechle
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2002 Momentum Computer
+ *
+ * Author: RidgeRun, Inc.
+ * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/timex.h>
+#include <linux/vmalloc.h>
+#include <asm/time.h>
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+#include <asm/reboot.h>
+#include <asm/traps.h>
+#include <linux/bootmem.h>
+#include <linux/initrd.h>
+#include <asm/gt64120.h>
+#include "ocelot_pld.h"
+
+unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
+
+/* These functions are used for rebooting or halting the machine*/
+extern void momenco_ocelot_restart(char *command);
+extern void momenco_ocelot_halt(void);
+extern void momenco_ocelot_power_off(void);
+
+extern void gt64120_time_init(void);
+extern void momenco_ocelot_irq_setup(void);
+
+static char reset_reason;
+
+#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
+
+static void __init setup_l3cache(unsigned long size);
+
+/* setup code for a handoff from a version 1 PMON 2000 PROM */
+void PMON_v1_setup()
+{
+ /* A wired TLB entry for the GT64120A and the serial port. The
+ GT64120A is going to be hit on every IRQ anyway - there's
+ absolutely no point in letting it be a random TLB entry, as
+ it'll just cause needless churning of the TLB. And we use
+ the other half for the serial port, which is just a PITA
+ otherwise :)
+
+ Device Physical Virtual
+ GT64120 Internal Regs 0x24000000 0xe0000000
+ UARTs (CS2) 0x2d000000 0xe0001000
+ */
+ add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
+
+ /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
+ in the CS[012] region. We can't use ioremap() yet. The NVRAM
+ is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
+
+ Ocelot PLD (CS0) 0x2c000000 0xe0020000
+ NVRAM 0x2c800000 0xe0030000
+ */
+
+ add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
+
+ /* Relocate the CS3/BootCS region */
+ GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
+
+ /* Relocate CS[012] */
+ GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
+
+ /* Relocate the GT64120A itself... */
+ GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
+ mb();
+ gt64120_base = 0xe0000000;
+
+ /* ...and the PCI0 view of it. */
+ GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
+ GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
+ GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
+ GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
+}
+
+/* setup code for a handoff from a version 2 PMON 2000 PROM */
+void PMON_v2_setup()
+{
+ /* A wired TLB entry for the GT64120A and the serial port. The
+ GT64120A is going to be hit on every IRQ anyway - there's
+ absolutely no point in letting it be a random TLB entry, as
+ it'll just cause needless churning of the TLB. And we use
+ the other half for the serial port, which is just a PITA
+ otherwise :)
+
+ Device Physical Virtual
+ GT64120 Internal Regs 0xf4000000 0xe0000000
+ UARTs (CS2) 0xfd000000 0xe0001000
+ */
+ add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
+
+ /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
+ in the CS[012] region. We can't use ioremap() yet. The NVRAM
+ is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
+
+ Ocelot PLD (CS0) 0xfc000000 0xe0020000
+ NVRAM 0xfc800000 0xe0030000
+ */
+ add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
+
+ gt64120_base = 0xe0000000;
+}
+
+static void __init momenco_ocelot_setup(void)
+{
+ void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
+ unsigned int tmpword;
+
+ board_time_init = gt64120_time_init;
+
+ _machine_restart = momenco_ocelot_restart;
+ _machine_halt = momenco_ocelot_halt;
+ _machine_power_off = momenco_ocelot_power_off;
+
+ /*
+ * initrd_start = (ulong)ocelot_initrd_start;
+ * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
+ * initrd_below_start_ok = 1;
+ */
+
+ /* do handoff reconfiguration */
+ if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
+ PMON_v1_setup();
+ else
+ PMON_v2_setup();
+
+ /* Turn off the Bit-Error LED */
+ OCELOT_PLD_WRITE(0x80, INTCLR);
+
+ /* Relocate all the PCI1 stuff, not that we use it */
+ GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
+ GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
+ GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
+
+ /* Relocate PCI0 I/O and Mem0 */
+ GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
+ GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
+
+ /* Relocate PCI0 Mem1 */
+ GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
+
+ /* For the initial programming, we assume 512MB configuration */
+ /* Relocate the CPU's view of the RAM... */
+ GT_WRITE(GT_SCS10LD_OFS, 0);
+ GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
+ GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
+ GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
+
+ GT_WRITE(GT_SCS1LD_OFS, 0xff);
+ GT_WRITE(GT_SCS1HD_OFS, 0x00);
+ GT_WRITE(GT_SCS0LD_OFS, 0);
+ GT_WRITE(GT_SCS0HD_OFS, 0xff);
+ GT_WRITE(GT_SCS3LD_OFS, 0xff);
+ GT_WRITE(GT_SCS3HD_OFS, 0x00);
+ GT_WRITE(GT_SCS2LD_OFS, 0);
+ GT_WRITE(GT_SCS2HD_OFS, 0xff);
+
+ /* ...and the PCI0 view of it. */
+ GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
+ GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
+ GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+ GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
+ GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
+ GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
+
+ tmpword = OCELOT_PLD_READ(BOARDREV);
+ if (tmpword < 26)
+ printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
+ else
+ printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
+
+ tmpword = OCELOT_PLD_READ(PLD1_ID);
+ printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
+ tmpword = OCELOT_PLD_READ(PLD2_ID);
+ printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
+ tmpword = OCELOT_PLD_READ(RESET_STATUS);
+ printk("Reset reason: 0x%x\n", tmpword);
+ reset_reason = tmpword;
+ OCELOT_PLD_WRITE(0xff, RESET_STATUS);
+
+ tmpword = OCELOT_PLD_READ(BOARD_STATUS);
+ printk("Board Status register: 0x%02x\n", tmpword);
+ printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
+ printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
+ printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
+ printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
+ printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
+
+ if (tmpword&12)
+ l3func((1<<(((tmpword&12) >> 2)+20)));
+
+ switch(tmpword &3) {
+ case 3:
+ /* 512MiB */
+ /* Decoders are allready set -- just add the
+ * appropriate region */
+ add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM);
+ add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
+ break;
+ case 2:
+ /* 256MiB -- two banks of 128MiB */
+ GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
+ GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
+ GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
+
+ GT_WRITE(GT_SCS0HD_OFS, 0x7f);
+ GT_WRITE(GT_SCS2LD_OFS, 0x80);
+ GT_WRITE(GT_SCS2HD_OFS, 0xff);
+
+ /* reconfigure the PCI0 interface view of memory */
+ GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+ GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
+ GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
+ GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
+
+ add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
+ add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
+ break;
+ case 1:
+ /* 128MiB -- 64MiB per bank */
+ GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
+ GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
+ GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
+
+ GT_WRITE(GT_SCS0HD_OFS, 0x3f);
+ GT_WRITE(GT_SCS2LD_OFS, 0x40);
+ GT_WRITE(GT_SCS2HD_OFS, 0x7f);
+
+ /* reconfigure the PCI0 interface view of memory */
+ GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+ GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
+ GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
+ GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
+
+ /* add the appropriate region */
+ add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
+ break;
+ case 0:
+ /* 64MiB */
+ GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
+ GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
+ GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
+
+ GT_WRITE(GT_SCS0HD_OFS, 0x1f);
+ GT_WRITE(GT_SCS2LD_OFS, 0x20);
+ GT_WRITE(GT_SCS2HD_OFS, 0x3f);
+
+ /* reconfigure the PCI0 interface view of memory */
+ GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
+ GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
+ GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
+ GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
+
+ break;
+ }
+
+ /* Fix up the DiskOnChip mapping */
+ GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
+}
+
+early_initcall(momenco_ocelot_setup);
+
+extern int rm7k_tcache_enabled;
+/*
+ * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
+ */
+#define Page_Invalidate_T 0x16
+static void __init setup_l3cache(unsigned long size)
+{
+ int register i;
+ unsigned long tmp;
+
+ printk("Enabling L3 cache...");
+
+ /* Enable the L3 cache in the GT64120A's CPU Configuration register */
+ tmp = GT_READ(GT_CPU_OFS);
+ GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
+
+ /* Enable the L3 cache in the CPU */
+ set_c0_config(1<<12 /* CONF_TE */);
+
+ /* Clear the cache */
+ write_c0_taglo(0);
+ write_c0_taghi(0);
+
+ for (i=0; i < size; i+= 4096) {
+ __asm__ __volatile__ (
+ ".set noreorder\n\t"
+ ".set mips3\n\t"
+ "cache %1, (%0)\n\t"
+ ".set mips0\n\t"
+ ".set reorder"
+ :
+ : "r" (KSEG0ADDR(i)),
+ "i" (Page_Invalidate_T));
+ }
+
+ /* Let the RM7000 MM code know that the tertiary cache is enabled */
+ rm7k_tcache_enabled = 1;
+
+ printk("Done\n");
+}
+
+
+/* This needs to be one of the first initcalls, because no I/O port access
+ can work before this */
+
+static int io_base_ioremap(void)
+{
+ void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
+
+ if (!io_remap_range) {
+ panic("Could not ioremap I/O port range");
+ }
+ set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
+
+ return 0;
+}
+
+module_init(io_base_ioremap);
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-19 17:32:35 +0000