diff options
| author | Borislav Petkov <borislav.petkov@amd.com> | 2009-10-09 19:14:43 +0200 |
|---|---|---|
| committer | Borislav Petkov <borislav.petkov@amd.com> | 2009-12-07 19:14:26 +0100 |
| commit | 72381bd55e4ce2aaed8660551e8f56a2c959c11f (patch) | |
| tree | c727201496a65f6c8c6434aec9c9a3af30160e11 /drivers/edac/amd64_edac.c | |
| parent | 6ec22f9b037fc0c2e00ddb7023fad279c365324d (diff) | |
amd64_edac: clarify DRAM CTL debug reporting
Make debug info formulations about the DRAM and DCT configuration of the
machine more human readable.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac/amd64_edac.c')
| -rw-r--r-- | drivers/edac/amd64_edac.c | 37 |
1 files changed, 23 insertions, 14 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index a38831c8264..0252a61f3d2 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1402,27 +1402,36 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, &pvt->dram_ctl_select_low); if (err) { - debugf0("Reading F10_DCTL_SEL_LOW failed\n"); + debugf0("Reading F2x110 (DCTL Sel. Low) failed\n"); } else { - debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n", - pvt->dram_ctl_select_low, dct_sel_baseaddr(pvt)); - - debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-" - "sel-hi-range=%s\n", - (dct_ganging_enabled(pvt) ? "GANGED" : "NOT GANGED"), - (dct_dram_enabled(pvt) ? "Enabled" : "Disabled"), - (dct_high_range_enabled(pvt) ? "Enabled" : "Disabled")); - - debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n", - (dct_data_intlv_enabled(pvt) ? "Enabled" : "Disabled"), - (dct_memory_cleared(pvt) ? "True " : "False "), + debugf0("F2x110 (DCTL Sel. Low): 0x%08x, " + "High range addresses at: 0x%x\n", + pvt->dram_ctl_select_low, + dct_sel_baseaddr(pvt)); + + debugf0(" DCT mode: %s, All DCTs on: %s\n", + (dct_ganging_enabled(pvt) ? "ganged" : "unganged"), + (dct_dram_enabled(pvt) ? "yes" : "no")); + + if (!dct_ganging_enabled(pvt)) + debugf0(" Address range split per DCT: %s\n", + (dct_high_range_enabled(pvt) ? "yes" : "no")); + + debugf0(" DCT data interleave for ECC: %s, " + "DRAM cleared since last warm reset: %s\n", + (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), + (dct_memory_cleared(pvt) ? "yes" : "no")); + + debugf0(" DCT channel interleave: %s, " + "DCT interleave bits selector: 0x%x\n", + (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), dct_sel_interleave_addr(pvt)); } err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, &pvt->dram_ctl_select_high); if (err) - debugf0("Reading F10_DCTL_SEL_HIGH failed\n"); + debugf0("Reading F2x114 (DCT Sel. High) failed\n"); } /* |