diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-10 17:39:40 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-10 17:39:40 -0800 |
commit | 06792c4dde2ad143928cc95c1ba218c6269c494b (patch) | |
tree | 92bdd4631612c9e3d8e5f6f06839f75c5473300a /Documentation/devicetree/bindings/c6x/timer64.txt | |
parent | 4690dfa8cd66c37fbe99bb8cd5baa86102110776 (diff) | |
parent | 166c0eaedfc3157dc1394c27e827add19f05fb27 (diff) |
Merge tag 'for-linux-3.3-merge-window' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming
* tag 'for-linux-3.3-merge-window' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming: (29 commits)
C6X: replace tick_nohz_stop/restart_sched_tick calls
C6X: add register_cpu call
C6X: deal with memblock API changes
C6X: fix timer64 initialization
C6X: fix layout of EMIFA registers
C6X: MAINTAINERS
C6X: DSCR - Device State Configuration Registers
C6X: EMIF - External Memory Interface
C6X: general SoC support
C6X: library code
C6X: headers
C6X: ptrace support
C6X: loadable module support
C6X: cache control
C6X: clocks
C6X: build infrastructure
C6X: syscalls
C6X: interrupt handling
C6X: time management
C6X: signal management
...
Diffstat (limited to 'Documentation/devicetree/bindings/c6x/timer64.txt')
-rw-r--r-- | Documentation/devicetree/bindings/c6x/timer64.txt | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/c6x/timer64.txt b/Documentation/devicetree/bindings/c6x/timer64.txt new file mode 100644 index 00000000000..95911fe7022 --- /dev/null +++ b/Documentation/devicetree/bindings/c6x/timer64.txt @@ -0,0 +1,26 @@ +Timer64 +------- + +The timer64 node describes C6X event timers. + +Required properties: + +- compatible: must be "ti,c64x+timer64" +- reg: base address and size of register region +- interrupt-parent: interrupt controller +- interrupts: interrupt id + +Optional properties: + +- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface. + +- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer. + +Example: + timer0: timer@25e0000 { + compatible = "ti,c64x+timer64"; + ti,core-mask = < 0x01 >; + reg = <0x25e0000 0x40>; + interrupt-parent = <&megamod_pic>; + interrupts = < 16 >; + }; |