diff options
| author | Noe Rubinstein <nrubinstein@avencall.com> | 2012-10-25 11:36:51 +0200 |
|---|---|---|
| committer | Noe Rubinstein <nrubinstein@avencall.com> | 2012-10-25 11:36:51 +0200 |
| commit | 054d48ac8501d6c121e1fb47d3c0fe392f3a7424 (patch) | |
| tree | 4987e3abedd11fa465b7c8a7c2d928b97d4a761e /XIOHV5.13.sch | |
Initial publication of the sources for XIOHv5
Diffstat (limited to 'XIOHV5.13.sch')
| -rw-r--r-- | XIOHV5.13.sch | 58099 |
1 files changed, 58099 insertions, 0 deletions
diff --git a/XIOHV5.13.sch b/XIOHV5.13.sch new file mode 100644 index 0000000..7271da9 --- /dev/null +++ b/XIOHV5.13.sch @@ -0,0 +1,58099 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="6.2"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="9" visible="no" active="no"/> +<layer number="2" name="Route2" color="6" fill="9" visible="no" active="no"/> +<layer number="3" name="Route3" color="5" fill="13" visible="no" active="no"/> +<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/> +<layer number="5" name="Route5" color="3" fill="4" visible="no" active="no"/> +<layer number="6" name="Route6" color="7" fill="12" visible="no" active="no"/> +<layer number="7" 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+<pin name="DDR_DQ[23]" x="-16.51" y="-24.13" length="middle"/> +<pin name="DDR_DQ[24]" x="-16.51" y="-26.67" length="middle"/> +<pin name="DDR_DQ[25]" x="-16.51" y="-29.21" length="middle"/> +<pin name="DDR_DQ[26]" x="-16.51" y="-31.75" length="middle"/> +<pin name="DDR_DQ[27]" x="-16.51" y="-34.29" length="middle"/> +<pin name="DDR_DQ[28]" x="-16.51" y="-36.83" length="middle"/> +<pin name="DDR_DQ[29]" x="-16.51" y="-39.37" length="middle"/> +<pin name="DDR_DQ[30]" x="-16.51" y="-41.91" length="middle"/> +<pin name="DDR_DQ[31]" x="-16.51" y="-44.45" length="middle"/> +<pin name="DDR_DQ[32]" x="-16.51" y="-46.99" length="middle"/> +<pin name="DDR_DQ[33]" x="-16.51" y="-49.53" length="middle"/> +<pin name="DDR_DQ[34]" x="-16.51" y="-52.07" length="middle"/> +<pin name="DDR_DQ[35]" x="-16.51" y="-54.61" length="middle"/> +<pin name="DDR_DQ[36]" x="-16.51" y="-57.15" length="middle"/> +<pin name="DDR_DQ[37]" x="-16.51" y="-59.69" length="middle"/> +<pin name="DDR_DQ[38]" x="-16.51" y="-62.23" length="middle"/> +<pin name="DDR_DQ[39]" x="-16.51" y="-64.77" length="middle"/> +<pin name="DDR_DQ[40]" x="-16.51" y="-67.31" length="middle"/> +<pin name="DDR_DQ[41]" x="-16.51" y="-69.85" length="middle"/> +<pin name="DDR_DQ[42]" x="-16.51" y="-72.39" length="middle"/> +<pin name="DDR_DQ[43]" x="-16.51" y="-74.93" length="middle"/> +<pin name="DDR_DQ[44]" x="-16.51" y="-77.47" length="middle"/> +<pin name="DDR_DQ[45]" x="-16.51" y="-80.01" length="middle"/> +<pin name="DDR_DQ[46]" x="-16.51" y="-82.55" length="middle"/> +<pin name="DDR_DQ[47]" x="-16.51" y="-85.09" length="middle"/> +<pin name="DDR_DQ[48]" x="-16.51" y="-87.63" length="middle"/> +<pin name="DDR_DQ[49]" x="-16.51" y="-90.17" length="middle"/> +<pin name="DDR_DQ[50]" x="-16.51" y="-92.71" length="middle"/> +<pin name="DDR_DQ[51]" x="-16.51" y="-95.25" length="middle"/> +<pin name="DDR_DQ[52]" x="-16.51" y="-97.79" length="middle"/> +<pin name="DDR_DQ[53]" x="-16.51" y="-100.33" length="middle"/> +<pin name="DDR_DQ[54]" x="-16.51" y="-102.87" length="middle"/> +<pin name="DDR_DQ[55]" x="-16.51" y="-105.41" length="middle"/> +<pin name="DDR_DQ[56]" x="-16.51" y="-107.95" length="middle"/> +<pin name="DDR_DQ[57]" x="-16.51" y="-110.49" length="middle"/> +<pin name="DDR_DQ[58]" x="-16.51" y="-113.03" length="middle"/> +<pin name="DDR_DQ[59]" x="-16.51" y="-115.57" length="middle"/> +<pin name="DDR_DQ[60]" x="-16.51" y="-118.11" length="middle"/> +<pin name="DDR_DQ[61]" x="-16.51" y="-120.65" length="middle"/> +<pin name="DDR_DQ[62]" x="-16.51" y="-123.19" length="middle"/> +<pin name="DDR_DQ[63]" x="-16.51" y="-125.73" length="middle"/> +<pin name="DDR_DM[0]" x="-16.51" y="-129.54" length="middle" direction="in"/> +<pin name="DDR_DM[1]" x="-16.51" y="-132.08" length="middle" direction="in"/> +<pin name="DDR_DM[2]" x="-16.51" y="-134.62" length="middle" direction="in"/> +<pin name="DDR_DM[3]" x="-16.51" y="-137.16" length="middle" direction="in"/> +<pin name="DDR_DM[4]" x="-16.51" y="-139.7" length="middle" direction="in"/> +<pin name="DDR_DM[5]" x="-16.51" y="-142.24" length="middle" direction="in"/> +<pin name="DDR_DM[6]" x="-16.51" y="-144.78" length="middle" direction="in"/> +<pin name="DDR_DM[7]" x="-16.51" y="-147.32" length="middle" direction="in"/> +<pin name="DDR_DM[8]" x="-16.51" y="-149.86" length="middle" direction="in"/> +</symbol> +<symbol name="EP80-GBE0"> +<wire x1="-12.7" y1="10.16" x2="13.97" y2="10.16" width="0.1524" layer="94"/> +<wire x1="13.97" y1="10.16" x2="13.97" y2="-40.64" width="0.1524" layer="94"/> +<wire x1="13.97" y1="-40.64" x2="-12.7" y2="-40.64" width="0.1524" layer="94"/> +<wire x1="-12.7" y1="-40.64" x2="-12.7" y2="10.16" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="9.8425" x2="13.6525" y2="9.8425" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="9.8425" x2="13.6525" y2="-40.3225" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="-40.3225" x2="-12.3825" y2="-40.3225" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="-40.3225" x2="-12.3825" y2="9.8425" width="0.1524" layer="94"/> +<text x="10.16" y="8.89" size="1.9304" layer="94" rot="R270">GbE0 - cf p1760</text> +<text x="17.145" y="-1.905" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="17.145" y="-40.64" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="GBE0_TXCLK" x="-17.78" y="-16.51" length="middle" direction="out" function="clk"/> +<pin name="GBE0_TXCTL" x="-17.78" y="-19.05" length="middle" direction="out"/> +<pin name="GBE0_TXDATA[0]" x="-17.78" y="7.62" length="middle" direction="out"/> +<pin name="GBE0_TXDATA[1]" x="-17.78" y="5.08" length="middle" direction="out"/> +<pin name="GBE0_TXDATA[2]" x="-17.78" y="2.54" length="middle" direction="out"/> +<pin name="GBE0_TXDATA[3]" x="-17.78" y="0" length="middle" direction="out"/> +<pin name="GBE0_RXCLK" x="-17.78" y="-13.97" length="middle" direction="in" function="clk"/> +<pin name="GBE0_RXCTL" x="-17.78" y="-21.59" length="middle" direction="in"/> +<pin name="GBE0_RXDATA[0]" x="-17.78" y="-30.48" length="middle" direction="in"/> +<pin name="GBE0_RXDATA[1]" x="-17.78" y="-33.02" length="middle" direction="in"/> +<pin name="GBE0_RXDATA[2]" x="-17.78" y="-35.56" length="middle" direction="in"/> +<pin name="GBE0_RXDATA[3]" x="-17.78" y="-38.1" length="middle" direction="in"/> +</symbol> +<symbol name="EP80-GBE1"> +<wire x1="-12.7" y1="10.16" x2="13.97" y2="10.16" width="0.1524" layer="94"/> +<wire x1="13.97" y1="10.16" x2="13.97" y2="-40.64" width="0.1524" layer="94"/> +<wire x1="13.97" y1="-40.64" x2="-12.7" y2="-40.64" width="0.1524" layer="94"/> +<wire x1="-12.7" y1="-40.64" x2="-12.7" y2="10.16" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="9.8425" x2="13.6525" y2="9.8425" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="9.8425" x2="13.6525" y2="-40.3225" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="-40.3225" x2="-12.3825" y2="-40.3225" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="-40.3225" x2="-12.3825" y2="9.8425" width="0.1524" layer="94"/> +<text x="10.16" y="8.89" size="1.9304" layer="94" rot="R270">GbE1 - cf p1760</text> +<text x="17.145" y="1.905" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="17.145" y="-19.05" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="GBE1_TXCLK" x="-17.78" y="-16.51" length="middle" direction="out" function="clk"/> +<pin name="GBE1_TXCTL" x="-17.78" y="-19.05" length="middle" direction="out"/> +<pin name="GBE1_TXDATA[0]" x="-17.78" y="7.62" length="middle" direction="out"/> +<pin name="GBE1_TXDATA[1]" x="-17.78" y="5.08" length="middle" direction="out"/> +<pin name="GBE1_TXDATA[2]" x="-17.78" y="2.54" length="middle" direction="out"/> +<pin name="GBE1_TXDATA[3]" x="-17.78" y="0" length="middle" direction="out"/> +<pin name="GBE1_RXCLK" x="-17.78" y="-13.97" length="middle" direction="in" function="clk"/> +<pin name="GBE1_RXCTL" x="-17.78" y="-21.59" length="middle" direction="in"/> +<pin name="GBE1_RXDATA[0]" x="-17.78" y="-30.48" length="middle" direction="in"/> +<pin name="GBE1_RXDATA[1]" x="-17.78" y="-33.02" length="middle" direction="in"/> +<pin name="GBE1_RXDATA[2]" x="-17.78" y="-35.56" length="middle" direction="in"/> +<pin name="GBE1_RXDATA[3]" x="-17.78" y="-38.1" length="middle" direction="in"/> +</symbol> +<symbol name="EP80-GBE2"> +<wire x1="-12.7" y1="10.16" x2="13.97" y2="10.16" width="0.1524" layer="94"/> +<wire x1="13.97" y1="10.16" x2="13.97" y2="-40.64" width="0.1524" layer="94"/> +<wire x1="13.97" y1="-40.64" x2="-12.7" y2="-40.64" width="0.1524" layer="94"/> +<wire x1="-12.7" y1="-40.64" x2="-12.7" y2="10.16" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="9.8425" x2="13.6525" y2="9.8425" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="9.8425" x2="13.6525" y2="-40.3225" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="-40.3225" x2="-12.3825" y2="-40.3225" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="-40.3225" x2="-12.3825" y2="9.8425" width="0.1524" layer="94"/> +<text x="10.16" y="8.89" size="1.9304" layer="94" rot="R270">GbE2 - cf p1760</text> +<text x="17.145" y="0.635" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="17.145" y="-21.59" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="GBE2_TXCLK" x="-17.78" y="-16.51" length="middle" direction="out" function="clk"/> +<pin name="GBE2_TXCTL" x="-17.78" y="-19.05" length="middle" direction="out"/> +<pin name="GBE2_TXDATA[0]" x="-17.78" y="7.62" length="middle" direction="out"/> +<pin name="GBE2_TXDATA[1]" x="-17.78" y="5.08" length="middle" direction="out"/> +<pin name="GBE2_TXDATA[2]" x="-17.78" y="2.54" length="middle" direction="out"/> +<pin name="GBE2_TXDATA[3]" x="-17.78" y="0" length="middle" direction="out"/> +<pin name="GBE2_RXCLK" x="-17.78" y="-13.97" length="middle" direction="in" function="clk"/> +<pin name="GBE2_RXCTL" x="-17.78" y="-21.59" length="middle" direction="in"/> +<pin name="GBE2_RXDATA[0]" x="-17.78" y="-30.48" length="middle" direction="in"/> +<pin name="GBE2_RXDATA[1]" x="-17.78" y="-33.02" length="middle" direction="in"/> +<pin name="GBE2_RXDATA[2]" x="-17.78" y="-35.56" length="middle" direction="in"/> +<pin name="GBE2_RXDATA[3]" x="-17.78" y="-38.1" length="middle" direction="in"/> +</symbol> +<symbol name="EP80-GPIO"> +<wire x1="-11.43" y1="27.94" x2="10.16" y2="27.94" width="0.1524" layer="94"/> +<wire x1="10.16" y1="27.94" x2="10.16" y2="-5.08" width="0.1524" layer="94"/> +<wire x1="10.16" y1="-5.08" x2="-11.43" y2="-5.08" width="0.1524" layer="94"/> +<wire x1="-11.43" y1="-5.08" x2="-11.43" y2="27.94" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="27.6225" x2="9.8425" y2="27.6225" width="0.1524" layer="94"/> +<wire x1="9.8425" y1="27.6225" x2="9.8425" y2="-4.7625" width="0.1524" layer="94"/> +<wire x1="9.8425" y1="-4.7625" x2="-11.1125" y2="-4.7625" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="-4.7625" x2="-11.1125" y2="27.6225" width="0.1524" layer="94"/> +<text x="6.35" y="26.67" size="1.9304" layer="94" rot="R270">GPIO - cf p1744</text> +<text x="13.335" y="13.335" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="13.335" y="-5.08" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="GPIO[0]" x="-16.51" y="25.4" length="middle" direction="in"/> +<pin name="GPIO[7]" x="-16.51" y="17.78" length="middle" direction="in"/> +<pin name="GPIO[1]" x="-16.51" y="22.86" length="middle" direction="in"/> +<pin name="GPIO[6]" x="-16.51" y="20.32" length="middle" direction="in"/> +<pin name="GPIO[8]" x="-16.51" y="15.24" length="middle" direction="in"/> +<pin name="GPIO[9]" x="-16.51" y="12.7" length="middle" direction="in"/> +<pin name="GPIO[10]" x="-16.51" y="10.16" length="middle" direction="in"/> +<pin name="GPIO[12]" x="-16.51" y="7.62" length="middle" direction="in"/> +<pin name="GPIO[14]" x="-16.51" y="2.54" length="middle" direction="in"/> +<pin name="GPIO[13]" x="-16.51" y="5.08" length="middle" direction="in"/> +<pin name="GPIO[15]" x="-16.51" y="0" length="middle" direction="in"/> +<pin name="GPIO[48]" x="-16.51" y="-2.54" length="middle" direction="out"/> +</symbol> +<symbol name="EP80-GPIOIRQ"> +<wire x1="-13.97" y1="15.24" x2="7.62" y2="15.24" width="0.1524" layer="94"/> +<wire x1="7.62" y1="15.24" x2="7.62" y2="-27.94" width="0.1524" layer="94"/> +<wire x1="7.62" y1="-27.94" x2="-13.97" y2="-27.94" width="0.1524" layer="94"/> +<wire x1="-13.97" y1="-27.94" x2="-13.97" y2="15.24" width="0.1524" layer="94"/> +<wire x1="-13.6525" y1="14.9225" x2="7.3025" y2="14.9225" width="0.1524" layer="94"/> +<wire x1="7.3025" y1="14.9225" x2="7.3025" y2="-27.6225" width="0.1524" layer="94"/> +<wire x1="7.3025" y1="-27.6225" x2="-13.6525" y2="-27.6225" width="0.1524" layer="94"/> +<wire x1="-13.6525" y1="-27.6225" x2="-13.6525" y2="14.9225" width="0.1524" layer="94"/> +<text x="3.81" y="13.97" size="1.9304" layer="94" rot="R270">GPIO_IRQ - cf p1745</text> +<text x="10.795" y="-5.715" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="10.795" y="-27.94" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="GP16_IRQ24" x="-19.05" y="12.7" length="middle"/> +<pin name="GP19_IRQ37" x="-19.05" y="5.08" length="middle"/> +<pin name="GP17_IRQ25" x="-19.05" y="10.16" length="middle"/> +<pin name="GP18_IRQ36" x="-19.05" y="7.62" length="middle"/> +<pin name="GP20_IRQ26" x="-19.05" y="2.54" length="middle"/> +<pin name="GP21_IRQ27" x="-19.05" y="0" length="middle"/> +<pin name="GP23_IRQ28" x="-19.05" y="-2.54" length="middle"/> +<pin name="GP24_IRQ29" x="-19.05" y="-5.08" length="middle"/> +<pin name="GP27_IRQ39" x="-19.05" y="-10.16" length="middle"/> +<pin name="GP25_IRQ38" x="-19.05" y="-7.62" length="middle"/> +<pin name="GP28_IRQ30" x="-19.05" y="-12.7" length="middle"/> +<pin name="GP30_IRQ31" x="-19.05" y="-15.24" length="middle" direction="in"/> +<pin name="GP31_IRQ32" x="-19.05" y="-17.78" length="middle"/> +<pin name="GP33_IRQ33" x="-19.05" y="-20.32" length="middle"/> +<pin name="GP34_IRQ34" x="-19.05" y="-22.86" length="middle"/> +<pin name="GP40_IRQ35" x="-19.05" y="-25.4" length="middle" direction="in"/> +</symbol> +<symbol name="EP80-IA32CORE"> +<wire x1="-11.43" y1="21.59" x2="12.7" y2="21.59" width="0.1524" layer="94"/> +<wire x1="12.7" y1="21.59" x2="12.7" y2="-21.59" width="0.1524" layer="94"/> +<wire x1="12.7" y1="-21.59" x2="-11.43" y2="-21.59" width="0.1524" layer="94"/> +<wire x1="-11.43" y1="-21.59" x2="-11.43" y2="21.59" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="21.2725" x2="12.3825" y2="21.2725" width="0.1524" layer="94"/> +<wire x1="12.3825" y1="21.2725" x2="12.3825" y2="-21.2725" width="0.1524" layer="94"/> +<wire x1="12.3825" y1="-21.2725" x2="-11.1125" y2="-21.2725" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="-21.2725" x2="-11.1125" y2="21.2725" width="0.1524" layer="94"/> +<text x="8.89" y="20.32" size="1.9304" layer="94" rot="R270">IA32CORE - cf p1737</text> +<text x="15.875" y="-0.635" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="15.875" y="-21.59" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="THERMDC" x="-16.51" y="19.05" length="middle"/> +<pin name="THERMDA" x="-16.51" y="16.51" length="middle"/> +<pin name="CLKP100" x="-16.51" y="11.43" length="middle" direction="in" function="clk"/> +<pin name="CLKN100" x="-16.51" y="8.89" length="middle" direction="in" function="dotclk"/> +<pin name="CPUSLP_OUT_N" x="-16.51" y="3.81" length="middle" direction="out"/> +<pin name="INIT33V_OUT_N" x="-16.51" y="1.27" length="middle"/> +<pin name="NMI" x="-16.51" y="-1.27" length="middle"/> +<pin name="SMI_OUT_N" x="-16.51" y="-3.81" length="middle" direction="in"/> +<pin name="STPCLK_OUT_N" x="-16.51" y="-6.35" length="middle" direction="out"/> +<pin name="RCIN_N" x="-16.51" y="-8.89" length="middle" direction="in"/> +<pin name="A20GATE" x="-16.51" y="-11.43" length="middle" direction="in"/> +<pin name="CPURST_N" x="-16.51" y="-13.97" length="middle" direction="out"/> +<pin name="CPUPWRGD_OUT" x="-16.51" y="-16.51" length="middle" direction="oc"/> +<pin name="IERR_N" x="-16.51" y="-19.05" length="middle" direction="out"/> +</symbol> +<symbol name="EP80-IEEE1588"> +<wire x1="-12.7" y1="17.78" x2="19.05" y2="17.78" width="0.1524" layer="94"/> +<wire x1="19.05" y1="17.78" x2="19.05" y2="-10.16" width="0.1524" layer="94"/> +<wire x1="19.05" y1="-10.16" x2="-12.7" y2="-10.16" width="0.1524" layer="94"/> +<wire x1="-12.7" y1="-10.16" x2="-12.7" y2="17.78" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="17.4625" x2="18.7325" y2="17.4625" width="0.1524" layer="94"/> +<wire x1="18.7325" y1="17.4625" x2="18.7325" y2="-9.8425" width="0.1524" layer="94"/> +<wire x1="18.7325" y1="-9.8425" x2="-12.3825" y2="-9.8425" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="-9.8425" x2="-12.3825" y2="17.4625" width="0.1524" layer="94"/> +<text x="-10.16" y="13.97" size="1.6764" layer="94">IEEE1588 - cf p1768</text> +<text x="-12.7" y="-12.7" size="1.778" layer="96">>VALUE</text> +<text x="-12.7" y="18.415" size="1.778" layer="95">>NAME</text> +<pin name="1588_TESTMODE_DATA" x="-17.78" y="11.43" length="middle" direction="out"/> +<pin name="1588_PPS" x="-17.78" y="7.62" length="middle" direction="out"/> +<pin name="ASMSSIG" x="-17.78" y="3.81" length="middle" direction="in"/> +<pin name="AMMSSIG" x="-17.78" y="0" length="middle" direction="in"/> +<pin name="1588_RX_SNAP" x="-17.78" y="-3.81" length="middle" direction="out"/> +<pin name="1588_TX_SNAP" x="-17.78" y="-7.62" length="middle" direction="out"/> +</symbol> +<symbol name="EP80-IICHIMCH"> +<wire x1="-11.43" y1="21.59" x2="22.86" y2="21.59" width="0.1524" layer="94"/> +<wire x1="22.86" y1="21.59" x2="22.86" y2="-27.94" width="0.1524" layer="94"/> +<wire x1="22.86" y1="-27.94" x2="-11.43" y2="-27.94" width="0.1524" layer="94"/> +<wire x1="-11.43" y1="-27.94" x2="-11.43" y2="21.59" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="21.2725" x2="22.5425" y2="21.2725" width="0.1524" layer="94"/> +<wire x1="22.5425" y1="21.2725" x2="22.5425" y2="-27.6225" width="0.1524" layer="94"/> +<wire x1="22.5425" y1="-27.6225" x2="-11.1125" y2="-27.6225" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="-27.6225" x2="-11.1125" y2="21.2725" width="0.1524" layer="94"/> +<text x="-10.16" y="17.78" size="1.6764" layer="94">IMCH RESET - cf p1739</text> +<text x="-10.16" y="-17.78" size="1.6764" layer="94">IICH Misc Sig- cf p1758</text> +<text x="-10.16" y="0" size="1.6764" layer="94">IICH IRQ - cf p1748</text> +<text x="-10.16" y="6.35" size="1.6764" layer="94">IICH CLK - cf p1744</text> +<text x="-11.43" y="-30.48" size="1.778" layer="96">>VALUE</text> +<text x="-10.795" y="22.225" size="1.778" layer="95">>NAME</text> +<pin name="RSTIN_N" x="-16.51" y="15.24" length="middle" direction="in"/> +<pin name="PWRGD" x="-16.51" y="12.7" length="middle" direction="in"/> +<pin name="CLK14" x="-16.51" y="-20.32" length="middle" direction="in"/> +<pin name="PE_HPINTR_N" x="-16.51" y="-22.86" length="middle" direction="in"/> +<pin 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y1="16.51" x2="12.7" y2="-26.67" width="0.1524" layer="94"/> +<wire x1="12.7" y1="-26.67" x2="-11.43" y2="-26.67" width="0.1524" layer="94"/> +<wire x1="-11.43" y1="-26.67" x2="-11.43" y2="16.51" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="16.1925" x2="12.3825" y2="16.1925" width="0.1524" layer="94"/> +<wire x1="12.3825" y1="16.1925" x2="12.3825" y2="-26.3525" width="0.1524" layer="94"/> +<wire x1="12.3825" y1="-26.3525" x2="-11.1125" y2="-26.3525" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="-26.3525" x2="-11.1125" y2="16.1925" width="0.1524" layer="94"/> +<text x="8.89" y="15.24" size="1.9304" layer="94" rot="R270">JTAG - cf p1769</text> +<text x="15.24" y="-6.985" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="15.24" y="-26.67" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="TMS" x="-16.51" y="13.97" length="middle"/> +<pin name="TDI" x="-16.51" y="10.16" length="middle"/> +<pin name="TDO" x="-16.51" y="6.35" length="middle"/> +<pin name="TCK" x="-16.51" y="2.54" length="middle" function="clk"/> +<pin name="TRST_N" x="-16.51" y="-1.27" length="middle"/> +<pin name="BPM0" x="-16.51" y="-5.08" length="middle"/> +<pin name="BPM1" x="-16.51" y="-7.62" length="middle"/> +<pin name="BPM2" x="-16.51" y="-10.16" length="middle"/> +<pin name="BPM3" x="-16.51" y="-12.7" length="middle"/> +<pin name="BPM3_IN" x="-16.51" y="-16.51" length="middle"/> +<pin name="BPM4_PRDY_OUT" x="-16.51" y="-20.32" length="middle"/> +<pin name="BPM5_PREQ_IN" x="-16.51" y="-24.13" length="middle"/> +</symbol> +<symbol name="EP80-LEB"> +<wire x1="-10.16" y1="11.43" x2="13.97" y2="11.43" width="0.1524" layer="94"/> +<wire x1="13.97" y1="11.43" x2="13.97" y2="-68.58" width="0.1524" layer="94"/> +<wire x1="13.97" y1="-68.58" x2="-10.16" y2="-68.58" width="0.1524" layer="94"/> +<wire x1="-10.16" y1="-68.58" x2="-10.16" y2="11.43" width="0.1524" layer="94"/> +<wire x1="-9.8425" y1="11.1125" x2="13.6525" y2="11.1125" width="0.1524" layer="94"/> +<wire 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y="-10.16" length="middle"/> +<pin name="EX_ADDR[7]" x="-15.24" y="-12.7" length="middle"/> +<pin name="EX_ADDR[8]" x="-15.24" y="-15.24" length="middle"/> +<pin name="EX_ADDR[9]" x="-15.24" y="-17.78" length="middle"/> +<pin name="EX_ADDR[10]" x="-15.24" y="-20.32" length="middle"/> +<pin name="EX_ADDR[11]" x="-15.24" y="-22.86" length="middle"/> +<pin name="EX_ADDR[12]" x="-15.24" y="-25.4" length="middle"/> +<pin name="EX_ADDR[13]" x="-15.24" y="-27.94" length="middle"/> +<pin name="EX_ADDR[14]" x="-15.24" y="-30.48" length="middle"/> +<pin name="EX_ADDR[15]" x="-15.24" y="-33.02" length="middle"/> +<pin name="EX_ADDR[16]" x="-15.24" y="-35.56" length="middle"/> +<pin name="EX_ADDR[17]" x="-15.24" y="-38.1" length="middle"/> +<pin name="EX_ADDR[18]" x="-15.24" y="-40.64" length="middle"/> +<pin name="EX_ADDR[19]" x="-15.24" y="-43.18" length="middle"/> +<pin name="EX_ADDR[20]" x="-15.24" y="-45.72" length="middle"/> +<pin name="EX_ADDR[21]" x="-15.24" y="-48.26" length="middle"/> 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y="-34.29" length="middle"/> +<pin name="EX_DATA[1]" x="-16.51" y="-31.75" length="middle"/> +<pin name="EX_DATA[2]" x="-16.51" y="-29.21" length="middle"/> +<pin name="EX_DATA[3]" x="-16.51" y="-26.67" length="middle"/> +<pin name="EX_DATA[4]" x="-16.51" y="-24.13" length="middle"/> +<pin name="EX_DATA[5]" x="-16.51" y="-21.59" length="middle"/> +<pin name="EX_DATA[6]" x="-16.51" y="-19.05" length="middle"/> +<pin name="EX_DATA[7]" x="-16.51" y="-16.51" length="middle"/> +<pin name="EX_DATA[8]" x="-16.51" y="-13.97" length="middle"/> +<pin name="EX_DATA[9]" x="-16.51" y="-11.43" length="middle"/> +<pin name="EX_DATA[10]" x="-16.51" y="-8.89" length="middle"/> +<pin name="EX_DATA[11]" x="-16.51" y="-6.35" length="middle"/> +<pin name="EX_DATA[12]" x="-16.51" y="-3.81" length="middle"/> +<pin name="EX_DATA[13]" x="-16.51" y="-1.27" length="middle"/> +<pin name="EX_DATA[14]" x="-16.51" y="1.27" length="middle"/> +<pin name="EX_DATA[15]" x="-16.51" y="3.81" length="middle"/> +<pin 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+<pin name="NC37" x="-16.51" y="-26.67" length="middle"/> +<pin name="NC38" x="-16.51" y="-29.21" length="middle"/> +<pin name="NC40" x="-16.51" y="-31.75" length="middle"/> +<pin name="NC41" x="-16.51" y="-34.29" length="middle"/> +<pin name="NC42" x="-16.51" y="-36.83" length="middle"/> +<pin name="NC43" x="-16.51" y="-39.37" length="middle"/> +<pin name="NC44" x="-16.51" y="-41.91" length="middle"/> +<pin name="NC45" x="-16.51" y="-44.45" length="middle"/> +<pin name="NC46" x="-16.51" y="-46.99" length="middle"/> +<pin name="NC47" x="-16.51" y="-49.53" length="middle"/> +<pin name="NC48" x="-16.51" y="-52.07" length="middle"/> +<pin name="NC50" x="-16.51" y="-54.61" length="middle"/> +<pin name="NC51" x="-16.51" y="-57.15" length="middle"/> +<pin name="NC52" x="-16.51" y="-59.69" length="middle"/> +<pin name="NC53" x="-16.51" y="-62.23" length="middle"/> +<pin name="NC54" x="-16.51" y="-64.77" length="middle"/> +<pin name="NC55" x="-16.51" y="-67.31" length="middle"/> +<pin name="NC56" x="-16.51" y="-69.85" length="middle"/> +<pin name="NC57" x="-16.51" y="-72.39" length="middle"/> +<pin name="NC58" x="-16.51" y="-74.93" length="middle"/> +<pin name="NC59" x="-16.51" y="-77.47" length="middle"/> +</symbol> +<symbol name="EP80-PCI"> +<wire x1="-10.16" y1="36.83" x2="13.97" y2="36.83" width="0.1524" layer="94"/> +<wire x1="13.97" y1="36.83" x2="13.97" y2="-82.55" width="0.1524" layer="94"/> +<wire x1="13.97" y1="-82.55" x2="-10.16" y2="-82.55" width="0.1524" layer="94"/> +<wire x1="-10.16" y1="-82.55" x2="-10.16" y2="36.83" width="0.1524" layer="94"/> +<wire x1="-9.8425" y1="36.5125" x2="13.6525" y2="36.5125" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="36.5125" x2="13.6525" y2="-82.2325" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="-82.2325" x2="-9.8425" y2="-82.2325" width="0.1524" layer="94"/> +<wire x1="-9.8425" y1="-82.2325" x2="-9.8425" y2="36.5125" width="0.1524" layer="94"/> +<text x="10.16" y="35.56" size="1.9304" layer="94" rot="R270">PCI - cf p1742</text> +<text x="17.145" y="-20.955" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="17.145" y="-82.55" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="PEA0_TP[0]" x="-15.24" y="34.29" length="middle"/> +<pin name="PEA0_TN[0]" x="-15.24" y="31.75" length="middle" function="dot"/> +<pin name="PEA0_RP[0]" x="-15.24" y="27.94" length="middle"/> +<pin name="PEA0_RN[0]" x="-15.24" y="25.4" length="middle" function="dot"/> +<pin name="PEA0_TP[1]" x="-15.24" y="21.59" length="middle"/> +<pin name="PEA0_TN[1]" x="-15.24" y="19.05" length="middle" function="dot"/> +<pin name="PEA0_RP[1]" x="-15.24" y="15.24" length="middle"/> +<pin name="PEA0_RN[1]" x="-15.24" y="12.7" length="middle" function="dot"/> +<pin name="PEA0_TP[2]" x="-15.24" y="8.89" length="middle"/> +<pin name="PEA0_TN[2]" x="-15.24" y="6.35" length="middle" function="dot"/> +<pin name="PEA0_RP[2]" x="-15.24" y="2.54" length="middle"/> +<pin name="PEA0_RN[2]" x="-15.24" y="0" length="middle" function="dot"/> +<pin name="PEA0_TP[3]" x="-15.24" y="-3.81" length="middle"/> +<pin name="PEA0_TN[3]" x="-15.24" y="-6.35" length="middle" function="dot"/> +<pin name="PEA0_RP[3]" x="-15.24" y="-10.16" length="middle"/> +<pin name="PEA0_RN[3]" x="-15.24" y="-12.7" length="middle" function="dot"/> +<pin name="PEA0_TP[4]" x="-15.24" y="-16.51" length="middle"/> +<pin name="PEA0_TN[4]" x="-15.24" y="-19.05" length="middle" function="dot"/> +<pin name="PEA0_RP[4]" x="-15.24" y="-22.86" length="middle"/> +<pin name="PEA0_RN[4]" x="-15.24" y="-25.4" length="middle" function="dot"/> +<pin name="PEA0_TP[5]" x="-15.24" y="-29.21" length="middle"/> +<pin name="PEA0_TN[5]" x="-15.24" y="-31.75" length="middle" function="dot"/> +<pin name="PEA0_RP[5]" x="-15.24" y="-35.56" length="middle"/> +<pin name="PEA0_RN[5]" x="-15.24" y="-38.1" length="middle" function="dot"/> +<pin name="PEA0_TP[6]" x="-15.24" y="-41.91" length="middle"/> +<pin name="PEA0_TN[6]" x="-15.24" y="-44.45" length="middle" function="dot"/> +<pin name="PEA0_RP[6]" x="-15.24" y="-48.26" length="middle"/> +<pin name="PEA0_RN[6]" x="-15.24" y="-50.8" length="middle" function="dot"/> +<pin name="PEA0_TP[7]" x="-15.24" y="-54.61" length="middle"/> +<pin name="PEA0_TN[7]" x="-15.24" y="-57.15" length="middle" function="dot"/> +<pin name="PEA0_RP[7]" x="-15.24" y="-60.96" length="middle"/> +<pin name="PEA0_RN[7]" x="-15.24" y="-63.5" length="middle" function="dot"/> +<pin name="PEA_CLKN" x="-15.24" y="-67.31" length="middle" function="dot"/> +<pin name="PEA_CLKP" x="-15.24" y="-71.12" length="middle"/> +<pin name="PEA_RCOMPO" x="-15.24" y="-80.01" length="middle"/> +<pin name="PEA_ICOMPI" x="-15.24" y="-74.93" length="middle"/> +<pin name="PEA_ICOMPO" x="-15.24" y="-77.47" length="middle"/> +</symbol> +<symbol name="EP80-POWERMANAGE"> +<wire x1="-11.43" y1="22.86" x2="12.7" y2="22.86" width="0.1524" layer="94"/> +<wire x1="12.7" y1="22.86" x2="12.7" y2="-29.21" width="0.1524" layer="94"/> +<wire x1="12.7" y1="-29.21" x2="-11.43" y2="-29.21" width="0.1524" layer="94"/> +<wire x1="-11.43" y1="-29.21" x2="-11.43" y2="22.86" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="22.5425" x2="12.3825" y2="22.5425" width="0.1524" layer="94"/> +<wire x1="12.3825" y1="22.5425" x2="12.3825" y2="-28.8925" width="0.1524" layer="94"/> +<wire x1="12.3825" y1="-28.8925" x2="-11.1125" y2="-28.8925" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="-28.8925" x2="-11.1125" y2="22.5425" width="0.1524" layer="94"/> +<text x="8.89" y="21.59" size="1.9304" layer="94" rot="R270">POWER MANAGER - cf p1756</text> +<text x="15.24" y="-5.715" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="15.24" y="-29.21" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="PLTRST_N" x="-16.51" y="20.32" length="middle" direction="out"/> +<pin name="PROCHOT_N" x="-16.51" y="16.51" length="middle" direction="out"/> +<pin name="THRMTRIP_N" x="-16.51" y="12.7" length="middle" direction="oc"/> +<pin name="SLP_S3_N" x="-16.51" y="8.89" length="middle" direction="out"/> +<pin name="SLP_S4_N" x="-16.51" y="6.35" length="middle" direction="out"/> +<pin name="SLP_S5_N" x="-16.51" y="3.81" length="middle" direction="out"/> +<pin name="PWROK" x="-16.51" y="0" length="middle" direction="in"/> +<pin name="PWRBTN_N" x="-16.51" y="-3.81" length="middle" direction="in"/> +<pin name="RI_N" x="-16.51" y="-7.62" length="middle" direction="in"/> +<pin name="SYS_RESET_N" x="-16.51" y="-11.43" length="middle" direction="in"/> +<pin name="RSMRST_N" x="-16.51" y="-15.24" length="middle" direction="in"/> +<pin name="SUS_STAT_N" x="-16.51" y="-19.05" length="middle" direction="out"/> +<pin name="SUSCLK" x="-16.51" y="-22.86" length="middle"/> +<pin name="VRMPWRGD" x="-16.51" y="-26.67" length="middle" direction="in"/> +</symbol> +<symbol name="EP80-RESERVED"> +<wire x1="-11.43" y1="17.78" x2="12.7" y2="17.78" width="0.1524" layer="94"/> +<wire x1="12.7" y1="17.78" x2="12.7" y2="-38.1" width="0.1524" layer="94"/> +<wire x1="12.7" y1="-38.1" x2="-11.43" y2="-38.1" width="0.1524" layer="94"/> +<wire x1="-11.43" y1="-38.1" x2="-11.43" y2="17.78" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="17.4625" x2="12.3825" y2="17.4625" width="0.1524" layer="94"/> +<wire x1="12.3825" y1="17.4625" x2="12.3825" y2="-37.7825" width="0.1524" layer="94"/> +<wire x1="12.3825" y1="-37.7825" x2="-11.1125" y2="-37.7825" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="-37.7825" x2="-11.1125" y2="17.4625" width="0.1524" layer="94"/> +<text x="8.89" y="16.51" size="1.9304" layer="94" rot="R270"> Reserved Pin List - cf p1770</text> +<text x="15.24" y="-13.335" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="15.24" y="-38.1" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="RESERVED0" x="-16.51" y="15.24" length="middle"/> +<pin name="RESERVED1" x="-16.51" y="12.7" length="middle"/> +<pin name="RESERVED2" x="-16.51" y="10.16" length="middle"/> +<pin name="RESERVED3" x="-16.51" y="7.62" length="middle"/> +<pin name="RESERVED4" x="-16.51" y="5.08" length="middle"/> +<pin name="RESERVED5" x="-16.51" y="2.54" length="middle"/> +<pin name="RESERVED6" x="-16.51" y="0" length="middle"/> +<pin name="RESERVED7" x="-16.51" y="-2.54" length="middle"/> +<pin name="RESERVED8" x="-16.51" y="-5.08" length="middle"/> +<pin name="RESERVED9" x="-16.51" y="-7.62" length="middle"/> +<pin name="RESERVED10" x="-16.51" y="-10.16" length="middle"/> +<pin name="RESERVED11" x="-16.51" y="-12.7" length="middle"/> +<pin name="RESERVED12" x="-16.51" y="-15.24" length="middle"/> +<pin name="RESERVED13" x="-16.51" y="-17.78" length="middle"/> +<pin name="RESERVED14" x="-16.51" y="-20.32" length="middle"/> +<pin name="RESERVED15" x="-16.51" y="-22.86" length="middle"/> +<pin name="RESERVED16" x="-16.51" y="-25.4" length="middle"/> +<pin name="RESERVED17" x="-16.51" y="-27.94" length="middle"/> +<pin name="RESERVED18" x="-16.51" y="-30.48" length="middle"/> +<pin name="RESERVED19" x="-16.51" y="-33.02" length="middle"/> +<pin name="RESERVED20" x="-16.51" y="-35.56" length="middle"/> +</symbol> +<symbol name="EP80-SBUS"> +<wire x1="-13.97" y1="19.05" x2="24.13" y2="19.05" width="0.1524" layer="94"/> +<wire x1="24.13" y1="19.05" x2="24.13" y2="-44.45" width="0.1524" layer="94"/> +<wire x1="24.13" y1="-44.45" x2="-13.97" y2="-44.45" width="0.1524" layer="94"/> +<wire x1="-13.97" y1="-44.45" x2="-13.97" y2="19.05" width="0.1524" layer="94"/> +<wire x1="-13.6525" y1="18.7325" x2="23.8125" y2="18.7325" width="0.1524" layer="94"/> +<wire x1="23.8125" y1="18.7325" x2="23.8125" y2="-44.1325" width="0.1524" layer="94"/> +<wire x1="23.8125" y1="-44.1325" x2="-13.6525" y2="-44.1325" width="0.1524" layer="94"/> +<wire x1="-13.6525" y1="-44.1325" x2="-13.6525" y2="18.7325" width="0.1524" layer="94"/> +<text x="-12.7" y="15.24" size="1.6764" layer="94">SMBUS - cf p1750</text> +<text x="-12.7" y="-32.385" size="1.6764" layer="94">SPI - cf p1749</text> +<text x="-12.7" y="-15.24" size="1.6764" layer="94">SSP Interface - cf p1768</text> +<text x="-1.27" y="7.62" size="1.6764" layer="94">USB - cf p1755</text> +<text x="-13.335" y="-47.625" size="1.778" layer="96">>VALUE</text> +<text x="-13.97" y="19.685" size="1.778" layer="95">>NAME</text> +<pin name="SMBDATA" x="-19.05" y="12.7" length="middle" direction="oc"/> +<pin name="INTRUDER_N" x="-19.05" y="-1.27" length="middle" direction="in"/> +<pin name="SMBCLK" x="-19.05" y="8.89" length="middle" direction="oc" function="clk"/> +<pin name="GP11_SMBALERT_N" x="-19.05" y="-11.43" length="middle" direction="in"/> +<pin name="SMLINK[0]" x="-19.05" y="5.08" length="middle" direction="oc"/> +<pin name="SMBSDA" x="-19.05" y="-5.08" length="middle" direction="oc"/> +<pin name="SMBSCL" x="-19.05" y="-7.62" length="middle" direction="oc"/> +<pin name="SMLINK[1]" x="-19.05" y="2.54" length="middle" direction="oc"/> +<pin name="SPI_SCLK" x="-19.05" y="-41.91" length="middle" direction="out"/> +<pin name="SPI_MOSI" x="-19.05" y="-36.83" length="middle" direction="out"/> +<pin name="SPI_CS_N" x="-19.05" y="-39.37" length="middle" direction="out"/> +<pin name="SPI_MISO" x="-19.05" y="-34.29" length="middle" direction="in"/> +<pin name="SSP_SCLK" x="-19.05" y="-19.05" length="middle" direction="out" function="clk"/> +<pin name="SSP_SFRM" x="-19.05" y="-21.59" length="middle" direction="out"/> +<pin name="SSP_TXD" x="-19.05" y="-24.13" length="middle" direction="out"/> +<pin name="SSP_RXD" x="-19.05" y="-26.67" length="middle" direction="in"/> +<pin name="SSP_EXTCLK" x="-19.05" y="-16.51" length="middle" direction="in" function="clk"/> +<pin name="USBP0" x="29.21" y="5.08" length="middle" rot="R180"/> +<pin name="USBN1" x="29.21" y="-3.81" length="middle" function="dot" rot="R180"/> +<pin name="USBN0" x="29.21" y="2.54" length="middle" function="dot" rot="R180"/> +<pin name="USBP1" x="29.21" y="-1.27" length="middle" rot="R180"/> +<pin name="OC[1]_N" x="29.21" y="-7.62" length="middle" direction="in" rot="R180"/> +<pin name="OC[0]_N" x="29.21" y="-10.16" length="middle" direction="in" function="dot" rot="R180"/> +<pin name="USB_RBIASP" x="29.21" y="-19.05" length="middle" direction="out" rot="R180"/> +<pin name="USB_RBIASN" x="29.21" y="-22.86" length="middle" direction="in" function="dot" rot="R180"/> +<pin name="CLK48" x="29.21" y="-29.21" length="middle" direction="in" function="dotclk" rot="R180"/> +</symbol> +<symbol name="EP80-TDM"> +<wire x1="-12.7" y1="21.59" x2="13.97" y2="21.59" width="0.1524" layer="94"/> +<wire x1="13.97" y1="21.59" x2="13.97" y2="-40.64" width="0.1524" layer="94"/> +<wire x1="13.97" y1="-40.64" x2="-12.7" y2="-40.64" width="0.1524" layer="94"/> +<wire x1="-12.7" y1="-40.64" x2="-12.7" y2="21.59" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="21.2725" x2="13.6525" y2="21.2725" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="21.2725" x2="13.6525" y2="-40.3225" width="0.1524" layer="94"/> +<wire x1="13.6525" y1="-40.3225" x2="-12.3825" y2="-40.3225" width="0.1524" layer="94"/> +<wire x1="-12.3825" y1="-40.3225" x2="-12.3825" y2="21.2725" width="0.1524" layer="94"/> +<text x="10.16" y="20.32" size="1.9304" layer="94" rot="R270">TDM - cf p1764</text> +<text x="-12.7" y="-43.18" size="1.778" layer="96">>VALUE</text> +<text x="-12.7" y="22.225" size="1.778" layer="95">>NAME</text> +<pin name="RX_CLK0" x="-17.78" y="19.05" length="middle" function="clk"/> +<pin name="TX_CLK0" x="-17.78" y="8.89" length="middle"/> +<pin name="TX_FRAME0" x="-17.78" y="-11.43" length="middle"/> +<pin name="TX_DATA_OUT0" x="-17.78" y="-31.75" length="middle" direction="out"/> +<pin name="RX_FRAME0" x="-17.78" y="-1.27" length="middle"/> +<pin name="RX_DATA_IN0" x="-17.78" y="-21.59" length="middle" direction="in"/> +<pin name="RX_CLK1" x="-17.78" y="16.51" length="middle" function="clk"/> +<pin name="TX_CLK1" x="-17.78" y="6.35" length="middle"/> +<pin name="TX_FRAME1" x="-17.78" y="-13.97" length="middle"/> +<pin name="TX_DATA_OUT1" x="-17.78" y="-34.29" length="middle" direction="out"/> +<pin name="RX_FRAME1" x="-17.78" y="-3.81" length="middle"/> +<pin name="RX_DATA_IN1" x="-17.78" y="-24.13" length="middle" direction="in"/> +<pin name="RX_CLK2" x="-17.78" y="13.97" length="middle" function="clk"/> +<pin name="TX_CLK2" x="-17.78" y="3.81" length="middle"/> +<pin name="TX_FRAME2" x="-17.78" y="-16.51" length="middle"/> +<pin name="TX_DATA_OUT2" x="-17.78" y="-36.83" length="middle" direction="out"/> +<pin name="RX_FRAME2" x="-17.78" y="-6.35" length="middle"/> +<pin name="RX_DATA_IN2" x="-17.78" y="-26.67" length="middle" direction="in"/> +</symbol> +<symbol name="EP80-UART"> +<wire x1="-11.43" y1="27.94" x2="10.16" y2="27.94" width="0.1524" layer="94"/> +<wire x1="10.16" y1="27.94" x2="10.16" y2="-20.32" width="0.1524" layer="94"/> +<wire x1="10.16" y1="-20.32" x2="-11.43" y2="-20.32" width="0.1524" layer="94"/> +<wire x1="-11.43" y1="-20.32" x2="-11.43" y2="27.94" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="27.6225" x2="9.8425" y2="27.6225" width="0.1524" layer="94"/> +<wire x1="9.8425" y1="27.6225" x2="9.8425" y2="-20.0025" width="0.1524" layer="94"/> +<wire x1="9.8425" y1="-20.0025" x2="-11.1125" y2="-20.0025" width="0.1524" layer="94"/> +<wire x1="-11.1125" y1="-20.0025" x2="-11.1125" y2="27.6225" width="0.1524" layer="94"/> +<text x="6.35" y="26.67" size="1.9304" layer="94" rot="R270">UART - cf p1750</text> +<text x="12.7" y="0.635" size="1.778" layer="96" rot="R90">>VALUE</text> +<text x="12.7" y="-20.32" size="1.778" layer="95" rot="R90">>NAME</text> +<pin name="SIU_CTS1#" x="-16.51" y="17.78" length="middle"/> +<pin name="SIU_DCD2#" x="-16.51" y="0" length="middle"/> +<pin name="SIU_CTS2#" x="-16.51" y="-7.62" length="middle"/> +<pin name="SIU_DCD1#" x="-16.51" y="25.4" length="middle"/> +<pin name="SIU_DSR1#" x="-16.51" y="22.86" length="middle"/> +<pin name="SIU_DSR2#" x="-16.51" y="-2.54" length="middle"/> +<pin name="SIU_DTR1#" x="-16.51" y="7.62" length="middle"/> +<pin name="SIU_DTR2#" x="-16.51" y="-17.78" length="middle"/> +<pin name="SIU_RXD2" x="-16.51" y="-5.08" length="middle"/> +<pin name="SIU_TXD1" x="-16.51" y="10.16" length="middle"/> +<pin name="SIU_RI2#" x="-16.51" y="-10.16" length="middle"/> +<pin name="SIU_RI1#" x="-16.51" y="15.24" length="middle"/> +<pin name="SIU_RXD1" x="-16.51" y="20.32" length="middle"/> +<pin name="SIU_RTS1#" x="-16.51" y="12.7" length="middle"/> +<pin name="SIU_RTS2#" x="-16.51" y="-12.7" length="middle"/> +<pin name="SIU_TXD2" x="-16.51" y="-15.24" length="middle"/> +<pin name="UART_CLK" x="-16.51" y="3.81" length="middle" direction="in" function="clk"/> +</symbol> +<symbol name="M881141-CORE"> +<wire x1="-24.13" y1="-19.05" x2="15.24" y2="-19.05" width="0.4064" layer="94"/> +<wire x1="15.24" y1="11.43" x2="15.24" y2="-19.05" width="0.4064" layer="94"/> +<wire x1="15.24" y1="11.43" x2="-24.13" y2="11.43" width="0.4064" layer="94"/> +<wire x1="-24.13" y1="-19.05" x2="-24.13" y2="11.43" width="0.4064" layer="94"/> +<text x="-5.08" y="12.7" size="1.778" layer="96">>VALUE</text> +<text x="-24.13" y="12.7" size="1.778" layer="95">>NAME</text> +<text x="1.27" y="-2.54" size="2.54" layer="94" rot="R180">Core</text> +<text x="6.35" y="3.81" size="2.54" layer="94" rot="R180">M881141</text> +<pin name="125CLK" x="20.32" y="8.89" length="middle" direction="out" rot="R180"/> +<pin name="NC@2" x="20.32" y="-11.43" length="middle" direction="out" rot="R180"/> +<pin name="NC@1" x="20.32" y="-13.97" length="middle" direction="out" rot="R180"/> +<pin name="NC@3" x="20.32" y="-16.51" length="middle" direction="out" rot="R180"/> +<pin name="GCONFIG0" x="-29.21" y="0" length="middle" direction="in"/> +<pin name="GCONFIG1" x="-29.21" y="-7.62" length="middle" direction="in"/> +<pin name="RESETN" x="-29.21" y="-12.7" length="middle" direction="in"/> +<pin name="SEL_25V" x="-29.21" y="5.08" length="middle" direction="in"/> +<pin name="SEL_CLK" x="-29.21" y="8.89" length="middle" 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name="P2.4/TA2/A4/VREF+/VEREF+" x="-27.94" y="-10.16" length="middle"/> +<pin name="AVCC" x="-27.94" y="11.43" length="middle" direction="in"/> +<pin name="AVSS" x="-27.94" y="6.35" length="middle" direction="in"/> +</symbol> +<symbol name="MSP430F22X2_TIMERUARTPORT3PORT4"> +<wire x1="27.94" y1="13.335" x2="27.94" y2="-13.335" width="0.4064" layer="94"/> +<wire x1="-24.13" y1="-13.335" x2="27.94" y2="-13.335" width="0.4064" layer="94"/> +<wire x1="-24.13" y1="-13.335" x2="-24.13" y2="13.335" width="0.4064" layer="94"/> +<wire x1="27.94" y1="13.335" x2="-24.13" y2="13.335" width="0.4064" layer="94"/> +<text x="-23.495" y="13.97" size="1.778" layer="95">>NAME</text> +<text x="1.27" y="13.97" size="1.778" layer="96">>VALUE</text> +<text x="-7.62" y="10.795" size="1.778" layer="94">MSP430F22x2</text> +<text x="-16.51" y="8.255" size="1.778" layer="94">Timer & Uart & Port 3 & Port4</text> +<pin name="P3.0/UCB0STE.UCA0CLK/A5" x="-29.21" y="6.35" length="middle"/> +<pin name="P3.1/UCB0SIMO/UCB0SDA" x="-29.21" y="3.81" length="middle"/> +<pin name="P3.2/UCBOSOMI/UCB0SCL" x="-29.21" y="1.27" length="middle"/> +<pin name="P3.3/UCB0CLK/UCA0STE" x="-29.21" y="-1.27" length="middle"/> +<pin name="P4.0/TB0" x="33.02" y="6.35" length="middle" rot="R180"/> +<pin name="P4.1/TB1" x="33.02" y="3.81" length="middle" rot="R180"/> +<pin name="P4.2/TB2" x="33.02" y="1.27" length="middle" rot="R180"/> +<pin name="P4.3/TBO/A12" x="33.02" y="-1.27" length="middle" rot="R180"/> +<pin name="P4.4/TB1/A13" x="33.02" y="-3.81" length="middle" rot="R180"/> +<pin name="P4.5/TB2/A14" x="33.02" y="-6.35" length="middle" rot="R180"/> +<pin name="P4.6/TBOUTH/A15" x="33.02" y="-8.89" length="middle" rot="R180"/> +<pin name="P4.7/TBCLK" x="33.02" y="-11.43" length="middle" rot="R180"/> +<pin name="P3.4/UCA0TXD/UCA0SIMO" x="-29.21" y="-3.81" length="middle"/> +<pin name="P3.5/UCA0RXD/UCA0SOMI" x="-29.21" y="-6.35" length="middle"/> +<pin name="P3.6/A6" x="-29.21" y="-8.89" length="middle"/> +<pin name="P3.7/A7" x="-29.21" y="-11.43" length="middle"/> +</symbol> +<symbol name="VREG_TPS76XX"> +<wire x1="-6.35" y1="-6.35" x2="7.62" y2="-6.35" width="0.4064" layer="94"/> +<wire x1="7.62" y1="-6.35" x2="7.62" y2="5.08" width="0.4064" layer="94"/> +<wire x1="7.62" y1="5.08" x2="-6.35" y2="5.08" width="0.4064" layer="94"/> +<wire x1="-6.35" y1="5.08" x2="-6.35" y2="-6.35" width="0.4064" layer="94"/> +<text x="2.54" y="-8.89" size="1.778" layer="95">>NAME</text> +<text x="2.54" y="-11.43" size="1.778" layer="96">>VALUE</text> +<text x="-3.302" y="-5.588" size="1.524" layer="95">DGND</text> +<text x="-5.08" y="2.54" size="1.524" layer="95">IN</text> +<text x="1.27" y="2.54" size="1.524" layer="95">OUT</text> +<text x="-5.08" y="-2.54" size="1.524" layer="95">EN</text> +<text x="0" y="-2.54" size="1.524" layer="95">NC/FB</text> +<pin name="IN" x="-8.89" y="2.54" visible="pad" length="short" direction="in"/> +<pin name="DGND" x="0" y="-13.97" visible="pad" direction="in" rot="R90"/> +<pin name="OUT" x="10.16" y="2.54" visible="pad" length="short" direction="pas" rot="R180"/> +<pin name="EN" x="-8.89" y="-2.54" visible="pad" length="short" direction="in"/> +<pin name="NC/FB" x="10.16" y="-2.54" visible="pad" length="short" direction="pas" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="V1P8-DDR" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="V1P8_DDR" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="DDR2-VTT" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="DDR2-VTT" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVDD"> +<gates> +<gate name="G$1" symbol="AVDD" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="SST25VF016" prefix="U" uservalue="yes"> +<gates> +<gate name="AT26" symbol="SERIALFLASH" x="1.27" y="0"/> +</gates> +<devices> +<device name="SMSOIC8" package="SMSOIC8"> +<connects> +<connect gate="AT26" pin="CE" pad="1"/> +<connect gate="AT26" pin="GND" pad="4"/> +<connect gate="AT26" pin="H" pad="7"/> +<connect gate="AT26" pin="SCK" pad="6"/> +<connect gate="AT26" pin="SI" pad="5"/> +<connect gate="AT26" pin="SO" pad="2"/> +<connect gate="AT26" pin="VCC" pad="8"/> +<connect gate="AT26" pin="WP" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="74HC374" uservalue="yes"> +<description>ON SEMICONDUCTOR +MC74HC374ADTG + +Ref Farnell 1104725</description> +<gates> +<gate name="P" symbol="PWRN" x="-45.72" y="2.54" addlevel="must"/> +<gate name="G" symbol="74374" x="-3.81" y="-3.81"/> +</gates> +<devices> +<device name="" package="TSSOP20"> +<connects> +<connect gate="G" pin="CLK" pad="11"/> +<connect gate="G" pin="D0" pad="3"/> +<connect gate="G" pin="D1" pad="4"/> +<connect gate="G" pin="D2" pad="7"/> +<connect gate="G" pin="D3" pad="8"/> +<connect gate="G" pin="D4" pad="13"/> +<connect gate="G" pin="D5" pad="14"/> +<connect gate="G" pin="D6" pad="17"/> +<connect gate="G" pin="D7" pad="18"/> +<connect gate="G" pin="OC" pad="1"/> +<connect gate="G" pin="Q0" pad="2"/> +<connect gate="G" pin="Q1" pad="5"/> +<connect gate="G" pin="Q2" pad="6"/> +<connect gate="G" pin="Q3" pad="9"/> +<connect gate="G" pin="Q4" pad="12"/> +<connect gate="G" pin="Q5" pad="15"/> +<connect gate="G" pin="Q6" pad="16"/> +<connect gate="G" pin="Q7" pad="19"/> +<connect gate="P" pin="GND" pad="10"/> +<connect gate="P" pin="VCC" pad="20"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="OR-2-74AHC1G32" prefix="U" uservalue="yes"> +<description>Fabricant: DIODES INC. +Code commande: 1845209 +Référence fabricant: 74LVC1G32SE-7 + +Conformité RoHS : Conforme RoHS Oui + +Description + + * LOGIC, POS OR, SINGLE, 2 IP, SOT353 + * Type de logique:OU + * Courant, sortie:32mA + * Nombre d'entrées:2 + * Gamme de tension d'alimentation:1.65V à 5.5V + * Type de boîtier CI logique:SOT-353 + * Nombre de broches:5 + * Température de fonctionnement:-40°C to +150°C + + +OR + + + +Fabricant: NXP +Code commande: 1085242 +Référence fabricant: 74AHC1G32GW/T1 + +Conformité RoHS : Conforme RoHS Oui + +Description + + * CIRCUIT LOGIQUE SERIE 74AHC CMS + * Type de logique:Porte OU + * Courant, sortie:8mA + * Nombre d'entrées:2 + * Gamme de tension d'alimentation:2V à 5.5V + * Type de boîtier CI logique:SOT-353 + * Nombre de broches:5 + * Température de fonctionnement:-40°C à +125°C + * SVHC:No SVHC (18-Jun-2010) + * Type de boîtier:CMS + * Courant, sortie max.:8mA + * Famille Circuit logique:AHC + * Fonction logique:2 entrées positives porte OU + * Nombre de portes:1 + * Numéro de base de la fonction logique:74132 + * Numéro de la fonction logique:32 + * Numéro générique:74AHC1G32 + * Racine de la référence:74 + * Température de fonctionnement max.:125°C + * Température de fonctionnement min.:-40°C + * Tension, alimentation:5V + * Tension, alimentation maxi:5.5V</description> +<gates> +<gate name="P" symbol="PWRN" x="-25.4" y="1.27"/> +<gate name="G" symbol="OR-2" x="0" y="0"/> +</gates> +<devices> +<device name="SC70-5L" package="SC70-5L"> +<connects> +<connect gate="G" pin="A" pad="2"/> +<connect gate="G" pin="B" pad="1"/> +<connect gate="G" pin="Y" pad="4"/> +<connect gate="P" pin="GND" pad="3"/> +<connect gate="P" pin="VCC" pad="5"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="M881141" uservalue="yes"> +<gates> +<gate name="PW1/2" symbol="M88E1141-PWR-1/2" x="25.4" y="34.29" addlevel="must"/> +<gate name="PW2/2" symbol="M88E1141-PWR-2/2" x="22.86" y="-1.27"/> +<gate name="CORE" symbol="M881141-CORE" x="143.51" y="30.48"/> +<gate name="GB0" symbol="M881141-GB0" x="-11.43" y="-68.58" addlevel="request"/> +<gate name="GB1" symbol="M881141-GB1" x="29.21" y="-78.74" addlevel="request"/> +<gate name="GB2" symbol="M881141-GB2" x="86.36" y="-78.74" addlevel="request"/> +<gate name="GB3" symbol="M881141-GB3" x="140.97" y="-78.74" addlevel="request"/> +</gates> +<devices> +<device name="HSBGA-388" package="388HSBGA"> +<connects> +<connect gate="CORE" pin="125CLK" pad="Y1"/> +<connect gate="CORE" pin="GCONFIG0" pad="AC23"/> +<connect gate="CORE" pin="GCONFIG1" pad="AC25"/> +<connect gate="CORE" pin="NC@1" pad="AC7"/> +<connect gate="CORE" pin="NC@2" pad="AC15"/> +<connect gate="CORE" pin="NC@3" pad="AD15"/> +<connect gate="CORE" pin="RESETN" pad="AA4"/> +<connect gate="CORE" pin="SEL_25V" pad="C14"/> +<connect gate="CORE" pin="SEL_CLK" pad="AE23"/> +<connect gate="CORE" pin="TCK" pad="AB2"/> +<connect gate="CORE" pin="TDI" pad="AA2"/> +<connect gate="CORE" pin="TDO" pad="AA3"/> +<connect gate="CORE" pin="TMS" pad="AB3"/> +<connect gate="CORE" pin="TRSTN" pad="AA1"/> +<connect gate="CORE" pin="VSSC" pad="AF23"/> +<connect gate="CORE" pin="XTAL1" pad="AC26"/> +<connect gate="CORE" pin="XTAL2" pad="AD26"/> +<connect gate="GB0" pin="P0_COL" pad="T1"/> +<connect gate="GB0" pin="P0_CONFIG0" pad="U26"/> +<connect gate="GB0" pin="P0_CONFIG1" pad="U25"/> +<connect gate="GB0" pin="P0_CONFIG2" pad="U24"/> +<connect gate="GB0" pin="P0_CONFIG3" pad="V26"/> +<connect gate="GB0" pin="P0_CONFIG4" pad="V25"/> +<connect gate="GB0" pin="P0_CRS" pad="T2"/> +<connect gate="GB0" pin="P0_DUPLEX" pad="K25"/> +<connect gate="GB0" pin="P0_GTX_CLK" pad="M1"/> +<connect gate="GB0" pin="P0_HSDAC+" pad="AE5"/> +<connect gate="GB0" pin="P0_HSDAC-" pad="AF5"/> +<connect gate="GB0" pin="P0_INTN" pad="Y3"/> +<connect gate="GB0" pin="P0_LED_RX" pad="K26"/> +<connect gate="GB0" pin="P0_LED_TX" pad="L24"/> +<connect gate="GB0" pin="P0_LINK10" pad="J25"/> +<connect gate="GB0" pin="P0_LINK100" pad="J26"/> +<connect gate="GB0" pin="P0_LINK1000" pad="K24"/> +<connect gate="GB0" pin="P0_MDC" pad="W1"/> +<connect gate="GB0" pin="P0_MDIO" pad="Y2"/> +<connect gate="GB0" pin="P0_MDI[0]+" pad="AE3"/> +<connect gate="GB0" pin="P0_MDI[0]-" pad="AF3"/> +<connect gate="GB0" pin="P0_MDI[1]+" pad="AE4"/> +<connect gate="GB0" pin="P0_MDI[1]-" pad="AF4"/> +<connect gate="GB0" pin="P0_MDI[2]+" pad="AE6"/> +<connect gate="GB0" pin="P0_MDI[2]-" pad="AF6"/> +<connect gate="GB0" pin="P0_MDI[3]+" pad="AE7"/> +<connect gate="GB0" pin="P0_MDI[3]-" pad="AF7"/> +<connect gate="GB0" pin="P0_RSET" pad="AB1"/> +<connect gate="GB0" pin="P0_RXD[0]" pad="T3"/> +<connect gate="GB0" pin="P0_RXD[1]" pad="R1"/> +<connect gate="GB0" pin="P0_RXD[2]" pad="R2"/> +<connect gate="GB0" pin="P0_RXD[3]" pad="R3"/> +<connect gate="GB0" pin="P0_RXD[4]" pad="P1"/> +<connect gate="GB0" pin="P0_RXD[5]" pad="P2"/> +<connect gate="GB0" pin="P0_RXD[6]" pad="P3"/> +<connect gate="GB0" pin="P0_RXD[7]" pad="N2"/> +<connect gate="GB0" pin="P0_RX_CLK" pad="N1"/> +<connect gate="GB0" pin="P0_RX_DV" pad="N3"/> +<connect gate="GB0" pin="P0_RX_ER" pad="N4"/> +<connect gate="GB0" pin="P0_S_CLK+" pad="D7"/> +<connect gate="GB0" pin="P0_S_CLK-" pad="C7"/> +<connect gate="GB0" pin="P0_S_IN+" pad="B6"/> +<connect gate="GB0" pin="P0_S_IN-" pad="A6"/> +<connect gate="GB0" pin="P0_S_OUT+" pad="B7"/> +<connect gate="GB0" pin="P0_S_OUT-" pad="A7"/> +<connect gate="GB0" pin="P0_TSTPT" pad="AC10"/> +<connect gate="GB0" pin="P0_TXD[0]" pad="M3"/> +<connect gate="GB0" pin="P0_TXD[1]" pad="L1"/> +<connect gate="GB0" pin="P0_TXD[2]" pad="L2"/> +<connect gate="GB0" pin="P0_TXD[3]" pad="L3"/> +<connect gate="GB0" pin="P0_TXD[4]" pad="K1"/> +<connect gate="GB0" pin="P0_TXD[5]" pad="K2"/> +<connect gate="GB0" pin="P0_TXD[6]" pad="K3"/> +<connect gate="GB0" pin="P0_TXD[7]" pad="J1"/> +<connect gate="GB0" pin="P0_TX_CLK" pad="M2"/> +<connect gate="GB0" pin="P0_TX_EN" pad="J2"/> +<connect gate="GB0" pin="P0_TX_ER" pad="J3"/> +<connect gate="GB1" pin="P1_COL" pad="H1"/> +<connect gate="GB1" pin="P1_CONFIG0" pad="V24"/> +<connect gate="GB1" pin="P1_CONFIG1" pad="V23"/> +<connect gate="GB1" pin="P1_CONFIG2" pad="W26"/> +<connect gate="GB1" pin="P1_CONFIG3" pad="W25"/> +<connect gate="GB1" pin="P1_CONFIG4" pad="Y24"/> +<connect gate="GB1" pin="P1_CRS" pad="H2"/> +<connect gate="GB1" pin="P1_DUPLEX" pad="M25"/> +<connect gate="GB1" pin="P1_GTX_CLK" pad="E1"/> +<connect gate="GB1" pin="P1_HSDAC+" pad="AF10"/> +<connect gate="GB1" pin="P1_HSDAC-" pad="AE10"/> +<connect gate="GB1" pin="P1_INTN" pad="V4"/> +<connect gate="GB1" pin="P1_LED_RX" pad="M26"/> +<connect gate="GB1" pin="P1_LED_TX" pad="N23"/> +<connect gate="GB1" pin="P1_LINK10" pad="L25"/> +<connect gate="GB1" pin="P1_LINK100" pad="L26"/> +<connect gate="GB1" pin="P1_LINK1000" pad="M24"/> +<connect gate="GB1" pin="P1_MDC" pad="V1"/> +<connect gate="GB1" pin="P1_MDIO" pad="W3"/> +<connect gate="GB1" pin="P1_MDI[0]+" pad="AF12"/> +<connect gate="GB1" pin="P1_MDI[0]-" pad="AE12"/> +<connect gate="GB1" pin="P1_MDI[1]+" pad="AF11"/> +<connect gate="GB1" pin="P1_MDI[1]-" pad="AE11"/> +<connect gate="GB1" pin="P1_MDI[2]+" pad="AF9"/> +<connect gate="GB1" pin="P1_MDI[2]-" pad="AE9"/> +<connect gate="GB1" pin="P1_MDI[3]+" pad="AF8"/> +<connect gate="GB1" pin="P1_MDI[3]-" pad="AE8"/> +<connect gate="GB1" pin="P1_RSET" pad="AC13"/> +<connect gate="GB1" pin="P1_RXD[0]" pad="H3"/> +<connect gate="GB1" pin="P1_RXD[1]" pad="G1"/> +<connect gate="GB1" pin="P1_RXD[2]" pad="G2"/> +<connect gate="GB1" pin="P1_RXD[3]" pad="G3"/> +<connect gate="GB1" pin="P1_RXD[4]" pad="F1"/> +<connect gate="GB1" pin="P1_RXD[5]" pad="F2"/> +<connect gate="GB1" pin="P1_RXD[6]" pad="F3"/> +<connect gate="GB1" pin="P1_RXD[7]" pad="F4"/> +<connect gate="GB1" pin="P1_RX_CLK" pad="E2"/> +<connect gate="GB1" pin="P1_RX_DV" pad="E3"/> +<connect gate="GB1" pin="P1_RX_ER" pad="E4"/> +<connect gate="GB1" pin="P1_S_CLK+" pad="D9"/> +<connect gate="GB1" pin="P1_S_CLK-" pad="C9"/> +<connect gate="GB1" pin="P1_S_IN+" pad="A9"/> +<connect gate="GB1" pin="P1_S_IN-" pad="B9"/> +<connect gate="GB1" pin="P1_S_OUT+" pad="A8"/> +<connect gate="GB1" pin="P1_S_OUT-" pad="B8"/> +<connect gate="GB1" pin="P1_TSTPT" pad="AD10"/> +<connect gate="GB1" pin="P1_TXD[0]" pad="D2"/> +<connect gate="GB1" pin="P1_TXD[1]" pad="D3"/> +<connect gate="GB1" pin="P1_TXD[2]" pad="D4"/> +<connect gate="GB1" pin="P1_TXD[3]" pad="C4"/> +<connect gate="GB1" pin="P1_TXD[4]" pad="B4"/> +<connect gate="GB1" pin="P1_TXD[5]" pad="A4"/> +<connect gate="GB1" pin="P1_TXD[6]" pad="C5"/> +<connect gate="GB1" pin="P1_TXD[7]" pad="B5"/> +<connect gate="GB1" pin="P1_TX_CLK" pad="D1"/> +<connect gate="GB1" pin="P1_TX_EN" pad="A5"/> +<connect gate="GB1" pin="P1_TX_ER" pad="D10"/> +<connect gate="GB2" pin="P2_COL" pad="A10"/> +<connect gate="GB2" pin="P2_CONFIG0" pad="Y23"/> +<connect gate="GB2" pin="P2_CONFIG1" pad="Y26"/> +<connect gate="GB2" pin="P2_CONFIG2" pad="Y25"/> +<connect gate="GB2" pin="P2_CONFIG3" pad="AA24"/> +<connect gate="GB2" pin="P2_CONFIG4" pad="AA26"/> +<connect gate="GB2" pin="P2_CRS" pad="C10"/> +<connect gate="GB2" pin="P2_DUPLEX" pad="P24"/> +<connect gate="GB2" pin="P2_GTX_CLK" pad="A14"/> +<connect gate="GB2" pin="P2_HSDAC+" pad="AE15"/> +<connect gate="GB2" pin="P2_HSDAC-" pad="AF15"/> +<connect gate="GB2" pin="P2_INTN" pad="V3"/> +<connect gate="GB2" pin="P2_LED_RX" pad="P25"/> +<connect gate="GB2" pin="P2_LED_TX" pad="P26"/> +<connect gate="GB2" pin="P2_LINK10" pad="N24"/> +<connect gate="GB2" pin="P2_LINK100" pad="N25"/> +<connect gate="GB2" pin="P2_LINK1000" pad="N26"/> +<connect gate="GB2" pin="P2_MDC" pad="W2"/> +<connect gate="GB2" pin="P2_MDIO" pad="V2"/> +<connect gate="GB2" pin="P2_MDI[0]+" pad="AE13"/> +<connect gate="GB2" pin="P2_MDI[0]-" pad="AF13"/> +<connect gate="GB2" pin="P2_MDI[1]+" pad="AE14"/> +<connect gate="GB2" pin="P2_MDI[1]-" pad="AF14"/> +<connect gate="GB2" pin="P2_MDI[2]+" pad="AE16"/> +<connect gate="GB2" pin="P2_MDI[2]-" pad="AF16"/> +<connect gate="GB2" pin="P2_MDI[3]+" pad="AE17"/> +<connect gate="GB2" pin="P2_MDI[3]-" pad="AF17"/> +<connect gate="GB2" pin="P2_RSET" pad="AD13"/> +<connect gate="GB2" pin="P2_RXD[0]" pad="B10"/> +<connect gate="GB2" pin="P2_RXD[1]" pad="D11"/> +<connect gate="GB2" pin="P2_RXD[2]" pad="C11"/> +<connect gate="GB2" pin="P2_RXD[3]" pad="B11"/> +<connect gate="GB2" pin="P2_RXD[4]" pad="A11"/> +<connect gate="GB2" pin="P2_RXD[5]" pad="D12"/> +<connect gate="GB2" pin="P2_RXD[6]" pad="C12"/> +<connect gate="GB2" pin="P2_RXD[7]" pad="B12"/> +<connect gate="GB2" pin="P2_RX_CLK" pad="A13"/> +<connect gate="GB2" pin="P2_RX_DV" pad="A12"/> +<connect gate="GB2" pin="P2_RX_ER" pad="B13"/> +<connect gate="GB2" pin="P2_S_CLK+" pad="C18"/> +<connect gate="GB2" pin="P2_S_CLK-" pad="D18"/> +<connect gate="GB2" pin="P2_S_IN+" pad="A18"/> +<connect gate="GB2" pin="P2_S_IN-" pad="B18"/> +<connect gate="GB2" pin="P2_S_OUT+" pad="A19"/> +<connect gate="GB2" pin="P2_S_OUT-" pad="B19"/> +<connect gate="GB2" pin="P2_TSTPT" pad="AD17"/> +<connect gate="GB2" pin="P2_TXD[0]" pad="D14"/> +<connect gate="GB2" pin="P2_TXD[1]" pad="A15"/> +<connect gate="GB2" pin="P2_TXD[2]" pad="B15"/> +<connect gate="GB2" pin="P2_TXD[3]" pad="A16"/> +<connect gate="GB2" pin="P2_TXD[4]" pad="B16"/> +<connect gate="GB2" pin="P2_TXD[5]" pad="C16"/> +<connect gate="GB2" pin="P2_TXD[6]" pad="D16"/> +<connect gate="GB2" pin="P2_TXD[7]" pad="A17"/> +<connect gate="GB2" pin="P2_TX_CLK" pad="B14"/> +<connect gate="GB2" pin="P2_TX_EN" pad="B17"/> +<connect gate="GB2" pin="P2_TX_ER" pad="C19"/> +<connect gate="GB3" pin="P3_COL" pad="A22"/> +<connect gate="GB3" pin="P3_CONFIG0" pad="AA25"/> +<connect gate="GB3" pin="P3_CONFIG1" pad="AB24"/> +<connect gate="GB3" pin="P3_CONFIG2" pad="AB26"/> +<connect gate="GB3" pin="P3_CONFIG3" pad="AB25"/> +<connect gate="GB3" pin="P3_CONFIG4" pad="AC24"/> +<connect gate="GB3" pin="P3_CRS" pad="D19"/> +<connect gate="GB3" pin="P3_DUPLEX" pad="T26"/> +<connect gate="GB3" pin="P3_GTX_CLK" pad="F23"/> +<connect gate="GB3" pin="P3_HSDAC+" pad="AE20"/> +<connect gate="GB3" pin="P3_HSDAC-" pad="AF20"/> +<connect gate="GB3" pin="P3_INTN" pad="U3"/> +<connect gate="GB3" pin="P3_LED_RX" pad="T25"/> +<connect gate="GB3" pin="P3_LED_TX" pad="T24"/> +<connect gate="GB3" pin="P3_LINK10" pad="R26"/> +<connect gate="GB3" pin="P3_LINK100" pad="R25"/> +<connect gate="GB3" pin="P3_LINK1000" pad="R24"/> +<connect gate="GB3" pin="P3_MDC" pad="U1"/> +<connect gate="GB3" pin="P3_MDIO" pad="U2"/> +<connect gate="GB3" pin="P3_MDI[0]+" pad="AE22"/> +<connect gate="GB3" pin="P3_MDI[0]-" pad="AF22"/> +<connect gate="GB3" pin="P3_MDI[1]+" pad="AE21"/> +<connect gate="GB3" pin="P3_MDI[1]-" pad="AF21"/> +<connect gate="GB3" pin="P3_MDI[2]+" pad="AE19"/> +<connect gate="GB3" pin="P3_MDI[2]-" pad="AF19"/> +<connect gate="GB3" pin="P3_MDI[3]+" pad="AE18"/> +<connect gate="GB3" pin="P3_MDI[3]-" pad="AF18"/> +<connect gate="GB3" pin="P3_RSET" pad="AD22"/> +<connect gate="GB3" pin="P3_RXD[0]" pad="B22"/> +<connect gate="GB3" pin="P3_RXD[1]" pad="A23"/> +<connect gate="GB3" pin="P3_RXD[2]" pad="B23"/> +<connect gate="GB3" pin="P3_RXD[3]" pad="C23"/> +<connect gate="GB3" pin="P3_RXD[4]" pad="D23"/> +<connect gate="GB3" pin="P3_RXD[5]" pad="D24"/> +<connect gate="GB3" pin="P3_RXD[6]" pad="D25"/> +<connect gate="GB3" pin="P3_RXD[7]" pad="D26"/> +<connect gate="GB3" pin="P3_RX_CLK" pad="E26"/> +<connect gate="GB3" pin="P3_RX_DV" pad="E23"/> +<connect gate="GB3" pin="P3_RX_ER" pad="E24"/> +<connect gate="GB3" pin="P3_S_CLK+" pad="D20"/> +<connect gate="GB3" pin="P3_S_CLK-" pad="C20"/> +<connect gate="GB3" pin="P3_S_IN+" pad="B21"/> +<connect gate="GB3" pin="P3_S_IN-" pad="A21"/> +<connect gate="GB3" pin="P3_S_OUT+" pad="B20"/> +<connect gate="GB3" pin="P3_S_OUT-" pad="A20"/> +<connect gate="GB3" pin="P3_TSTPT" pad="AC17"/> +<connect gate="GB3" pin="P3_TXD[0]" pad="F24"/> +<connect gate="GB3" pin="P3_TXD[1]" pad="F25"/> +<connect gate="GB3" pin="P3_TXD[2]" pad="F26"/> +<connect gate="GB3" pin="P3_TXD[3]" pad="G24"/> +<connect gate="GB3" pin="P3_TXD[4]" pad="G25"/> +<connect gate="GB3" pin="P3_TXD[5]" pad="G26"/> +<connect gate="GB3" pin="P3_TXD[6]" pad="H24"/> +<connect gate="GB3" pin="P3_TXD[7]" pad="H25"/> +<connect gate="GB3" pin="P3_TX_CLK" pad="E25"/> +<connect gate="GB3" pin="P3_TX_EN" pad="H26"/> +<connect gate="GB3" pin="P3_TX_ER" pad="J24"/> +<connect gate="PW1/2" pin="DVDD@1" pad="C15"/> +<connect gate="PW1/2" pin="DVDD@10" pad="U4"/> +<connect gate="PW1/2" pin="DVDD@11" pad="U23"/> +<connect gate="PW1/2" pin="DVDD@2" pad="D5"/> +<connect gate="PW1/2" pin="DVDD@3" pad="D15"/> +<connect gate="PW1/2" pin="DVDD@4" pad="G4"/> +<connect gate="PW1/2" pin="DVDD@5" pad="G23"/> +<connect gate="PW1/2" pin="DVDD@6" pad="H4"/> +<connect gate="PW1/2" pin="DVDD@7" pad="H23"/> +<connect gate="PW1/2" pin="DVDD@8" pad="T4"/> +<connect gate="PW1/2" pin="DVDD@9" pad="T23"/> +<connect gate="PW1/2" pin="VDDO@1" pad="C6"/> +<connect gate="PW1/2" pin="VDDO@2" pad="C22"/> +<connect gate="PW1/2" pin="VDDO@3" pad="D6"/> +<connect gate="PW1/2" pin="VDDO@4" pad="D22"/> +<connect gate="PW1/2" pin="VDDO@5" pad="L4"/> +<connect gate="PW1/2" pin="VDDO@6" pad="M4"/> +<connect gate="PW1/2" pin="VDDOH@1" pad="L23"/> +<connect gate="PW1/2" pin="VDDOH@2" pad="M23"/> +<connect gate="PW1/2" pin="VDDOH@3" pad="AA23"/> +<connect gate="PW1/2" pin="VDDOH@4" pad="AB23"/> +<connect gate="PW1/2" pin="VDDOX@1" pad="W4"/> +<connect gate="PW1/2" pin="VDDOX@2" pad="Y4"/> +<connect gate="PW1/2" pin="VSS@1" pad="A1"/> +<connect gate="PW1/2" pin="VSS@10" pad="B24"/> +<connect gate="PW1/2" pin="VSS@11" pad="B25"/> +<connect gate="PW1/2" pin="VSS@12" pad="B26"/> +<connect gate="PW1/2" pin="VSS@13" pad="C1"/> +<connect gate="PW1/2" pin="VSS@14" pad="C2"/> +<connect gate="PW1/2" pin="VSS@15" pad="P15"/> +<connect gate="PW1/2" pin="VSS@16" pad="P16"/> +<connect gate="PW1/2" pin="VSS@17" pad="P23"/> +<connect gate="PW1/2" pin="VSS@18" pad="R4"/> +<connect gate="PW1/2" pin="VSS@19" pad="R11"/> +<connect gate="PW1/2" pin="VSS@2" pad="A2"/> +<connect gate="PW1/2" pin="VSS@20" pad="R12"/> +<connect gate="PW1/2" pin="VSS@21" pad="R13"/> +<connect gate="PW1/2" pin="VSS@22" pad="R14"/> +<connect gate="PW1/2" pin="VSS@23" pad="R15"/> +<connect gate="PW1/2" pin="VSS@24" pad="R16"/> +<connect gate="PW1/2" pin="VSS@25" pad="R23"/> +<connect gate="PW1/2" pin="VSS@26" pad="T11"/> +<connect gate="PW1/2" pin="VSS@27" pad="T12"/> +<connect gate="PW1/2" pin="VSS@28" pad="T13"/> +<connect gate="PW1/2" pin="VSS@29" pad="T14"/> +<connect gate="PW1/2" pin="VSS@3" pad="A3"/> +<connect gate="PW1/2" pin="VSS@30" pad="T15"/> +<connect gate="PW1/2" pin="VSS@31" pad="T16"/> +<connect gate="PW1/2" pin="VSS@32" pad="W23"/> +<connect gate="PW1/2" pin="VSS@33" pad="W24"/> +<connect gate="PW1/2" pin="VSS@34" pad="AB4"/> +<connect gate="PW1/2" pin="VSS@35" pad="AC1"/> +<connect gate="PW1/2" pin="VSS@36" pad="AC2"/> +<connect gate="PW1/2" pin="VSS@37" pad="AC3"/> +<connect gate="PW1/2" pin="VSS@38" pad="AC4"/> +<connect gate="PW1/2" pin="VSS@39" pad="AC19"/> +<connect gate="PW1/2" pin="VSS@4" pad="A24"/> +<connect gate="PW1/2" pin="VSS@40" pad="C3"/> +<connect gate="PW1/2" pin="VSS@41" pad="C8"/> +<connect gate="PW1/2" pin="VSS@42" pad="C21"/> +<connect gate="PW1/2" pin="VSS@43" pad="C24"/> +<connect gate="PW1/2" pin="VSS@44" pad="C25"/> +<connect gate="PW1/2" pin="VSS@45" pad="C26"/> +<connect gate="PW1/2" pin="VSS@46" pad="D8"/> +<connect gate="PW1/2" pin="VSS@47" pad="D21"/> +<connect gate="PW1/2" pin="VSS@48" pad="J4"/> +<connect gate="PW1/2" pin="VSS@5" pad="A25"/> +<connect gate="PW1/2" pin="VSS@6" pad="A26"/> +<connect gate="PW1/2" pin="VSS@7" pad="B1"/> +<connect gate="PW1/2" pin="VSS@8" pad="B2"/> +<connect gate="PW1/2" pin="VSS@9" pad="B3"/> +<connect gate="PW2/2" pin="AVDDH@1" pad="AC6"/> +<connect gate="PW2/2" pin="AVDDH@2" pad="AC12"/> +<connect gate="PW2/2" pin="AVDDH@3" pad="AC16"/> +<connect gate="PW2/2" pin="AVDDH@4" pad="AD21"/> +<connect gate="PW2/2" pin="AVDDL@1" pad="C13"/> +<connect gate="PW2/2" pin="AVDDL@10" pad="AC18"/> +<connect gate="PW2/2" pin="AVDDL@11" pad="AC20"/> +<connect gate="PW2/2" pin="AVDDL@12" pad="AC21"/> +<connect gate="PW2/2" pin="AVDDL@13" pad="AD5"/> +<connect gate="PW2/2" pin="AVDDL@14" pad="AD6"/> +<connect gate="PW2/2" pin="AVDDL@15" pad="AD8"/> +<connect gate="PW2/2" pin="AVDDL@16" pad="AD9"/> +<connect gate="PW2/2" pin="AVDDL@17" pad="AD11"/> +<connect gate="PW2/2" pin="AVDDL@18" pad="AD14"/> +<connect gate="PW2/2" pin="AVDDL@19" pad="AD18"/> +<connect gate="PW2/2" pin="AVDDL@2" pad="C17"/> +<connect gate="PW2/2" pin="AVDDL@20" pad="AD20"/> +<connect gate="PW2/2" pin="AVDDL@3" pad="D13"/> +<connect gate="PW2/2" pin="AVDDL@4" pad="D17"/> +<connect gate="PW2/2" pin="AVDDL@5" pad="AC5"/> +<connect gate="PW2/2" pin="AVDDL@6" pad="AC8"/> +<connect gate="PW2/2" pin="AVDDL@7" pad="AC9"/> +<connect gate="PW2/2" pin="AVDDL@8" pad="AC11"/> +<connect gate="PW2/2" pin="AVDDL@9" pad="AC14"/> +<connect gate="PW2/2" pin="VSS@49" pad="J23"/> +<connect gate="PW2/2" pin="VSS@50" pad="K4"/> +<connect gate="PW2/2" pin="VSS@51" pad="K23"/> +<connect gate="PW2/2" pin="VSS@52" pad="L11"/> +<connect gate="PW2/2" pin="VSS@53" pad="L12"/> +<connect gate="PW2/2" pin="VSS@54" pad="L13"/> +<connect gate="PW2/2" pin="VSS@55" pad="L14"/> +<connect gate="PW2/2" pin="VSS@56" pad="L15"/> +<connect gate="PW2/2" pin="VSS@57" pad="L16"/> +<connect gate="PW2/2" pin="VSS@58" pad="M11"/> +<connect gate="PW2/2" pin="VSS@59" pad="M12"/> +<connect gate="PW2/2" pin="VSS@60" pad="M13"/> +<connect gate="PW2/2" pin="VSS@61" pad="M14"/> +<connect gate="PW2/2" pin="VSS@62" pad="M15"/> +<connect gate="PW2/2" pin="VSS@63" pad="M16"/> +<connect gate="PW2/2" pin="VSS@64" pad="N11"/> +<connect gate="PW2/2" pin="VSS@65" pad="N12"/> +<connect gate="PW2/2" pin="VSS@66" pad="N13"/> +<connect gate="PW2/2" pin="VSS@67" pad="N14"/> +<connect gate="PW2/2" pin="VSS@68" pad="N15"/> +<connect gate="PW2/2" pin="VSS@69" pad="N16"/> +<connect gate="PW2/2" pin="VSS@70" pad="P4"/> +<connect gate="PW2/2" pin="VSS@71" pad="P11"/> +<connect gate="PW2/2" pin="VSS@72" pad="P12"/> +<connect gate="PW2/2" pin="VSS@73" pad="P13"/> +<connect gate="PW2/2" pin="VSS@74" pad="P14"/> +<connect gate="PW2/2" pin="VSS@75" pad="AC22"/> +<connect gate="PW2/2" pin="VSS@76" pad="AD1"/> +<connect gate="PW2/2" pin="VSS@77" pad="AD2"/> +<connect gate="PW2/2" pin="VSS@78" pad="AD3"/> +<connect gate="PW2/2" pin="VSS@79" pad="AD4"/> +<connect gate="PW2/2" pin="VSS@80" pad="AD7"/> +<connect gate="PW2/2" pin="VSS@81" pad="AD12"/> +<connect gate="PW2/2" pin="VSS@82" pad="AD16"/> +<connect gate="PW2/2" pin="VSS@83" pad="AD19"/> +<connect gate="PW2/2" pin="VSS@84" pad="AD23"/> +<connect gate="PW2/2" pin="VSS@85" pad="AD24"/> +<connect gate="PW2/2" pin="VSS@86" pad="AD25"/> +<connect gate="PW2/2" pin="VSS@87" pad="AE1"/> +<connect gate="PW2/2" pin="VSS@88" pad="AE2"/> +<connect gate="PW2/2" pin="VSS@89" pad="AE24"/> +<connect gate="PW2/2" pin="VSS@90" pad="AE25"/> +<connect gate="PW2/2" pin="VSS@91" pad="AE26"/> +<connect gate="PW2/2" pin="VSS@92" pad="AF1"/> +<connect gate="PW2/2" pin="VSS@93" pad="AF2"/> +<connect gate="PW2/2" pin="VSS@94" pad="AF24"/> +<connect gate="PW2/2" pin="VSS@95" pad="AF25"/> +<connect gate="PW2/2" pin="VSS@96" pad="AF26"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="DDR2" uservalue="yes"> +<gates> +<gate name="CA" symbol="DDR2-ADR-CLK" x="-33.02" y="-8.89" addlevel="request" swaplevel="10"/> +<gate name="DAT" symbol="DDR2-DATA" x="16.51" y="-3.81" addlevel="request" swaplevel="10"/> +<gate name="PWR" symbol="DDR2-PWR2" x="-71.12" y="-7.62"/> +</gates> +<devices> +<device name="" package="DDR2"> +<connects> +<connect gate="CA" pin="/CAS" pad="74"/> +<connect gate="CA" pin="/CK0" pad="186"/> +<connect gate="CA" pin="/CK1" pad="138"/> +<connect gate="CA" pin="/CK2" pad="221"/> +<connect gate="CA" pin="/CS0" pad="193"/> +<connect gate="CA" pin="/CS1" pad="76"/> +<connect gate="CA" pin="/DQS0" pad="6"/> +<connect gate="CA" pin="/DQS1" pad="15"/> +<connect gate="CA" pin="/DQS2" pad="27"/> +<connect gate="CA" pin="/DQS3" pad="36"/> +<connect gate="CA" pin="/DQS4" pad="83"/> +<connect gate="CA" pin="/DQS5" pad="92"/> +<connect gate="CA" pin="/DQS6" pad="104"/> +<connect gate="CA" pin="/DQS7" pad="113"/> +<connect gate="CA" pin="/DQS8" pad="45"/> +<connect gate="CA" pin="/RAS" pad="192"/> +<connect gate="CA" pin="/WE" pad="73"/> +<connect gate="CA" pin="A0" pad="188"/> +<connect gate="CA" pin="A1" pad="183"/> +<connect gate="CA" pin="A10/AP" pad="70"/> +<connect gate="CA" pin="A11" pad="57"/> +<connect gate="CA" pin="A12" pad="176"/> +<connect gate="CA" pin="A13" pad="196"/> +<connect gate="CA" pin="A14" pad="174"/> +<connect gate="CA" pin="A15" pad="173"/> +<connect gate="CA" pin="A16/BA2" pad="54"/> +<connect gate="CA" pin="A2" pad="63"/> +<connect gate="CA" pin="A3" pad="182"/> +<connect gate="CA" pin="A4" pad="61"/> +<connect gate="CA" pin="A5" pad="60"/> +<connect gate="CA" pin="A6" pad="180"/> +<connect gate="CA" pin="A7" pad="58"/> +<connect gate="CA" pin="A8" pad="179"/> +<connect gate="CA" pin="A9" pad="177"/> +<connect gate="CA" pin="BA0" pad="71"/> +<connect gate="CA" pin="BA1" pad="190"/> +<connect gate="CA" pin="CB0" pad="42"/> +<connect gate="CA" pin="CB1" pad="43"/> +<connect gate="CA" pin="CB2" pad="48"/> +<connect gate="CA" pin="CB3" pad="49"/> +<connect gate="CA" pin="CB4" pad="161"/> +<connect gate="CA" pin="CB5" pad="162"/> +<connect gate="CA" pin="CB6" pad="167"/> +<connect gate="CA" pin="CB7" pad="168"/> +<connect gate="CA" pin="CK0" pad="185"/> +<connect gate="CA" pin="CK1" pad="137"/> +<connect gate="CA" pin="CK2" pad="220"/> +<connect gate="CA" pin="CKE0" pad="52"/> +<connect gate="CA" pin="CKE1" pad="171"/> +<connect gate="CA" pin="DM0" pad="125"/> +<connect gate="CA" pin="DM1" pad="134"/> +<connect gate="CA" pin="DM2" pad="146"/> +<connect gate="CA" pin="DM3" pad="155"/> +<connect gate="CA" pin="DM4" pad="202"/> +<connect gate="CA" pin="DM5" pad="211"/> +<connect gate="CA" pin="DM6" pad="223"/> +<connect gate="CA" pin="DM7" pad="232"/> +<connect gate="CA" pin="DM8" pad="164"/> +<connect gate="CA" pin="DQS0" pad="7"/> +<connect gate="CA" pin="DQS1" pad="16"/> +<connect gate="CA" pin="DQS2" pad="28"/> +<connect gate="CA" pin="DQS3" pad="37"/> +<connect gate="CA" pin="DQS4" pad="84"/> +<connect gate="CA" pin="DQS5" pad="93"/> +<connect gate="CA" pin="DQS6" pad="105"/> +<connect gate="CA" pin="DQS7" pad="114"/> +<connect gate="CA" pin="DQS8" pad="46"/> +<connect gate="CA" pin="ODT0" pad="195"/> +<connect gate="CA" pin="ODT1" pad="77"/> +<connect gate="CA" pin="RC0" pad="55"/> +<connect gate="CA" pin="RC1" pad="18"/> +<connect gate="CA" pin="SA0" pad="239"/> +<connect gate="CA" pin="SA1" pad="240"/> +<connect gate="CA" pin="SA2" pad="101"/> +<connect gate="CA" pin="SCL" pad="120"/> +<connect gate="CA" pin="SDA" pad="119"/> +<connect gate="CA" pin="VREF" pad="1"/> +<connect gate="DAT" pin="DQ0" pad="3"/> +<connect gate="DAT" pin="DQ1" pad="4"/> +<connect gate="DAT" pin="DQ10" pad="21"/> +<connect gate="DAT" pin="DQ11" pad="22"/> +<connect gate="DAT" pin="DQ12" pad="131"/> +<connect gate="DAT" pin="DQ13" pad="132"/> +<connect gate="DAT" pin="DQ14" pad="140"/> +<connect gate="DAT" pin="DQ15" pad="141"/> +<connect gate="DAT" pin="DQ16" pad="24"/> +<connect gate="DAT" pin="DQ17" pad="25"/> +<connect gate="DAT" pin="DQ18" pad="30"/> +<connect gate="DAT" pin="DQ19" pad="31"/> +<connect gate="DAT" pin="DQ2" pad="9"/> +<connect gate="DAT" pin="DQ20" pad="143"/> +<connect gate="DAT" pin="DQ21" pad="144"/> +<connect gate="DAT" pin="DQ22" pad="149"/> +<connect gate="DAT" pin="DQ23" pad="150"/> +<connect gate="DAT" pin="DQ24" pad="33"/> +<connect gate="DAT" pin="DQ25" pad="34"/> +<connect gate="DAT" pin="DQ26" pad="39"/> +<connect gate="DAT" pin="DQ27" pad="40"/> +<connect gate="DAT" pin="DQ28" pad="152"/> +<connect gate="DAT" pin="DQ29" pad="153"/> +<connect gate="DAT" pin="DQ3" pad="10"/> +<connect gate="DAT" pin="DQ30" pad="158"/> +<connect gate="DAT" pin="DQ31" pad="159"/> +<connect gate="DAT" pin="DQ32" pad="80"/> +<connect gate="DAT" pin="DQ33" pad="81"/> +<connect gate="DAT" pin="DQ34" pad="86"/> +<connect gate="DAT" pin="DQ35" pad="87"/> +<connect gate="DAT" pin="DQ36" pad="199"/> +<connect gate="DAT" pin="DQ37" pad="200"/> +<connect gate="DAT" pin="DQ38" pad="205"/> +<connect gate="DAT" pin="DQ39" pad="206"/> +<connect gate="DAT" pin="DQ4" pad="122"/> +<connect gate="DAT" pin="DQ40" pad="89"/> +<connect gate="DAT" pin="DQ41" pad="90"/> +<connect gate="DAT" pin="DQ42" pad="95"/> +<connect gate="DAT" pin="DQ43" pad="96"/> +<connect gate="DAT" pin="DQ44" pad="208"/> +<connect gate="DAT" pin="DQ45" pad="209"/> +<connect gate="DAT" pin="DQ46" pad="214"/> +<connect gate="DAT" pin="DQ47" pad="215"/> +<connect gate="DAT" pin="DQ48" pad="98"/> +<connect gate="DAT" pin="DQ49" pad="99"/> +<connect gate="DAT" pin="DQ5" pad="123"/> +<connect gate="DAT" pin="DQ50" pad="107"/> +<connect gate="DAT" pin="DQ51" pad="108"/> +<connect gate="DAT" pin="DQ52" pad="217"/> +<connect gate="DAT" pin="DQ53" pad="218"/> +<connect gate="DAT" pin="DQ54" pad="226"/> +<connect gate="DAT" pin="DQ55" pad="227"/> +<connect gate="DAT" pin="DQ56" pad="110"/> +<connect gate="DAT" pin="DQ57" pad="111"/> +<connect gate="DAT" pin="DQ58" pad="116"/> +<connect gate="DAT" pin="DQ59" pad="117"/> +<connect gate="DAT" pin="DQ6" pad="128"/> +<connect gate="DAT" pin="DQ60" pad="229"/> +<connect gate="DAT" pin="DQ61" pad="230"/> +<connect gate="DAT" pin="DQ62" pad="235"/> +<connect gate="DAT" pin="DQ63" pad="236"/> +<connect gate="DAT" pin="DQ7" pad="129"/> +<connect gate="DAT" pin="DQ8" pad="12"/> +<connect gate="DAT" pin="DQ9" pad="13"/> +<connect gate="PWR" pin="NC@1" pad="19"/> +<connect gate="PWR" pin="NC@10" pad="233"/> +<connect gate="PWR" pin="NC@12" pad="165"/> +<connect gate="PWR" pin="NC@15" pad="126"/> +<connect gate="PWR" pin="NC@16" pad="68"/> +<connect gate="PWR" pin="NC@18" pad="147"/> +<connect gate="PWR" pin="NC@2" pad="102"/> +<connect gate="PWR" pin="NC@3" pad="135"/> +<connect gate="PWR" pin="NC@5" pad="156"/> +<connect gate="PWR" pin="NC@6" pad="203"/> +<connect gate="PWR" pin="NC@7" pad="212"/> +<connect gate="PWR" pin="NC@8" pad="224"/> +<connect gate="PWR" pin="VDD@1" pad="53"/> +<connect gate="PWR" pin="VDD@10" pad="189"/> +<connect gate="PWR" pin="VDD@11" pad="197"/> +<connect gate="PWR" pin="VDD@2" pad="59"/> +<connect gate="PWR" pin="VDD@3" pad="64"/> +<connect gate="PWR" pin="VDD@4" pad="67"/> +<connect gate="PWR" pin="VDD@5" pad="69"/> +<connect gate="PWR" pin="VDD@6" pad="172"/> +<connect gate="PWR" pin="VDD@7" pad="178"/> +<connect gate="PWR" pin="VDD@8" pad="184"/> +<connect gate="PWR" pin="VDD@9" pad="187"/> +<connect gate="PWR" pin="VDDQ@1" pad="51"/> +<connect gate="PWR" pin="VDDQ@10" pad="191"/> +<connect gate="PWR" pin="VDDQ@11" pad="194"/> +<connect gate="PWR" pin="VDDQ@2" pad="56"/> +<connect gate="PWR" pin="VDDQ@3" pad="62"/> +<connect gate="PWR" pin="VDDQ@4" pad="72"/> +<connect gate="PWR" pin="VDDQ@5" pad="75"/> +<connect gate="PWR" pin="VDDQ@6" pad="78"/> +<connect gate="PWR" pin="VDDQ@7" pad="170"/> +<connect gate="PWR" pin="VDDQ@8" pad="175"/> +<connect gate="PWR" pin="VDDQ@9" pad="181"/> +<connect gate="PWR" pin="VDDSPD" pad="238"/> +<connect gate="PWR" pin="VSS@1" pad="2"/> +<connect gate="PWR" pin="VSS@10" pad="29"/> +<connect gate="PWR" pin="VSS@11" pad="32"/> +<connect gate="PWR" pin="VSS@12" pad="35"/> +<connect gate="PWR" pin="VSS@13" pad="38"/> +<connect gate="PWR" pin="VSS@14" pad="41"/> +<connect gate="PWR" pin="VSS@15" pad="44"/> +<connect gate="PWR" pin="VSS@16" pad="47"/> +<connect gate="PWR" pin="VSS@17" pad="50"/> +<connect gate="PWR" pin="VSS@18" pad="65"/> +<connect gate="PWR" pin="VSS@19" pad="66"/> +<connect gate="PWR" pin="VSS@2" pad="5"/> +<connect gate="PWR" pin="VSS@20" pad="79"/> +<connect gate="PWR" pin="VSS@21" pad="82"/> +<connect gate="PWR" pin="VSS@22" pad="85"/> +<connect gate="PWR" pin="VSS@23" pad="88"/> +<connect gate="PWR" pin="VSS@24" pad="91"/> +<connect gate="PWR" pin="VSS@25" pad="94"/> +<connect gate="PWR" pin="VSS@26" pad="97"/> +<connect gate="PWR" pin="VSS@27" pad="100"/> +<connect gate="PWR" pin="VSS@28" pad="103"/> +<connect gate="PWR" pin="VSS@29" pad="106"/> +<connect gate="PWR" pin="VSS@3" pad="8"/> +<connect gate="PWR" pin="VSS@30" pad="109"/> +<connect gate="PWR" pin="VSS@31" pad="112"/> +<connect gate="PWR" pin="VSS@32" pad="115"/> +<connect gate="PWR" pin="VSS@33" pad="118"/> +<connect gate="PWR" pin="VSS@34" pad="121"/> +<connect gate="PWR" pin="VSS@35" pad="124"/> +<connect gate="PWR" pin="VSS@36" pad="127"/> +<connect gate="PWR" pin="VSS@37" pad="130"/> +<connect gate="PWR" pin="VSS@38" pad="133"/> +<connect gate="PWR" pin="VSS@39" pad="136"/> +<connect gate="PWR" pin="VSS@4" pad="11"/> +<connect gate="PWR" pin="VSS@40" pad="139"/> +<connect gate="PWR" pin="VSS@41" pad="142"/> +<connect gate="PWR" pin="VSS@42" pad="145"/> +<connect gate="PWR" pin="VSS@43" pad="148"/> +<connect gate="PWR" pin="VSS@44" pad="151"/> +<connect gate="PWR" pin="VSS@45" pad="154"/> +<connect gate="PWR" pin="VSS@46" pad="157"/> +<connect gate="PWR" pin="VSS@47" pad="160"/> +<connect gate="PWR" pin="VSS@48" pad="163"/> +<connect gate="PWR" pin="VSS@49" pad="166"/> +<connect gate="PWR" pin="VSS@5" pad="14"/> +<connect gate="PWR" pin="VSS@50" pad="169"/> +<connect gate="PWR" pin="VSS@51" pad="198"/> +<connect gate="PWR" pin="VSS@52" pad="201"/> +<connect gate="PWR" pin="VSS@53" pad="204"/> +<connect gate="PWR" pin="VSS@54" pad="207"/> +<connect gate="PWR" pin="VSS@55" pad="210"/> +<connect gate="PWR" pin="VSS@56" pad="213"/> +<connect gate="PWR" pin="VSS@57" pad="216"/> +<connect gate="PWR" pin="VSS@58" pad="219"/> +<connect gate="PWR" pin="VSS@59" pad="222"/> +<connect gate="PWR" pin="VSS@6" pad="17"/> +<connect gate="PWR" pin="VSS@60" pad="225"/> +<connect gate="PWR" pin="VSS@61" pad="228"/> +<connect gate="PWR" pin="VSS@62" pad="231"/> +<connect gate="PWR" pin="VSS@63" pad="234"/> +<connect gate="PWR" pin="VSS@64" pad="237"/> +<connect gate="PWR" pin="VSS@7" pad="20"/> +<connect gate="PWR" pin="VSS@8" pad="23"/> +<connect gate="PWR" pin="VSS@9" pad="26"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="EP80579" uservalue="yes"> +<gates> +<gate name="CAN" symbol="EP80-CAN" x="-318.77" y="20.32" addlevel="request"/> +<gate name="DDR2ACCESS" symbol="EP80-DDR2ACCESS" x="-351.79" y="-38.1" addlevel="request"/> +<gate name="DDR2CLK" symbol="EP80-DDR2CLK" x="-318.77" y="66.04" addlevel="request"/> +<gate name="DDR2CMP" symbol="EP80-DDR2CMP" x="-353.06" y="48.26" addlevel="request"/> +<gate name="DDR2DATA" symbol="EP80-DDR2DATA" x="-383.54" y="46.99" addlevel="request"/> +<gate name="GBE0" symbol="EP80-GBE0" x="-317.5" y="-49.53" addlevel="request"/> +<gate name="GBE1" symbol="EP80-GBE1" x="-281.94" y="-95.25" addlevel="request"/> +<gate name="GBE2" symbol="EP80-GBE2" x="-317.5" y="-92.71" addlevel="request"/> +<gate name="GBE" symbol="EP80-GBEMANAGE" x="-317.5" y="-6.35" addlevel="request"/> +<gate name="GPIO" symbol="EP80-GPIO" x="-280.67" y="-66.04" addlevel="request"/> +<gate name="GPIOIRQ" symbol="EP80-GPIOIRQ" x="-278.13" y="-6.35" addlevel="request"/> +<gate name="IA32CORE" symbol="EP80-IA32CORE" x="-281.94" y="35.56" addlevel="request"/> +<gate name="IEEE1588" symbol="EP80-IEEE1588" x="-247.65" y="66.04" addlevel="request"/> +<gate name="IICHIMCH" symbol="EP80-IICHIMCH" x="-248.92" y="12.7" addlevel="request"/> +<gate name="JTAG" symbol="EP80-JTAG" x="-248.92" y="-34.29" addlevel="request"/> +<gate name="LEB" symbol="EP80-LEB" x="-201.93" y="72.39" addlevel="request"/> +<gate name="LEBDATA" symbol="EP80-LEBDATA" x="-201.93" y="-30.48" addlevel="request"/> +<gate name="LPC11" symbol="EP80-LPC11" x="-243.84" y="-100.33" addlevel="request"/> +<gate name="MISCSIG" symbol="EP80-MISCSIG" x="-281.94" y="67.31" addlevel="request"/> +<gate name="NC" symbol="EP80-NC" x="-421.64" y="58.42" addlevel="request"/> +<gate name="PCI" symbol="EP80-PCI" x="-461.01" y="63.5" addlevel="request"/> +<gate name="POWERMANAGE" symbol="EP80-POWERMANAGE" x="-422.91" y="-55.88" addlevel="request"/> +<gate name="RESERVED" symbol="EP80-RESERVED" x="-463.55" y="-52.07" addlevel="request"/> +<gate name="SATA" symbol="EP80-SATA2.0" x="-496.57" y="73.66" addlevel="request"/> +<gate name="SBUS" symbol="EP80-SBUS" x="-520.7" y="6.35" addlevel="request"/> +<gate name="TDM" symbol="EP80-TDM" x="-501.65" y="-76.2" addlevel="request"/> +<gate name="UART" symbol="EP80-UART" x="-530.86" y="55.88" addlevel="request"/> +<gate name="PWR-GBE" symbol="EP80-PWR-GBE" x="41.91" y="153.67" addlevel="request"/> +<gate name="PWR-MIS" symbol="EP80-PWR-MIS" x="57.15" y="134.62" addlevel="request"/> +<gate name="PWR-PCI" symbol="EP80-PWR-PCI" x="44.45" y="110.49" addlevel="request"/> +<gate name="PWR-SATA" symbol="EP80-PWR-SATA" x="46.99" y="91.44" addlevel="request"/> +<gate name="PWR-USB" symbol="EP80-PWR-USB" x="46.99" y="73.66" addlevel="request"/> +<gate name="VCC" symbol="EP80-PWR-VCC" x="7.62" y="54.61" addlevel="request"/> +<gate name="VCC18" symbol="EP80-PWR-VCC18-VTTDDR" x="-57.15" y="43.18" addlevel="request"/> +<gate name="VCC50VCC33" symbol="EP80-PWR-VCC50-VCC33" x="-55.88" y="31.75" addlevel="request"/> +<gate name="VCCVC" symbol="EP80-PWR-VCCVC" x="-24.13" y="17.78" addlevel="request"/> +<gate name="VSSA" symbol="EP80-PWR-VSS" x="-7.62" y="7.62" addlevel="must"/> +<gate name="VSSB" symbol="EP80-PWR-VSS" x="-7.62" y="-3.81" addlevel="request"/> +<gate name="VSSC" symbol="EP80-PWR-VSS" x="-7.62" y="-15.24" addlevel="request"/> +<gate name="VSSD" symbol="EP80-PWR-VSS" x="-7.62" y="-26.67" addlevel="request"/> +</gates> +<devices> +<device name="" package="EP80579"> +<connects> +<connect gate="CAN" pin="CN0RXD" pad="AF5"/> +<connect gate="CAN" pin="CN0TXD" pad="AD8"/> +<connect gate="CAN" pin="CN0TXEN" pad="AE7"/> +<connect gate="CAN" pin="CN1RXD" pad="AK2"/> +<connect gate="CAN" pin="CN1TXD" pad="AJ3"/> +<connect gate="CAN" pin="CN1TXEN" pad="AG5"/> +<connect gate="DDR2ACCESS" pin="DDR_A[0]" pad="AM26"/> +<connect gate="DDR2ACCESS" pin="DDR_A[10]" pad="AM27"/> +<connect gate="DDR2ACCESS" pin="DDR_A[11]" pad="AH28"/> +<connect gate="DDR2ACCESS" pin="DDR_A[12]" pad="AH26"/> +<connect gate="DDR2ACCESS" pin="DDR_A[13]" pad="AN27"/> +<connect gate="DDR2ACCESS" pin="DDR_A[14]" pad="AG27"/> +<connect gate="DDR2ACCESS" pin="DDR_A[1]" pad="AL27"/> +<connect gate="DDR2ACCESS" pin="DDR_A[2]" pad="AL28"/> +<connect gate="DDR2ACCESS" pin="DDR_A[3]" pad="AK28"/> +<connect gate="DDR2ACCESS" pin="DDR_A[4]" pad="AK27"/> +<connect gate="DDR2ACCESS" pin="DDR_A[5]" pad="AK26"/> +<connect gate="DDR2ACCESS" pin="DDR_A[6]" pad="AJ28"/> +<connect gate="DDR2ACCESS" pin="DDR_A[7]" pad="AJ26"/> +<connect gate="DDR2ACCESS" pin="DDR_A[8]" pad="AJ27"/> +<connect gate="DDR2ACCESS" pin="DDR_A[9]" pad="AH27"/> +<connect gate="DDR2ACCESS" pin="DDR_BA[0]" pad="AM28"/> +<connect gate="DDR2ACCESS" pin="DDR_BA[1]" pad="AM29"/> +<connect gate="DDR2ACCESS" pin="DDR_BA[2]" pad="AG26"/> +<connect gate="DDR2ACCESS" pin="DDR_CAS#" pad="AN26"/> +<connect gate="DDR2ACCESS" pin="DDR_CKE[0]" pad="AN29"/> +<connect gate="DDR2ACCESS" pin="DDR_CKE[1]" pad="M25"/> +<connect gate="DDR2ACCESS" pin="DDR_CS[0]#" pad="H28"/> +<connect gate="DDR2ACCESS" pin="DDR_CS[1]#" pad="K28"/> +<connect gate="DDR2ACCESS" pin="DDR_RAS#" pad="AF27"/> +<connect gate="DDR2ACCESS" pin="DDR_WE#" pad="AN28"/> +<connect gate="DDR2CLK" pin="DDR_CK[0]" pad="V30"/> +<connect gate="DDR2CLK" pin="DDR_CK[0]#" pad="V31"/> +<connect gate="DDR2CLK" pin="DDR_CK[1]" pad="W32"/> +<connect gate="DDR2CLK" pin="DDR_CK[1]#" pad="W33"/> +<connect gate="DDR2CLK" pin="DDR_CK[2]" pad="U32"/> +<connect gate="DDR2CLK" pin="DDR_CK[2]#" pad="U31"/> +<connect gate="DDR2CLK" pin="DDR_CK[3]" pad="J28"/> +<connect gate="DDR2CLK" pin="DDR_CK[3]#" pad="J27"/> +<connect gate="DDR2CLK" pin="DDR_CK[4]" pad="D31"/> +<connect gate="DDR2CLK" pin="DDR_CK[4]#" pad="D32"/> +<connect gate="DDR2CLK" pin="DDR_CK[5]" pad="G26"/> +<connect gate="DDR2CLK" pin="DDR_CK[5]#" pad="G27"/> +<connect gate="DDR2CMP" pin="DDR_CRES[0]" pad="V27"/> +<connect gate="DDR2CMP" pin="DDR_CRES[1]" pad="U30"/> +<connect gate="DDR2CMP" pin="DDR_CRES[2]" pad="U29"/> +<connect gate="DDR2CMP" pin="DDR_DQS[0]" pad="G32"/> +<connect gate="DDR2CMP" pin="DDR_DQS[0]#" pad="G33"/> +<connect gate="DDR2CMP" pin="DDR_DQS[1]" pad="L31"/> +<connect gate="DDR2CMP" pin="DDR_DQS[1]#" pad="L32"/> +<connect gate="DDR2CMP" pin="DDR_DQS[2]" pad="R29"/> +<connect gate="DDR2CMP" pin="DDR_DQS[2]#" pad="R30"/> +<connect gate="DDR2CMP" pin="DDR_DQS[3]" pad="T33"/> +<connect gate="DDR2CMP" pin="DDR_DQS[3]#" pad="T32"/> +<connect gate="DDR2CMP" pin="DDR_DQS[4]" pad="Y27"/> +<connect gate="DDR2CMP" pin="DDR_DQS[4]#" pad="Y28"/> +<connect gate="DDR2CMP" pin="DDR_DQS[5]" pad="AE32"/> +<connect gate="DDR2CMP" pin="DDR_DQS[5]#" pad="AE33"/> +<connect gate="DDR2CMP" pin="DDR_DQS[6]" pad="AE27"/> +<connect gate="DDR2CMP" pin="DDR_DQS[6]#" pad="AE28"/> +<connect gate="DDR2CMP" pin="DDR_DQS[7]" pad="AJ31"/> +<connect gate="DDR2CMP" pin="DDR_DQS[7]#" pad="AH31"/> +<connect gate="DDR2CMP" pin="DDR_DQS[8]" pad="AA32"/> +<connect gate="DDR2CMP" pin="DDR_DQS[8]#" pad="AA33"/> +<connect gate="DDR2CMP" pin="DDR_DRVCRES" pad="V33"/> +<connect gate="DDR2CMP" pin="DDR_ECC[0]" pad="Y32"/> +<connect gate="DDR2CMP" pin="DDR_ECC[1]" pad="Y33"/> +<connect gate="DDR2CMP" pin="DDR_ECC[2]" pad="AB31"/> +<connect gate="DDR2CMP" pin="DDR_ECC[3]" pad="AC32"/> +<connect gate="DDR2CMP" pin="DDR_ECC[4]" pad="V32"/> +<connect gate="DDR2CMP" pin="DDR_ECC[5]" pad="W31"/> +<connect gate="DDR2CMP" pin="DDR_ECC[6]" pad="AB32"/> +<connect gate="DDR2CMP" pin="DDR_ECC[7]" pad="AB33"/> +<connect gate="DDR2CMP" pin="DDR_ODT0" pad="AL29"/> +<connect gate="DDR2CMP" pin="DDR_ODT1" pad="L26"/> +<connect gate="DDR2CMP" pin="DDR_RCOMPX" pad="V26"/> +<connect gate="DDR2CMP" pin="DDR_SLEWCRES" pad="V28"/> +<connect gate="DDR2DATA" pin="DDR_DM[0]" pad="F31"/> +<connect gate="DDR2DATA" pin="DDR_DM[1]" pad="K33"/> +<connect gate="DDR2DATA" pin="DDR_DM[2]" pad="P28"/> +<connect gate="DDR2DATA" pin="DDR_DM[3]" pad="R32"/> +<connect gate="DDR2DATA" pin="DDR_DM[4]" pad="Y26"/> +<connect gate="DDR2DATA" pin="DDR_DM[5]" pad="AD31"/> +<connect gate="DDR2DATA" pin="DDR_DM[6]" pad="AD27"/> +<connect gate="DDR2DATA" pin="DDR_DM[7]" pad="AJ32"/> +<connect gate="DDR2DATA" pin="DDR_DM[8]" pad="Y31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[0]" pad="F32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[10]" pad="M31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[11]" pad="N33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[12]" pad="H33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[13]" pad="J33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[14]" pad="M33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[15]" pad="M32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[16]" pad="N28"/> +<connect gate="DDR2DATA" pin="DDR_DQ[17]" pad="N27"/> +<connect gate="DDR2DATA" pin="DDR_DQ[18]" pad="T28"/> +<connect gate="DDR2DATA" pin="DDR_DQ[19]" pad="U28"/> +<connect gate="DDR2DATA" pin="DDR_DQ[1]" pad="F33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[20]" pad="M28"/> +<connect gate="DDR2DATA" pin="DDR_DQ[21]" pad="M27"/> +<connect gate="DDR2DATA" pin="DDR_DQ[22]" pad="T30"/> +<connect gate="DDR2DATA" pin="DDR_DQ[23]" pad="T29"/> +<connect gate="DDR2DATA" pin="DDR_DQ[24]" pad="P33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[25]" pad="P32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[26]" pad="U33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[27]" pad="U27"/> +<connect gate="DDR2DATA" pin="DDR_DQ[28]" pad="N32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[29]" pad="N31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[2]" pad="J32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[30]" pad="T31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[31]" pad="T27"/> +<connect gate="DDR2DATA" pin="DDR_DQ[32]" pad="W27"/> +<connect gate="DDR2DATA" pin="DDR_DQ[33]" pad="W28"/> +<connect gate="DDR2DATA" pin="DDR_DQ[34]" pad="AB26"/> +<connect gate="DDR2DATA" pin="DDR_DQ[35]" pad="AB28"/> +<connect gate="DDR2DATA" pin="DDR_DQ[36]" pad="Y25"/> +<connect gate="DDR2DATA" pin="DDR_DQ[37]" pad="W26"/> +<connect gate="DDR2DATA" pin="DDR_DQ[38]" pad="AA27"/> +<connect gate="DDR2DATA" pin="DDR_DQ[39]" pad="AA28"/> +<connect gate="DDR2DATA" pin="DDR_DQ[3]" pad="J31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[40]" pad="AD32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[41]" pad="AD33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[42]" pad="AF32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[43]" pad="AG32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[44]" pad="AC33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[45]" pad="AC31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[46]" pad="AF31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[47]" pad="AF33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[48]" pad="AC27"/> +<connect gate="DDR2DATA" pin="DDR_DQ[49]" pad="AC26"/> +<connect gate="DDR2DATA" pin="DDR_DQ[4]" pad="E31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[50]" pad="AE26"/> +<connect gate="DDR2DATA" pin="DDR_DQ[51]" pad="AF26"/> +<connect gate="DDR2DATA" pin="DDR_DQ[52]" pad="AB27"/> +<connect gate="DDR2DATA" pin="DDR_DQ[53]" pad="AC28"/> +<connect gate="DDR2DATA" pin="DDR_DQ[54]" pad="AF28"/> +<connect gate="DDR2DATA" pin="DDR_DQ[55]" pad="AD26"/> +<connect gate="DDR2DATA" pin="DDR_DQ[56]" pad="AH32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[57]" pad="AH33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[58]" pad="AL30"/> +<connect gate="DDR2DATA" pin="DDR_DQ[59]" pad="AM30"/> +<connect gate="DDR2DATA" pin="DDR_DQ[5]" pad="E32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[60]" pad="AG33"/> +<connect gate="DDR2DATA" pin="DDR_DQ[61]" pad="AG31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[62]" pad="AL31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[63]" pad="AL32"/> +<connect gate="DDR2DATA" pin="DDR_DQ[6]" pad="H31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[7]" pad="H30"/> +<connect gate="DDR2DATA" pin="DDR_DQ[8]" pad="K31"/> +<connect gate="DDR2DATA" pin="DDR_DQ[9]" pad="K32"/> +<connect gate="GBE" pin="EECS" pad="AH16"/> +<connect gate="GBE" pin="EEDI" pad="AG16"/> +<connect gate="GBE" pin="EEDO" pad="AK16"/> +<connect gate="GBE" pin="EESK" pad="AF16"/> +<connect gate="GBE" pin="GBE_AUX_PWR_GOOD" pad="AN16"/> +<connect gate="GBE" pin="GBE_PME_WAKE" pad="AE16"/> +<connect gate="GBE" pin="GBE_RCOMPN" pad="AE17"/> +<connect gate="GBE" pin="GBE_RCOMPP" pad="AF17"/> +<connect gate="GBE" pin="GBE_REFCLK" pad="AN17"/> +<connect gate="GBE" pin="GBE_REFCLK_RMII" pad="AL17"/> +<connect gate="GBE" pin="MDC" pad="AG17"/> +<connect gate="GBE" pin="MDIO" pad="AH17"/> +<connect gate="GBE" pin="SYS_PWR_OK" pad="AJ17"/> +<connect gate="GBE0" pin="GBE0_RXCLK" pad="AL18"/> +<connect gate="GBE0" pin="GBE0_RXCTL" pad="AM18"/> +<connect gate="GBE0" pin="GBE0_RXDATA[0]" pad="AM20"/> +<connect gate="GBE0" pin="GBE0_RXDATA[1]" pad="AN20"/> +<connect gate="GBE0" pin="GBE0_RXDATA[2]" pad="AN19"/> +<connect gate="GBE0" pin="GBE0_RXDATA[3]" pad="AN18"/> +<connect gate="GBE0" pin="GBE0_TXCLK" pad="AL19"/> +<connect gate="GBE0" pin="GBE0_TXCTL" pad="AL20"/> +<connect gate="GBE0" pin="GBE0_TXDATA[0]" pad="AH18"/> +<connect gate="GBE0" pin="GBE0_TXDATA[1]" pad="AK20"/> +<connect gate="GBE0" pin="GBE0_TXDATA[2]" pad="AK19"/> +<connect gate="GBE0" pin="GBE0_TXDATA[3]" pad="AJ18"/> +<connect gate="GBE1" pin="GBE1_RXCLK" pad="AN21"/> +<connect gate="GBE1" pin="GBE1_RXCTL" pad="AM21"/> +<connect gate="GBE1" pin="GBE1_RXDATA[0]" pad="AK22"/> +<connect gate="GBE1" pin="GBE1_RXDATA[1]" pad="AN23"/> +<connect gate="GBE1" pin="GBE1_RXDATA[2]" pad="AN22"/> +<connect gate="GBE1" pin="GBE1_RXDATA[3]" pad="AL21"/> +<connect gate="GBE1" pin="GBE1_TXCLK" pad="AH19"/> +<connect gate="GBE1" pin="GBE1_TXCTL" pad="AF19"/> +<connect gate="GBE1" pin="GBE1_TXDATA[0]" pad="AK23"/> +<connect gate="GBE1" pin="GBE1_TXDATA[1]" pad="AF20"/> +<connect gate="GBE1" pin="GBE1_TXDATA[2]" pad="AK21"/> +<connect gate="GBE1" pin="GBE1_TXDATA[3]" pad="AH20"/> +<connect gate="GBE2" pin="GBE2_RXCLK" pad="AL22"/> +<connect gate="GBE2" pin="GBE2_RXCTL" pad="AN24"/> +<connect gate="GBE2" pin="GBE2_RXDATA[0]" pad="AL24"/> +<connect gate="GBE2" pin="GBE2_RXDATA[1]" pad="AH21"/> +<connect gate="GBE2" pin="GBE2_RXDATA[2]" pad="AL23"/> +<connect gate="GBE2" pin="GBE2_RXDATA[3]" pad="AM24"/> +<connect gate="GBE2" pin="GBE2_TXCLK" pad="AJ22"/> +<connect gate="GBE2" pin="GBE2_TXCTL" pad="AG21"/> +<connect gate="GBE2" pin="GBE2_TXDATA[0]" pad="AF22"/> +<connect gate="GBE2" pin="GBE2_TXDATA[1]" pad="AG22"/> +<connect gate="GBE2" pin="GBE2_TXDATA[2]" pad="AH22"/> +<connect gate="GBE2" pin="GBE2_TXDATA[3]" pad="AF21"/> +<connect gate="GPIO" pin="GPIO[0]" pad="L6"/> +<connect gate="GPIO" pin="GPIO[10]" pad="B4"/> +<connect gate="GPIO" pin="GPIO[12]" pad="H2"/> +<connect gate="GPIO" pin="GPIO[13]" pad="N8"/> +<connect gate="GPIO" pin="GPIO[14]" pad="G5"/> +<connect gate="GPIO" pin="GPIO[15]" pad="A4"/> +<connect gate="GPIO" pin="GPIO[1]" pad="J5"/> +<connect gate="GPIO" pin="GPIO[48]" pad="U5"/> +<connect gate="GPIO" pin="GPIO[6]" pad="N9"/> +<connect gate="GPIO" pin="GPIO[7]" pad="J4"/> +<connect gate="GPIO" pin="GPIO[8]" pad="D5"/> +<connect gate="GPIO" pin="GPIO[9]" pad="D4"/> +<connect gate="GPIOIRQ" pin="GP16_IRQ24" pad="H3"/> +<connect gate="GPIOIRQ" pin="GP17_IRQ25" pad="K3"/> +<connect gate="GPIOIRQ" pin="GP18_IRQ36" pad="K2"/> +<connect gate="GPIOIRQ" pin="GP19_IRQ37" pad="P8"/> +<connect gate="GPIOIRQ" pin="GP20_IRQ26" pad="P7"/> +<connect gate="GPIOIRQ" pin="GP21_IRQ27" pad="N4"/> +<connect gate="GPIOIRQ" pin="GP23_IRQ28" pad="L1"/> +<connect gate="GPIOIRQ" pin="GP24_IRQ29" pad="K7"/> +<connect gate="GPIOIRQ" pin="GP25_IRQ38" pad="J7"/> +<connect gate="GPIOIRQ" pin="GP27_IRQ39" pad="K8"/> +<connect gate="GPIOIRQ" pin="GP28_IRQ30" pad="J8"/> +<connect gate="GPIOIRQ" pin="GP30_IRQ31" pad="N5"/> +<connect gate="GPIOIRQ" pin="GP31_IRQ32" pad="W2"/> +<connect gate="GPIOIRQ" pin="GP33_IRQ33" pad="P4"/> +<connect gate="GPIOIRQ" pin="GP34_IRQ34" pad="T7"/> +<connect gate="GPIOIRQ" pin="GP40_IRQ35" pad="P3"/> +<connect gate="IA32CORE" pin="A20GATE" pad="V2"/> +<connect gate="IA32CORE" pin="CLKN100" pad="B31"/> +<connect gate="IA32CORE" pin="CLKP100" pad="C30"/> +<connect gate="IA32CORE" pin="CPUPWRGD_OUT" pad="M7"/> +<connect gate="IA32CORE" pin="CPURST_N" pad="U1"/> +<connect gate="IA32CORE" pin="CPUSLP_OUT_N" pad="P5"/> +<connect gate="IA32CORE" pin="IERR_N" pad="AC4"/> +<connect gate="IA32CORE" pin="INIT33V_OUT_N" pad="V1"/> +<connect gate="IA32CORE" pin="NMI" pad="R5"/> +<connect gate="IA32CORE" pin="RCIN_N" pad="M1"/> +<connect gate="IA32CORE" pin="SMI_OUT_N" pad="M2"/> +<connect gate="IA32CORE" pin="STPCLK_OUT_N" pad="N3"/> +<connect gate="IA32CORE" pin="THERMDA" pad="F26"/> +<connect gate="IA32CORE" pin="THERMDC" pad="F27"/> +<connect gate="IEEE1588" pin="1588_PPS" pad="AK1"/> +<connect gate="IEEE1588" pin="1588_RX_SNAP" pad="AG1"/> +<connect gate="IEEE1588" pin="1588_TESTMODE_DATA" pad="AL2"/> +<connect gate="IEEE1588" pin="1588_TX_SNAP" pad="AG3"/> +<connect gate="IEEE1588" pin="AMMSSIG" pad="AJ1"/> +<connect gate="IEEE1588" pin="ASMSSIG" pad="AH2"/> +<connect gate="IICHIMCH" pin="BSEL" pad="M8"/> +<connect gate="IICHIMCH" pin="CLK14" pad="N1"/> +<connect gate="IICHIMCH" pin="GP2_PIRQE_N" pad="D1"/> +<connect gate="IICHIMCH" pin="GP3_PIRQF_N" pad="H1"/> +<connect gate="IICHIMCH" pin="GP4_PIRQG_N" pad="N7"/> +<connect gate="IICHIMCH" pin="GP5_PIRQH_N" pad="G1"/> +<connect gate="IICHIMCH" pin="PE_HPINTR_N" pad="U2"/> +<connect gate="IICHIMCH" pin="PWRGD" pad="W6"/> +<connect gate="IICHIMCH" pin="RSTIN_N" pad="AC3"/> +<connect gate="IICHIMCH" pin="RTCX1" pad="F1"/> +<connect gate="IICHIMCH" pin="RTCX2" pad="F2"/> +<connect gate="IICHIMCH" pin="RTEST_N" pad="L7"/> +<connect gate="IICHIMCH" pin="SERIRQ" pad="J1"/> +<connect gate="IICHIMCH" pin="V_SEL" pad="G2"/> +<connect gate="IICHIMCH" pin="WDT_TOUT_N" pad="F4"/> +<connect gate="JTAG" pin="BPM0" pad="E33"/> +<connect gate="JTAG" pin="BPM1" pad="M26"/> +<connect gate="JTAG" pin="BPM2" pad="C32"/> +<connect gate="JTAG" pin="BPM3" pad="G28"/> +<connect gate="JTAG" pin="BPM3_IN" pad="Y2"/> +<connect gate="JTAG" pin="BPM4_PRDY_OUT" pad="AA3"/> +<connect gate="JTAG" pin="BPM5_PREQ_IN" pad="W5"/> +<connect gate="JTAG" pin="TCK" pad="Y3"/> +<connect gate="JTAG" pin="TDI" pad="AA1"/> +<connect gate="JTAG" pin="TDO" pad="AG2"/> +<connect gate="JTAG" pin="TMS" pad="AB5"/> +<connect gate="JTAG" pin="TRST_N" pad="Y7"/> +<connect gate="LEB" pin="EX_ADDR[0]" pad="AK9"/> +<connect gate="LEB" pin="EX_ADDR[10]" pad="AM5"/> +<connect gate="LEB" pin="EX_ADDR[11]" pad="AF9"/> +<connect gate="LEB" pin="EX_ADDR[12]" pad="AK7"/> +<connect gate="LEB" pin="EX_ADDR[13]" pad="AG8"/> +<connect gate="LEB" pin="EX_ADDR[14]" pad="AL6"/> +<connect gate="LEB" pin="EX_ADDR[15]" pad="AJ6"/> +<connect gate="LEB" pin="EX_ADDR[16]" pad="AN4"/> +<connect gate="LEB" pin="EX_ADDR[17]" pad="AG7"/> +<connect gate="LEB" pin="EX_ADDR[18]" pad="AM4"/> +<connect gate="LEB" pin="EX_ADDR[19]" pad="AF8"/> +<connect gate="LEB" pin="EX_ADDR[1]" pad="AH9"/> +<connect gate="LEB" pin="EX_ADDR[20]" pad="AH7"/> +<connect gate="LEB" pin="EX_ADDR[21]" pad="AH6"/> +<connect gate="LEB" pin="EX_ADDR[22]" pad="AM3"/> +<connect gate="LEB" pin="EX_ADDR[23]" pad="AJ5"/> +<connect gate="LEB" pin="EX_ADDR[24]" pad="AL3"/> +<connect gate="LEB" pin="EX_ADDR[2]" pad="AK8"/> +<connect gate="LEB" pin="EX_ADDR[3]" pad="AJ9"/> +<connect gate="LEB" pin="EX_ADDR[4]" pad="AM7"/> +<connect gate="LEB" pin="EX_ADDR[5]" pad="AF10"/> +<connect gate="LEB" pin="EX_ADDR[6]" pad="AN6"/> +<connect gate="LEB" pin="EX_ADDR[7]" pad="AG9"/> +<connect gate="LEB" pin="EX_ADDR[8]" pad="AN5"/> +<connect gate="LEB" pin="EX_ADDR[9]" pad="AK5"/> +<connect gate="LEB" pin="EX_ALE" pad="AK4"/> +<connect gate="LEB" pin="EX_BE_N[0]" pad="AN7"/> +<connect gate="LEB" pin="EX_BE_N[1]" pad="AL7"/> +<connect gate="LEB" pin="EX_CLK" pad="AH10"/> +<connect gate="LEBDATA" pin="EX_BURST" pad="AN14"/> +<connect gate="LEBDATA" pin="EX_CS_N[0]" pad="AL10"/> +<connect gate="LEBDATA" pin="EX_CS_N[1]" pad="AN9"/> +<connect gate="LEBDATA" pin="EX_CS_N[2]" pad="AM9"/> +<connect gate="LEBDATA" pin="EX_CS_N[3]" pad="AG10"/> +<connect gate="LEBDATA" pin="EX_CS_N[4]" pad="AN8"/> +<connect gate="LEBDATA" pin="EX_CS_N[5]" pad="AF11"/> +<connect gate="LEBDATA" pin="EX_CS_N[6]" pad="AM8"/> +<connect gate="LEBDATA" pin="EX_CS_N[7]" pad="AJ10"/> +<connect gate="LEBDATA" pin="EX_DATA[0]" pad="AN12"/> +<connect gate="LEBDATA" pin="EX_DATA[10]" pad="AM11"/> +<connect gate="LEBDATA" pin="EX_DATA[11]" pad="AH12"/> +<connect gate="LEBDATA" pin="EX_DATA[12]" pad="AL11"/> +<connect gate="LEBDATA" pin="EX_DATA[13]" pad="AG12"/> +<connect gate="LEBDATA" pin="EX_DATA[14]" pad="AK11"/> +<connect gate="LEBDATA" pin="EX_DATA[15]" pad="AN10"/> +<connect gate="LEBDATA" pin="EX_DATA[1]" pad="AF14"/> +<connect gate="LEBDATA" pin="EX_DATA[2]" pad="AL13"/> +<connect gate="LEBDATA" pin="EX_DATA[3]" pad="AH13"/> +<connect gate="LEBDATA" pin="EX_DATA[4]" pad="AK13"/> +<connect gate="LEBDATA" pin="EX_DATA[5]" pad="AG13"/> +<connect gate="LEBDATA" pin="EX_DATA[6]" pad="AM12"/> +<connect gate="LEBDATA" pin="EX_DATA[7]" pad="AJ13"/> +<connect gate="LEBDATA" pin="EX_DATA[8]" pad="AN11"/> +<connect gate="LEBDATA" pin="EX_DATA[9]" pad="AL12"/> +<connect gate="LEBDATA" pin="EX_IOWAIT_N" pad="AN13"/> +<connect gate="LEBDATA" pin="EX_PARITY[0]" pad="AM14"/> +<connect gate="LEBDATA" pin="EX_PARITY[1]" pad="AL14"/> +<connect gate="LEBDATA" pin="EX_RCOMPN" pad="AG11"/> +<connect gate="LEBDATA" pin="EX_RCOMPP" pad="AJ11"/> +<connect gate="LEBDATA" pin="EX_RDY_N[0]" pad="AM15"/> +<connect gate="LEBDATA" pin="EX_RDY_N[1]" pad="AF15"/> +<connect gate="LEBDATA" pin="EX_RDY_N[2]" pad="AJ15"/> +<connect gate="LEBDATA" pin="EX_RDY_N[3]" pad="AG15"/> +<connect gate="LEBDATA" pin="EX_RD_N" pad="AK14"/> +<connect gate="LEBDATA" pin="EX_WR_N" pad="AN15"/> +<connect gate="LPC11" pin="GP41_LDRQ[1]_N" pad="P6"/> +<connect gate="LPC11" pin="LAD[0]" pad="N6"/> +<connect gate="LPC11" pin="LAD[1]" pad="L5"/> +<connect gate="LPC11" pin="LAD[2]" pad="L3"/> +<connect gate="LPC11" pin="LAD[3]" pad="L4"/> +<connect gate="LPC11" pin="LDRQ[0]_N" pad="L2"/> +<connect gate="LPC11" pin="LFRAME_N" pad="K1"/> +<connect gate="LPC11" pin="PCICLK" pad="N2"/> +<connect gate="MISCSIG" pin="PCIRST_N" pad="G7"/> +<connect gate="MISCSIG" pin="PME_N" pad="B3"/> +<connect gate="MISCSIG" pin="SPKR" pad="P2"/> +<connect gate="NC" pin="NC10" pad="V9"/> +<connect gate="NC" pin="NC11" pad="W9"/> +<connect gate="NC" pin="NC12" pad="G19"/> +<connect gate="NC" pin="NC13" pad="H18"/> +<connect gate="NC" pin="NC14" pad="H19"/> +<connect gate="NC" pin="NC15" pad="G18"/> +<connect gate="NC" pin="NC16" pad="H20"/> +<connect gate="NC" pin="NC17" pad="E28"/> +<connect gate="NC" pin="NC18" pad="F28"/> +<connect gate="NC" pin="NC19" pad="D28"/> +<connect gate="NC" pin="NC20" pad="F12"/> +<connect gate="NC" pin="NC21" pad="B8"/> +<connect gate="NC" pin="NC22" pad="A8"/> +<connect gate="NC" pin="NC34" pad="E29"/> +<connect gate="NC" pin="NC35" pad="C31"/> +<connect gate="NC" pin="NC36" pad="K26"/> +<connect gate="NC" pin="NC37" pad="K27"/> +<connect gate="NC" pin="NC38" pad="D30"/> +<connect gate="NC" pin="NC40" pad="G31"/> +<connect gate="NC" pin="NC41" pad="L33"/> +<connect gate="NC" pin="NC42" pad="P27"/> +<connect gate="NC" pin="NC43" pad="R33"/> +<connect gate="NC" pin="NC44" pad="AA26"/> +<connect gate="NC" pin="NC45" pad="AE31"/> +<connect gate="NC" pin="NC46" pad="AD28"/> +<connect gate="NC" pin="NC47" pad="AJ33"/> +<connect gate="NC" pin="NC48" pad="K25"/> +<connect gate="NC" pin="NC50" pad="E30"/> +<connect gate="NC" pin="NC51" pad="J25"/> +<connect gate="NC" pin="NC52" pad="L27"/> +<connect gate="NC" pin="NC53" pad="AA31"/> +<connect gate="NC" pin="NC54" pad="D29"/> +<connect gate="NC" pin="NC55" pad="AL26"/> +<connect gate="NC" pin="NC56" pad="AE6"/> +<connect gate="NC" pin="NC57" pad="AG14"/> +<connect gate="NC" pin="NC58" pad="AH15"/> +<connect gate="NC" pin="NC59" pad="AD9"/> +<connect gate="NC" pin="NC7" pad="T8"/> +<connect gate="NC" pin="NC9" pad="W8"/> +<connect gate="NC" pin="NC_SUS_TWO" pad="J6"/> +<connect gate="NC" pin="NC_TWO" pad="U3"/> +<connect gate="PCI" pin="PEA0_RN[0]" pad="B27"/> +<connect gate="PCI" pin="PEA0_RN[1]" pad="A26"/> +<connect gate="PCI" pin="PEA0_RN[2]" pad="B25"/> +<connect gate="PCI" pin="PEA0_RN[3]" pad="A24"/> +<connect gate="PCI" pin="PEA0_RN[4]" pad="A19"/> +<connect gate="PCI" pin="PEA0_RN[5]" pad="B20"/> +<connect gate="PCI" pin="PEA0_RN[6]" pad="A17"/> +<connect gate="PCI" pin="PEA0_RN[7]" pad="B18"/> +<connect gate="PCI" pin="PEA0_RP[0]" pad="A27"/> +<connect gate="PCI" pin="PEA0_RP[1]" pad="B26"/> +<connect gate="PCI" pin="PEA0_RP[2]" pad="A25"/> +<connect gate="PCI" pin="PEA0_RP[3]" pad="B24"/> +<connect gate="PCI" pin="PEA0_RP[4]" pad="B19"/> +<connect gate="PCI" pin="PEA0_RP[5]" pad="A20"/> +<connect gate="PCI" pin="PEA0_RP[6]" pad="B17"/> +<connect gate="PCI" pin="PEA0_RP[7]" pad="A18"/> +<connect gate="PCI" pin="PEA0_TN[0]" pad="E27"/> +<connect gate="PCI" pin="PEA0_TN[1]" pad="D26"/> +<connect gate="PCI" pin="PEA0_TN[2]" pad="E25"/> +<connect gate="PCI" pin="PEA0_TN[3]" pad="D24"/> +<connect gate="PCI" pin="PEA0_TN[4]" pad="D19"/> +<connect gate="PCI" pin="PEA0_TN[5]" pad="E20"/> +<connect gate="PCI" pin="PEA0_TN[6]" pad="D17"/> +<connect gate="PCI" pin="PEA0_TN[7]" pad="E18"/> +<connect gate="PCI" pin="PEA0_TP[0]" pad="D27"/> +<connect gate="PCI" pin="PEA0_TP[1]" pad="E26"/> +<connect gate="PCI" pin="PEA0_TP[2]" pad="D25"/> +<connect gate="PCI" pin="PEA0_TP[3]" pad="E24"/> +<connect gate="PCI" pin="PEA0_TP[4]" pad="E19"/> +<connect gate="PCI" pin="PEA0_TP[5]" pad="D20"/> +<connect gate="PCI" pin="PEA0_TP[6]" pad="E17"/> +<connect gate="PCI" pin="PEA0_TP[7]" pad="D18"/> +<connect gate="PCI" pin="PEA_CLKN" pad="D22"/> +<connect gate="PCI" pin="PEA_CLKP" pad="E22"/> +<connect gate="PCI" pin="PEA_ICOMPI" pad="B22"/> +<connect gate="PCI" pin="PEA_ICOMPO" pad="A22"/> +<connect gate="PCI" pin="PEA_RCOMPO" pad="E21"/> +<connect gate="POWERMANAGE" pin="PLTRST_N" pad="A5"/> +<connect gate="POWERMANAGE" pin="PROCHOT_N" pad="T6"/> +<connect gate="POWERMANAGE" pin="PWRBTN_N" pad="H8"/> +<connect gate="POWERMANAGE" pin="PWROK" pad="K6"/> +<connect gate="POWERMANAGE" pin="RI_N" pad="D8"/> +<connect gate="POWERMANAGE" pin="RSMRST_N" pad="G3"/> +<connect gate="POWERMANAGE" pin="SLP_S3_N" pad="A6"/> +<connect gate="POWERMANAGE" pin="SLP_S4_N" pad="C7"/> +<connect gate="POWERMANAGE" pin="SLP_S5_N" pad="H9"/> +<connect gate="POWERMANAGE" pin="SUSCLK" pad="E7"/> +<connect gate="POWERMANAGE" pin="SUS_STAT_N" pad="B6"/> +<connect gate="POWERMANAGE" pin="SYS_RESET_N" pad="D7"/> +<connect gate="POWERMANAGE" pin="THRMTRIP_N" pad="U4"/> +<connect gate="POWERMANAGE" pin="VRMPWRGD" pad="V7"/> +<connect gate="PWR-GBE" pin="VCC25@1" pad="AE20"/> +<connect gate="PWR-GBE" pin="VCC25@2" pad="AJ19"/> +<connect gate="PWR-GBE" pin="VCC25@3" pad="AJ21"/> +<connect gate="PWR-GBE" pin="VCC25@4" pad="AM22"/> +<connect gate="PWR-GBE" pin="VCCGBE33" pad="AE19"/> +<connect gate="PWR-GBE" pin="VCCGBEPSUS" pad="AG20"/> +<connect gate="PWR-GBE" pin="VCCSUS25@1" pad="AE18"/> +<connect gate="PWR-GBE" pin="VCCSUS25@2" pad="AG18"/> +<connect gate="PWR-GBE" pin="VCCSUS25@3" pad="AK18"/> +<connect gate="PWR-GBE" pin="VCCSUS25@4" pad="AM17"/> +<connect gate="PWR-MIS" pin="VCCAHPLL" pad="T19"/> +<connect gate="PWR-MIS" pin="VCCA[1]" pad="G24"/> +<connect gate="PWR-MIS" pin="VCCA[2]" pad="F24"/> +<connect gate="PWR-MIS" pin="VCCPRTC" pad="M5"/> +<connect gate="PWR-MIS" pin="VCCPSUS@1" pad="F10"/> +<connect gate="PWR-MIS" pin="VCCPSUS@2" pad="G11"/> +<connect gate="PWR-MIS" pin="VCCPSUS@3" pad="J11"/> +<connect gate="PWR-MIS" pin="VCCSUS1@1" pad="H10"/> +<connect gate="PWR-MIS" pin="VCCSUS1@2" pad="J10"/> +<connect gate="PWR-MIS" pin="VCCSUS1@3" pad="M9"/> +<connect gate="PWR-MIS" pin="VCCSUS1@4" pad="M10"/> +<connect gate="PWR-MIS" pin="VCCTMP18" pad="N25"/> +<connect gate="PWR-MIS" pin="VSSA" pad="U19"/> +<connect gate="PWR-PCI" pin="VCCABGP033" pad="G15"/> +<connect gate="PWR-PCI" pin="VCCAPE0PLL12@1" pad="F18"/> +<connect gate="PWR-PCI" pin="VCCAPE0PLL12@2" pad="F20"/> +<connect gate="PWR-PCI" pin="VCCAPE@1" pad="A28"/> +<connect gate="PWR-PCI" pin="VCCAPE@10" pad="F25"/> +<connect gate="PWR-PCI" pin="VCCAPE@11" pad="G16"/> +<connect gate="PWR-PCI" pin="VCCAPE@12" pad="G20"/> +<connect gate="PWR-PCI" pin="VCCAPE@2" pad="B21"/> +<connect gate="PWR-PCI" pin="VCCAPE@3" pad="C19"/> +<connect gate="PWR-PCI" pin="VCCAPE@4" pad="C22"/> +<connect gate="PWR-PCI" pin="VCCAPE@5" pad="C24"/> +<connect gate="PWR-PCI" pin="VCCAPE@6" pad="C28"/> +<connect gate="PWR-PCI" pin="VCCAPE@7" pad="F19"/> +<connect gate="PWR-PCI" pin="VCCAPE@8" pad="F21"/> +<connect gate="PWR-PCI" pin="VCCAPE@9" pad="F23"/> +<connect gate="PWR-PCI" pin="VCCRPE@1" pad="B23"/> +<connect gate="PWR-PCI" pin="VCCRPE@2" pad="C18"/> +<connect gate="PWR-PCI" pin="VCCRPE@3" pad="C26"/> +<connect gate="PWR-PCI" pin="VCCRPE@4" pad="D21"/> +<connect gate="PWR-PCI" pin="VCCRPE@5" pad="D23"/> +<connect gate="PWR-PCI" pin="VCCRPE@6" pad="E23"/> +<connect gate="PWR-PCI" pin="VCCRPE@7" pad="F17"/> +<connect gate="PWR-PCI" pin="VCCRPE@8" pad="F22"/> +<connect gate="PWR-SATA" pin="VCCAPLL" pad="C15"/> +<connect gate="PWR-SATA" pin="VCCARX@1" pad="B13"/> +<connect gate="PWR-SATA" pin="VCCARX@2" pad="C14"/> +<connect gate="PWR-SATA" pin="VCCARX@3" pad="F14"/> +<connect gate="PWR-SATA" pin="VCCASATABG3P3" pad="H15"/> +<connect gate="PWR-SATA" pin="VCCATX@1" pad="B16"/> +<connect gate="PWR-SATA" pin="VCCATX@2" pad="C16"/> +<connect gate="PWR-SATA" pin="VCCATX@3" pad="E16"/> +<connect gate="PWR-SATA" pin="VCCSATA33" pad="C13"/> +<connect gate="PWR-SATA" pin="VCCSATA@1" pad="H14"/> +<connect gate="PWR-SATA" pin="VCCSATA@2" pad="J14"/> +<connect gate="PWR-USB" pin="VCC1P2_USBSUS" pad="J12"/> +<connect gate="PWR-USB" pin="VCCABG3P3_USB" pad="H12"/> +<connect gate="PWR-USB" pin="VCCAUSB12@1" pad="D13"/> +<connect gate="PWR-USB" pin="VCCAUSB12@2" pad="F13"/> +<connect gate="PWR-USB" pin="VCCAUSB12@3" pad="J13"/> +<connect gate="PWR-USB" pin="VCCUSB12@1" pad="B7"/> +<connect gate="PWR-USB" pin="VCCUSB12@2" pad="B10"/> +<connect gate="PWR-USB" pin="VCCUSB12@3" pad="C8"/> +<connect gate="PWR-USB" pin="VCCUSB12@4" pad="C11"/> +<connect gate="PWR-USB" pin="VCCUSB12@5" pad="E9"/> +<connect gate="PWR-USB" pin="VCCUSB12@6" pad="F11"/> +<connect gate="PWR-USB" pin="VCCUSB12@7" pad="G10"/> +<connect gate="RESERVED" pin="RESERVED0" pad="AB3"/> +<connect gate="RESERVED" pin="RESERVED1" pad="AC5"/> +<connect gate="RESERVED" pin="RESERVED10" pad="D6"/> +<connect gate="RESERVED" pin="RESERVED11" pad="F3"/> +<connect gate="RESERVED" pin="RESERVED12" pad="AJ16"/> +<connect gate="RESERVED" pin="RESERVED13" pad="AL16"/> +<connect gate="RESERVED" pin="RESERVED14" pad="AM16"/> +<connect gate="RESERVED" pin="RESERVED15" pad="W7"/> +<connect gate="RESERVED" pin="RESERVED16" pad="Y6"/> +<connect gate="RESERVED" pin="RESERVED17" pad="B29"/> +<connect gate="RESERVED" pin="RESERVED18" pad="AB9"/> +<connect gate="RESERVED" pin="RESERVED19" pad="AE15"/> +<connect gate="RESERVED" pin="RESERVED2" pad="AH1"/> +<connect gate="RESERVED" pin="RESERVED20" pad="AJ14"/> +<connect gate="RESERVED" pin="RESERVED3" pad="AB2"/> +<connect gate="RESERVED" pin="RESERVED4" pad="AB6"/> +<connect gate="RESERVED" pin="RESERVED5" pad="AB1"/> +<connect gate="RESERVED" pin="RESERVED6" pad="Y8"/> +<connect gate="RESERVED" pin="RESERVED7" pad="AA7"/> +<connect gate="RESERVED" pin="RESERVED8" pad="AA5"/> +<connect gate="RESERVED" pin="RESERVED9" pad="G21"/> +<connect gate="SATA" pin="GP26_SATA0GP" pad="P1"/> +<connect gate="SATA" pin="GP29_SATA1GP" pad="G4"/> +<connect gate="SATA" pin="SATALED#" pad="J3"/> +<connect gate="SATA" pin="SATA_CLKREFN" pad="G14"/> +<connect gate="SATA" pin="SATA_CLKREFP" pad="G13"/> +<connect gate="SATA" pin="SATA_RBIAS" pad="F15"/> +<connect gate="SATA" pin="SATA_RBIAS#" pad="F16"/> +<connect gate="SATA" pin="SATA_RXN0" pad="B14"/> +<connect gate="SATA" pin="SATA_RXN1" pad="B15"/> +<connect gate="SATA" pin="SATA_RXP0" pad="A14"/> +<connect gate="SATA" pin="SATA_RXP1" pad="A15"/> +<connect gate="SATA" pin="SATA_TXN0" pad="E14"/> +<connect gate="SATA" pin="SATA_TXN1" pad="E15"/> +<connect gate="SATA" pin="SATA_TXP0" pad="D14"/> +<connect gate="SATA" pin="SATA_TXP1" pad="D15"/> +<connect gate="SBUS" pin="CLK48" pad="D11"/> +<connect gate="SBUS" pin="GP11_SMBALERT_N" pad="E4"/> +<connect gate="SBUS" pin="INTRUDER_N" pad="L8"/> +<connect gate="SBUS" pin="OC[0]_N" pad="E12"/> +<connect gate="SBUS" pin="OC[1]_N" pad="D12"/> +<connect gate="SBUS" pin="SMBCLK" pad="C5"/> +<connect gate="SBUS" pin="SMBDATA" pad="G6"/> +<connect gate="SBUS" pin="SMBSCL" pad="Y5"/> +<connect gate="SBUS" pin="SMBSDA" pad="Y1"/> +<connect gate="SBUS" pin="SMLINK[0]" pad="H7"/> +<connect gate="SBUS" pin="SMLINK[1]" pad="B5"/> +<connect gate="SBUS" pin="SPI_CS_N" pad="AF2"/> +<connect gate="SBUS" pin="SPI_MISO" pad="AF1"/> +<connect gate="SBUS" pin="SPI_MOSI" pad="AC8"/> +<connect gate="SBUS" pin="SPI_SCLK" pad="AF3"/> +<connect gate="SBUS" pin="SSP_EXTCLK" pad="AH3"/> +<connect gate="SBUS" pin="SSP_RXD" pad="AF7"/> +<connect gate="SBUS" pin="SSP_SCLK" pad="AJ4"/> +<connect gate="SBUS" pin="SSP_SFRM" pad="AH4"/> +<connect gate="SBUS" pin="SSP_TXD" pad="AK3"/> +<connect gate="SBUS" pin="USBN0" pad="A11"/> +<connect gate="SBUS" pin="USBN1" pad="A12"/> +<connect gate="SBUS" pin="USBP0" pad="B11"/> +<connect gate="SBUS" pin="USBP1" pad="B12"/> +<connect gate="SBUS" pin="USB_RBIASN" pad="A9"/> +<connect gate="SBUS" pin="USB_RBIASP" pad="B9"/> +<connect gate="TDM" pin="RX_CLK0" pad="AC6"/> +<connect gate="TDM" pin="RX_CLK1" pad="AD2"/> +<connect gate="TDM" pin="RX_CLK2" pad="AE5"/> +<connect gate="TDM" pin="RX_DATA_IN0" pad="AE4"/> +<connect gate="TDM" pin="RX_DATA_IN1" pad="AE1"/> +<connect gate="TDM" pin="RX_DATA_IN2" pad="AD7"/> +<connect gate="TDM" pin="RX_FRAME0" pad="AC2"/> +<connect gate="TDM" pin="RX_FRAME1" pad="AB8"/> +<connect gate="TDM" pin="RX_FRAME2" pad="AE3"/> +<connect gate="TDM" pin="TX_CLK0" pad="AB4"/> +<connect gate="TDM" pin="TX_CLK1" pad="AF4"/> +<connect gate="TDM" pin="TX_CLK2" pad="AD5"/> +<connect gate="TDM" pin="TX_DATA_OUT0" pad="AC1"/> +<connect gate="TDM" pin="TX_DATA_OUT1" pad="AA9"/> +<connect gate="TDM" pin="TX_DATA_OUT2" pad="AE2"/> +<connect gate="TDM" pin="TX_FRAME0" pad="AB7"/> +<connect gate="TDM" pin="TX_FRAME1" pad="AD1"/> +<connect gate="TDM" pin="TX_FRAME2" pad="AD6"/> +<connect gate="UART" pin="SIU_CTS1#" pad="R1"/> +<connect gate="UART" pin="SIU_CTS2#" pad="T2"/> +<connect gate="UART" pin="SIU_DCD1#" pad="T5"/> +<connect gate="UART" pin="SIU_DCD2#" pad="T1"/> +<connect gate="UART" pin="SIU_DSR1#" pad="V5"/> +<connect gate="UART" pin="SIU_DSR2#" pad="W4"/> +<connect gate="UART" pin="SIU_DTR1#" pad="U7"/> +<connect gate="UART" pin="SIU_DTR2#" pad="AA2"/> +<connect gate="UART" pin="SIU_RI1#" pad="W3"/> +<connect gate="UART" pin="SIU_RI2#" pad="W1"/> +<connect gate="UART" pin="SIU_RTS1#" pad="U6"/> +<connect gate="UART" pin="SIU_RTS2#" pad="Y4"/> +<connect gate="UART" pin="SIU_RXD1" pad="R3"/> +<connect gate="UART" pin="SIU_RXD2" pad="T4"/> +<connect gate="UART" pin="SIU_TXD1" pad="R2"/> +<connect gate="UART" pin="SIU_TXD2" pad="T3"/> +<connect gate="UART" pin="UART_CLK" pad="U8"/> +<connect gate="VCC" pin="VCC@1" pad="K11"/> +<connect gate="VCC" pin="VCC@10" pad="N12"/> +<connect gate="VCC" pin="VCC@11" pad="N14"/> +<connect gate="VCC" pin="VCC@12" pad="N16"/> +<connect gate="VCC" pin="VCC@13" pad="P11"/> +<connect gate="VCC" pin="VCC@14" pad="P13"/> +<connect gate="VCC" pin="VCC@15" pad="P15"/> +<connect gate="VCC" pin="VCC@16" pad="P17"/> +<connect gate="VCC" pin="VCC@17" pad="R8"/> +<connect gate="VCC" pin="VCC@18" pad="R10"/> +<connect gate="VCC" pin="VCC@19" pad="R12"/> +<connect gate="VCC" pin="VCC@2" pad="K13"/> +<connect gate="VCC" pin="VCC@20" pad="R14"/> +<connect gate="VCC" pin="VCC@21" pad="R16"/> +<connect gate="VCC" pin="VCC@22" pad="T11"/> +<connect gate="VCC" pin="VCC@23" pad="T13"/> +<connect gate="VCC" pin="VCC@24" pad="T15"/> +<connect gate="VCC" pin="VCC@25" pad="T17"/> +<connect gate="VCC" pin="VCC@26" pad="U10"/> +<connect gate="VCC" pin="VCC@27" pad="U12"/> +<connect gate="VCC" pin="VCC@28" pad="U14"/> +<connect gate="VCC" pin="VCC@29" pad="U16"/> +<connect gate="VCC" pin="VCC@3" pad="L10"/> +<connect gate="VCC" pin="VCC@30" pad="U18"/> +<connect gate="VCC" pin="VCC@31" pad="U20"/> +<connect gate="VCC" pin="VCC@32" pad="U22"/> +<connect gate="VCC" pin="VCC@33" pad="U24"/> +<connect gate="VCC" pin="VCC@34" pad="V11"/> +<connect gate="VCC" pin="VCC@35" pad="V13"/> +<connect gate="VCC" pin="VCC@36" pad="V15"/> +<connect gate="VCC" pin="VCC@37" pad="V17"/> +<connect gate="VCC" pin="VCC@38" pad="V19"/> +<connect gate="VCC" pin="VCC@39" pad="V21"/> +<connect gate="VCC" pin="VCC@4" pad="L12"/> +<connect gate="VCC" pin="VCC@40" pad="V23"/> +<connect gate="VCC" pin="VCC@41" pad="W10"/> +<connect gate="VCC" pin="VCC@42" pad="W12"/> +<connect gate="VCC" pin="VCC@43" pad="W14"/> +<connect gate="VCC" pin="VCC@44" pad="W16"/> +<connect gate="VCC" pin="VCC@45" pad="W18"/> +<connect gate="VCC" pin="VCC@46" pad="W20"/> +<connect gate="VCC" pin="VCC@47" pad="W22"/> +<connect gate="VCC" pin="VCC@48" pad="W24"/> +<connect gate="VCC" pin="VCC@49" pad="Y11"/> +<connect gate="VCC" pin="VCC@5" pad="L14"/> +<connect gate="VCC" pin="VCC@50" pad="Y13"/> +<connect gate="VCC" pin="VCC@51" pad="Y15"/> +<connect gate="VCC" pin="VCC@52" pad="Y17"/> +<connect gate="VCC" pin="VCC@53" pad="Y19"/> +<connect gate="VCC" pin="VCC@54" pad="Y21"/> +<connect gate="VCC" pin="VCC@55" pad="Y23"/> +<connect gate="VCC" pin="VCC@56" pad="AA10"/> +<connect gate="VCC" pin="VCC@57" pad="AA12"/> +<connect gate="VCC" pin="VCC@58" pad="AA14"/> +<connect gate="VCC" pin="VCC@59" pad="AA16"/> +<connect gate="VCC" pin="VCC@6" pad="M11"/> +<connect gate="VCC" pin="VCC@60" pad="AA18"/> +<connect gate="VCC" pin="VCC@61" pad="AA20"/> +<connect gate="VCC" pin="VCC@62" pad="AA22"/> +<connect gate="VCC" pin="VCC@63" pad="AA24"/> +<connect gate="VCC" pin="VCC@64" pad="AB11"/> +<connect gate="VCC" pin="VCC@65" pad="AB13"/> +<connect gate="VCC" pin="VCC@66" pad="AB15"/> +<connect gate="VCC" pin="VCC@67" pad="AB17"/> +<connect gate="VCC" pin="VCC@68" pad="AB19"/> +<connect gate="VCC" pin="VCC@69" pad="AB21"/> +<connect gate="VCC" pin="VCC@7" pad="M13"/> +<connect gate="VCC" pin="VCC@70" pad="AB23"/> +<connect gate="VCC" pin="VCC@71" pad="AC10"/> +<connect gate="VCC" pin="VCC@72" pad="AC12"/> +<connect gate="VCC" pin="VCC@73" pad="AC14"/> +<connect gate="VCC" pin="VCC@74" pad="AC16"/> +<connect gate="VCC" pin="VCC@75" pad="AC18"/> +<connect gate="VCC" pin="VCC@76" pad="AC20"/> +<connect gate="VCC" pin="VCC@77" pad="AC22"/> +<connect gate="VCC" pin="VCC@78" pad="AC24"/> +<connect gate="VCC" pin="VCC@79" pad="AD11"/> +<connect gate="VCC" pin="VCC@8" pad="M15"/> +<connect gate="VCC" pin="VCC@80" pad="AD13"/> +<connect gate="VCC" pin="VCC@81" pad="AD15"/> +<connect gate="VCC" pin="VCC@82" pad="AD17"/> +<connect gate="VCC" pin="VCC@83" pad="AD19"/> +<connect gate="VCC" pin="VCC@84" pad="AD21"/> +<connect gate="VCC" pin="VCC@85" pad="AD23"/> +<connect gate="VCC" pin="VCC@9" pad="N10"/> +<connect gate="VCC18" pin="VCC18@1" pad="G30"/> +<connect gate="VCC18" pin="VCC18@10" pad="Y29"/> +<connect gate="VCC18" pin="VCC18@11" pad="AA30"/> +<connect gate="VCC18" pin="VCC18@12" pad="AC30"/> +<connect gate="VCC18" pin="VCC18@13" pad="AD29"/> +<connect gate="VCC18" pin="VCC18@14" pad="AE30"/> +<connect gate="VCC18" pin="VCC18@15" pad="AG30"/> +<connect gate="VCC18" pin="VCC18@16" pad="AH29"/> +<connect gate="VCC18" pin="VCC18@17" pad="AJ30"/> +<connect gate="VCC18" pin="VCC18@18" pad="AK25"/> +<connect gate="VCC18" pin="VCC18@19" pad="AM25"/> +<connect gate="VCC18" pin="VCC18@2" pad="J29"/> +<connect gate="VCC18" pin="VCC18@20" pad="AM31"/> +<connect gate="VCC18" pin="VCC18@3" pad="K30"/> +<connect gate="VCC18" pin="VCC18@4" pad="M30"/> +<connect gate="VCC18" pin="VCC18@5" pad="N29"/> +<connect gate="VCC18" pin="VCC18@6" pad="P30"/> +<connect gate="VCC18" pin="VCC18@7" pad="R27"/> +<connect gate="VCC18" pin="VCC18@8" pad="T25"/> +<connect gate="VCC18" pin="VCC18@9" pad="W30"/> +<connect gate="VCC18" pin="VTTDDR@1" pad="F29"/> +<connect gate="VCC18" pin="VTTDDR@10" pad="AF23"/> +<connect gate="VCC18" pin="VTTDDR@11" pad="AF29"/> +<connect gate="VCC18" pin="VTTDDR@12" pad="AG25"/> +<connect gate="VCC18" pin="VTTDDR@13" pad="AJ25"/> +<connect gate="VCC18" pin="VTTDDR@14" pad="AK29"/> +<connect gate="VCC18" pin="VTTDDR@2" pad="L29"/> +<connect gate="VCC18" pin="VTTDDR@3" pad="V22"/> +<connect gate="VCC18" pin="VTTDDR@4" pad="V24"/> +<connect gate="VCC18" pin="VTTDDR@5" pad="V29"/> +<connect gate="VCC18" pin="VTTDDR@6" pad="AA25"/> +<connect gate="VCC18" pin="VTTDDR@7" pad="AB29"/> +<connect gate="VCC18" pin="VTTDDR@8" pad="AC25"/> +<connect gate="VCC18" pin="VTTDDR@9" pad="AE24"/> +<connect gate="VCC50VCC33" pin="VCC33@1" pad="E5"/> +<connect gate="VCC50VCC33" pin="VCC33@10" pad="AE9"/> +<connect gate="VCC50VCC33" pin="VCC33@11" pad="AF6"/> +<connect gate="VCC50VCC33" pin="VCC33@12" pad="AH11"/> +<connect gate="VCC50VCC33" pin="VCC33@13" pad="AL5"/> +<connect gate="VCC50VCC33" pin="VCC33@14" pad="AL9"/> +<connect gate="VCC50VCC33" pin="VCC33@15" pad="AL15"/> +<connect gate="VCC50VCC33" pin="VCC33@2" pad="H4"/> +<connect gate="VCC50VCC33" pin="VCC33@3" pad="H6"/> +<connect gate="VCC50VCC33" pin="VCC33@4" pad="M4"/> +<connect gate="VCC50VCC33" pin="VCC33@5" pad="R6"/> +<connect gate="VCC50VCC33" pin="VCC33@6" pad="R9"/> +<connect gate="VCC50VCC33" pin="VCC33@7" pad="V4"/> +<connect gate="VCC50VCC33" pin="VCC33@8" pad="AA6"/> +<connect gate="VCC50VCC33" pin="VCC33@9" pad="AD4"/> +<connect gate="VCC50VCC33" pin="VCC50@1" pad="K9"/> +<connect gate="VCC50VCC33" pin="VCC50@2" pad="P9"/> +<connect gate="VCC50VCC33" pin="VCC50@3" pad="U9"/> +<connect gate="VCC50VCC33" pin="VCC50@4" pad="Y9"/> +<connect gate="VCC50VCC33" pin="VCC50@5" pad="AC9"/> +<connect gate="VCC50VCC33" pin="VCC50@6" pad="AE11"/> +<connect gate="VCC50VCC33" pin="VCC50@7" pad="AE14"/> +<connect gate="VCC50VCC33" pin="VCC50_SUS" pad="K4"/> +<connect gate="VCCVC" pin="VCCVC@1" pad="A29"/> +<connect gate="VCCVC" pin="VCCVC@10" pad="J18"/> +<connect gate="VCCVC" pin="VCCVC@11" pad="J20"/> +<connect gate="VCCVC" pin="VCCVC@12" pad="J22"/> +<connect gate="VCCVC" pin="VCCVC@13" pad="J24"/> +<connect gate="VCCVC" pin="VCCVC@14" pad="J26"/> +<connect gate="VCCVC" pin="VCCVC@15" pad="K15"/> +<connect gate="VCCVC" pin="VCCVC@16" pad="K17"/> +<connect gate="VCCVC" pin="VCCVC@17" pad="K19"/> +<connect gate="VCCVC" pin="VCCVC@18" pad="K21"/> +<connect gate="VCCVC" pin="VCCVC@19" pad="K23"/> +<connect gate="VCCVC" pin="VCCVC@2" pad="B30"/> +<connect gate="VCCVC" pin="VCCVC@20" pad="L16"/> +<connect gate="VCCVC" pin="VCCVC@21" pad="L18"/> +<connect gate="VCCVC" pin="VCCVC@22" pad="L20"/> +<connect gate="VCCVC" pin="VCCVC@23" pad="L22"/> +<connect gate="VCCVC" pin="VCCVC@24" pad="L24"/> +<connect gate="VCCVC" pin="VCCVC@25" pad="M17"/> +<connect gate="VCCVC" pin="VCCVC@26" pad="M19"/> +<connect gate="VCCVC" pin="VCCVC@27" pad="M21"/> +<connect gate="VCCVC" pin="VCCVC@28" pad="M23"/> +<connect gate="VCCVC" pin="VCCVC@29" pad="N18"/> +<connect gate="VCCVC" pin="VCCVC@3" pad="G22"/> +<connect gate="VCCVC" pin="VCCVC@30" pad="N20"/> +<connect gate="VCCVC" pin="VCCVC@31" pad="N22"/> +<connect gate="VCCVC" pin="VCCVC@32" pad="N24"/> +<connect gate="VCCVC" pin="VCCVC@33" pad="P19"/> +<connect gate="VCCVC" pin="VCCVC@34" pad="P21"/> +<connect gate="VCCVC" pin="VCCVC@35" pad="P23"/> +<connect gate="VCCVC" pin="VCCVC@36" pad="P25"/> +<connect gate="VCCVC" pin="VCCVC@37" pad="R18"/> +<connect gate="VCCVC" pin="VCCVC@38" pad="R20"/> +<connect gate="VCCVC" pin="VCCVC@39" pad="R22"/> +<connect gate="VCCVC" pin="VCCVC@4" pad="H21"/> +<connect gate="VCCVC" pin="VCCVC@40" pad="R24"/> +<connect gate="VCCVC" pin="VCCVC@41" pad="T21"/> +<connect gate="VCCVC" pin="VCCVC@42" pad="T23"/> +<connect gate="VCCVC" pin="VCCVC@43" pad="T24"/> +<connect gate="VCCVC" pin="VCCVC@44" pad="U23"/> +<connect gate="VCCVC" pin="VCCVC@45" pad="U25"/> +<connect gate="VCCVC" pin="VCCVC@46" pad="U26"/> +<connect gate="VCCVC" pin="VCCVC@5" pad="H23"/> +<connect gate="VCCVC" pin="VCCVC@6" pad="H24"/> +<connect gate="VCCVC" pin="VCCVC@7" pad="H26"/> +<connect gate="VCCVC" pin="VCCVC@8" pad="H27"/> +<connect gate="VCCVC" pin="VCCVC@9" pad="J16"/> +<connect gate="VSSA" pin="VSS@1" pad="A2"/> +<connect gate="VSSA" pin="VSS@10" pad="A31"/> +<connect gate="VSSA" pin="VSS@11" pad="A32"/> +<connect gate="VSSA" pin="VSS@12" pad="A33"/> +<connect gate="VSSA" pin="VSS@13" pad="B1"/> +<connect gate="VSSA" pin="VSS@14" pad="B2"/> +<connect gate="VSSA" pin="VSS@15" pad="B28"/> +<connect gate="VSSA" pin="VSS@16" pad="B32"/> +<connect gate="VSSA" pin="VSS@17" pad="B33"/> +<connect gate="VSSA" pin="VSS@18" pad="C1"/> +<connect gate="VSSA" pin="VSS@19" pad="C2"/> +<connect gate="VSSA" pin="VSS@2" pad="A3"/> +<connect gate="VSSA" pin="VSS@20" pad="C3"/> +<connect gate="VSSA" pin="VSS@21" pad="C4"/> +<connect gate="VSSA" pin="VSS@22" pad="C6"/> +<connect gate="VSSA" pin="VSS@23" pad="C9"/> +<connect gate="VSSA" pin="VSS@24" pad="C10"/> +<connect gate="VSSA" pin="VSS@25" pad="C12"/> +<connect gate="VSSA" pin="VSS@26" pad="C17"/> +<connect gate="VSSA" pin="VSS@27" pad="C20"/> +<connect gate="VSSA" pin="VSS@28" pad="C21"/> +<connect gate="VSSA" pin="VSS@29" pad="C23"/> +<connect gate="VSSA" pin="VSS@3" pad="A7"/> +<connect gate="VSSA" pin="VSS@30" pad="C25"/> +<connect gate="VSSA" pin="VSS@31" pad="C27"/> +<connect gate="VSSA" pin="VSS@32" pad="C29"/> +<connect gate="VSSA" pin="VSS@33" pad="C33"/> +<connect gate="VSSA" pin="VSS@34" pad="D2"/> +<connect gate="VSSA" pin="VSS@35" pad="D3"/> +<connect gate="VSSA" pin="VSS@36" pad="D9"/> +<connect gate="VSSA" pin="VSS@37" pad="D10"/> +<connect gate="VSSA" pin="VSS@38" pad="D16"/> +<connect gate="VSSA" pin="VSS@39" pad="D33"/> +<connect gate="VSSA" pin="VSS@4" pad="A10"/> +<connect gate="VSSA" pin="VSS@40" pad="E1"/> +<connect gate="VSSA" pin="VSS@41" pad="E2"/> +<connect gate="VSSA" pin="VSS@42" pad="E3"/> +<connect gate="VSSA" pin="VSS@43" pad="E6"/> +<connect gate="VSSA" pin="VSS@44" pad="E8"/> +<connect gate="VSSA" pin="VSS@45" pad="E10"/> +<connect gate="VSSA" pin="VSS@46" pad="E11"/> +<connect gate="VSSA" pin="VSS@47" pad="E13"/> +<connect gate="VSSA" pin="VSS@48" pad="F5"/> +<connect gate="VSSA" pin="VSS@49" pad="F6"/> +<connect gate="VSSA" pin="VSS@5" pad="A13"/> +<connect gate="VSSA" pin="VSS@50" pad="F7"/> +<connect gate="VSSA" pin="VSS@51" pad="F8"/> +<connect gate="VSSA" pin="VSS@52" pad="F9"/> +<connect gate="VSSA" pin="VSS@53" pad="F30"/> +<connect gate="VSSA" pin="VSS@54" pad="G8"/> +<connect gate="VSSA" pin="VSS@55" pad="G9"/> +<connect gate="VSSA" pin="VSS@56" pad="G12"/> +<connect gate="VSSA" pin="VSS@57" pad="G17"/> +<connect gate="VSSA" pin="VSS@58" pad="G23"/> +<connect gate="VSSA" pin="VSS@59" pad="G25"/> +<connect gate="VSSA" pin="VSS@6" pad="A16"/> +<connect gate="VSSA" pin="VSS@60" pad="G29"/> +<connect gate="VSSA" pin="VSS@61" pad="H5"/> +<connect gate="VSSA" pin="VSS@62" pad="H11"/> +<connect gate="VSSA" pin="VSS@63" pad="H13"/> +<connect gate="VSSA" pin="VSS@64" pad="H16"/> +<connect gate="VSSA" pin="VSS@65" pad="H17"/> +<connect gate="VSSA" pin="VSS@66" pad="H22"/> +<connect gate="VSSA" pin="VSS@67" pad="H25"/> +<connect gate="VSSA" pin="VSS@68" pad="H29"/> +<connect gate="VSSA" pin="VSS@69" pad="H32"/> +<connect gate="VSSA" pin="VSS@7" pad="A21"/> +<connect gate="VSSA" pin="VSS@70" pad="J2"/> +<connect gate="VSSA" pin="VSS@71" pad="J9"/> +<connect gate="VSSA" pin="VSS@72" pad="J15"/> +<connect gate="VSSA" pin="VSS@73" pad="J17"/> +<connect gate="VSSA" pin="VSS@8" pad="A23"/> +<connect gate="VSSA" pin="VSS@9" pad="A30"/> +<connect gate="VSSB" pin="VSS@1" pad="J19"/> +<connect gate="VSSB" pin="VSS@10" pad="K18"/> +<connect gate="VSSB" pin="VSS@11" pad="K20"/> +<connect gate="VSSB" pin="VSS@12" pad="K22"/> +<connect gate="VSSB" pin="VSS@13" pad="K24"/> +<connect gate="VSSB" pin="VSS@14" pad="K29"/> +<connect gate="VSSB" pin="VSS@15" pad="L9"/> +<connect gate="VSSB" pin="VSS@16" pad="L11"/> +<connect gate="VSSB" pin="VSS@17" pad="L13"/> +<connect gate="VSSB" pin="VSS@18" pad="L15"/> +<connect gate="VSSB" pin="VSS@19" pad="L17"/> +<connect gate="VSSB" pin="VSS@2" pad="J21"/> +<connect gate="VSSB" pin="VSS@20" pad="L19"/> +<connect gate="VSSB" pin="VSS@21" pad="L21"/> +<connect gate="VSSB" pin="VSS@22" pad="L23"/> +<connect gate="VSSB" pin="VSS@23" pad="L25"/> +<connect gate="VSSB" pin="VSS@24" pad="L28"/> +<connect gate="VSSB" pin="VSS@25" pad="L30"/> +<connect gate="VSSB" pin="VSS@26" pad="M3"/> +<connect gate="VSSB" pin="VSS@27" pad="M6"/> +<connect gate="VSSB" pin="VSS@28" pad="M12"/> +<connect gate="VSSB" pin="VSS@29" pad="M14"/> +<connect gate="VSSB" pin="VSS@3" pad="J23"/> +<connect gate="VSSB" pin="VSS@30" pad="M16"/> +<connect gate="VSSB" pin="VSS@31" pad="M18"/> +<connect gate="VSSB" pin="VSS@32" pad="M20"/> +<connect gate="VSSB" pin="VSS@33" pad="M22"/> +<connect gate="VSSB" pin="VSS@34" pad="M24"/> +<connect gate="VSSB" pin="VSS@35" pad="M29"/> +<connect gate="VSSB" pin="VSS@36" pad="N11"/> +<connect gate="VSSB" pin="VSS@37" pad="N13"/> +<connect gate="VSSB" pin="VSS@38" pad="N15"/> +<connect gate="VSSB" pin="VSS@39" pad="N17"/> +<connect gate="VSSB" pin="VSS@4" pad="J30"/> +<connect gate="VSSB" pin="VSS@40" pad="N19"/> +<connect gate="VSSB" pin="VSS@41" pad="N21"/> +<connect gate="VSSB" pin="VSS@42" pad="N23"/> +<connect gate="VSSB" pin="VSS@43" pad="N26"/> +<connect gate="VSSB" pin="VSS@44" pad="N30"/> +<connect gate="VSSB" pin="VSS@45" pad="P10"/> +<connect gate="VSSB" pin="VSS@46" pad="P12"/> +<connect gate="VSSB" pin="VSS@47" pad="P14"/> +<connect gate="VSSB" pin="VSS@48" pad="P16"/> +<connect gate="VSSB" pin="VSS@49" pad="P18"/> +<connect gate="VSSB" pin="VSS@5" pad="K5"/> +<connect gate="VSSB" pin="VSS@50" pad="P20"/> +<connect gate="VSSB" pin="VSS@51" pad="P22"/> +<connect gate="VSSB" pin="VSS@52" pad="P24"/> +<connect gate="VSSB" pin="VSS@53" pad="P26"/> +<connect gate="VSSB" pin="VSS@54" pad="P29"/> +<connect gate="VSSB" pin="VSS@55" pad="P31"/> +<connect gate="VSSB" pin="VSS@56" pad="R4"/> +<connect gate="VSSB" pin="VSS@57" pad="R7"/> +<connect gate="VSSB" pin="VSS@58" pad="R11"/> +<connect gate="VSSB" pin="VSS@59" pad="R13"/> +<connect gate="VSSB" pin="VSS@6" pad="K10"/> +<connect gate="VSSB" pin="VSS@60" pad="R15"/> +<connect gate="VSSB" pin="VSS@61" pad="R17"/> +<connect gate="VSSB" pin="VSS@62" pad="R19"/> +<connect gate="VSSB" pin="VSS@63" pad="R21"/> +<connect gate="VSSB" pin="VSS@64" pad="R23"/> +<connect gate="VSSB" pin="VSS@65" pad="R25"/> +<connect gate="VSSB" pin="VSS@66" pad="R26"/> +<connect gate="VSSB" pin="VSS@67" pad="R28"/> +<connect gate="VSSB" pin="VSS@68" pad="R31"/> +<connect gate="VSSB" pin="VSS@69" pad="T9"/> +<connect gate="VSSB" pin="VSS@7" pad="K12"/> +<connect gate="VSSB" pin="VSS@70" pad="T10"/> +<connect gate="VSSB" pin="VSS@71" pad="T12"/> +<connect gate="VSSB" pin="VSS@72" pad="T14"/> +<connect gate="VSSB" pin="VSS@73" pad="T16"/> +<connect gate="VSSB" pin="VSS@8" pad="K14"/> +<connect gate="VSSB" pin="VSS@9" pad="K16"/> +<connect gate="VSSC" pin="VSS@1" pad="T18"/> +<connect gate="VSSC" pin="VSS@10" pad="V3"/> +<connect gate="VSSC" pin="VSS@11" pad="V6"/> +<connect gate="VSSC" pin="VSS@12" pad="V8"/> +<connect gate="VSSC" pin="VSS@13" pad="V10"/> +<connect gate="VSSC" pin="VSS@14" pad="V12"/> +<connect gate="VSSC" pin="VSS@15" pad="V14"/> +<connect gate="VSSC" pin="VSS@16" pad="V16"/> +<connect gate="VSSC" pin="VSS@17" pad="V18"/> +<connect gate="VSSC" pin="VSS@18" pad="V20"/> +<connect gate="VSSC" pin="VSS@19" pad="V25"/> +<connect gate="VSSC" pin="VSS@2" pad="T20"/> +<connect gate="VSSC" pin="VSS@20" pad="W11"/> +<connect gate="VSSC" pin="VSS@21" pad="W13"/> +<connect gate="VSSC" pin="VSS@22" pad="W15"/> +<connect gate="VSSC" pin="VSS@23" pad="W17"/> +<connect gate="VSSC" pin="VSS@24" pad="W19"/> +<connect gate="VSSC" pin="VSS@25" pad="W21"/> +<connect gate="VSSC" pin="VSS@26" pad="W23"/> +<connect gate="VSSC" pin="VSS@27" pad="W25"/> +<connect gate="VSSC" pin="VSS@28" pad="W29"/> +<connect gate="VSSC" pin="VSS@29" pad="Y10"/> +<connect gate="VSSC" pin="VSS@3" pad="T22"/> +<connect gate="VSSC" pin="VSS@30" pad="Y12"/> +<connect gate="VSSC" pin="VSS@31" pad="Y14"/> +<connect gate="VSSC" pin="VSS@32" pad="Y16"/> +<connect gate="VSSC" pin="VSS@33" pad="Y18"/> +<connect gate="VSSC" pin="VSS@34" pad="Y20"/> +<connect gate="VSSC" pin="VSS@35" pad="Y22"/> +<connect gate="VSSC" pin="VSS@36" pad="Y24"/> +<connect gate="VSSC" pin="VSS@37" pad="Y30"/> +<connect gate="VSSC" pin="VSS@38" pad="AA4"/> +<connect gate="VSSC" pin="VSS@39" pad="AA8"/> +<connect gate="VSSC" pin="VSS@4" pad="T26"/> +<connect gate="VSSC" pin="VSS@40" pad="AA11"/> +<connect gate="VSSC" pin="VSS@41" pad="AA13"/> +<connect gate="VSSC" pin="VSS@42" pad="AA15"/> +<connect gate="VSSC" pin="VSS@43" pad="AA17"/> +<connect gate="VSSC" pin="VSS@44" pad="AA19"/> +<connect gate="VSSC" pin="VSS@45" pad="AA21"/> +<connect gate="VSSC" pin="VSS@46" pad="AA23"/> +<connect gate="VSSC" pin="VSS@47" pad="AA29"/> +<connect gate="VSSC" pin="VSS@48" pad="AB10"/> +<connect gate="VSSC" pin="VSS@49" pad="AB12"/> +<connect gate="VSSC" pin="VSS@5" pad="U11"/> +<connect gate="VSSC" pin="VSS@50" pad="AB14"/> +<connect gate="VSSC" pin="VSS@51" pad="AB16"/> +<connect gate="VSSC" pin="VSS@52" pad="AB18"/> +<connect gate="VSSC" pin="VSS@53" pad="AB20"/> +<connect gate="VSSC" pin="VSS@54" pad="AB22"/> +<connect gate="VSSC" pin="VSS@55" pad="AB24"/> +<connect gate="VSSC" pin="VSS@56" pad="AB25"/> +<connect gate="VSSC" pin="VSS@57" pad="AB30"/> +<connect gate="VSSC" pin="VSS@58" pad="AC7"/> +<connect gate="VSSC" pin="VSS@59" pad="AC11"/> +<connect gate="VSSC" pin="VSS@6" pad="U13"/> +<connect gate="VSSC" pin="VSS@60" pad="AC13"/> +<connect gate="VSSC" pin="VSS@61" pad="AC15"/> +<connect gate="VSSC" pin="VSS@62" pad="AC17"/> +<connect gate="VSSC" pin="VSS@63" pad="AC19"/> +<connect gate="VSSC" pin="VSS@64" pad="AC21"/> +<connect gate="VSSC" pin="VSS@65" pad="AC23"/> +<connect gate="VSSC" pin="VSS@66" pad="AC29"/> +<connect gate="VSSC" pin="VSS@67" pad="AD3"/> +<connect gate="VSSC" pin="VSS@68" pad="AD10"/> +<connect gate="VSSC" pin="VSS@69" pad="AD12"/> +<connect gate="VSSC" pin="VSS@7" pad="U15"/> +<connect gate="VSSC" pin="VSS@70" pad="AD14"/> +<connect gate="VSSC" pin="VSS@71" pad="AD16"/> +<connect gate="VSSC" pin="VSS@72" pad="AD18"/> +<connect gate="VSSC" pin="VSS@73" pad="AD20"/> +<connect gate="VSSC" pin="VSS@8" pad="U17"/> +<connect gate="VSSC" pin="VSS@9" pad="U21"/> +<connect gate="VSSD" pin="VSS@1" pad="AD22"/> +<connect gate="VSSD" pin="VSS@10" pad="AE22"/> +<connect gate="VSSD" pin="VSS@11" pad="AE23"/> +<connect gate="VSSD" pin="VSS@12" pad="AE25"/> +<connect gate="VSSD" pin="VSS@13" pad="AE29"/> +<connect gate="VSSD" pin="VSS@14" pad="AF12"/> +<connect gate="VSSD" pin="VSS@15" pad="AF13"/> +<connect gate="VSSD" pin="VSS@16" pad="AF18"/> +<connect gate="VSSD" pin="VSS@17" pad="AF24"/> +<connect gate="VSSD" pin="VSS@18" pad="AF25"/> +<connect gate="VSSD" pin="VSS@19" pad="AF30"/> +<connect gate="VSSD" pin="VSS@2" pad="AD24"/> +<connect gate="VSSD" pin="VSS@20" pad="AG4"/> +<connect gate="VSSD" pin="VSS@21" pad="AG6"/> +<connect gate="VSSD" pin="VSS@22" pad="AG19"/> +<connect gate="VSSD" pin="VSS@23" pad="AG23"/> +<connect gate="VSSD" pin="VSS@24" pad="AG24"/> +<connect gate="VSSD" pin="VSS@25" pad="AG28"/> +<connect gate="VSSD" pin="VSS@26" pad="AG29"/> +<connect gate="VSSD" pin="VSS@27" pad="AH5"/> +<connect gate="VSSD" pin="VSS@28" pad="AH8"/> +<connect gate="VSSD" pin="VSS@29" pad="AH14"/> +<connect gate="VSSD" pin="VSS@3" pad="AD25"/> +<connect gate="VSSD" pin="VSS@30" pad="AH23"/> +<connect gate="VSSD" pin="VSS@31" pad="AH24"/> +<connect gate="VSSD" pin="VSS@32" pad="AH25"/> +<connect gate="VSSD" pin="VSS@33" pad="AH30"/> +<connect gate="VSSD" pin="VSS@34" pad="AJ2"/> +<connect gate="VSSD" pin="VSS@35" pad="AJ7"/> +<connect gate="VSSD" pin="VSS@36" pad="AJ8"/> +<connect gate="VSSD" pin="VSS@37" pad="AJ12"/> +<connect gate="VSSD" pin="VSS@38" pad="AJ20"/> +<connect gate="VSSD" pin="VSS@39" pad="AJ23"/> +<connect gate="VSSD" pin="VSS@4" pad="AD30"/> +<connect gate="VSSD" pin="VSS@40" pad="AJ24"/> +<connect gate="VSSD" pin="VSS@41" pad="AJ29"/> +<connect gate="VSSD" pin="VSS@42" pad="AK6"/> +<connect gate="VSSD" pin="VSS@43" pad="AK10"/> +<connect gate="VSSD" pin="VSS@44" pad="AK12"/> +<connect gate="VSSD" pin="VSS@45" pad="AK15"/> +<connect gate="VSSD" pin="VSS@46" pad="AK17"/> +<connect gate="VSSD" pin="VSS@47" pad="AK24"/> +<connect gate="VSSD" pin="VSS@48" pad="AK30"/> +<connect gate="VSSD" pin="VSS@49" pad="AK31"/> +<connect gate="VSSD" pin="VSS@5" pad="AE8"/> +<connect gate="VSSD" pin="VSS@50" pad="AK32"/> +<connect gate="VSSD" pin="VSS@51" pad="AK33"/> +<connect gate="VSSD" pin="VSS@52" pad="AL1"/> +<connect gate="VSSD" pin="VSS@53" pad="AL4"/> +<connect gate="VSSD" pin="VSS@54" pad="AL8"/> +<connect gate="VSSD" pin="VSS@55" pad="AL25"/> +<connect gate="VSSD" pin="VSS@56" pad="AL33"/> +<connect gate="VSSD" pin="VSS@57" pad="AM1"/> +<connect gate="VSSD" pin="VSS@58" pad="AM2"/> +<connect gate="VSSD" pin="VSS@59" pad="AM6"/> +<connect gate="VSSD" pin="VSS@6" pad="AE10"/> +<connect gate="VSSD" pin="VSS@60" pad="AM10"/> +<connect gate="VSSD" pin="VSS@61" pad="AM13"/> +<connect gate="VSSD" pin="VSS@62" pad="AM19"/> +<connect gate="VSSD" pin="VSS@63" pad="AM23"/> +<connect gate="VSSD" pin="VSS@64" pad="AM32"/> +<connect gate="VSSD" pin="VSS@65" pad="AM33"/> +<connect gate="VSSD" pin="VSS@66" pad="AN1"/> +<connect gate="VSSD" pin="VSS@67" pad="AN2"/> +<connect gate="VSSD" pin="VSS@68" pad="AN3"/> +<connect gate="VSSD" pin="VSS@69" pad="AN25"/> +<connect gate="VSSD" pin="VSS@7" pad="AE12"/> +<connect gate="VSSD" pin="VSS@70" pad="AN30"/> +<connect gate="VSSD" pin="VSS@71" pad="AN31"/> +<connect gate="VSSD" pin="VSS@72" pad="AN32"/> +<connect gate="VSSD" pin="VSS@73" pad="AN33"/> +<connect gate="VSSD" pin="VSS@8" pad="AE13"/> +<connect gate="VSSD" pin="VSS@9" pad="AE21"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ISL65332" prefix="U" uservalue="yes"> +<gates> +<gate name="ISL6532" symbol="ISL6532" x="0" y="7.62"/> +</gates> +<devices> +<device name="" package="MLF20P"> +<connects> +<connect gate="ISL6532" pin="5VSBY" pad="1"/> +<connect gate="ISL6532" pin="COMP" pad="12"/> +<connect gate="ISL6532" pin="FB" pad="11"/> +<connect gate="ISL6532" pin="GND@1" pad="2"/> +<connect gate="ISL6532" pin="GND@2" pad="13"/> +<connect gate="ISL6532" pin="GND@3" pad="21"/> +<connect gate="ISL6532" pin="LGATE" pad="19"/> +<connect gate="ISL6532" pin="NCH" pad="15"/> +<connect gate="ISL6532" pin="P12V" pad="18"/> +<connect gate="ISL6532" pin="P5VSBY" pad="8"/> +<connect gate="ISL6532" pin="PGOOD" pad="14"/> +<connect gate="ISL6532" pin="S3#" pad="16"/> +<connect gate="ISL6532" pin="S5#" pad="17"/> +<connect gate="ISL6532" pin="UGATE" pad="20"/> +<connect gate="ISL6532" pin="VDDQ@1" pad="5"/> +<connect gate="ISL6532" pin="VDDQ@2" pad="6"/> +<connect gate="ISL6532" pin="VREF-IN" pad="10"/> +<connect gate="ISL6532" pin="VREF-OUT" pad="9"/> +<connect gate="ISL6532" pin="VTT@1" pad="3"/> +<connect gate="ISL6532" pin="VTT@2" pad="4"/> +<connect gate="ISL6532" pin="VTTSNS" pad="7"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="MSP430F22X2" prefix="U"> +<gates> +<gate name="CORE" symbol="MSP430F22X2_COREPORT1" x="5.08" y="24.13" addlevel="must"/> +<gate name="ADC" symbol="MSP430F22X2_OSCADCPORT2" x="7.62" y="-7.62"/> +<gate name="UART" symbol="MSP430F22X2_TIMERUARTPORT3PORT4" x="5.08" y="-40.64"/> +</gates> +<devices> +<device name="TSSOP38" package="TSSOP38"> +<connects> +<connect gate="ADC" pin="AVCC" pad="16"/> +<connect gate="ADC" pin="AVSS" pad="15"/> +<connect gate="ADC" pin="P2.0/ACLK/A0" pad="8"/> +<connect gate="ADC" pin="P2.1/TAINCLK/SMCLK/A1" pad="9"/> +<connect gate="ADC" pin="P2.2/TA0/A2/BSL-RX" pad="10"/> +<connect gate="ADC" pin="P2.3/TA1/A3/VREF-/VEREF-" pad="29"/> +<connect gate="ADC" pin="P2.4/TA2/A4/VREF+/VEREF+" pad="30"/> +<connect gate="ADC" pin="P2.5/ROSC" pad="3"/> +<connect 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length="middle" direction="in" rot="R270"/> +<pin name="VDD@2" x="-21.59" y="13.97" visible="pad" length="middle" direction="in" rot="R270"/> +<pin name="VDD@3" x="-19.05" y="13.97" visible="pad" length="middle" direction="in" rot="R270"/> +<pin name="VDD@4" x="-16.51" y="13.97" visible="pad" length="middle" direction="in" rot="R270"/> +<pin name="VDD@5" x="-13.97" y="13.97" visible="pad" length="middle" direction="in" rot="R270"/> +<pin name="VDD@6" x="-11.43" y="13.97" visible="pad" length="middle" direction="in" rot="R270"/> +<pin name="VDD@7" x="-8.89" y="13.97" visible="pad" length="middle" direction="in" rot="R270"/> +<pin name="VDD@8" x="-6.35" y="13.97" visible="pad" length="middle" direction="in" rot="R270"/> +<pin name="GND@1" x="-24.13" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@2" x="-21.59" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@3" x="-19.05" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@4" x="-16.51" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@5" x="-13.97" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@6" x="-11.43" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@7" x="-8.89" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@8" x="-6.35" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@9" x="-3.81" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@10" x="-1.27" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@11" x="1.27" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="GND@12" x="3.81" y="-12.7" visible="pad" length="middle" direction="in" rot="R90"/> +<pin name="NC@1" x="3.81" y="11.43" visible="pad" length="short" direction="pas" rot="R270"/> +<pin name="NC@2" x="6.35" y="11.43" visible="pad" length="short" direction="pas" rot="R270"/> +<pin name="NC@3" x="8.89" y="11.43" visible="pad" length="short" direction="pas" rot="R270"/> +<pin name="NC@4" x="11.43" y="11.43" visible="pad" length="short" direction="pas" rot="R270"/> +<pin name="NC@5" x="13.97" y="11.43" visible="pad" length="short" direction="pas" rot="R270"/> +<pin name="NC@6" x="16.51" y="11.43" visible="pad" length="short" direction="pas" rot="R270"/> +<pin name="NC@7" x="8.89" y="-10.16" visible="pad" length="short" direction="pas" rot="R90"/> +<pin name="NC@8" x="11.43" y="-10.16" visible="pad" length="short" direction="pas" rot="R90"/> +<pin name="NC@9" x="13.97" y="-10.16" visible="pad" length="short" direction="pas" rot="R90"/> +<pin name="NC@10" x="16.51" y="-10.16" visible="pad" length="short" direction="pas" rot="R90"/> +<pin name="NC@11" x="19.05" y="-10.16" visible="pad" length="short" direction="pas" rot="R90"/> +<pin name="NC@12" x="21.59" y="-10.16" visible="pad" length="short" direction="pas" rot="R90"/> +<pin name="NC@13" x="19.05" y="11.43" visible="pad" length="short" direction="pas" rot="R270"/> +<pin name="VDD@9" x="-3.81" y="13.97" visible="pad" length="middle" direction="in" rot="R270"/> +<pin name="VDD@10" x="-1.27" y="13.97" visible="pad" length="middle" direction="in" rot="R270"/> +</symbol> +<symbol name="XHFC-STUP0"> +<wire x1="10.16" y1="-12.7" x2="10.16" y2="16.51" width="0.4064" layer="94"/> +<wire x1="-10.16" y1="16.51" x2="10.16" y2="16.51" width="0.4064" layer="94"/> +<wire x1="-10.16" y1="16.51" x2="-10.16" y2="-12.7" width="0.4064" layer="94"/> +<wire x1="10.16" y1="-12.7" x2="-10.16" y2="-12.7" width="0.4064" layer="94"/> +<text x="-10.16" y="-15.24" size="1.778" layer="96">>VALUE</text> +<text x="-10.16" y="17.145" size="1.778" layer="95">>NAME</text> +<text x="-7.62" y="13.97" size="1.778" layer="94">XHFC ST/UP 0</text> +<pin name="T_B0/GPIO17" x="15.24" y="7.62" length="middle" swaplevel="7" rot="R180"/> +<pin name="T_A0/GPIO16" x="15.24" y="5.08" length="middle" swaplevel="8" rot="R180"/> +<pin name="ADJ_0" x="15.24" y="1.27" length="middle" direction="oc" swaplevel="9" rot="R180"/> +<pin name="R_B0/GPIO11" x="15.24" y="-10.16" length="middle" swaplevel="10" rot="R180"/> +<pin name="L_B0/GPIO10" x="15.24" y="-7.62" length="middle" swaplevel="11" rot="R180"/> +<pin name="L_A0/GPIO9" x="15.24" y="-5.08" length="middle" swaplevel="12" rot="R180"/> +<pin name="R_A0/GPIO8" x="15.24" y="-2.54" length="middle" swaplevel="13" rot="R180"/> +<pin name="VDD_SU0" x="15.24" y="11.43" length="middle" direction="in" swaplevel="23" rot="R180"/> +</symbol> +<symbol name="XHFC-STUP1"> +<wire x1="10.16" y1="-13.97" x2="10.16" y2="15.24" width="0.4064" layer="94"/> +<wire x1="-10.16" y1="15.24" x2="10.16" y2="15.24" width="0.4064" layer="94"/> +<wire x1="-10.16" y1="15.24" x2="-10.16" y2="-13.97" width="0.4064" layer="94"/> +<wire x1="10.16" y1="-13.97" x2="-10.16" y2="-13.97" width="0.4064" layer="94"/> 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width="0.4064" layer="94"/> +<wire x1="-10.16" y1="15.24" x2="10.16" y2="15.24" width="0.4064" layer="94"/> +<wire x1="-10.16" y1="15.24" x2="-10.16" y2="-13.97" width="0.4064" layer="94"/> +<wire x1="10.16" y1="-13.97" x2="-10.16" y2="-13.97" width="0.4064" layer="94"/> +<text x="-10.16" y="-16.51" size="1.778" layer="96">>VALUE</text> +<text x="-10.16" y="15.875" size="1.778" layer="95">>NAME</text> +<text x="-7.62" y="12.7" size="1.778" layer="94">XHFC ST/UP 2</text> +<pin name="VDD_SU2" x="15.24" y="10.16" length="middle" direction="in" swaplevel="23" rot="R180"/> +<pin name="T_B2/GPIO21" x="15.24" y="6.35" length="middle" swaplevel="22" rot="R180"/> +<pin name="T_A2/GPIO20" x="15.24" y="3.81" length="middle" swaplevel="23" rot="R180"/> +<pin name="ADJ_2" x="15.24" y="0" length="middle" direction="oc" swaplevel="24" rot="R180"/> +<pin name="R_B2/GPIO27" x="15.24" y="-11.43" length="middle" swaplevel="25" rot="R180"/> +<pin name="L_B2/GPIO26" x="15.24" y="-8.89" length="middle" swaplevel="26" rot="R180"/> +<pin name="L_A2/GPIO25" x="15.24" y="-6.35" length="middle" swaplevel="27" rot="R180"/> +<pin name="R_A2/GPIO24" x="15.24" y="-3.81" length="middle" swaplevel="28" rot="R180"/> +</symbol> +<symbol name="XHFC-STUP3"> +<wire x1="11.43" y1="-13.97" x2="11.43" y2="15.24" width="0.4064" layer="94"/> +<wire x1="-8.89" y1="15.24" x2="11.43" y2="15.24" width="0.4064" layer="94"/> +<wire x1="-8.89" y1="15.24" x2="-8.89" y2="-13.97" width="0.4064" layer="94"/> +<wire x1="11.43" y1="-13.97" x2="-8.89" y2="-13.97" width="0.4064" layer="94"/> +<text x="-8.89" y="-16.51" size="1.778" layer="96">>VALUE</text> +<text x="-8.89" y="15.875" size="1.778" layer="95">>NAME</text> +<text x="-6.35" y="12.7" size="1.778" layer="94">XHFC ST/UP 3</text> +<pin name="VDD_SU3" x="16.51" y="10.16" length="middle" direction="in" swaplevel="23" rot="R180"/> +<pin name="R_A3/GPIO31" x="16.51" y="-3.81" length="middle" swaplevel="14" rot="R180"/> +<pin name="L_A3/GPIO30" x="16.51" y="-6.35" length="middle" swaplevel="15" rot="R180"/> +<pin name="L_B3/GPIO29" x="16.51" y="-8.89" length="middle" swaplevel="16" rot="R180"/> +<pin name="R_B3/GPIO28" x="16.51" y="-11.43" length="middle" swaplevel="17" rot="R180"/> +<pin name="ADJ_3" x="16.51" y="0" length="middle" direction="oc" swaplevel="18" rot="R180"/> +<pin name="T_A3/GPIO23" x="16.51" y="3.81" length="middle" swaplevel="19" rot="R180"/> +<pin name="T_B3/GPIO22" x="16.51" y="6.35" length="middle" swaplevel="20" rot="R180"/> +</symbol> +<symbol name="XHFC-CLK"> +<wire x1="16.51" y1="-6.985" x2="16.51" y2="8.89" width="0.4064" layer="94"/> +<wire x1="-7.62" y1="8.89" x2="16.51" y2="8.89" width="0.4064" layer="94"/> +<wire x1="-7.62" y1="8.89" x2="-7.62" y2="-6.985" width="0.4064" layer="94"/> +<wire x1="16.51" y1="-6.985" x2="-7.62" y2="-6.985" width="0.4064" layer="94"/> +<text x="6.35" y="9.525" size="1.778" layer="96">>VALUE</text> +<text x="-7.62" y="9.525" size="1.778" layer="95">>NAME</text> +<text x="-3.81" y="-6.35" size="1.778" layer="94" rot="R90">XHFC Clock</text> +<pin name="OSC_IN" x="21.59" y="-5.08" length="middle" direction="in" swaplevel="9" rot="R180"/> +<pin name="OSC_OUT" x="21.59" y="-1.27" length="middle" direction="out" swaplevel="10" rot="R180"/> +<pin name="CLK_OUT/GPIO7" x="21.59" y="2.54" length="middle" direction="out" swaplevel="11" rot="R180"/> +<pin name="WAKEUP//WD" x="21.59" y="6.35" length="middle" direction="in" swaplevel="10" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="RJ45-8" prefix="J"> +<description><b>FICHE FEMELLE MODULAIRE CI 8 VOIES</b> +<li>Type de connecteur: RJ45</li> +<li>Genre: Embase</li> +<li>Nombre de contacts: 8</li> +<li>Nombre de positions: 8</li> +<li>Nombre de ports: 1</li> +<li>Catégorie LAN: Cat3</li> +<li> +<a href="http://www.farnell.com/datasheets/8292.pdf" > Data Sheet (182.20KB)</a> +</li></description> +<gates> +<gate name="J" symbol="RJ45-8" x="-2.54" y="0"/> +</gates> +<devices> +<device name="RJ45-8" package="RJ45_8"> +<connects> +<connect gate="J" pin="1" pad="1"/> +<connect gate="J" pin="2" pad="2"/> +<connect gate="J" pin="3" pad="3"/> +<connect gate="J" pin="4" pad="4"/> +<connect gate="J" pin="5" pad="5"/> +<connect gate="J" pin="6" pad="6"/> +<connect gate="J" pin="7" pad="7"/> +<connect gate="J" pin="8" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MOLEX" value="95501-2881" constant="no"/> +<attribute name="REF" value="1524544" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="ISDN-DUAL-TRANS" prefix="TR"> +<gates> +<gate name="A" symbol="ISDN-TRANS" x="-15.24" y="0"/> +<gate name="B" symbol="ISDN-TRANS" x="16.51" y="0"/> +</gates> +<devices> +<device name="" package="ISDNDUALTRANS"> +<connects> +<connect gate="A" pin="P11" pad="1"/> +<connect gate="A" pin="P12" pad="2"/> +<connect gate="A" pin="P21" pad="3"/> +<connect gate="A" pin="P22" pad="4"/> +<connect gate="A" pin="S11" pad="16"/> +<connect gate="A" pin="S12" pad="15"/> +<connect gate="A" pin="S21" pad="14"/> +<connect gate="A" pin="S22" pad="13"/> +<connect gate="B" pin="P11" pad="5"/> +<connect gate="B" pin="P12" pad="6"/> +<connect gate="B" pin="P21" pad="7"/> +<connect gate="B" pin="P22" pad="8"/> +<connect gate="B" pin="S11" pad="12"/> +<connect gate="B" pin="S12" pad="11"/> +<connect gate="B" pin="S21" pad="10"/> +<connect gate="B" pin="S22" pad="9"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="BC847CD" prefix="Q"> +<gates> +<gate name="A" symbol="NPN" x="-10.16" y="6.35" swaplevel="1"/> +<gate name="B" symbol="NPN" x="13.97" y="7.62" swaplevel="1"/> +</gates> +<devices> +<device name="" package="SOT563-6L"> +<connects> +<connect gate="A" pin="B" pad="5"/> +<connect gate="A" pin="C" pad="3"/> +<connect gate="A" pin="E" pad="4"/> +<connect gate="B" pin="B" pad="2"/> +<connect gate="B" pin="C" pad="6"/> +<connect gate="B" pin="E" pad="1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="SWITCH" prefix="U" uservalue="yes"> +<gates> +<gate name="S" symbol="SWITCH" x="0" y="0"/> +<gate name="PWR" symbol="SWITCH-PWR" x="19.05" y="0" addlevel="must"/> +</gates> +<devices> +<device name="" package="SC70-6L"> +<connects> +<connect gate="PWR" pin="G" pad="2"/> +<connect gate="PWR" pin="V" pad="5"/> +<connect gate="S" pin="S" pad="6"/> +<connect gate="S" pin="Y0" pad="3"/> +<connect gate="S" pin="Y1" pad="1"/> +<connect gate="S" pin="Z" pad="4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="BAV99DW" prefix="D"> +<gates> +<gate name="F" symbol="BAV99DW" x="-1.27" y="0"/> +</gates> +<devices> +<device name="" package="SC70-6L"> +<connects> +<connect gate="F" pin="A1" pad="1"/> +<connect gate="F" pin="A2" pad="4"/> +<connect gate="F" pin="AC1" pad="6"/> +<connect gate="F" pin="AC2" pad="3"/> +<connect gate="F" pin="C1" pad="2"/> +<connect gate="F" pin="C2" pad="5"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="CRYSTAL" prefix="Q" uservalue="yes"> +<description><b>CRYSTAL</b></description> +<gates> +<gate name="G$1" symbol="Q" x="0" y="0"/> +</gates> +<devices> +<device name="HC49S" package="HC49S"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="HC49GW" package="HC49GW"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="HC49TL-H" package="HC49TL-H"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="HC49U-H" package="HC49U-H"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="HC49U-LM" package="HC49U-LM"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="HC49U-V" package="HC49U-V"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="HC49U70" package="HC49U70"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="HC49UP" package="HC49UP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" 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device="R0402-C" value="22"> +<attribute name="POWER" value="1/16W"/> +</part> +<part name="RF7" library="PbxLRCDTA" deviceset="R-EU_" device="R0402-C" value="22"> +<attribute name="POWER" value="1/16W"/> +</part> +<part name="RF8" library="PbxLRCDTA" deviceset="R-EU_" device="R0402-C" value="22"> +<attribute name="POWER" value="1/16W"/> +</part> +<part name="RF9" library="PbxLRCDTA" deviceset="R-EU_" device="R0402-C" value="1k"> +<attribute name="POWER" value="1/16W"/> +<attribute name="TOLERANCE" value="1%"/> +</part> +<part name="RF3" library="PbxLRCDTA" deviceset="R-EU_" device="R0402-C" value="0"> +<attribute name="DNP" value="DNP"/> +<attribute name="POWER" value="1/16W"/> +</part> +<part name="DFSB1" library="PbxLRCDTA" deviceset="DIODE_SMALLSIGNAL" device="" value="FDLL4148"/> +<part name="CFSG2" library="PbxFX" deviceset="C-EU" device="0805LF" value="100nF"/> +<part name="U$108" library="PbxLRCDTA" deviceset="GND-CHASSIS" device=""/> +<part name="C13" library="PbxLRCDTA" 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deviceset="TESTPOINT" device="TESTPT-2X2" value="TP"> +<attribute name="DNP" value="DNP"/> +</part> +<part name="R3R18" library="PbxLRCDTA" deviceset="R-EU_" device="R0603-C" value="10k"> +<attribute name="POWER" value="1/10W"/> +</part> +<part name="U$134" library="PbxLRCDTA" deviceset="GND" device=""/> +</parts> +<sheets> +<sheet> +<plain> +<text x="107.95" y="172.72" size="3.81" layer="94">Power Management</text> +<text x="143.51" y="132.08" size="2.54" layer="94">JUST STARTED</text> +</plain> +<instances> +<instance part="U$551" gate="G$1" x="11.43" y="22.86"/> +<instance part="U$557" gate="G$1" x="73.66" y="30.48" rot="R270"/> +<instance part="U$590" gate="G$1" x="148.59" y="72.39" rot="R90"/> +<instance part="U$602" gate="G$1" x="118.11" y="68.58" rot="R90"/> +<instance part="U$603" gate="G$1" x="172.72" y="59.69" rot="MR0"/> +<instance part="LED14" gate="DL" x="125.73" y="33.02" smashed="yes" rot="MR90"> +<attribute name="NAME" x="122.555" y="39.6875" size="1.778" layer="95" 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size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="SV1" gate="1" pin="5"/> +</segment> +</net> +<net name="TDI" class="0"> +<segment> +<wire x1="128.27" y1="55.88" x2="113.03" y2="55.88" width="0.1524" layer="91"/> +<label x="128.27" y="55.88" size="1.778" layer="92" xref="yes"/> +<pinref part="U10" gate="CORE" pin="P1.6/TA1/TDI"/> +</segment> +<segment> +<wire x1="88.9" y1="38.1" x2="85.09" y2="38.1" width="0.1524" layer="91"/> +<label x="85.09" y="38.1" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="SV1" gate="1" pin="3"/> +</segment> +</net> +<net name="TDO/TDI" class="0"> +<segment> +<wire x1="128.27" y1="52.07" x2="113.03" y2="52.07" width="0.1524" layer="91"/> +<label x="128.27" y="52.07" size="1.778" layer="92" xref="yes"/> +<pinref part="U10" gate="CORE" pin="P1.7/TA2/TDO/TDI"/> +</segment> +<segment> +<wire x1="88.9" y1="40.64" x2="74.93" y2="40.64" width="0.1524" layer="91"/> +<label x="74.93" y="40.64" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="SV1" gate="1" pin="1"/> +</segment> +</net> +<net name="MSP-BSL-RST" class="0"> +<segment> +<wire x1="11.43" y1="39.37" x2="11.43" y2="36.83" width="0.1524" layer="91"/> +<wire x1="57.15" y1="46.99" x2="57.15" y2="36.83" width="0.1524" layer="91"/> +<wire x1="57.15" y1="36.83" x2="11.43" y2="36.83" width="0.1524" layer="91"/> +<wire x1="11.43" y1="36.83" x2="11.43" y2="33.02" width="0.1524" layer="91"/> +<wire x1="57.15" y1="36.83" x2="57.15" y2="27.94" width="0.1524" layer="91"/> +<wire x1="57.15" y1="27.94" x2="40.64" y2="27.94" width="0.1524" layer="91"/> +<junction x="11.43" y="36.83"/> +<junction x="57.15" y="36.83"/> +<label x="40.64" y="27.94" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="U10" gate="CORE" pin="RST/NMI/SBWTDIO"/> +<wire x1="57.15" y1="27.94" x2="88.9" y2="27.94" width="0.1524" layer="91"/> +<junction x="57.15" y="27.94"/> +<pinref part="R87" gate="R" pin="1"/> +<pinref part="C1" gate="C" pin="2"/> +<pinref part="SV1" gate="1" pin="11"/> +</segment> +</net> +<net name="GND" class="0"> +<segment> +<wire x1="116.84" y1="68.58" x2="113.03" y2="68.58" width="0.1524" layer="91"/> +<pinref part="U$602" gate="G$1" pin="GND"/> +<pinref part="U10" gate="CORE" pin="DVSS"/> +</segment> +<segment> +<wire x1="147.32" y1="72.39" x2="143.51" y2="72.39" width="0.1524" layer="91"/> +<pinref part="U$590" gate="G$1" pin="GND"/> +<pinref part="C12" gate="C" pin="2"/> +<wire x1="143.51" y1="72.39" x2="133.35" y2="72.39" width="0.1524" layer="91"/> +<wire x1="133.35" y1="78.74" x2="143.51" y2="78.74" width="0.1524" layer="91"/> +<wire x1="143.51" y1="78.74" x2="143.51" y2="72.39" width="0.1524" layer="91"/> +<junction x="143.51" y="72.39"/> +<pinref part="C9" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="74.93" y1="30.48" x2="88.9" y2="30.48" width="0.1524" layer="91"/> +<pinref part="U$557" gate="G$1" pin="GND"/> +<pinref part="SV1" gate="1" pin="9"/> +</segment> +<segment> +<wire x1="172.72" y1="60.96" x2="173.99" y2="60.96" width="0.1524" layer="91"/> +<pinref part="U$603" gate="G$1" pin="GND"/> +<pinref part="U10" gate="ADC" pin="AVSS"/> +</segment> +<segment> +<wire x1="11.43" y1="24.13" x2="11.43" y2="25.4" width="0.1524" layer="91"/> +<pinref part="U$551" gate="G$1" pin="GND"/> +<pinref part="C1" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="19.05" y1="76.2" x2="20.32" y2="76.2" width="0.1524" layer="91"/> +<wire x1="20.32" y1="76.2" x2="20.32" y2="78.74" width="0.1524" layer="91"/> +<wire x1="20.32" y1="78.74" x2="21.59" y2="78.74" width="0.1524" layer="91"/> +<wire x1="21.59" y1="73.66" x2="20.32" y2="73.66" width="0.1524" layer="91"/> +<wire x1="20.32" y1="73.66" x2="20.32" y2="76.2" width="0.1524" layer="91"/> +<junction x="20.32" y="76.2"/> +<pinref part="SW1" gate="PB" pin="3"/> +<pinref part="U$651" gate="G$1" pin="GND"/> +<pinref part="SW1" gate="PB" pin="4"/> +</segment> +<segment> +<wire x1="19.05" y1="48.26" x2="20.32" y2="48.26" width="0.1524" layer="91"/> +<wire x1="20.32" y1="48.26" x2="20.32" y2="50.8" width="0.1524" layer="91"/> +<wire x1="20.32" y1="50.8" x2="21.59" y2="50.8" width="0.1524" layer="91"/> +<wire x1="21.59" y1="45.72" x2="20.32" y2="45.72" width="0.1524" layer="91"/> +<wire x1="20.32" y1="45.72" x2="20.32" y2="48.26" width="0.1524" layer="91"/> +<junction x="20.32" y="48.26"/> +<pinref part="SW2" gate="PB" pin="3"/> +<pinref part="U$652" gate="G$1" pin="GND"/> +<pinref part="SW2" gate="PB" pin="4"/> +</segment> +<segment> +<pinref part="U$52" gate="G$1" pin="GND"/> +<wire x1="119.38" y1="33.02" x2="120.65" y2="33.02" width="0.1524" layer="91"/> +<wire x1="120.65" y1="33.02" x2="120.65" y2="34.29" width="0.1524" layer="91"/> +<pinref part="LED14" gate="DL" pin="K2"/> +<wire x1="120.65" y1="34.29" x2="121.92" y2="34.29" width="0.1524" layer="91"/> +<wire x1="120.65" y1="33.02" x2="120.65" y2="31.75" width="0.1524" layer="91"/> +<junction x="120.65" y="33.02"/> +<pinref part="LED14" gate="DL" pin="K1"/> +<wire x1="120.65" y1="31.75" x2="121.92" y2="31.75" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U11" gate="G" pin="DGND"/> +<pinref part="U$61" gate="G$1" pin="GND"/> +<wire x1="166.37" y1="22.86" x2="166.37" y2="24.13" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C3" gate="C" pin="1"/> +<pinref part="U$181" gate="G$1" pin="GND"/> +<wire x1="26.67" y1="120.65" x2="27.94" y2="120.65" width="0.1524" layer="91"/> +<pinref part="R88" gate="R" pin="1"/> +<wire x1="27.94" y1="120.65" x2="27.94" y2="119.38" width="0.1524" layer="91"/> +<wire x1="27.94" y1="119.38" x2="33.02" y2="119.38" width="0.1524" layer="91"/> +<wire x1="31.75" y1="123.19" x2="27.94" y2="123.19" width="0.1524" layer="91"/> +<wire x1="27.94" y1="123.19" x2="27.94" y2="120.65" width="0.1524" layer="91"/> +<junction x="27.94" y="120.65"/> +</segment> +<segment> +<pinref part="C4" gate="C" pin="1"/> +<pinref part="U$182" gate="G$1" pin="GND"/> +<wire x1="55.88" y1="116.84" x2="57.15" y2="116.84" width="0.1524" layer="91"/> +<pinref part="R92" gate="R" pin="1"/> +<wire x1="57.15" y1="116.84" x2="57.15" y2="115.57" width="0.1524" layer="91"/> +<wire x1="57.15" y1="115.57" x2="59.69" y2="115.57" width="0.1524" layer="91"/> +<wire x1="58.42" y1="119.38" x2="57.15" y2="119.38" width="0.1524" layer="91"/> +<wire x1="57.15" y1="119.38" x2="57.15" y2="116.84" width="0.1524" layer="91"/> +<junction x="57.15" y="116.84"/> +</segment> +<segment> +<pinref part="C6" gate="C" pin="1"/> +<pinref part="U$183" gate="G$1" pin="GND"/> +<wire x1="26.67" y1="107.95" x2="27.94" y2="107.95" width="0.1524" layer="91"/> +<pinref part="R94" gate="R" pin="1"/> +<wire x1="27.94" y1="107.95" x2="27.94" y2="106.68" width="0.1524" layer="91"/> +<wire x1="27.94" y1="106.68" x2="33.02" y2="106.68" width="0.1524" layer="91"/> +<wire x1="31.75" y1="110.49" x2="27.94" y2="110.49" width="0.1524" layer="91"/> +<wire x1="27.94" y1="110.49" x2="27.94" y2="107.95" width="0.1524" layer="91"/> +<junction x="27.94" y="107.95"/> +</segment> +<segment> +<pinref part="C7" gate="C" pin="1"/> +<pinref part="U$186" gate="G$1" pin="GND"/> +<wire x1="55.88" y1="104.14" x2="57.15" y2="104.14" width="0.1524" layer="91"/> +<pinref part="R96" gate="R" pin="1"/> +<wire x1="57.15" y1="104.14" x2="57.15" y2="102.87" width="0.1524" layer="91"/> +<wire x1="57.15" y1="102.87" x2="59.69" y2="102.87" width="0.1524" layer="91"/> +<wire x1="58.42" y1="106.68" x2="57.15" y2="106.68" width="0.1524" layer="91"/> +<wire x1="57.15" y1="106.68" x2="57.15" y2="104.14" width="0.1524" layer="91"/> +<junction x="57.15" y="104.14"/> +</segment> +<segment> +<pinref part="C10" gate="C" pin="1"/> +<pinref part="U$193" gate="G$1" pin="GND"/> +<wire x1="219.71" y1="135.89" x2="217.17" y2="135.89" width="0.1524" layer="91"/> +<pinref part="R98" gate="R" pin="1"/> +<wire x1="217.17" y1="135.89" x2="217.17" y2="132.08" width="0.1524" layer="91"/> +<wire x1="217.17" y1="132.08" x2="212.09" y2="132.08" width="0.1524" layer="91"/> +<wire x1="213.36" y1="138.43" x2="217.17" y2="138.43" width="0.1524" layer="91"/> +<wire x1="217.17" y1="138.43" x2="217.17" y2="135.89" width="0.1524" layer="91"/> +<junction x="217.17" y="135.89"/> +</segment> +<segment> +<pinref part="R13" gate="R" pin="1"/> +<pinref part="U$95" gate="G$1" pin="GND"/> +<wire x1="99.06" y1="121.92" x2="106.68" y2="121.92" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$73" class="0"> +<segment> +<wire x1="36.83" y1="78.74" x2="38.1" y2="78.74" width="0.1524" layer="91"/> +<wire x1="38.1" y1="78.74" x2="38.1" y2="76.2" width="0.1524" layer="91"/> +<wire x1="38.1" y1="76.2" x2="38.1" y2="73.66" width="0.1524" layer="91"/> +<wire x1="38.1" y1="73.66" x2="36.83" y2="73.66" width="0.1524" layer="91"/> +<pinref part="SW1" gate="PB" pin="2"/> +<pinref part="SW1" gate="PB" pin="1"/> +<wire x1="31.75" y1="83.82" x2="38.1" y2="83.82" width="0.1524" layer="91"/> +<pinref part="R23" gate="R" pin="2"/> +<wire x1="38.1" y1="78.74" x2="38.1" y2="83.82" width="0.1524" layer="91"/> +<junction x="38.1" y="78.74"/> +<wire x1="38.1" y1="73.66" x2="55.88" y2="73.66" width="0.1524" layer="91"/> +<junction x="38.1" y="73.66"/> +<pinref part="U10" gate="CORE" pin="P1.0/TACLK/ADC10CLK"/> +<wire x1="55.88" y1="73.66" x2="55.88" y2="67.31" width="0.1524" layer="91"/> +<wire x1="55.88" y1="67.31" x2="57.15" y2="67.31" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$75" class="0"> +<segment> +<wire x1="36.83" y1="50.8" x2="38.1" y2="50.8" width="0.1524" layer="91"/> +<wire x1="38.1" y1="50.8" x2="38.1" y2="48.26" width="0.1524" layer="91"/> +<wire x1="38.1" y1="48.26" x2="38.1" y2="45.72" width="0.1524" layer="91"/> +<wire x1="38.1" y1="45.72" x2="36.83" y2="45.72" width="0.1524" layer="91"/> +<wire x1="38.1" y1="48.26" x2="48.26" y2="48.26" width="0.1524" layer="91"/> +<wire x1="48.26" y1="48.26" x2="48.26" y2="54.61" width="0.1524" layer="91"/> +<junction x="38.1" y="48.26"/> +<pinref part="SW2" gate="PB" pin="2"/> +<pinref part="SW2" gate="PB" pin="1"/> +<wire x1="34.29" y1="54.61" x2="48.26" y2="54.61" width="0.1524" layer="91"/> +<pinref part="R54" gate="R" pin="2"/> +<pinref part="U10" gate="CORE" pin="P1.2/TA1"/> +<wire x1="48.26" y1="54.61" x2="57.15" y2="54.61" width="0.1524" layer="91"/> +<junction x="48.26" y="54.61"/> +<pinref part="R6U1" gate="R" pin="1"/> +<wire x1="39.37" y1="11.43" x2="48.26" y2="11.43" width="0.1524" layer="91"/> +<wire x1="48.26" y1="11.43" x2="48.26" y2="48.26" width="0.1524" layer="91"/> +<junction x="48.26" y="48.26"/> +</segment> +</net> +<net name="VSBY3-3" class="0"> +<segment> +<wire x1="125.73" y1="72.39" x2="116.84" y2="72.39" width="0.1524" layer="91"/> +<wire x1="116.84" y1="72.39" x2="113.03" y2="72.39" width="0.1524" layer="91"/> +<wire x1="116.84" y1="72.39" x2="116.84" y2="78.74" width="0.1524" layer="91"/> +<junction x="116.84" y="72.39"/> +<pinref part="U$70" gate="G$1" pin="VSBY3-3"/> +<pinref part="U10" gate="CORE" pin="DVCC"/> +<pinref part="C12" gate="C" pin="1"/> +<wire x1="116.84" y1="78.74" x2="116.84" y2="86.36" width="0.1524" layer="91"/> +<wire x1="125.73" y1="78.74" x2="116.84" y2="78.74" width="0.1524" layer="91"/> +<junction x="116.84" y="78.74"/> +<pinref part="C9" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="172.72" y1="66.04" x2="172.72" y2="68.58" width="0.1524" layer="91"/> +<wire x1="173.99" y1="66.04" x2="172.72" y2="66.04" width="0.1524" layer="91"/> +<pinref part="U$79" gate="G$1" pin="VSBY3-3"/> +<pinref part="U10" gate="ADC" pin="AVCC"/> +</segment> +<segment> +<wire x1="11.43" y1="49.53" x2="11.43" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U$75" gate="G$1" pin="VSBY3-3"/> +<wire x1="11.43" y1="50.8" x2="11.43" y2="54.61" width="0.1524" layer="91"/> +<pinref part="R87" gate="R" pin="2"/> +<pinref part="R23" gate="R" pin="1"/> +<wire x1="11.43" y1="54.61" x2="11.43" y2="83.82" width="0.1524" layer="91"/> +<wire x1="11.43" y1="83.82" x2="11.43" y2="90.17" width="0.1524" layer="91"/> +<wire x1="21.59" y1="83.82" x2="11.43" y2="83.82" width="0.1524" layer="91"/> +<junction x="11.43" y="83.82"/> +<pinref part="R54" gate="R" pin="1"/> +<wire x1="24.13" y1="54.61" x2="11.43" y2="54.61" width="0.1524" layer="91"/> +<junction x="11.43" y="54.61"/> +</segment> +<segment> +<pinref part="U11" gate="G" pin="VCC"/> +<pinref part="U$137" gate="G$1" pin="VSBY3-3"/> +<wire x1="166.37" y1="43.18" x2="166.37" y2="41.91" width="0.1524" layer="91"/> +</segment> +<segment> +<wire x1="110.49" y1="38.1" x2="104.14" y2="38.1" width="0.1524" layer="91"/> +<pinref part="U$83" gate="G$1" pin="VSBY3-3"/> +<wire x1="110.49" y1="38.1" x2="110.49" y2="39.37" width="0.1524" layer="91"/> +<pinref part="SV1" gate="1" pin="4"/> +</segment> +</net> +<net name="V1P8-CMD" class="0"> +<segment> +<label x="118.11" y="102.87" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="U10" gate="UART" pin="P4.7/TBCLK"/> +<wire x1="118.11" y1="102.87" x2="127" y2="102.87" width="0.1524" layer="91"/> +</segment> +</net> +<net name="IMCH-RSMRST-N" class="0"> +<segment> +<wire x1="227.33" y1="60.96" x2="233.68" y2="60.96" width="0.1524" layer="91"/> +<label x="233.68" y="60.96" size="1.778" layer="92" xref="yes"/> +<pinref part="U10" gate="ADC" pin="XOUT/P2.7"/> +</segment> +</net> +<net name="ATX-PWROK" class="0"> +<segment> +<wire x1="106.68" y1="127" x2="95.25" y2="127" width="0.1524" layer="91"/> +<label x="95.25" y="127" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="R52" gate="R" pin="1"/> +</segment> +</net> +<net name="P1V8-PGOOD" class="0"> +<segment> +<label x="201.93" y="105.41" size="1.778" layer="92" xref="yes"/> +<pinref part="U10" gate="UART" pin="P3.6/A6"/> +<wire x1="201.93" y1="105.41" x2="189.23" y2="105.41" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SLP-S3-N" class="0"> +<segment> +<wire x1="125.73" y1="132.08" x2="105.41" y2="132.08" width="0.1524" layer="91"/> +<label x="105.41" y="132.08" size="1.778" layer="92" rot="R180" xref="yes"/> +<wire x1="125.73" y1="132.08" x2="125.73" y2="120.65" width="0.1524" layer="91"/> +<pinref part="U10" gate="UART" pin="P4.0/TB0"/> +<wire x1="125.73" y1="120.65" x2="127" y2="120.65" width="0.1524" layer="91"/> +</segment> +</net> +<net name="CPU-VCCP-EN-N" class="0"> +<segment> +<label x="233.68" y="38.1" size="1.778" layer="92" rot="MR180" xref="yes"/> +<pinref part="R100" gate="R" pin="1"/> +<wire x1="220.98" y1="38.1" x2="228.6" y2="38.1" width="0.1524" layer="91"/> +<wire x1="228.6" y1="38.1" x2="228.6" y2="46.99" width="0.1524" layer="91"/> +<pinref part="U10" gate="ADC" pin="P2.2/TA0/A2/BSL-RX"/> +<wire x1="228.6" y1="46.99" x2="227.33" y2="46.99" width="0.1524" layer="91"/> +<wire x1="233.68" y1="38.1" x2="228.6" y2="38.1" width="0.1524" layer="91"/> +<junction x="228.6" y="38.1"/> +</segment> +</net> +<net name="VRMPWRGD" class="0"> +<segment> +<wire x1="189.23" y1="102.87" x2="231.14" y2="102.87" width="0.1524" layer="91"/> +<label x="231.14" y="102.87" size="1.778" layer="92" rot="MR180" xref="yes"/> +<pinref part="U10" gate="UART" pin="P3.7/A7"/> +</segment> +</net> +<net name="SYS-PWR-OK" class="0"> +<segment> +<wire x1="189.23" y1="113.03" x2="231.14" y2="113.03" width="0.1524" layer="91"/> +<label x="231.14" y="113.03" size="1.778" layer="92" rot="MR180" xref="yes"/> +<pinref part="U10" gate="UART" pin="P3.3/UCB0CLK/UCA0STE"/> +</segment> +</net> +<net name="CK410-PWR-GD-N" class="0"> +<segment> +<wire x1="227.33" y1="52.07" x2="231.14" y2="52.07" width="0.1524" layer="91"/> +<label x="231.14" y="52.07" size="1.778" layer="92" rot="MR180" xref="yes"/> +<pinref part="U10" gate="ADC" pin="P2.0/ACLK/A0"/> +</segment> +</net> +<net name="V1P2-CORE-EN-N" class="0"> +<segment> +<wire x1="53.34" y1="67.31" x2="41.91" y2="67.31" width="0.1524" layer="91"/> +<label x="41.91" y="67.31" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="U10" gate="CORE" pin="P1.1/TA0/BSL-TX"/> +<pinref part="R99" gate="R" pin="2"/> +<wire x1="49.53" y1="62.23" x2="53.34" y2="62.23" width="0.1524" layer="91"/> +<wire x1="53.34" y1="62.23" x2="57.15" y2="62.23" width="0.1524" layer="91"/> +<wire x1="53.34" y1="67.31" x2="53.34" y2="62.23" width="0.1524" layer="91"/> +<junction x="53.34" y="62.23"/> +</segment> +</net> +<net name="WDT-TOUT-N" class="0"> +<segment> +<wire x1="53.34" y1="40.64" x2="43.18" y2="40.64" width="0.1524" layer="91"/> +<label x="43.18" y="40.64" size="1.778" layer="92" rot="MR0" xref="yes"/> +<wire x1="53.34" y1="40.64" x2="53.34" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U10" gate="CORE" pin="P1.3/TA2"/> +<wire x1="53.34" y1="50.8" x2="57.15" y2="50.8" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SYS-RESET-N" class="0"> +<segment> +<wire x1="227.33" y1="57.15" x2="228.6" y2="57.15" width="0.1524" layer="91"/> +<label x="233.68" y="57.15" size="1.778" layer="92" rot="MR180" xref="yes"/> +<pinref part="U10" gate="ADC" pin="P2.5/ROSC"/> +<pinref part="R48" gate="R" pin="1"/> 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layer="91"/> +<label x="245.11" y="46.99" size="1.778" layer="92" xref="yes"/> +<pinref part="U10" gate="ADC" pin="P2.1/TAINCLK/SMCLK/A1"/> +</segment> +</net> +<net name="I2C-SMBCLK" class="0"> +<segment> +<wire x1="189.23" y1="115.57" x2="196.85" y2="115.57" width="0.1524" layer="91"/> +<label x="196.85" y="115.57" size="1.778" layer="92" rot="MR180" xref="yes"/> +<pinref part="U10" gate="UART" pin="P3.2/UCBOSOMI/UCB0SCL"/> +</segment> +</net> +<net name="I2C-SMBDAT" class="0"> +<segment> +<wire x1="189.23" y1="118.11" x2="231.14" y2="118.11" width="0.1524" layer="91"/> +<label x="231.14" y="118.11" size="1.778" layer="92" rot="MR180" xref="yes"/> +<pinref part="U10" gate="UART" pin="P3.1/UCB0SIMO/UCB0SDA"/> +</segment> +</net> +<net name="MSP-BSL-TEST" class="0"> +<segment> +<wire x1="125.73" y1="48.26" x2="128.27" y2="48.26" width="0.1524" layer="91"/> +<label x="128.27" y="48.26" size="1.778" layer="92" xref="yes"/> +<pinref part="R73" gate="R" pin="2"/> +</segment> +<segment> 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x1="204.47" y1="38.1" x2="210.82" y2="38.1" width="0.1524" layer="91"/> +<pinref part="R100" gate="R" pin="2"/> +<wire x1="233.68" y1="107.95" x2="189.23" y2="107.95" width="0.1524" layer="91"/> +<label x="233.68" y="107.95" size="1.778" layer="92" xref="yes"/> +<pinref part="U10" gate="UART" pin="P3.5/UCA0RXD/UCA0SOMI"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<pinref part="U10" gate="CORE" pin="TEST/SBWTCH"/> +<wire x1="115.57" y1="48.26" x2="113.03" y2="48.26" width="0.1524" layer="91"/> +<pinref part="R73" gate="R" pin="1"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="LED14" gate="DL" pin="A2"/> +<wire x1="132.08" y1="34.29" x2="132.08" y2="36.83" width="0.1524" layer="91"/> +<wire x1="132.08" y1="36.83" x2="135.89" y2="36.83" width="0.1524" layer="91"/> +<pinref part="R74" gate="R" pin="2"/> +</segment> +</net> +<net name="N$12" class="0"> +<segment> +<pinref part="LED14" gate="DL" pin="A1"/> +<wire x1="132.08" y1="31.75" x2="132.08" y2="29.21" width="0.1524" layer="91"/> +<wire x1="132.08" y1="29.21" x2="135.89" y2="29.21" width="0.1524" layer="91"/> +<pinref part="R69" gate="R" pin="2"/> +</segment> +</net> +<net name="N$13" class="0"> +<segment> +<pinref part="U11" gate="G" pin="OUTY2"/> +<wire x1="146.05" y1="29.21" x2="148.59" y2="29.21" width="0.1524" layer="91"/> +<pinref part="R69" gate="R" pin="1"/> +</segment> +</net> +<net name="N$14" class="0"> +<segment> +<pinref part="U11" gate="G" pin="OUTY1"/> +<wire x1="146.05" y1="36.83" x2="148.59" y2="36.83" width="0.1524" layer="91"/> +<pinref part="R74" gate="R" pin="1"/> +</segment> +</net> +<net name="N$17" class="0"> +<segment> +<pinref part="U10" gate="ADC" pin="P2.4/TA2/A4/VREF+/VEREF+"/> +<wire x1="173.99" y1="44.45" x2="168.91" y2="44.45" width="0.1524" layer="91"/> +<pinref part="U11" gate="G" pin="INA1"/> +<wire x1="168.91" y1="44.45" x2="168.91" y2="36.83" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$25" class="0"> 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y1="125.73" x2="74.93" y2="125.73" width="0.1524" layer="91"/> +<wire x1="74.93" y1="125.73" x2="74.93" y2="119.38" width="0.1524" layer="91"/> +<wire x1="74.93" y1="119.38" x2="82.55" y2="119.38" width="0.1524" layer="91"/> +<wire x1="82.55" y1="119.38" x2="82.55" y2="113.03" width="0.1524" layer="91"/> +<junction x="45.72" y="125.73"/> +<pinref part="U10" gate="UART" pin="P4.3/TBO/A12"/> +<wire x1="82.55" y1="113.03" x2="127" y2="113.03" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$35" class="0"> +<segment> +<pinref part="R92" gate="R" pin="2"/> +<wire x1="68.58" y1="119.38" x2="72.39" y2="119.38" width="0.1524" layer="91"/> +<wire x1="72.39" y1="119.38" x2="72.39" y2="118.11" width="0.1524" layer="91"/> +<pinref part="C4" gate="C" pin="2"/> +<wire x1="72.39" y1="118.11" x2="72.39" y2="115.57" width="0.1524" layer="91"/> +<wire x1="72.39" y1="115.57" x2="67.31" y2="115.57" width="0.1524" layer="91"/> +<pinref part="R91" gate="R" pin="2"/> +<wire x1="68.58" y1="121.92" x2="72.39" y2="121.92" width="0.1524" layer="91"/> +<wire x1="72.39" y1="121.92" x2="72.39" y2="119.38" width="0.1524" layer="91"/> +<junction x="72.39" y="119.38"/> +<wire x1="72.39" y1="115.57" x2="80.01" y2="115.57" width="0.1524" layer="91"/> +<wire x1="80.01" y1="115.57" x2="80.01" y2="110.49" width="0.1524" layer="91"/> +<junction x="72.39" y="115.57"/> +<pinref part="U10" gate="UART" pin="P4.4/TB1/A13"/> +<wire x1="80.01" y1="110.49" x2="127" y2="110.49" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$50" class="0"> +<segment> +<pinref part="R94" gate="R" pin="2"/> +<wire x1="41.91" y1="110.49" x2="45.72" y2="110.49" width="0.1524" layer="91"/> +<wire x1="45.72" y1="110.49" x2="45.72" y2="106.68" width="0.1524" layer="91"/> +<pinref part="C6" gate="C" pin="2"/> +<wire x1="45.72" y1="106.68" x2="40.64" y2="106.68" width="0.1524" layer="91"/> +<pinref part="R93" gate="R" pin="2"/> +<wire x1="41.91" y1="113.03" x2="45.72" y2="113.03" width="0.1524" layer="91"/> +<wire x1="45.72" y1="113.03" x2="45.72" y2="110.49" width="0.1524" layer="91"/> +<junction x="45.72" y="110.49"/> +<wire x1="45.72" y1="113.03" x2="77.47" y2="113.03" width="0.1524" layer="91"/> +<wire x1="77.47" y1="113.03" x2="77.47" y2="107.95" width="0.1524" layer="91"/> +<junction x="45.72" y="113.03"/> +<pinref part="U10" gate="UART" pin="P4.5/TB2/A14"/> +<wire x1="77.47" y1="107.95" x2="127" y2="107.95" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$55" class="0"> +<segment> +<pinref part="R96" gate="R" pin="2"/> +<wire x1="68.58" y1="106.68" x2="72.39" y2="106.68" width="0.1524" layer="91"/> +<wire x1="72.39" y1="106.68" x2="72.39" y2="102.87" width="0.1524" layer="91"/> +<pinref part="C7" gate="C" pin="2"/> +<wire x1="72.39" y1="102.87" x2="67.31" y2="102.87" width="0.1524" layer="91"/> +<pinref part="R95" gate="R" pin="2"/> +<wire x1="68.58" y1="109.22" x2="72.39" y2="109.22" width="0.1524" layer="91"/> +<wire x1="72.39" y1="109.22" x2="72.39" y2="106.68" width="0.1524" layer="91"/> +<junction x="72.39" y="106.68"/> +<wire x1="72.39" y1="109.22" x2="74.93" y2="109.22" width="0.1524" layer="91"/> +<wire x1="74.93" y1="109.22" x2="74.93" y2="105.41" width="0.1524" layer="91"/> +<junction x="72.39" y="109.22"/> +<pinref part="U10" gate="UART" pin="P4.6/TBOUTH/A15"/> +<wire x1="74.93" y1="105.41" x2="127" y2="105.41" width="0.1524" layer="91"/> +</segment> +</net> +<net name="V1P0" class="0"> +<segment> +<pinref part="R86" gate="R" pin="1"/> +<wire x1="31.75" y1="125.73" x2="22.86" y2="125.73" width="0.1524" layer="91"/> +<pinref part="U$87" gate="G$1" pin="V1P0"/> +</segment> +</net> +<net name="V1P2" class="0"> +<segment> +<pinref part="R91" gate="R" pin="1"/> +<wire x1="58.42" y1="121.92" x2="53.34" y2="121.92" width="0.1524" layer="91"/> +<pinref part="U$139" gate="PW-V1P2" pin="V1P2"/> +</segment> +</net> +<net name="V2P5" class="0"> +<segment> +<pinref part="R95" gate="R" pin="1"/> +<wire x1="58.42" y1="109.22" x2="53.34" y2="109.22" width="0.1524" layer="91"/> +<pinref part="U$155" gate="G$1" pin="V2P5"/> +</segment> +</net> +<net name="N$56" class="0"> +<segment> +<pinref part="R98" gate="R" pin="2"/> +<wire x1="203.2" y1="138.43" x2="199.39" y2="138.43" width="0.1524" layer="91"/> +<wire x1="199.39" y1="138.43" x2="199.39" y2="132.08" width="0.1524" layer="91"/> +<pinref part="C10" gate="C" pin="2"/> +<wire x1="199.39" y1="132.08" x2="204.47" y2="132.08" width="0.1524" layer="91"/> +<pinref part="R97" gate="R" pin="2"/> +<wire x1="203.2" y1="142.24" x2="199.39" y2="142.24" width="0.1524" layer="91"/> +<wire x1="199.39" y1="142.24" x2="199.39" y2="138.43" width="0.1524" layer="91"/> +<junction x="199.39" y="138.43"/> +<pinref part="U10" gate="UART" pin="P3.0/UCB0STE.UCA0CLK/A5"/> +<wire x1="189.23" y1="120.65" x2="199.39" y2="120.65" width="0.1524" layer="91"/> +<wire x1="199.39" y1="120.65" x2="199.39" y2="132.08" width="0.1524" layer="91"/> +<junction x="199.39" y="132.08"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<pinref part="R97" gate="R" pin="1"/> +<wire x1="213.36" y1="142.24" x2="222.25" y2="142.24" width="0.1524" layer="91"/> +<pinref part="U$180" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<pinref part="R48" gate="R" pin="2"/> +<pinref part="U$89" gate="PW-VCC3" pin="VCC3"/> +<wire x1="228.6" y1="93.98" x2="228.6" y2="92.71" width="0.1524" layer="91"/> +<pinref part="R7" gate="R" pin="2"/> +<wire x1="228.6" y1="92.71" x2="228.6" y2="87.63" width="0.1524" layer="91"/> +<wire x1="232.41" y1="87.63" x2="232.41" y2="92.71" width="0.1524" layer="91"/> +<wire x1="232.41" y1="92.71" x2="228.6" y2="92.71" width="0.1524" layer="91"/> +<junction x="228.6" y="92.71"/> +</segment> +</net> +<net name="V1P8-DDR" class="0"> +<segment> +<pinref part="R93" gate="R" pin="1"/> +<wire x1="31.75" y1="113.03" x2="22.86" y2="113.03" width="0.1524" layer="91"/> +<pinref part="U$195" gate="V1P8-DDR" pin="V1P8-DDR"/> +</segment> +</net> +<net name="CMDPWR" class="0"> +<segment> +<label x="101.6" y="115.57" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="U10" gate="UART" pin="P4.2/TB2"/> +<wire x1="101.6" y1="115.57" x2="127" y2="115.57" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$65" class="0"> +<segment> +<pinref part="U10" gate="UART" pin="P4.1/TB1"/> +<wire x1="121.92" y1="118.11" x2="127" y2="118.11" width="0.1524" layer="91"/> +<pinref part="R52" gate="R" pin="2"/> +<wire x1="116.84" y1="127" x2="121.92" y2="127" width="0.1524" layer="91"/> +<wire x1="121.92" y1="127" x2="121.92" y2="121.92" width="0.1524" layer="91"/> +<pinref part="R13" gate="R" pin="2"/> +<wire x1="121.92" y1="121.92" x2="121.92" y2="118.11" width="0.1524" layer="91"/> +<wire x1="116.84" y1="121.92" x2="121.92" y2="121.92" width="0.1524" layer="91"/> +<junction x="121.92" y="121.92"/> +</segment> +</net> +<net name="ITP-DBRST-N" class="0"> +<segment> +<wire x1="29.21" y1="11.43" x2="25.4" y2="11.43" width="0.1524" layer="91"/> +<label x="25.4" y="11.43" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="R6U1" gate="R" pin="2"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="78.74" y="162.56" size="3.81" layer="94">Debug & JTAG connection</text> +</plain> +<instances> +<instance part="FRAME31" gate="G$1" x="0" y="0"/> +<instance part="FRAME31" gate="G$2" x="180.34" y="0"/> +<instance part="P+4" gate="1" x="125.73" y="148.59"/> +<instance part="U$123" gate="PW-V1P2" x="101.6" y="140.97"/> +<instance part="U$437" gate="G$1" x="179.07" y="48.26" rot="R90"/> +<instance part="U$454" gate="G$1" x="120.65" y="29.21" rot="R270"/> +<instance part="R5U8" gate="R" x="101.6" y="128.27" rot="R270"> +<attribute name="DNP" x="100.076" y="126.238" size="1.778" layer="96" rot="R90"/> +<attribute name="POWER" x="101.6" y="128.27" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="101.6" y="128.27" size="1.778" layer="96" display="off"/> +</instance> +<instance part="J4G4" gate="CONITPXDP" x="149.86" y="73.66" smashed="yes"> +<attribute name="NAME" x="134.62" y="15.24" size="1.778" layer="95"/> +<attribute name="VALUE" x="133.35" y="120.65" size="1.778" layer="96"/> +<attribute name="DNP" x="156.21" y="15.24" size="1.778" layer="96" display="name"/> +</instance> +<instance part="R6U5" gate="R" x="95.25" y="128.27" rot="R270"> +<attribute name="POWER" x="95.25" y="128.27" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6U3" gate="R" x="114.3" y="128.27" rot="R270"> +<attribute name="POWER" x="114.3" y="128.27" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="114.3" y="128.27" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6U4" gate="R" x="102.87" y="77.47" smashed="yes"> +<attribute name="NAME" x="99.06" y="78.105" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="106.68" y="78.105" size="1.778" layer="96"/> +<attribute name="POWER" x="102.87" y="77.47" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="102.87" y="77.47" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6U1" gate="C" x="90.17" y="81.28" smashed="yes" rot="R90"> +<attribute name="NAME" x="81.28" y="82.55" size="1.778" layer="95"/> +<attribute name="VALUE" x="95.25" y="82.55" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="90.17" y="81.28" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="90.17" y="81.28" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="90.17" y="81.28" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$455" gate="G$1" x="76.2" y="81.28" rot="R270"/> +<instance part="R6U17" gate="R" x="95.25" y="62.23" smashed="yes" rot="R180"> +<attribute name="NAME" x="88.9" y="63.5" size="1.778" layer="95"/> +<attribute name="VALUE" x="97.79" y="63.5" size="1.778" layer="96"/> +<attribute name="DNP" x="92.71" y="58.42" size="1.778" layer="96"/> +<attribute name="POWER" x="95.25" y="62.23" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="95.25" y="62.23" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$457" gate="PW-V1P2" x="83.82" y="66.04"/> +<instance part="R4T1" gate="R" x="187.96" y="22.86" rot="R180"> +<attribute name="POWER" x="187.96" y="22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$459" gate="G$1" x="177.8" y="22.86" rot="R270"/> +<instance part="R6U18" gate="R" x="199.39" y="53.34" rot="R90"> +<attribute name="POWER" x="199.39" y="53.34" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4T17" gate="R" x="204.47" y="53.34" rot="R90"> +<attribute name="POWER" x="204.47" y="53.34" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4T18" gate="R" x="209.55" y="54.61" rot="R90"> +<attribute name="POWER" x="209.55" y="54.61" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4R13" gate="R" x="185.42" y="40.64"> +<attribute name="POWER" x="185.42" y="40.64" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$461" gate="PW-V1P2" x="199.39" y="66.04"/> +<instance part="R6U12" gate="R" x="91.44" y="100.33"> +<attribute name="POWER" x="91.44" y="100.33" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="91.44" y="100.33" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6U20" gate="R" x="82.55" y="128.27" rot="R270"> +<attribute name="DNP" x="80.772" y="125.984" size="1.778" layer="96" rot="R90"/> +<attribute name="POWER" x="82.55" y="128.27" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$462" gate="PW-V1P2" x="82.55" y="148.59" rot="MR0"/> +<instance part="R6U10" gate="R" x="78.74" y="91.44"> +<attribute name="POWER" x="78.74" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$469" gate="PW-VCC3" x="110.49" y="157.48"/> +<instance part="R6U9" gate="R" x="107.95" y="128.27" rot="R270"> +<attribute name="DNP" x="106.172" y="126.238" size="1.778" layer="96" rot="R90"/> +<attribute name="POWER" x="107.95" y="128.27" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U6U1" gate="A" x="63.5" y="27.94" smashed="yes" rot="R270"> +<attribute name="NAME" x="67.31" y="20.32" size="1.778" layer="95"/> +<attribute name="VALUE" x="67.31" y="17.78" size="1.778" layer="96"/> +<attribute name="DNP" x="57.15" y="30.48" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="U6U1" gate="PW" x="232.41" y="92.71"/> +<instance part="U5U1" gate="A" x="99.06" y="27.94" smashed="yes" rot="R270"> +<attribute name="NAME" x="100.33" y="20.32" size="1.778" layer="95"/> +<attribute name="VALUE" x="100.33" y="17.78" size="1.778" layer="96"/> +<attribute name="DNP" x="92.71" y="29.21" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="U5U1" gate="PW" x="242.57" y="92.71"/> +<instance part="U$472" gate="G$1" x="97.79" y="17.78"/> +<instance part="U$485" gate="G$1" x="62.23" y="17.78"/> +<instance part="U$486" gate="PW-VCC3" x="232.41" y="119.38"/> +<instance part="U$489" gate="G$1" x="232.41" y="77.47"/> +<instance part="R4T15" gate="R" x="109.22" y="40.64" rot="R180"> +<attribute name="POWER" x="109.22" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="109.22" y="40.64" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4T16" gate="R" x="109.22" y="35.56" rot="R180"> +<attribute name="POWER" x="109.22" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="109.22" y="35.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$490" gate="PW-VCC3" x="26.67" y="33.02"/> +<instance part="R6U21" gate="R" x="38.1" y="26.67"> +<attribute name="POWER" x="38.1" y="26.67" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6U22" gate="R" x="38.1" y="11.43" rot="R180"> +<attribute name="DNP" x="36.83" y="13.97" size="1.778" layer="96"/> +<attribute name="POWER" x="38.1" y="11.43" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$491" gate="G$1" x="26.67" y="11.43" rot="R270"/> +<instance part="R3G25" gate="R" x="53.34" y="74.93" smashed="yes"> +<attribute name="NAME" x="49.6834" y="75.4994" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="56.8315" y="75.8114" size="1.778" layer="96"/> +<attribute name="POWER" x="53.34" y="74.93" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="53.34" y="74.93" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2G13" gate="R" x="68.58" y="60.96" rot="R270"> +<attribute name="POWER" x="68.58" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="68.58" y="60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3G22" gate="R" x="53.34" y="71.12" smashed="yes"> +<attribute name="NAME" x="49.6834" y="71.6894" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="56.8315" y="72.0014" size="1.778" layer="96"/> +<attribute name="POWER" x="53.34" y="71.12" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="53.34" y="71.12" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2G12" gate="R" x="63.5" y="58.42" rot="R270"> +<attribute name="POWER" x="63.5" y="58.42" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="63.5" y="58.42" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$405" gate="G$1" x="63.5" y="44.45"/> +<instance part="R4T19" gate="R" x="120.65" y="128.27" rot="R270"> +<attribute name="DNP" x="119.126" y="126.238" size="1.778" layer="96" rot="R90"/> +<attribute name="POWER" x="120.65" y="128.27" size="1.778" layer="96" display="off"/> +</instance> +</instances> +<busses> +<bus name="NC-RSVD[0..17]"> +<segment> +<wire x1="194.31" y1="73.66" x2="194.31" y2="119.38" width="0.4064" layer="92"/> +<wire x1="194.31" y1="119.38" x2="217.17" y2="119.38" width="0.4064" layer="92"/> +<wire x1="217.17" y1="119.38" x2="217.17" y2="120.65" width="0.4064" layer="92"/> +<wire x1="217.17" y1="120.65" x2="219.71" y2="120.65" width="0.4064" layer="92"/> +<wire x1="219.71" y1="120.65" x2="219.71" y2="119.38" width="0.4064" layer="92"/> +<label x="214.63" y="120.3325" size="1.778" layer="92" rot="MR0"/> +</segment> +</bus> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="177.8" y1="48.26" x2="175.26" y2="48.26" width="0.1524" layer="91"/> +<wire x1="175.26" y1="48.26" x2="172.72" y2="48.26" width="0.1524" layer="91"/> +<wire x1="172.72" y1="45.72" x2="175.26" y2="45.72" width="0.1524" layer="91" style="longdash"/> +<wire x1="175.26" y1="45.72" x2="175.26" y2="48.26" width="0.1524" layer="91" style="longdash"/> +<wire x1="175.26" y1="48.26" x2="175.26" y2="50.8" width="0.1524" layer="91"/> +<wire x1="175.26" y1="50.8" x2="172.72" y2="50.8" width="0.1524" layer="91"/> +<wire x1="175.26" y1="50.8" x2="175.26" y2="53.34" width="0.1524" layer="91"/> +<wire x1="175.26" y1="53.34" x2="175.26" y2="55.88" width="0.1524" layer="91"/> +<wire x1="175.26" y1="55.88" x2="175.26" y2="58.42" width="0.1524" layer="91"/> +<wire x1="175.26" y1="58.42" x2="175.26" y2="60.96" width="0.1524" layer="91"/> +<wire x1="175.26" y1="60.96" x2="175.26" y2="63.5" width="0.1524" layer="91"/> +<wire x1="175.26" y1="63.5" x2="173.99" y2="63.5" width="0.1524" layer="91"/> +<wire x1="173.99" y1="63.5" x2="172.72" y2="63.5" width="0.1524" layer="91"/> +<wire x1="172.72" y1="60.96" x2="175.26" y2="60.96" width="0.1524" layer="91"/> +<wire x1="172.72" y1="58.42" x2="175.26" y2="58.42" width="0.1524" layer="91"/> +<wire x1="172.72" y1="55.88" x2="175.26" y2="55.88" width="0.1524" layer="91"/> +<wire x1="172.72" y1="53.34" x2="175.26" y2="53.34" width="0.1524" layer="91"/> +<wire x1="180.34" y1="40.64" x2="175.26" y2="40.64" width="0.1524" layer="91"/> +<wire x1="175.26" y1="40.64" x2="175.26" y2="45.72" width="0.1524" layer="91"/> +<junction x="175.26" y="48.26"/> +<junction x="175.26" y="50.8"/> +<junction x="175.26" y="60.96"/> +<junction x="175.26" y="58.42"/> +<junction x="175.26" y="55.88"/> +<junction x="175.26" y="53.34"/> +<junction x="175.26" y="45.72"/> +<pinref part="U$437" gate="G$1" pin="GND"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@10"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@11"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@12"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@13"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@14"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@15"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@16"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@17"/> +<pinref part="R4R13" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="121.92" y1="29.21" x2="124.46" y2="29.21" width="0.1524" layer="91"/> +<wire x1="124.46" y1="29.21" x2="127" y2="29.21" width="0.1524" layer="91"/> +<wire x1="127" y1="24.13" x2="124.46" y2="24.13" width="0.1524" layer="91"/> +<wire x1="124.46" y1="24.13" x2="124.46" y2="26.67" width="0.1524" layer="91"/> +<wire x1="124.46" y1="26.67" x2="124.46" y2="29.21" width="0.1524" layer="91"/> +<wire x1="124.46" y1="29.21" x2="124.46" y2="31.75" width="0.1524" layer="91"/> +<wire x1="124.46" y1="31.75" x2="124.46" y2="34.29" width="0.1524" layer="91"/> +<wire x1="124.46" y1="34.29" x2="124.46" y2="36.83" width="0.1524" layer="91"/> +<wire x1="124.46" y1="36.83" x2="124.46" y2="39.37" width="0.1524" layer="91"/> +<wire x1="124.46" y1="39.37" x2="124.46" y2="41.91" width="0.1524" layer="91"/> +<wire x1="124.46" y1="41.91" x2="124.46" y2="44.45" width="0.1524" layer="91"/> +<wire x1="124.46" y1="44.45" x2="127" y2="44.45" width="0.1524" layer="91"/> +<wire x1="127" y1="41.91" x2="124.46" y2="41.91" width="0.1524" layer="91"/> +<wire x1="127" y1="39.37" x2="124.46" y2="39.37" width="0.1524" layer="91"/> +<wire x1="127" y1="36.83" x2="124.46" y2="36.83" width="0.1524" layer="91"/> +<wire x1="127" y1="34.29" x2="124.46" y2="34.29" width="0.1524" layer="91"/> +<wire x1="127" y1="31.75" x2="124.46" y2="31.75" width="0.1524" layer="91"/> +<wire x1="127" y1="26.67" x2="124.46" y2="26.67" width="0.1524" layer="91"/> +<junction x="124.46" y="29.21"/> +<junction x="124.46" y="41.91"/> +<junction x="124.46" y="39.37"/> +<junction x="124.46" y="36.83"/> +<junction x="124.46" y="34.29"/> +<junction x="124.46" y="31.75"/> +<junction x="124.46" y="26.67"/> +<pinref part="U$454" gate="G$1" pin="GND"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@1"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@2"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@3"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@4"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@5"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@6"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@7"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@8"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GND@9"/> +</segment> +<segment> +<wire x1="87.63" y1="81.28" x2="80.01" y2="81.28" width="0.1524" layer="91"/> +<wire x1="80.01" y1="81.28" x2="80.01" y2="77.47" width="0.1524" layer="91"/> +<wire x1="80.01" y1="77.47" x2="97.79" y2="77.47" width="0.1524" layer="91"/> +<wire x1="77.47" y1="81.28" x2="80.01" y2="81.28" width="0.1524" layer="91"/> +<junction x="80.01" y="81.28"/> +<pinref part="C6U1" gate="C" pin="2"/> +<pinref part="R6U4" gate="R" pin="1"/> +<pinref part="U$455" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="179.07" y1="22.86" x2="182.88" y2="22.86" width="0.1524" layer="91"/> +<pinref part="R4T1" gate="R" pin="2"/> +<pinref part="U$459" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="97.79" y1="19.05" x2="97.79" y2="20.32" width="0.1524" layer="91"/> +<pinref part="U5U1" gate="A" pin="B"/> +<pinref part="U$472" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="62.23" y1="19.05" x2="62.23" y2="20.32" width="0.1524" layer="91"/> +<pinref part="U6U1" gate="A" pin="B"/> +<pinref part="U$485" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="232.41" y1="80.01" x2="242.57" y2="80.01" width="0.1524" layer="91"/> +<wire x1="242.57" y1="80.01" x2="242.57" y2="83.82" width="0.1524" layer="91"/> +<wire x1="232.41" y1="80.01" x2="232.41" y2="83.82" width="0.1524" layer="91"/> +<wire x1="232.41" y1="78.74" x2="232.41" y2="80.01" width="0.1524" layer="91"/> +<junction x="232.41" y="80.01"/> +<pinref part="U5U1" gate="PW" pin="VDD"/> +<pinref part="U6U1" gate="PW" pin="VDD"/> +<pinref part="U$489" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="27.94" y1="11.43" x2="33.02" y2="11.43" width="0.1524" layer="91"/> +<pinref part="R6U22" gate="R" pin="2"/> +<pinref part="U$491" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="63.5" y1="45.72" x2="63.5" y2="50.8" width="0.1524" layer="91"/> +<wire x1="63.5" y1="50.8" x2="63.5" y2="53.34" width="0.1524" layer="91"/> +<wire x1="63.5" y1="50.8" x2="68.58" y2="50.8" width="0.1524" layer="91"/> +<wire x1="68.58" y1="50.8" x2="68.58" y2="55.88" width="0.1524" layer="91"/> +<junction x="63.5" y="50.8"/> +<pinref part="R2G12" gate="R" pin="2"/> +<pinref part="U$405" gate="G$1" pin="GND"/> +<pinref part="R2G13" gate="R" pin="2"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="107.95" y1="133.35" x2="107.95" y2="146.05" width="0.1524" layer="91"/> +<wire x1="107.95" y1="146.05" x2="110.49" y2="146.05" width="0.1524" layer="91"/> +<wire x1="110.49" y1="146.05" x2="114.3" y2="146.05" width="0.1524" layer="91"/> +<wire x1="114.3" y1="146.05" x2="114.3" y2="133.35" width="0.1524" layer="91"/> +<wire x1="110.49" y1="146.05" x2="110.49" y2="154.94" width="0.1524" layer="91"/> +<junction x="110.49" y="146.05"/> +<pinref part="R6U9" gate="R" pin="1"/> +<pinref part="U$469" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R6U3" gate="R" pin="1"/> +<wire x1="95.25" y1="133.35" x2="95.25" y2="146.05" width="0.1524" layer="91"/> +<pinref part="R6U5" gate="R" pin="1"/> +<wire x1="107.95" y1="146.05" x2="95.25" y2="146.05" width="0.1524" layer="91"/> +<junction x="107.95" y="146.05"/> +</segment> +<segment> +<wire x1="232.41" y1="104.14" x2="232.41" y2="114.3" width="0.1524" layer="91"/> +<wire x1="232.41" y1="114.3" x2="232.41" y2="116.84" width="0.1524" layer="91"/> +<wire x1="232.41" y1="114.3" x2="242.57" y2="114.3" width="0.1524" layer="91"/> +<wire x1="242.57" y1="114.3" x2="242.57" y2="104.14" width="0.1524" layer="91"/> +<junction x="232.41" y="114.3"/> +<pinref part="U6U1" gate="PW" pin="VSS"/> +<pinref part="U$486" gate="PW-VCC3" pin="VCC3"/> +<pinref part="U5U1" gate="PW" pin="VSS"/> +</segment> +<segment> +<wire x1="33.02" y1="26.67" x2="26.67" y2="26.67" width="0.1524" layer="91"/> +<wire x1="26.67" y1="26.67" x2="26.67" y2="30.48" width="0.1524" layer="91"/> +<pinref part="R6U21" gate="R" pin="1"/> +<pinref part="U$490" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="V1P8-DDR" class="0"> +<segment> +<wire x1="125.73" y1="146.05" x2="125.73" y2="140.97" width="0.1524" layer="91"/> +<wire x1="125.73" y1="140.97" x2="125.73" y2="135.89" width="0.1524" layer="91"/> +<wire x1="125.73" y1="135.89" x2="125.73" y2="134.62" width="0.1524" layer="91"/> +<wire x1="125.73" y1="134.62" x2="125.73" y2="116.84" width="0.1524" layer="91"/> +<wire x1="125.73" y1="116.84" x2="127" y2="116.84" width="0.1524" layer="91"/> +<wire x1="127" y1="114.3" x2="125.73" y2="114.3" width="0.1524" layer="91"/> +<wire x1="125.73" y1="114.3" x2="125.73" y2="116.84" width="0.1524" layer="91"/> +<wire x1="120.65" y1="133.35" x2="120.65" y2="135.89" width="0.1524" layer="91"/> +<wire x1="120.65" y1="135.89" x2="125.73" y2="135.89" width="0.1524" layer="91"/> +<junction x="125.73" y="116.84"/> +<junction x="125.73" y="135.89"/> +<pinref part="P+4" gate="1" pin="V1P8-DDR"/> +<pinref part="J4G4" gate="CONITPXDP" pin="1.0V@2"/> +<pinref part="J4G4" gate="CONITPXDP" pin="1.0V@1"/> +<pinref part="R4T19" gate="R" pin="1"/> +</segment> +</net> +<net name="BPM5-PREQ-N" class="0"> +<segment> +<wire x1="127" y1="106.68" x2="120.65" y2="106.68" width="0.1524" layer="91"/> +<wire x1="120.65" y1="106.68" x2="101.6" y2="106.68" width="0.1524" layer="91"/> +<wire x1="101.6" y1="106.68" x2="69.85" y2="106.68" width="0.1524" layer="91"/> +<wire x1="69.85" y1="106.68" x2="69.85" y2="109.22" width="0.1524" layer="91"/> +<wire x1="69.85" y1="109.22" x2="53.34" y2="109.22" width="0.1524" layer="91"/> +<wire x1="101.6" y1="106.68" x2="101.6" y2="123.19" width="0.1524" layer="91"/> +<wire x1="120.65" y1="123.19" x2="120.65" y2="106.68" width="0.1524" layer="91"/> +<wire x1="114.3" y1="35.56" x2="120.65" y2="35.56" width="0.1524" layer="91"/> +<wire x1="120.65" y1="35.56" x2="120.65" y2="106.68" width="0.1524" layer="91"/> +<junction x="101.6" y="106.68"/> +<junction x="120.65" y="106.68"/> +<pinref part="J4G4" gate="CONITPXDP" pin="PREQ-N"/> +<pinref part="R5U8" gate="R" pin="2"/> +<pinref part="R4T16" gate="R" pin="1"/> +<label x="53.34" y="109.22" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="R4T19" gate="R" pin="2"/> +</segment> +</net> +<net name="BPM4-PRDY-N" class="0"> +<segment> +<wire x1="53.34" y1="104.14" x2="118.11" y2="104.14" width="0.1524" layer="91"/> +<wire x1="118.11" y1="104.14" x2="127" y2="104.14" width="0.1524" layer="91"/> +<pinref part="J4G4" gate="CONITPXDP" pin="PRDY-N"/> +<label x="53.34" y="104.14" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="V1P2" class="0"> +<segment> +<wire x1="101.6" y1="138.43" x2="101.6" y2="133.35" width="0.1524" layer="91"/> +<pinref part="R5U8" gate="R" pin="1"/> +<pinref part="U$123" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="82.55" y1="146.05" x2="82.55" y2="133.35" width="0.1524" layer="91"/> +<pinref part="R6U20" gate="R" pin="1"/> +<pinref part="U$462" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="90.17" y1="62.23" x2="83.82" y2="62.23" width="0.1524" layer="91"/> +<wire x1="83.82" y1="62.23" x2="83.82" y2="63.5" width="0.1524" layer="91"/> +<pinref part="R6U17" gate="R" pin="2"/> +<pinref part="U$457" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="199.39" y1="63.5" x2="199.39" y2="62.23" width="0.1524" layer="91"/> +<pinref part="R6U18" gate="R" pin="2"/> +<pinref part="U$461" gate="PW-V1P2" pin="V1P2"/> +<wire x1="199.39" y1="62.23" x2="199.39" y2="58.42" width="0.1524" layer="91"/> +<wire x1="209.55" y1="62.23" x2="209.55" y2="59.69" width="0.1524" layer="91"/> +<wire x1="204.47" y1="62.23" x2="209.55" y2="62.23" width="0.1524" layer="91"/> +<wire x1="204.47" y1="62.23" x2="204.47" y2="58.42" width="0.1524" layer="91"/> +<pinref part="R4T18" gate="R" pin="2"/> +<pinref part="R4T17" gate="R" pin="2"/> +<wire x1="204.47" y1="62.23" x2="199.39" y2="62.23" width="0.1524" layer="91"/> +<junction x="204.47" y="62.23"/> +<junction x="199.39" y="62.23"/> +</segment> +</net> +<net name="NC-RSVD0" class="0"> +<segment> +<wire x1="194.31" y1="118.11" x2="191.77" y2="116.84" width="0.1524" layer="91"/> +<wire x1="191.77" y1="116.84" x2="172.72" y2="116.84" width="0.1524" layer="91"/> +<label x="175.26" y="117.1575" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="BPM3/RSVD0"/> +</segment> +</net> +<net name="NC-RSVD1" class="0"> +<segment> +<wire x1="194.31" y1="115.57" x2="191.77" y2="114.3" width="0.1524" layer="91"/> +<wire x1="191.77" y1="114.3" x2="172.72" y2="114.3" width="0.1524" layer="91"/> +<label x="175.26" y="114.6175" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="BPM2/RSVD1"/> +</segment> +</net> +<net name="NC-RSVD2" class="0"> +<segment> +<wire x1="194.31" y1="113.03" x2="191.77" y2="111.76" width="0.1524" layer="91"/> +<wire x1="191.77" y1="111.76" x2="172.72" y2="111.76" width="0.1524" layer="91"/> +<label x="175.26" y="112.0775" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="BPM1/RSVD2"/> +</segment> +</net> +<net name="NC-RSVD3" class="0"> +<segment> +<wire x1="194.31" y1="110.49" x2="191.77" y2="109.22" width="0.1524" layer="91"/> +<wire x1="191.77" y1="109.22" x2="172.72" y2="109.22" width="0.1524" layer="91"/> +<label x="175.26" y="109.5375" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="BPM0/RSVD3"/> +</segment> +</net> +<net name="NC-RSVD4" class="0"> +<segment> +<wire x1="194.31" y1="107.95" x2="191.77" y2="106.68" width="0.1524" layer="91"/> +<wire x1="191.77" y1="106.68" x2="172.72" y2="106.68" width="0.1524" layer="91"/> +<label x="175.26" y="106.9975" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD4"/> +</segment> +</net> +<net name="NC-RSVD5" class="0"> +<segment> +<wire x1="194.31" y1="105.41" x2="191.77" y2="104.14" width="0.1524" layer="91"/> +<wire x1="191.77" y1="104.14" x2="172.72" y2="104.14" width="0.1524" layer="91"/> +<label x="175.26" y="104.4575" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD5"/> +</segment> +</net> +<net name="NC-RSVD6" class="0"> +<segment> +<wire x1="194.31" y1="102.87" x2="191.77" y2="101.6" width="0.1524" layer="91"/> +<wire x1="191.77" y1="101.6" x2="172.72" y2="101.6" width="0.1524" layer="91"/> +<label x="175.26" y="101.9175" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD6"/> +</segment> +</net> +<net name="NC-RSVD7" class="0"> +<segment> +<wire x1="194.31" y1="100.33" x2="191.77" y2="99.06" width="0.1524" layer="91"/> +<wire x1="191.77" y1="99.06" x2="172.72" y2="99.06" width="0.1524" layer="91"/> +<label x="175.26" y="99.3775" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD7"/> +</segment> +</net> +<net name="NC-RSVD8" class="0"> +<segment> +<wire x1="194.31" y1="97.79" x2="191.77" y2="96.52" width="0.1524" layer="91"/> +<wire x1="191.77" y1="96.52" x2="172.72" y2="96.52" width="0.1524" layer="91"/> +<label x="175.26" y="96.8375" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD8"/> +</segment> +</net> +<net name="NC-RSVD9" class="0"> +<segment> +<wire x1="194.31" y1="95.25" x2="191.77" y2="93.98" width="0.1524" layer="91"/> +<wire x1="191.77" y1="93.98" x2="172.72" y2="93.98" width="0.1524" layer="91"/> +<label x="175.26" y="94.2975" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD9"/> +</segment> +</net> +<net name="NC-RSVD11" class="0"> +<segment> +<wire x1="194.31" y1="90.17" x2="191.77" y2="88.9" width="0.1524" layer="91"/> +<wire x1="191.77" y1="88.9" x2="172.72" y2="88.9" width="0.1524" layer="91"/> +<label x="175.26" y="89.2175" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD11"/> +</segment> +</net> +<net name="NC-RSVD12" class="0"> +<segment> +<wire x1="194.31" y1="87.63" x2="191.77" y2="86.36" width="0.1524" layer="91"/> +<wire x1="191.77" y1="86.36" x2="172.72" y2="86.36" width="0.1524" layer="91"/> +<label x="175.26" y="86.6775" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD12"/> +</segment> +</net> +<net name="NC-RSVD13" class="0"> +<segment> +<wire x1="194.31" y1="85.09" x2="191.77" y2="83.82" width="0.1524" layer="91"/> +<wire x1="191.77" y1="83.82" x2="172.72" y2="83.82" width="0.1524" layer="91"/> +<label x="175.26" y="84.1375" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD13"/> +</segment> +</net> +<net name="NC-RSVD14" class="0"> +<segment> +<wire x1="194.31" y1="82.55" x2="191.77" y2="81.28" width="0.1524" layer="91"/> +<wire x1="191.77" y1="81.28" x2="172.72" y2="81.28" width="0.1524" layer="91"/> +<label x="175.26" y="81.5975" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD14"/> +</segment> +</net> +<net name="NC-RSVD15" class="0"> +<segment> +<wire x1="194.31" y1="80.01" x2="191.77" y2="78.74" width="0.1524" layer="91"/> +<wire x1="191.77" y1="78.74" x2="172.72" y2="78.74" width="0.1524" layer="91"/> +<label x="175.26" y="79.0575" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD15"/> +</segment> +</net> +<net name="NC-RSVD16" class="0"> +<segment> +<wire x1="194.31" y1="77.47" x2="191.77" y2="76.2" width="0.1524" layer="91"/> +<wire x1="191.77" y1="76.2" x2="172.72" y2="76.2" width="0.1524" layer="91"/> +<label x="175.26" y="76.5175" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD16"/> +</segment> +</net> +<net name="NC-RSVD17" class="0"> +<segment> +<wire x1="194.31" y1="74.93" x2="191.77" y2="73.66" width="0.1524" layer="91"/> +<wire x1="191.77" y1="73.66" x2="172.72" y2="73.66" width="0.1524" layer="91"/> +<label x="175.26" y="73.9775" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD17"/> +</segment> +</net> +<net name="NC-RSVD10" class="0"> +<segment> +<wire x1="194.31" y1="92.71" x2="191.77" y2="91.44" width="0.1524" layer="91"/> +<wire x1="191.77" y1="91.44" x2="172.72" y2="91.44" width="0.1524" layer="91"/> +<label x="175.26" y="91.7575" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RSVD10"/> +</segment> +</net> +<net name="RSVD10" class="0"> +<segment> +<wire x1="127" y1="110.49" x2="95.25" y2="110.49" width="0.1524" layer="91"/> +<wire x1="95.25" y1="110.49" x2="72.39" y2="110.49" width="0.1524" layer="91"/> +<wire x1="72.39" y1="110.49" x2="72.39" y2="114.3" width="0.1524" layer="91"/> +<wire x1="72.39" y1="114.3" x2="45.72" y2="114.3" width="0.1524" layer="91"/> +<wire x1="95.25" y1="110.49" x2="95.25" y2="123.19" width="0.1524" layer="91"/> +<junction x="95.25" y="110.49"/> +<pinref part="J4G4" gate="CONITPXDP" pin="TESTINB-N"/> +<pinref part="R6U5" gate="R" pin="2"/> +<label x="45.72" y="114.3" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ITP-CPUPWRGD" class="0"> +<segment> +<wire x1="127" y1="91.44" x2="107.95" y2="91.44" width="0.1524" layer="91"/> +<wire x1="107.95" y1="91.44" x2="83.82" y2="91.44" width="0.1524" layer="91"/> +<wire x1="107.95" y1="91.44" x2="107.95" y2="123.19" width="0.1524" layer="91"/> +<junction x="107.95" y="91.44"/> +<label x="87.3125" y="91.7575" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="PWRGOOD"/> +<pinref part="R6U10" gate="R" pin="2"/> +<pinref part="R6U9" gate="R" pin="2"/> +</segment> +</net> +<net name="ITP-PCI-CLK-33MHZ-R" class="0"> +<segment> +<wire x1="127" y1="85.09" x2="43.18" y2="85.09" width="0.1524" layer="91"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GCLK-P"/> +<label x="43.18" y="85.09" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ITP-BCLK-P" class="0"> +<segment> +<wire x1="127" y1="74.93" x2="68.58" y2="74.93" width="0.1524" layer="91"/> +<wire x1="68.58" y1="74.93" x2="58.42" y2="74.93" width="0.1524" layer="91"/> +<wire x1="68.58" y1="66.04" x2="68.58" y2="74.93" width="0.1524" layer="91"/> +<junction x="68.58" y="74.93"/> +<label x="72.0725" y="75.2475" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="BCLK-P"/> +<pinref part="R3G25" gate="R" pin="2"/> +<pinref part="R2G13" gate="R" pin="1"/> +</segment> +</net> +<net name="ITP-BCLK-N" class="0"> +<segment> +<wire x1="127" y1="71.12" x2="63.5" y2="71.12" width="0.1524" layer="91"/> +<wire x1="63.5" y1="71.12" x2="58.42" y2="71.12" width="0.1524" layer="91"/> +<wire x1="63.5" y1="63.5" x2="63.5" y2="71.12" width="0.1524" layer="91"/> +<junction x="63.5" y="71.12"/> +<label x="72.0725" y="71.4375" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="BCLK-N"/> +<pinref part="R3G22" gate="R" pin="2"/> +<pinref part="R2G12" gate="R" pin="1"/> +</segment> +</net> +<net name="BPM3" class="0"> +<segment> +<wire x1="127" y1="58.42" x2="116.84" y2="58.42" width="0.1524" layer="91"/> +<wire x1="116.84" y1="58.42" x2="114.3" y2="58.42" width="0.1524" layer="91"/> +<wire x1="116.84" y1="62.23" x2="116.84" y2="58.42" width="0.1524" layer="91"/> +<wire x1="114.3" y1="40.64" x2="116.84" y2="40.64" width="0.1524" layer="91"/> +<wire x1="116.84" y1="40.64" x2="116.84" y2="58.42" width="0.1524" layer="91"/> +<wire x1="100.33" y1="62.23" x2="116.84" y2="62.23" width="0.1524" layer="91"/> +<junction x="116.84" y="58.42"/> +<pinref part="J4G4" gate="CONITPXDP" pin="NC4"/> +<pinref part="R4T15" gate="R" pin="1"/> +<pinref part="R6U17" gate="R" pin="1"/> +<label x="114.3" y="58.42" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MCH-SMBDAT" class="0"> +<segment> +<wire x1="127" y1="50.8" x2="114.3" y2="50.8" width="0.1524" layer="91"/> +<pinref part="J4G4" gate="CONITPXDP" pin="SDA"/> +<label x="114.3" y="50.8" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MCH-SMBCLK" class="0"> +<segment> +<wire x1="127" y1="48.26" x2="91.44" y2="48.26" width="0.1524" layer="91"/> +<pinref part="J4G4" gate="CONITPXDP" pin="SCL"/> +<label x="91.44" y="48.26" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ITP-TCK0" class="0"> +<segment> +<wire x1="172.72" y1="27.94" x2="199.39" y2="27.94" width="0.1524" layer="91"/> +<wire x1="199.39" y1="27.94" x2="199.39" y2="22.86" width="0.1524" layer="91"/> +<wire x1="199.39" y1="22.86" x2="223.52" y2="22.86" width="0.1524" layer="91"/> +<wire x1="193.04" y1="22.86" x2="199.39" y2="22.86" width="0.1524" layer="91"/> +<junction x="199.39" y="22.86"/> +<pinref part="J4G4" gate="CONITPXDP" pin="TCK"/> +<pinref part="R4T1" gate="R" pin="1"/> +<label x="223.52" y="22.86" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="ITP-TRST-IMCH-N" class="0"> +<segment> +<wire x1="172.72" y1="38.1" x2="194.31" y2="38.1" width="0.1524" layer="91"/> +<wire x1="194.31" y1="38.1" x2="194.31" y2="40.64" width="0.1524" layer="91"/> +<wire x1="194.31" y1="40.64" x2="213.36" y2="40.64" width="0.1524" layer="91"/> +<wire x1="190.5" y1="40.64" x2="194.31" y2="40.64" width="0.1524" layer="91"/> +<junction x="194.31" y="40.64"/> +<pinref part="J4G4" gate="CONITPXDP" pin="TRSTN"/> +<pinref part="R4R13" gate="R" pin="2"/> +<label x="213.36" y="40.64" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="ITP-TDO-IMCH" class="0"> +<segment> +<wire x1="172.72" y1="33.02" x2="199.39" y2="33.02" width="0.1524" layer="91"/> +<wire x1="199.39" y1="33.02" x2="207.01" y2="33.02" width="0.1524" layer="91"/> +<wire x1="207.01" y1="33.02" x2="207.01" y2="30.48" width="0.1524" layer="91"/> +<wire x1="207.01" y1="30.48" x2="217.17" y2="30.48" width="0.1524" layer="91"/> +<wire x1="199.39" y1="48.26" x2="199.39" y2="33.02" width="0.1524" layer="91"/> +<junction x="199.39" y="33.02"/> +<pinref part="J4G4" gate="CONITPXDP" pin="TDO"/> +<pinref part="R6U18" gate="R" pin="1"/> +<label x="217.17" y="30.48" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="ITP-TMS-IMCH" class="0"> +<segment> +<wire x1="172.72" y1="35.56" x2="209.55" y2="35.56" width="0.1524" layer="91"/> +<wire x1="209.55" y1="35.56" x2="217.17" y2="35.56" width="0.1524" layer="91"/> +<wire x1="209.55" y1="49.53" x2="209.55" y2="35.56" width="0.1524" layer="91"/> +<junction x="209.55" y="35.56"/> +<pinref part="J4G4" gate="CONITPXDP" pin="TMS"/> +<pinref part="R4T18" gate="R" pin="1"/> +<label x="217.17" y="35.56" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="ITP-TDI-IMCH" class="0"> +<segment> +<wire x1="172.72" y1="30.48" x2="204.47" y2="30.48" width="0.1524" layer="91"/> +<wire x1="204.47" y1="30.48" x2="204.47" y2="26.67" width="0.1524" layer="91"/> +<wire x1="204.47" y1="26.67" x2="218.44" y2="26.67" width="0.1524" layer="91"/> +<wire x1="204.47" y1="48.26" x2="204.47" y2="30.48" width="0.1524" layer="91"/> +<junction x="204.47" y="30.48"/> +<pinref part="J4G4" gate="CONITPXDP" pin="TDI"/> +<pinref part="R4T17" gate="R" pin="1"/> +<label x="218.44" y="26.67" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="N$36" class="0"> +<segment> +<wire x1="104.14" y1="95.25" x2="127" y2="95.25" width="0.1524" layer="91"/> +<wire x1="104.14" y1="95.25" x2="104.14" y2="100.33" width="0.1524" layer="91"/> +<wire x1="104.14" y1="100.33" x2="96.52" y2="100.33" width="0.1524" layer="91"/> +<pinref part="J4G4" gate="CONITPXDP" pin="RESET-N"/> +<pinref part="R6U12" gate="R" pin="2"/> +</segment> +</net> +<net name="CPURST-N" class="0"> +<segment> +<wire x1="86.36" y1="100.33" x2="82.55" y2="100.33" width="0.1524" layer="91"/> +<wire x1="74.93" y1="100.33" x2="82.55" y2="100.33" width="0.1524" layer="91"/> +<wire x1="82.55" y1="100.33" x2="50.8" y2="100.33" width="0.1524" layer="91"/> +<wire x1="82.55" y1="100.33" x2="82.55" y2="123.19" width="0.1524" layer="91"/> +<junction x="82.55" y="100.33"/> +<pinref part="R6U12" gate="R" pin="1"/> +<pinref part="R6U20" gate="R" pin="2"/> +<label x="50.8" y="100.33" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ITP-DBRST-N" class="0"> +<segment> +<wire x1="172.72" y1="69.85" x2="218.44" y2="69.85" width="0.1524" layer="91"/> +<pinref part="J4G4" gate="CONITPXDP" pin="DBR-N"/> +<label x="218.44" y="69.85" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="XDP-PRESENT-N" class="0"> +<segment> +<wire x1="127" y1="20.32" x2="127" y2="11.43" width="0.1524" layer="91"/> +<wire x1="91.44" y1="26.67" x2="88.9" y2="26.67" width="0.1524" layer="91"/> +<wire x1="88.9" y1="26.67" x2="88.9" y2="11.43" width="0.1524" layer="91"/> +<wire x1="88.9" y1="11.43" x2="53.34" y2="11.43" width="0.1524" layer="91"/> +<wire x1="55.88" y1="26.67" x2="53.34" y2="26.67" width="0.1524" layer="91"/> +<wire x1="53.34" y1="26.67" x2="53.34" y2="11.43" width="0.1524" layer="91"/> +<wire x1="88.9" y1="11.43" x2="127" y2="11.43" width="0.1524" layer="91"/> +<wire x1="43.18" y1="26.67" x2="53.34" y2="26.67" width="0.1524" layer="91"/> +<wire x1="43.18" y1="11.43" x2="53.34" y2="11.43" width="0.1524" layer="91"/> +<junction x="88.9" y="11.43"/> +<junction x="53.34" y="26.67"/> +<junction x="53.34" y="11.43"/> +<label x="63.8175" y="11.7475" size="1.778" layer="92"/> +<pinref part="J4G4" gate="CONITPXDP" pin="XDPPRESENT-N"/> +<pinref part="U5U1" gate="A" pin="OE"/> +<pinref part="U6U1" gate="A" pin="OE"/> +<pinref part="R6U21" gate="R" pin="2"/> +<pinref part="R6U22" gate="R" pin="1"/> +</segment> +</net> +<net name="CPU-PWR-GD" class="0"> +<segment> +<wire x1="73.66" y1="91.44" x2="54.61" y2="91.44" width="0.1524" layer="91"/> +<pinref part="R6U10" gate="R" pin="1"/> +<label x="54.61" y="91.44" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="BPM5-PREQ-N-R" class="0"> +<segment> +<wire x1="104.14" y1="35.56" x2="97.79" y2="35.56" width="0.1524" layer="91"/> +<wire x1="97.79" y1="35.56" x2="97.79" y2="34.29" width="0.1524" layer="91"/> +<pinref part="R4T16" gate="R" pin="2"/> +<pinref part="U5U1" gate="A" pin="A"/> +</segment> +</net> +<net name="BPM3-R" class="0"> +<segment> +<wire x1="104.14" y1="40.64" x2="62.23" y2="40.64" width="0.1524" layer="91"/> +<wire x1="62.23" y1="40.64" x2="62.23" y2="34.29" width="0.1524" layer="91"/> +<pinref part="R4T15" gate="R" pin="2"/> +<pinref part="U6U1" gate="A" pin="A"/> +</segment> +</net> +<net name="ITP-BCLK-R-P" class="0"> +<segment> +<wire x1="48.26" y1="74.93" x2="33.02" y2="74.93" width="0.1524" layer="91"/> +<pinref part="R3G25" gate="R" pin="1"/> +<label x="33.02" y="74.93" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ITP-BCLK-R-N" class="0"> +<segment> +<wire x1="48.26" y1="71.12" x2="33.02" y2="71.12" width="0.1524" layer="91"/> +<pinref part="R3G22" gate="R" pin="1"/> +<label x="33.02" y="71.12" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$41" class="0"> +<segment> +<wire x1="114.3" y1="77.47" x2="107.95" y2="77.47" width="0.1524" layer="91"/> +<wire x1="127" y1="81.28" x2="114.3" y2="81.28" width="0.1524" layer="91"/> +<wire x1="114.3" y1="81.28" x2="114.3" y2="123.19" width="0.1524" layer="91"/> +<wire x1="114.3" y1="81.28" x2="110.49" y2="81.28" width="0.1524" layer="91"/> +<wire x1="110.49" y1="81.28" x2="95.25" y2="81.28" width="0.1524" layer="91"/> +<wire x1="114.3" y1="77.47" x2="114.3" y2="81.28" width="0.1524" layer="91"/> +<junction x="114.3" y="81.28"/> +<pinref part="R6U4" gate="R" pin="2"/> +<pinref part="R6U3" gate="R" pin="2"/> +<pinref part="J4G4" gate="CONITPXDP" pin="GCL-N"/> +<pinref part="C6U1" gate="C" pin="1"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +</plain> +<instances> +<instance part="FRAME32" gate="G$1" x="0" y="0"/> +<instance part="FRAME32" gate="G$2" x="180.34" y="0"/> +<instance part="R5E17" gate="R" x="129.54" y="111.76" smashed="yes"> +<attribute name="NAME" x="133.7574" y="112.0754" size="1.778" layer="95"/> +<attribute name="VALUE" x="125.729" y="112.0064" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="111.76" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$467" gate="G$1" x="147.32" y="91.44" rot="R90"/> +<instance part="R4T13" gate="R" x="129.54" y="93.98" smashed="yes" rot="R180"> +<attribute name="NAME" x="133.0325" y="96.2025" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="126.365" y="94.2975" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="93.98" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4T9" gate="R" x="129.54" y="134.62" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.5034" y="136.5906" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="125.096" y="135.1839" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="134.62" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3T1" gate="R" x="129.54" y="132.08" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.5034" y="134.0506" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="125.096" y="132.3264" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="132.08" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4T8" gate="R" x="129.54" y="129.54" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.5034" y="131.5106" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="125.096" y="129.7864" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="129.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4T11" gate="R" x="129.54" y="127" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.5034" y="128.9706" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="125.096" y="127.2464" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="127" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3R36" gate="R" x="129.54" y="124.46" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.5034" y="126.4306" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="125.096" y="124.7064" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="124.46" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4T10" gate="R" x="129.54" y="121.92" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.5034" y="123.8906" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="125.096" y="122.1664" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="121.92" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3R31" gate="R" x="129.54" y="119.38" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.5034" y="121.3506" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="125.096" y="119.6264" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="119.38" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3R34" gate="R" x="129.54" y="116.84" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.5034" y="118.8106" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="125.096" y="117.0864" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="116.84" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3T17" gate="R" x="129.54" y="114.3" smashed="yes"> +<attribute name="NAME" x="133.6675" y="114.6175" size="1.778" layer="95"/> +<attribute name="VALUE" x="125.4125" y="114.6175" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="114.3" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R5T13" gate="R" x="129.54" y="109.22" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.985" y="111.125" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="126.366" y="109.4664" size="1.778" layer="96" rot="MR0"/> +<attribute name="DNP" x="142.875" y="109.22" size="1.778" layer="96"/> +<attribute name="POWER" x="129.54" y="109.22" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4R7" gate="R" x="129.54" y="99.06" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.6675" y="100.965" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="126.6825" y="99.3775" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="99.06" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4R9" gate="R" x="129.54" y="101.6" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.6675" y="103.8225" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="126.6825" y="101.9175" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="101.6" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R4R11" gate="R" x="129.54" y="104.14" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.6675" y="106.3625" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="126.6825" y="104.4575" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="129.54" y="104.14" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R7J1" gate="R" x="129.54" y="88.9" smashed="yes" rot="MR180"> +<attribute name="NAME" x="133.0325" y="91.1225" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="126.6825" y="91.1225" size="1.778" layer="96" rot="R180"/> +<attribute name="POWER" x="129.54" y="88.9" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U6E1" gate="CAN" x="87.63" y="153.67" rot="MR0"/> +<instance part="U6E1" gate="JTAG" x="187.96" y="50.8" smashed="yes" rot="MR0"> +<attribute name="NAME" x="172.72" y="24.13" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="172.72" y="36.195" size="1.778" layer="96" rot="MR90"/> +</instance> +<instance part="U6E1" gate="NC" x="187.96" y="148.59" smashed="yes" rot="MR0"> +<attribute name="NAME" x="172.085" y="107.95" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="172.085" y="142.875" size="1.778" layer="96" rot="MR90"/> +</instance> +<instance part="U6E1" gate="PCI" x="34.29" y="95.25" rot="MR0"/> +<instance part="U6E1" gate="RESERVED" x="87.63" y="119.38" rot="MR0"/> +<instance part="U$477" gate="G$1" x="147.32" y="121.92" rot="R90"/> +<instance part="U$466" gate="G$1" x="147.32" y="106.68" rot="R90"/> +<instance part="R6Y7" gate="R" x="129.54" y="86.36" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.35" y="88.265" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="126.6825" y="88.5825" size="1.778" layer="96" rot="R180"/> +<attribute name="POWER" x="129.54" y="86.36" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6Y8" gate="R" x="129.54" y="83.82" smashed="yes" rot="MR0"> +<attribute name="NAME" x="133.6675" y="85.725" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="126.6825" y="86.0425" size="1.778" layer="96" rot="R180"/> +<attribute name="POWER" x="129.54" y="83.82" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$15" gate="G$1" x="232.41" y="78.74" rot="MR270"/> +<instance part="R18" gate="R" x="219.71" y="78.74" smashed="yes"> +<attribute name="NAME" x="223.52" y="80.01" size="1.778" layer="95"/> +<attribute name="VALUE" x="217.17" y="80.01" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="219.71" y="78.74" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R5E3" gate="R" x="80.01" y="15.24" rot="R180"> +<attribute name="POWER" x="80.01" y="15.24" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="80.01" y="15.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R34" gate="R" x="119.38" y="152.4" rot="MR180"> +<attribute name="POWER" x="119.38" y="152.4" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R43" gate="R" x="119.38" y="162.56" rot="MR180"> +<attribute name="POWER" x="119.38" y="162.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$4" gate="PW-V1P2" x="102.87" y="19.05"/> +<instance part="U$31" gate="PW-VCC3" x="132.08" y="170.18"/> +<instance part="U$33" gate="PW-VCC3" x="153.67" y="114.3"/> +</instances> +<busses> +<bus name="NC-RSVD[0..17]"> +<segment> +<wire x1="228.6" y1="96.52" x2="228.6" y2="132.08" width="0.4064" layer="92"/> +<wire x1="228.6" y1="132.08" x2="246.38" y2="132.08" width="0.4064" layer="92"/> +<wire x1="246.38" y1="132.08" x2="246.38" y2="133.35" width="0.4064" layer="92"/> +<wire x1="246.38" y1="133.35" x2="248.92" y2="133.35" width="0.4064" layer="92"/> +<wire x1="248.92" y1="133.35" x2="248.92" y2="132.08" width="0.4064" layer="92"/> +<label x="225.7425" y="132.715" size="1.778" layer="92"/> +</segment> +<segment> +<wire x1="227.33" y1="38.1" x2="227.33" y2="46.99" width="0.4064" layer="92"/> +<wire x1="227.33" y1="46.99" x2="227.33" y2="43.18" width="0.4064" layer="92"/> +<wire x1="227.33" y1="43.18" x2="254" y2="43.18" width="0.4064" layer="92"/> +<wire x1="254" y1="43.18" x2="254" y2="44.45" width="0.4064" layer="92"/> +<wire x1="254" y1="44.45" x2="256.54" y2="44.45" width="0.4064" layer="92"/> +<wire x1="256.54" y1="44.45" x2="256.54" y2="43.18" width="0.4064" layer="92"/> +<label x="229.87" y="43.815" size="1.778" layer="92"/> +</segment> +</bus> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="134.62" y1="111.76" x2="143.51" y2="111.76" width="0.1524" layer="91"/> +<wire x1="143.51" y1="116.84" x2="143.51" y2="119.38" width="0.1524" layer="91"/> +<wire x1="143.51" y1="119.38" x2="143.51" y2="121.92" width="0.1524" layer="91"/> +<wire x1="143.51" y1="121.92" x2="143.51" y2="124.46" width="0.1524" layer="91"/> +<wire x1="143.51" y1="124.46" x2="143.51" y2="127" width="0.1524" layer="91"/> +<wire x1="143.51" y1="127" x2="143.51" y2="129.54" width="0.1524" layer="91"/> +<wire x1="143.51" y1="129.54" x2="143.51" y2="132.08" width="0.1524" layer="91"/> +<wire x1="143.51" y1="132.08" x2="143.51" y2="134.62" width="0.1524" layer="91"/> +<wire x1="134.62" y1="116.84" x2="143.51" y2="116.84" width="0.1524" layer="91"/> +<wire x1="143.51" y1="119.38" x2="134.62" y2="119.38" width="0.1524" layer="91"/> +<wire x1="134.62" y1="121.92" x2="143.51" y2="121.92" width="0.1524" layer="91"/> +<wire x1="134.62" y1="124.46" x2="143.51" y2="124.46" width="0.1524" layer="91"/> +<wire x1="134.62" y1="127" x2="143.51" y2="127" width="0.1524" layer="91"/> +<wire x1="134.62" y1="129.54" x2="143.51" y2="129.54" width="0.1524" layer="91"/> +<wire x1="134.62" y1="132.08" x2="143.51" y2="132.08" width="0.1524" layer="91"/> +<wire x1="134.62" y1="134.62" x2="143.51" y2="134.62" width="0.1524" layer="91"/> +<wire x1="143.51" y1="116.84" x2="143.51" y2="114.3" width="0.1524" layer="91"/> +<wire x1="143.51" y1="114.3" x2="143.51" y2="111.76" width="0.1524" layer="91"/> +<wire x1="134.62" y1="114.3" x2="143.51" y2="114.3" width="0.1524" layer="91"/> +<wire x1="146.05" y1="121.92" x2="143.51" y2="121.92" width="0.1524" layer="91"/> +<junction x="143.51" y="132.08"/> +<junction x="143.51" y="129.54"/> +<junction x="143.51" y="127"/> +<junction x="143.51" y="124.46"/> +<junction x="143.51" y="121.92"/> +<junction x="143.51" y="119.38"/> +<junction x="143.51" y="116.84"/> +<junction x="143.51" y="114.3"/> +<pinref part="R5E17" gate="R" pin="2"/> +<pinref part="R3R34" gate="R" pin="1"/> +<pinref part="R3R31" gate="R" pin="1"/> +<pinref part="R4T10" gate="R" pin="1"/> +<pinref part="R3R36" gate="R" pin="1"/> +<pinref part="R4T11" gate="R" pin="1"/> +<pinref part="R4T8" gate="R" pin="1"/> +<pinref part="R3T1" gate="R" pin="1"/> +<pinref part="R4T9" gate="R" pin="1"/> +<pinref part="R3T17" gate="R" pin="2"/> +<pinref part="U$477" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="146.05" y1="106.68" x2="143.51" y2="106.68" width="0.1524" layer="91"/> +<wire x1="143.51" y1="106.68" x2="104.14" y2="106.68" width="0.1524" layer="91"/> +<wire x1="134.62" y1="104.14" x2="143.51" y2="104.14" width="0.1524" layer="91"/> +<wire x1="143.51" y1="104.14" x2="143.51" y2="106.68" width="0.1524" layer="91"/> +<wire x1="134.62" y1="99.06" x2="143.51" y2="99.06" width="0.1524" layer="91"/> +<wire x1="143.51" y1="99.06" x2="143.51" y2="101.6" width="0.1524" layer="91"/> +<wire x1="143.51" y1="101.6" x2="143.51" y2="104.14" width="0.1524" layer="91"/> +<wire x1="134.62" y1="101.6" x2="143.51" y2="101.6" width="0.1524" layer="91"/> +<wire x1="143.51" y1="96.52" x2="104.14" y2="96.52" width="0.1524" layer="91"/> +<wire x1="143.51" y1="96.52" x2="143.51" y2="99.06" width="0.1524" layer="91"/> +<junction x="143.51" y="106.68"/> +<junction x="143.51" y="104.14"/> +<junction x="143.51" y="101.6"/> +<junction x="143.51" y="99.06"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED11"/> +<pinref part="U$466" gate="G$1" pin="GND"/> +<pinref part="R4R11" gate="R" pin="1"/> +<pinref part="R4R7" gate="R" pin="1"/> +<pinref part="R4R9" gate="R" pin="1"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED15"/> +</segment> +<segment> +<wire x1="104.14" y1="91.44" x2="143.51" y2="91.44" width="0.1524" layer="91"/> +<wire x1="143.51" y1="91.44" x2="146.05" y2="91.44" width="0.1524" layer="91"/> +<wire x1="134.62" y1="88.9" x2="143.51" y2="88.9" width="0.1524" layer="91"/> +<wire x1="143.51" y1="88.9" x2="143.51" y2="91.44" width="0.1524" layer="91"/> +<junction x="143.51" y="91.44"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED17"/> +<pinref part="U$467" gate="G$1" pin="GND"/> +<pinref part="R7J1" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="224.79" y1="78.74" x2="231.14" y2="78.74" width="0.1524" layer="91"/> +<pinref part="U$15" gate="G$1" pin="GND"/> +<pinref part="R18" gate="R" pin="2"/> +</segment> +</net> +<net name="N$534" class="0"> +<segment> +<wire x1="104.14" y1="111.76" x2="124.46" y2="111.76" width="0.1524" layer="91"/> +<pinref part="R5E17" gate="R" pin="1"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED9"/> +</segment> +</net> +<net name="TEST0" class="0"> +<segment> +<wire x1="104.14" y1="134.62" x2="124.46" y2="134.62" width="0.1524" layer="91"/> +<label x="115.57" y="136.525" size="1.778" layer="92" rot="R180"/> +<pinref part="R4T9" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED0"/> +</segment> +</net> +<net name="TEST1" class="0"> +<segment> +<wire x1="104.14" y1="132.08" x2="124.46" y2="132.08" width="0.1524" layer="91"/> +<label x="115.57" y="133.985" size="1.778" layer="92" rot="R180"/> +<pinref part="R3T1" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED1"/> +</segment> +</net> +<net name="TEST2" class="0"> +<segment> +<wire x1="104.14" y1="129.54" x2="124.46" y2="129.54" width="0.1524" layer="91"/> +<label x="115.57" y="131.445" size="1.778" layer="92" rot="R180"/> +<pinref part="R4T8" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED2"/> +</segment> +</net> +<net name="TEST3" class="0"> +<segment> +<wire x1="104.14" y1="127" x2="124.46" y2="127" width="0.1524" layer="91"/> +<label x="115.8875" y="128.905" size="1.778" layer="92" rot="R180"/> +<pinref part="R4T11" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED3"/> +</segment> +</net> +<net name="TEST4" class="0"> +<segment> +<wire x1="104.14" y1="124.46" x2="124.46" y2="124.46" width="0.1524" layer="91"/> +<label x="115.57" y="126.365" size="1.778" layer="92" rot="R180"/> +<pinref part="R3R36" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED4"/> +</segment> +</net> +<net name="TEST5" class="0"> +<segment> +<wire x1="104.14" y1="121.92" x2="124.46" y2="121.92" width="0.1524" layer="91"/> +<label x="115.57" y="123.825" size="1.778" layer="92" rot="R180"/> +<pinref part="R4T10" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED5"/> +</segment> +</net> +<net name="TEST6" class="0"> +<segment> +<wire x1="104.14" y1="119.38" x2="124.46" y2="119.38" width="0.1524" layer="91"/> +<label x="115.57" y="121.285" size="1.778" layer="92" rot="R180"/> +<pinref part="R3R31" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED6"/> +</segment> +</net> +<net name="TEST7" class="0"> +<segment> +<wire x1="104.14" y1="116.84" x2="124.46" y2="116.84" width="0.1524" layer="91"/> +<label x="115.57" y="118.745" size="1.778" layer="92" rot="R180"/> +<pinref part="R3R34" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED7"/> +</segment> +</net> +<net name="N$536" class="0"> +<segment> +<wire x1="104.14" y1="93.98" x2="124.46" y2="93.98" width="0.1524" layer="91"/> +<pinref part="R4T13" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED16"/> +</segment> +</net> +<net name="N$135" class="0"> +<segment> +<wire x1="124.46" y1="114.3" x2="104.14" y2="114.3" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED8"/> +<pinref part="R3T17" gate="R" pin="1"/> +</segment> +</net> +<net name="N$140" class="0"> +<segment> +<wire x1="124.46" y1="104.14" x2="104.14" y2="104.14" width="0.1524" layer="91"/> +<pinref part="R4R11" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED12"/> +</segment> +</net> +<net name="N$141" class="0"> +<segment> +<wire x1="104.14" y1="101.6" x2="124.46" y2="101.6" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED13"/> +<pinref part="R4R9" gate="R" pin="2"/> +</segment> +</net> +<net name="N$142" class="0"> +<segment> +<wire x1="104.14" y1="99.06" x2="124.46" y2="99.06" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED14"/> +<pinref part="R4R7" gate="R" pin="2"/> +</segment> +</net> +<net name="N$143" class="0"> +<segment> +<wire x1="124.46" y1="88.9" x2="104.14" y2="88.9" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED18"/> +<pinref part="R7J1" gate="R" pin="1"/> +</segment> +</net> +<net name="N$144" class="0"> +<segment> +<wire x1="124.46" y1="86.36" x2="104.14" y2="86.36" width="0.1524" layer="91"/> +<pinref part="R6Y7" gate="R" pin="2"/> +<pinref part="U6E1" gate="RESERVED" pin="RESERVED19"/> +</segment> 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size="2.54" layer="94">LEDs ISDN GPIO FXO FXS</text> +<text x="21.59" y="68.58" size="2.54" layer="94">SATA / PWRGD / ERROR CPU</text> +<text x="80.01" y="173.99" size="3.81" layer="94">FRONT PANEL LED</text> +</plain> +<instances> +<instance part="FRAME33" gate="G$1" x="0" y="0"/> +<instance part="FRAME33" gate="G$2" x="180.34" y="0"/> +<instance part="U9" gate="P" x="68.58" y="139.7" rot="R90"/> +<instance part="U9" gate="G" x="83.82" y="107.95" smashed="yes"> +<attribute name="NAME" x="77.47" y="123.825" size="1.778" layer="95" font="vector"/> +</instance> +<instance part="U12" gate="P" x="7.62" y="119.38"/> +<instance part="U12" gate="G" x="33.02" y="97.79" smashed="yes"> +<attribute name="NAME" x="27.94" y="106.68" size="1.778" layer="95"/> +<attribute name="VALUE" x="25.4" y="88.9" size="1.778" layer="96"/> +</instance> +<instance part="U$373" gate="G$1" x="7.62" y="107.95"/> +<instance part="C5" gate="C" x="68.58" y="132.08" rot="R90"> +<attribute name="VOLTAGE" x="68.58" y="132.08" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="68.58" y="132.08" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="68.58" y="132.08" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$374" gate="G$1" x="83.82" y="132.08" rot="R90"/> +<instance part="R2" gate="R" x="121.92" y="157.48" smashed="yes" rot="R180"> +<attribute name="NAME" x="119.0625" y="157.7975" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="125.4125" y="157.7975" size="1.778" layer="96"/> +<attribute name="POWER" x="121.92" y="157.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$558" gate="PW-VCC3" x="53.34" y="139.7" rot="R90"/> +<instance part="U$559" gate="PW-VCC3" x="7.62" y="132.08"/> +<instance part="R55" gate="R" x="228.6" y="139.7" rot="MR180"> +<attribute name="POWER" x="228.6" y="139.7" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED9" gate="DL" x="242.57" y="143.51" smashed="yes" rot="R90"> +<attribute name="NAME" x="244.475" y="139.3825" size="1.778" layer="95"/> +<attribute name="VALUE" x="238.76" y="135.89" size="1.778" layer="96"/> +</instance> +<instance part="R56" gate="R" x="228.6" y="147.32" rot="MR0"> +<attribute name="POWER" x="228.6" y="147.32" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R57" gate="R" x="228.6" y="101.6" rot="MR180"> +<attribute name="POWER" x="228.6" y="101.6" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED10" gate="DL" x="242.57" y="105.41" smashed="yes" rot="R90"> +<attribute name="NAME" x="244.475" y="101.2825" size="1.778" layer="95"/> +<attribute name="VALUE" x="241.3" y="97.79" size="1.778" layer="96"/> +</instance> +<instance part="R58" gate="R" x="228.6" y="109.22" rot="MR0"> +<attribute name="POWER" x="228.6" y="109.22" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R59" gate="R" x="228.6" y="62.23" rot="MR180"> +<attribute name="POWER" x="228.6" y="62.23" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED11" gate="DL" x="242.57" y="66.04" smashed="yes" rot="R90"> +<attribute name="NAME" x="244.475" y="61.9125" size="1.778" layer="95"/> +<attribute name="VALUE" x="240.03" y="58.42" size="1.778" layer="96"/> +</instance> +<instance part="R60" gate="R" x="228.6" y="69.85" rot="MR0"> +<attribute name="POWER" x="228.6" y="69.85" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED1" gate="DL" x="139.7" y="156.21" smashed="yes" rot="MR270"> +<attribute name="NAME" x="149.225" y="158.4325" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="154.94" y="161.29" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="R47" gate="R" x="121.92" y="143.51" smashed="yes" rot="R180"> +<attribute name="NAME" x="119.0625" y="143.8275" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="125.4125" y="143.8275" size="1.778" layer="96"/> +<attribute name="POWER" x="121.92" y="143.51" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED2" gate="DL" x="139.7" y="142.24" smashed="yes" rot="MR270"> +<attribute name="NAME" x="149.225" y="144.4625" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="154.94" y="147.32" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="R49" gate="R" x="121.92" y="130.81" smashed="yes" rot="R180"> +<attribute name="NAME" x="119.0625" y="131.1275" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="125.4125" y="131.1275" size="1.778" layer="96"/> +<attribute name="POWER" x="121.92" y="130.81" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED3" gate="DL" x="139.7" y="129.54" smashed="yes" rot="MR270"> +<attribute name="NAME" x="149.225" y="131.7625" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="154.94" y="134.62" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="R51" gate="R" x="121.92" y="116.84" smashed="yes" rot="R180"> +<attribute name="NAME" x="119.0625" y="117.1575" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="125.4125" y="117.1575" size="1.778" layer="96"/> +<attribute name="POWER" x="121.92" y="116.84" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED4" gate="DL" x="139.7" y="115.57" smashed="yes" rot="MR270"> +<attribute name="NAME" x="149.225" y="117.7925" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="154.94" y="120.65" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="R61" gate="R" x="121.92" y="102.87" smashed="yes" rot="R180"> +<attribute name="NAME" x="119.0625" y="103.1875" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="125.4125" y="103.1875" size="1.778" layer="96"/> +<attribute name="POWER" x="121.92" y="102.87" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED5" gate="DL" x="139.7" y="101.6" smashed="yes" rot="MR270"> +<attribute name="NAME" x="149.225" y="103.8225" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="154.94" y="106.68" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="R62" gate="R" x="121.92" y="100.33" smashed="yes" rot="R180"> +<attribute name="NAME" x="119.0625" y="100.6475" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="125.4125" y="100.6475" size="1.778" layer="96"/> +<attribute name="POWER" x="121.92" y="100.33" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R63" gate="R" x="121.92" y="88.9" smashed="yes" rot="R180"> +<attribute name="NAME" x="119.0625" y="89.2175" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="125.4125" y="89.2175" size="1.778" layer="96"/> +<attribute name="POWER" x="121.92" y="88.9" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED6" gate="DL" x="139.7" y="87.63" smashed="yes" rot="MR270"> +<attribute name="NAME" x="142.875" y="91.7575" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="154.94" y="92.71" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="R64" gate="R" x="121.92" y="86.36" smashed="yes" rot="R180"> +<attribute name="NAME" x="119.0625" y="86.6775" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="125.4125" y="86.6775" size="1.778" layer="96"/> +<attribute name="POWER" x="121.92" y="86.36" size="1.778" layer="96" display="off"/> +</instance> +<instance part="LED12" gate="DL" x="101.6" y="48.26" smashed="yes" rot="R90"> +<attribute name="NAME" x="109.22" y="48.26" size="1.778" layer="95"/> +<attribute name="VALUE" x="109.22" y="45.72" size="1.778" layer="96"/> +</instance> +<instance part="R70" gate="R" x="76.2" y="46.99" smashed="yes" rot="MR0"> +<attribute name="NAME" x="73.3425" y="47.3075" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="81.915" y="47.3075" size="1.778" layer="96"/> +<attribute name="POWER" x="76.2" y="46.99" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$99" gate="G$1" x="106.68" y="29.21"/> +<instance part="LED13" gate="DL" x="101.6" y="36.83" smashed="yes" rot="MR270"> +<attribute name="NAME" x="109.22" y="38.1" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="109.22" y="35.56" size="1.778" layer="96" rot="MR180"/> +</instance> +<instance part="R72" gate="R" x="76.2" y="39.37" smashed="yes" rot="MR0"> +<attribute name="NAME" x="73.3425" y="39.6875" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="79.375" y="39.6875" size="1.778" layer="96"/> +<attribute name="POWER" x="76.2" y="39.37" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$428" gate="G$1" x="251.46" y="144.78" rot="R90"/> +<instance part="U$429" gate="G$1" x="251.46" y="106.68" rot="R90"/> +<instance part="U$445" gate="G$1" x="251.46" y="67.31" rot="R90"/> +<instance part="R21" gate="R" x="76.2" y="49.53" smashed="yes" rot="MR0"> +<attribute name="NAME" x="73.3425" y="49.8475" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="81.915" y="49.8475" size="1.778" layer="96"/> +<attribute name="DNP" x="74.93" y="50.8" size="1.778" layer="96"/> +<attribute name="POWER" x="76.2" y="49.53" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$569" gate="G$1" x="60.96" y="87.63"/> +<instance part="U8" gate="G" x="208.28" y="143.51"/> +<instance part="U$588" gate="G$1" x="190.5" y="134.62" rot="R270"/> +<instance part="U13" gate="G" x="208.28" y="105.41"/> +<instance part="U$604" gate="G$1" x="191.77" y="96.52" rot="R270"/> +<instance part="U15" gate="G" x="208.28" y="66.04"/> +<instance part="U$607" gate="G$1" x="191.77" y="57.15" rot="R270"/> +<instance part="U$80" gate="G$1" x="179.07" y="153.67"/> +<instance part="U$81" gate="G$1" x="180.34" y="123.19"/> +<instance part="U$84" gate="G$1" x="181.61" y="76.2"/> +<instance part="U$197" gate="G$1" x="156.21" y="78.74"/> +<instance part="U17" gate="G" x="52.07" y="43.18"/> +<instance part="U$200" gate="G$1" x="35.56" y="34.29" rot="R270"/> +<instance part="U$204" gate="PW-VCC3" x="35.56" y="64.77" rot="MR0"/> +<instance part="C13" gate="C" x="50.8" y="60.96" rot="R270"> +<attribute name="VOLTAGE" x="50.8" y="60.96" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TOLERANCE" x="50.8" y="60.96" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TYPE" x="50.8" y="60.96" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="U$176" gate="G$1" x="63.5" y="60.96" rot="R90"/> +<instance part="C14" gate="C" x="196.85" y="119.38" rot="R270"> +<attribute name="VOLTAGE" x="196.85" y="119.38" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TOLERANCE" x="196.85" y="119.38" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TYPE" x="196.85" y="119.38" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="U$202" gate="G$1" x="208.28" y="119.38" rot="R90"/> +</instances> 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width="0.1524" layer="91"/> +<wire x1="81.28" y1="139.7" x2="76.2" y2="139.7" width="0.1524" layer="91"/> +<junction x="81.28" y="132.08"/> +<pinref part="C5" gate="C" pin="1"/> +<pinref part="U$374" gate="G$1" pin="GND"/> +<pinref part="U9" gate="P" pin="GND"/> +</segment> +<segment> +<wire x1="246.38" y1="144.78" x2="247.65" y2="144.78" width="0.1524" layer="91"/> +<wire x1="247.65" y1="144.78" x2="247.65" y2="142.24" width="0.1524" layer="91"/> +<wire x1="247.65" y1="142.24" x2="246.38" y2="142.24" width="0.1524" layer="91"/> +<wire x1="247.65" y1="144.78" x2="250.19" y2="144.78" width="0.1524" layer="91"/> +<junction x="247.65" y="144.78"/> +<pinref part="LED9" gate="DL" pin="K2"/> +<pinref part="LED9" gate="DL" pin="K1"/> +<pinref part="U$428" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="246.38" y1="106.68" x2="247.65" y2="106.68" width="0.1524" layer="91"/> +<wire x1="247.65" y1="106.68" x2="247.65" y2="104.14" width="0.1524" layer="91"/> +<wire x1="247.65" y1="104.14" x2="246.38" y2="104.14" width="0.1524" layer="91"/> +<wire x1="247.65" y1="106.68" x2="250.19" y2="106.68" width="0.1524" layer="91"/> +<junction x="247.65" y="106.68"/> +<pinref part="LED10" gate="DL" pin="K2"/> +<pinref part="LED10" gate="DL" pin="K1"/> +<pinref part="U$429" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="246.38" y1="67.31" x2="247.65" y2="67.31" width="0.1524" layer="91"/> +<wire x1="247.65" y1="67.31" x2="247.65" y2="64.77" width="0.1524" layer="91"/> +<wire x1="247.65" y1="64.77" x2="246.38" y2="64.77" width="0.1524" layer="91"/> +<wire x1="247.65" y1="67.31" x2="250.19" y2="67.31" width="0.1524" layer="91"/> +<junction x="247.65" y="67.31"/> +<pinref part="LED11" gate="DL" pin="K2"/> +<pinref part="LED11" gate="DL" pin="K1"/> +<pinref part="U$445" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="106.68" y1="46.99" x2="106.68" y2="38.1" width="0.1524" layer="91"/> +<wire x1="106.68" y1="38.1" x2="106.68" y2="35.56" width="0.1524" layer="91"/> +<wire x1="106.68" y1="35.56" x2="106.68" y2="30.48" width="0.1524" layer="91"/> +<wire x1="106.68" y1="46.99" x2="105.41" y2="46.99" width="0.1524" layer="91"/> +<wire x1="105.41" y1="49.53" x2="106.68" y2="49.53" width="0.1524" layer="91"/> +<wire x1="106.68" y1="49.53" x2="106.68" y2="46.99" width="0.1524" layer="91"/> +<junction x="106.68" y="46.99"/> +<pinref part="U$99" gate="G$1" pin="GND"/> +<pinref part="LED12" gate="DL" pin="K1"/> +<pinref part="LED12" gate="DL" pin="K2"/> +<pinref part="LED13" gate="DL" pin="K1"/> +<wire x1="106.68" y1="38.1" x2="105.41" y2="38.1" width="0.1524" layer="91"/> +<junction x="106.68" y="38.1"/> +<pinref part="LED13" gate="DL" pin="K2"/> +<wire x1="106.68" y1="35.56" x2="105.41" y2="35.56" width="0.1524" layer="91"/> +<junction x="106.68" y="35.56"/> +</segment> +<segment> +<wire x1="60.96" y1="88.9" x2="60.96" y2="93.98" width="0.1524" layer="91"/> +<wire x1="60.96" y1="93.98" x2="71.12" y2="93.98" width="0.1524" layer="91"/> +<pinref part="U9" gate="G" pin="OC"/> +<pinref part="U$569" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="191.77" y1="134.62" x2="200.66" y2="134.62" width="0.1524" layer="91"/> +<pinref part="U8" gate="G" pin="DGND"/> +<pinref part="U$588" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="193.04" y1="96.52" x2="200.66" y2="96.52" width="0.1524" layer="91"/> +<pinref part="U13" gate="G" pin="DGND"/> +<pinref part="U$604" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="193.04" y1="57.15" x2="200.66" y2="57.15" width="0.1524" layer="91"/> +<pinref part="U15" gate="G" pin="DGND"/> +<pinref part="U$607" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="156.21" y1="80.01" x2="156.21" y2="86.36" width="0.1524" layer="91"/> +<wire x1="156.21" y1="86.36" x2="156.21" y2="88.9" width="0.1524" layer="91"/> +<wire x1="156.21" y1="88.9" x2="156.21" y2="100.33" width="0.1524" layer="91"/> +<wire x1="156.21" y1="100.33" x2="156.21" y2="102.87" width="0.1524" layer="91"/> +<wire x1="156.21" y1="102.87" x2="156.21" y2="114.3" width="0.1524" layer="91"/> +<wire x1="156.21" y1="114.3" x2="156.21" y2="116.84" width="0.1524" layer="91"/> +<wire x1="156.21" y1="116.84" x2="156.21" y2="128.27" width="0.1524" layer="91"/> +<wire x1="156.21" y1="128.27" x2="156.21" y2="130.81" width="0.1524" layer="91"/> +<wire x1="156.21" y1="130.81" x2="156.21" y2="140.97" width="0.1524" layer="91"/> +<wire x1="156.21" y1="140.97" x2="156.21" y2="143.51" width="0.1524" layer="91"/> +<wire x1="156.21" y1="143.51" x2="156.21" y2="154.94" width="0.1524" layer="91"/> +<wire x1="156.21" y1="154.94" x2="156.21" y2="157.48" width="0.1524" layer="91"/> +<pinref part="U$197" gate="G$1" pin="GND"/> +<pinref part="LED1" gate="DL" pin="K1"/> +<wire x1="143.51" y1="157.48" x2="156.21" y2="157.48" width="0.1524" layer="91"/> +<pinref part="LED2" gate="DL" pin="K1"/> +<wire x1="143.51" y1="143.51" x2="156.21" y2="143.51" width="0.1524" layer="91"/> +<junction x="156.21" y="143.51"/> +<pinref part="LED2" gate="DL" pin="K2"/> +<wire x1="143.51" y1="140.97" x2="156.21" y2="140.97" width="0.1524" layer="91"/> +<junction x="156.21" y="140.97"/> +<pinref part="LED1" gate="DL" pin="K2"/> +<wire x1="143.51" y1="154.94" x2="156.21" y2="154.94" width="0.1524" layer="91"/> +<junction x="156.21" y="154.94"/> +<pinref part="LED5" gate="DL" pin="K1"/> +<wire x1="143.51" y1="102.87" x2="156.21" y2="102.87" width="0.1524" layer="91"/> +<junction x="156.21" y="102.87"/> +<pinref part="LED5" gate="DL" pin="K2"/> +<wire x1="143.51" y1="100.33" x2="156.21" y2="100.33" width="0.1524" layer="91"/> +<junction x="156.21" y="100.33"/> +<pinref part="LED4" gate="DL" pin="K1"/> +<wire x1="143.51" y1="116.84" x2="156.21" y2="116.84" width="0.1524" layer="91"/> +<junction x="156.21" y="116.84"/> +<pinref part="LED4" gate="DL" pin="K2"/> +<wire x1="143.51" y1="114.3" x2="156.21" y2="114.3" width="0.1524" layer="91"/> +<junction x="156.21" y="114.3"/> +<pinref part="LED3" gate="DL" pin="K2"/> +<wire x1="143.51" y1="128.27" x2="156.21" y2="128.27" width="0.1524" layer="91"/> +<junction x="156.21" y="128.27"/> +<pinref part="LED3" gate="DL" pin="K1"/> +<wire x1="143.51" y1="130.81" x2="156.21" y2="130.81" width="0.1524" layer="91"/> +<junction x="156.21" y="130.81"/> +<pinref part="LED6" gate="DL" pin="K1"/> +<wire x1="143.51" y1="88.9" x2="156.21" y2="88.9" width="0.1524" layer="91"/> +<junction x="156.21" y="88.9"/> +<pinref part="LED6" gate="DL" pin="K2"/> +<wire x1="143.51" y1="86.36" x2="156.21" y2="86.36" width="0.1524" layer="91"/> +<junction x="156.21" y="86.36"/> +</segment> +<segment> +<wire x1="36.83" y1="34.29" x2="44.45" y2="34.29" width="0.1524" layer="91"/> +<pinref part="U17" gate="G" pin="DGND"/> +<pinref part="U$200" gate="G$1" pin="GND"/> +</segment> +<segment> +<pinref part="C13" gate="C" pin="2"/> +<pinref part="U$176" gate="G$1" pin="GND"/> +<wire x1="62.23" y1="60.96" x2="53.34" y2="60.96" width="0.1524" layer="91"/> +</segment> +<segment> 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class="0"> +<segment> +<wire x1="71.12" y1="113.03" x2="41.91" y2="113.03" width="0.1524" layer="91"/> +<wire x1="41.91" y1="113.03" x2="40.64" y2="114.3" width="0.1524" layer="91"/> +<label x="43.18" y="113.3475" size="1.778" layer="92"/> +<pinref part="U9" gate="G" pin="D3"/> +</segment> +</net> +<net name="EX-DATA-BUF13" class="0"> +<segment> +<wire x1="71.12" y1="115.57" x2="41.91" y2="115.57" width="0.1524" layer="91"/> +<wire x1="41.91" y1="115.57" x2="40.64" y2="116.84" width="0.1524" layer="91"/> +<label x="43.18" y="115.8875" size="1.778" layer="92"/> +<pinref part="U9" gate="G" pin="D2"/> +</segment> +</net> +<net name="EX-DATA-BUF14" class="0"> +<segment> +<wire x1="71.12" y1="118.11" x2="41.91" y2="118.11" width="0.1524" layer="91"/> +<wire x1="41.91" y1="118.11" x2="40.64" y2="119.38" width="0.1524" layer="91"/> +<label x="43.18" y="118.4275" size="1.778" layer="92"/> +<pinref part="U9" gate="G" pin="D1"/> +</segment> +</net> +<net name="EX-DATA-BUF15" class="0"> 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pin="OUTY1"/> +</segment> +</net> +<net name="N$248" class="0"> +<segment> +<wire x1="233.68" y1="139.7" x2="234.95" y2="139.7" width="0.1524" layer="91"/> +<wire x1="234.95" y1="139.7" x2="234.95" y2="142.24" width="0.1524" layer="91"/> +<wire x1="234.95" y1="142.24" x2="236.22" y2="142.24" width="0.1524" layer="91"/> +<pinref part="R55" gate="R" pin="2"/> +<pinref part="LED9" gate="DL" pin="A1"/> +</segment> +</net> +<net name="N$249" class="0"> +<segment> +<wire x1="233.68" y1="147.32" x2="234.95" y2="147.32" width="0.1524" layer="91"/> +<wire x1="234.95" y1="147.32" x2="234.95" y2="144.78" width="0.1524" layer="91"/> +<wire x1="234.95" y1="144.78" x2="236.22" y2="144.78" width="0.1524" layer="91"/> +<pinref part="R56" gate="R" pin="1"/> +<pinref part="LED9" gate="DL" pin="A2"/> +</segment> +</net> +<net name="N$250" class="0"> +<segment> +<wire x1="223.52" y1="101.6" x2="218.44" y2="101.6" width="0.1524" layer="91"/> +<pinref part="R57" gate="R" pin="1"/> +<pinref part="U13" gate="G" pin="OUTY2"/> +</segment> +</net> +<net name="N$255" class="0"> +<segment> +<wire x1="223.52" y1="109.22" x2="218.44" y2="109.22" width="0.1524" layer="91"/> +<pinref part="R58" gate="R" pin="2"/> +<pinref part="U13" gate="G" pin="OUTY1"/> +</segment> +</net> +<net name="N$257" class="0"> +<segment> +<wire x1="233.68" y1="101.6" x2="234.95" y2="101.6" width="0.1524" layer="91"/> +<wire x1="234.95" y1="101.6" x2="234.95" y2="104.14" width="0.1524" layer="91"/> +<wire x1="234.95" y1="104.14" x2="236.22" y2="104.14" width="0.1524" layer="91"/> +<pinref part="R57" gate="R" pin="2"/> +<pinref part="LED10" gate="DL" pin="A1"/> +</segment> +</net> +<net name="N$258" class="0"> +<segment> +<wire x1="233.68" y1="109.22" x2="234.95" y2="109.22" width="0.1524" layer="91"/> +<wire x1="234.95" y1="109.22" x2="234.95" y2="106.68" width="0.1524" layer="91"/> +<wire x1="234.95" y1="106.68" x2="236.22" y2="106.68" width="0.1524" layer="91"/> +<pinref part="R58" gate="R" pin="1"/> +<pinref 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pin="2"/> +<pinref part="U17" gate="G" pin="OUTY1"/> +</segment> +</net> +<net name="N$79" class="0"> +<segment> +<wire x1="81.28" y1="46.99" x2="95.25" y2="46.99" width="0.1524" layer="91"/> +<pinref part="R70" gate="R" pin="1"/> +<pinref part="LED12" gate="DL" pin="A1"/> +</segment> +</net> +<net name="N$44" class="0"> +<segment> +<wire x1="71.12" y1="39.37" x2="62.23" y2="39.37" width="0.1524" layer="91"/> +<pinref part="R72" gate="R" pin="2"/> +<pinref part="U17" gate="G" pin="OUTY2"/> +</segment> +</net> +<net name="EP0-LINK1000" class="0"> +<segment> +<wire x1="195.58" y1="147.32" x2="198.12" y2="147.32" width="0.1524" layer="91"/> +<pinref part="U8" gate="G" pin="INA1"/> +<label x="195.58" y="147.32" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP0-LINK100" class="0"> +<segment> +<wire x1="198.12" y1="139.7" x2="195.58" y2="139.7" width="0.1524" layer="91"/> +<pinref part="U8" gate="G" pin="INA2"/> +<label x="195.58" y="139.7" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP1-LINK1000" class="0"> +<segment> +<wire x1="195.58" y1="109.22" x2="198.12" y2="109.22" width="0.1524" layer="91"/> +<pinref part="U13" gate="G" pin="INA1"/> +<label x="195.58" y="109.22" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP1-LINK100" class="0"> +<segment> +<wire x1="198.12" y1="101.6" x2="195.58" y2="101.6" width="0.1524" layer="91"/> +<pinref part="U13" gate="G" pin="INA2"/> +<label x="195.58" y="101.6" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-LINK1000" class="0"> +<segment> +<wire x1="195.58" y1="69.85" x2="198.12" y2="69.85" width="0.1524" layer="91"/> +<pinref part="U15" gate="G" pin="INA1"/> +<label x="195.58" y="69.85" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-LINK100" class="0"> +<segment> +<wire x1="198.12" y1="62.23" x2="195.58" y2="62.23" width="0.1524" layer="91"/> +<pinref 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layer="91"/> +<wire x1="193.04" y1="114.3" x2="180.34" y2="114.3" width="0.1524" layer="91"/> +<wire x1="180.34" y1="114.3" x2="180.34" y2="115.57" width="0.1524" layer="91"/> +<wire x1="180.34" y1="115.57" x2="180.34" y2="119.38" width="0.1524" layer="91"/> +<pinref part="U13" gate="G" pin="VCC"/> +<pinref part="U$81" gate="G$1" pin="V2P5"/> +<pinref part="C14" gate="C" pin="1"/> +<wire x1="180.34" y1="119.38" x2="180.34" y2="121.92" width="0.1524" layer="91"/> +<wire x1="191.77" y1="119.38" x2="180.34" y2="119.38" width="0.1524" layer="91"/> +<junction x="180.34" y="119.38"/> +</segment> +<segment> +<wire x1="193.04" y1="74.93" x2="200.66" y2="74.93" width="0.1524" layer="91"/> +<wire x1="193.04" y1="74.93" x2="181.61" y2="74.93" width="0.1524" layer="91"/> +<pinref part="U15" gate="G" pin="VCC"/> +<pinref part="U$84" gate="G$1" pin="V2P5"/> +</segment> +</net> +<net name="N$16" class="0"> +<segment> +<wire x1="101.6" y1="102.87" x2="96.52" y2="102.87" width="0.1524" layer="91"/> +<pinref part="U9" gate="G" pin="Q7"/> +<pinref part="R64" gate="R" pin="2"/> +<wire x1="116.84" y1="86.36" x2="101.6" y2="86.36" width="0.1524" layer="91"/> +<wire x1="101.6" y1="86.36" x2="101.6" y2="102.87" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$29" class="0"> +<segment> +<pinref part="LED1" gate="DL" pin="A1"/> +<pinref part="R2" gate="R" pin="1"/> +<wire x1="133.35" y1="157.48" x2="127" y2="157.48" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$32" class="0"> +<segment> +<pinref part="LED2" gate="DL" pin="A1"/> +<pinref part="R47" gate="R" pin="1"/> +<wire x1="133.35" y1="143.51" x2="127" y2="143.51" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$39" class="0"> +<segment> +<pinref part="LED5" gate="DL" pin="A1"/> +<pinref part="R61" gate="R" pin="1"/> +<wire x1="133.35" y1="102.87" x2="127" y2="102.87" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$54" class="0"> +<segment> +<pinref part="LED5" gate="DL" pin="A2"/> +<pinref part="R62" gate="R" pin="1"/> +<wire x1="133.35" y1="100.33" x2="127" y2="100.33" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$57" class="0"> +<segment> +<pinref part="LED3" gate="DL" pin="A1"/> +<pinref part="R49" gate="R" pin="1"/> +<wire x1="133.35" y1="130.81" x2="127" y2="130.81" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$58" class="0"> +<segment> +<pinref part="LED4" gate="DL" pin="A1"/> +<pinref part="R51" gate="R" pin="1"/> +<wire x1="133.35" y1="116.84" x2="127" y2="116.84" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$59" class="0"> +<segment> +<pinref part="R63" gate="R" pin="1"/> +<pinref part="LED6" gate="DL" pin="A1"/> +<wire x1="127" y1="88.9" x2="133.35" y2="88.9" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$60" class="0"> +<segment> +<pinref part="R64" gate="R" pin="1"/> +<pinref part="LED6" gate="DL" pin="A2"/> +<wire x1="127" y1="86.36" x2="133.35" y2="86.36" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="R72" gate="R" pin="1"/> +<wire x1="81.28" y1="39.37" x2="88.9" y2="39.37" width="0.1524" layer="91"/> +<wire x1="88.9" y1="39.37" x2="88.9" y2="35.56" width="0.1524" layer="91"/> +<pinref part="LED13" gate="DL" pin="A2"/> +<wire x1="88.9" y1="35.56" x2="95.25" y2="35.56" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="88.9" y="171.45" size="3.81" layer="94">ATX POWER SUPPLY CONN</text> +</plain> +<instances> +<instance part="FRAME8" gate="G$1" x="0" y="0"/> +<instance part="FRAME8" gate="G$2" x="180.34" y="0"/> +<instance part="C5V6" gate="C" x="149.86" y="35.56" rot="R180"> +<attribute name="VOLTAGE" x="149.86" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="149.86" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="149.86" y="35.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C5V5" gate="C" x="157.48" y="35.56" rot="R180"> +<attribute name="VOLTAGE" x="157.48" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="157.48" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="157.48" y="35.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C5V4" gate="C" x="165.1" y="35.56" rot="R180"> +<attribute name="VOLTAGE" x="165.1" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="165.1" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="165.1" y="35.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6V4" gate="C" x="72.39" y="38.1"> +<attribute name="VOLTAGE" x="72.39" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="72.39" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="72.39" y="38.1" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6V8" gate="C" x="64.77" y="38.1"> +<attribute name="VOLTAGE" x="64.77" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="64.77" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="64.77" y="38.1" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6V5" gate="C" x="105.41" y="36.83" rot="R180"> +<attribute name="VOLTAGE" x="105.41" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="105.41" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="105.41" y="36.83" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6V9" gate="C" x="123.19" y="36.83" rot="R180"> +<attribute name="VOLTAGE" x="123.19" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="123.19" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="123.19" y="36.83" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6V7" gate="C" x="36.83" y="36.83" rot="R180"> +<attribute name="VOLTAGE" x="36.83" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="36.83" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="36.83" y="36.83" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C5V7" gate="C" x="45.72" y="36.83" rot="R180"> +<attribute name="VOLTAGE" x="45.72" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="45.72" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="45.72" y="36.83" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6V10" gate="C" x="54.61" y="36.83" rot="R180"> +<attribute name="VOLTAGE" x="54.61" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="54.61" y="36.83" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="54.61" y="36.83" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6V3" gate="C" x="38.1" y="80.01" rot="R180"> +<attribute name="VOLTAGE" x="38.1" y="80.01" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="38.1" y="80.01" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="38.1" y="80.01" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$151" gate="+12VPC" x="134.62" y="52.07"/> +<instance part="U$156" gate="G$1" x="22.86" y="66.04"/> +<instance part="U$157" gate="G$1" x="21.59" y="20.32"/> +<instance part="U$158" gate="G$1" x="90.17" y="20.32"/> +<instance part="U$159" gate="G$1" x="80.01" y="53.34" rot="R180"/> +<instance part="U$160" gate="G$1" x="134.62" y="20.32"/> +<instance part="U$161" gate="-12VPC" x="80.01" y="17.78" rot="R180"/> +<instance part="U$162" gate="PW-VCC3" x="90.17" y="53.34"/> +<instance part="P+12" gate="1" x="21.59" y="53.34"/> +<instance part="U$163" gate="VSBY5" x="22.86" y="97.79"/> +<instance part="U$164" gate="+12VPC" x="170.18" y="130.81"/> +<instance part="U$165" gate="G$1" x="109.22" y="134.62" rot="R270"/> +<instance part="U$166" gate="G$1" x="109.22" y="121.92" rot="R270"/> +<instance part="P+13" gate="1" x="100.33" y="114.3" rot="R90"/> +<instance part="P+14" gate="1" x="140.97" y="114.3" rot="R270"/> +<instance part="P+15" gate="1" x="151.13" y="138.43"/> +<instance part="U$169" gate="PW-VCC3" x="111.76" y="147.32"/> +<instance part="U$170" gate="PW-VCC3" x="100.33" y="124.46" rot="R90"/> +<instance part="U$173" gate="-12VPC" x="180.34" y="128.27"/> +<instance part="R6V2" gate="R" x="190.5" y="133.35" rot="R270"> +<attribute name="POWER" x="190.5" y="133.35" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="190.5" y="133.35" size="1.778" layer="96" display="off"/> +</instance> +<instance part="T1" gate="T" x="193.04" y="102.87" smashed="yes" rot="MR0"> +<attribute name="NAME" x="187.96" y="101.854" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="187.706" y="112.014" size="1.778" layer="96" rot="MR270"/> +</instance> +<instance part="U$613" gate="G$1" x="190.5" y="86.36"/> +<instance part="CON-ATX" gate="C" x="127" y="123.19"/> +<instance part="U$107" gate="G$1" x="144.78" y="119.38" rot="R90"/> +<instance part="U$138" gate="G$1" x="119.38" y="97.79" rot="MR0"/> +<instance part="U16" gate="U" x="80.01" y="91.44"/> +<instance part="U$144" gate="G$1" x="80.01" y="67.31"/> +<instance part="C2" gate="C" x="102.87" y="82.55"> +<attribute name="TYPE" x="102.87" y="82.55" size="1.778" layer="96" display="off"/> +<attribute name="VOLTAGE" x="102.87" y="82.55" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6V11" gate="C" x="107.95" y="82.55"> +<attribute name="VOLTAGE" x="107.95" y="82.55" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="107.95" y="82.55" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="107.95" y="82.55" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6V12" gate="C" x="113.03" y="82.55"> +<attribute name="VOLTAGE" x="113.03" y="82.55" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="113.03" y="82.55" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="113.03" y="82.55" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6V1" gate="R" x="201.93" y="93.98" smashed="yes" rot="R270"> +<attribute name="NAME" x="204.47" y="93.98" size="1.778" layer="95"/> +<attribute name="VALUE" x="204.47" y="92.71" size="1.778" layer="96" rot="MR180"/> +<attribute name="POWER" x="201.93" y="93.98" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$191" gate="G$1" x="201.93" y="86.36"/> +<instance part="C4H7" gate="C" x="134.62" y="38.1"> +<attribute name="VOLTAGE" x="134.62" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TOLERANCE" x="134.62" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TYPE" x="134.62" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C5H2" gate="C" x="142.24" y="38.1"> +<attribute name="VOLTAGE" x="142.24" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TOLERANCE" x="142.24" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TYPE" x="142.24" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C4H6" gate="C" x="22.86" y="82.55"> +<attribute name="TYPE" x="22.86" y="82.55" size="1.778" layer="96" display="off"/> +<attribute name="VOLTAGE" x="22.86" y="82.55" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C4H4" gate="C" x="29.21" y="36.83" smashed="yes"> +<attribute name="NAME" x="28.575" y="33.9725" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="28.194" y="37.084" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="29.21" y="36.83" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TYPE" x="29.21" y="36.83" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C4H3" gate="C" x="21.59" y="36.83" smashed="yes"> +<attribute name="NAME" x="20.955" y="33.9725" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="20.574" y="37.084" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="21.59" y="36.83" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TYPE" x="21.59" y="36.83" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C4H2" gate="C" x="97.79" y="34.29" smashed="yes" rot="MR180"> +<attribute name="NAME" x="97.155" y="37.1475" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="96.774" y="34.036" size="1.778" layer="96" rot="MR270"/> +<attribute name="VOLTAGE" x="97.79" y="34.29" size="1.778" layer="96" rot="MR0" display="off"/> +<attribute name="TYPE" x="97.79" y="34.29" size="1.778" layer="96" rot="MR0" display="off"/> +</instance> +<instance part="C3H5" gate="C" x="90.17" y="34.29" smashed="yes" rot="MR180"> +<attribute name="NAME" x="89.535" y="37.1475" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="89.154" y="34.036" size="1.778" layer="96" rot="MR270"/> +<attribute name="VOLTAGE" x="90.17" y="34.29" size="1.778" layer="96" rot="MR0" display="off"/> +<attribute name="TYPE" x="90.17" y="34.29" size="1.778" layer="96" rot="MR0" display="off"/> +</instance> +<instance part="C4H1" gate="C" x="80.01" y="38.1"> +<attribute name="VOLTAGE" x="80.01" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TOLERANCE" x="80.01" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TYPE" x="80.01" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="VCC3" class="0"> +<segment> +<wire x1="90.17" y1="39.37" x2="90.17" y2="49.53" width="0.1524" layer="91"/> +<wire x1="90.17" y1="49.53" x2="97.79" y2="49.53" width="0.1524" layer="91"/> +<wire x1="97.79" y1="49.53" x2="105.41" y2="49.53" width="0.1524" layer="91"/> +<wire x1="105.41" y1="49.53" x2="114.3" y2="49.53" width="0.1524" layer="91"/> +<wire x1="114.3" y1="49.53" x2="123.19" y2="49.53" width="0.1524" layer="91"/> +<wire x1="123.19" y1="49.53" x2="123.19" y2="41.91" width="0.1524" layer="91"/> +<wire x1="97.79" y1="39.37" x2="97.79" y2="49.53" width="0.1524" layer="91"/> +<wire x1="105.41" y1="41.91" x2="105.41" y2="49.53" width="0.1524" layer="91"/> +<wire x1="90.17" y1="49.53" x2="90.17" y2="50.8" width="0.1524" layer="91"/> +<junction x="105.41" y="49.53"/> +<junction x="97.79" y="49.53"/> +<junction x="90.17" y="49.53"/> +<pinref part="C6V9" gate="C" pin="1"/> +<pinref part="C6V5" gate="C" pin="1"/> +<pinref part="U$162" gate="PW-VCC3" pin="VCC3"/> +<pinref part="C3H5" gate="C" pin="1"/> +<pinref part="C4H2" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="118.11" y1="124.46" x2="102.87" y2="124.46" width="0.1524" layer="91"/> +<pinref part="U$170" gate="PW-VCC3" pin="VCC3"/> +<pinref part="CON-ATX" gate="C" pin="11"/> +</segment> +<segment> +<wire x1="118.11" y1="137.16" x2="111.76" y2="137.16" width="0.1524" layer="91"/> +<wire x1="111.76" y1="137.16" x2="111.76" y2="143.51" width="0.1524" layer="91"/> +<wire x1="111.76" y1="143.51" x2="111.76" y2="144.78" width="0.1524" layer="91"/> +<wire x1="111.76" y1="143.51" x2="143.51" y2="143.51" width="0.1524" layer="91"/> +<wire x1="135.89" y1="137.16" x2="143.51" y2="137.16" width="0.1524" layer="91"/> +<wire x1="143.51" y1="137.16" x2="143.51" y2="143.51" width="0.1524" layer="91"/> +<junction x="111.76" y="143.51"/> +<pinref part="U$169" gate="PW-VCC3" pin="VCC3"/> +<pinref part="CON-ATX" gate="C" pin="1"/> +<pinref part="CON-ATX" gate="C" pin="2"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<wire x1="21.59" y1="39.37" x2="21.59" y2="49.53" width="0.1524" layer="91"/> +<wire x1="21.59" y1="49.53" x2="29.21" y2="49.53" width="0.1524" layer="91"/> +<wire x1="29.21" y1="49.53" x2="36.83" y2="49.53" width="0.1524" layer="91"/> +<wire x1="36.83" y1="49.53" x2="45.72" y2="49.53" width="0.1524" layer="91"/> +<wire x1="45.72" y1="49.53" x2="54.61" y2="49.53" width="0.1524" layer="91"/> +<wire x1="54.61" y1="49.53" x2="54.61" y2="41.91" width="0.1524" layer="91"/> +<wire x1="45.72" y1="49.53" x2="45.72" y2="41.91" width="0.1524" layer="91"/> +<wire x1="36.83" y1="49.53" x2="36.83" y2="41.91" width="0.1524" layer="91"/> +<wire x1="29.21" y1="49.53" x2="29.21" y2="39.37" width="0.1524" layer="91"/> +<wire x1="21.59" y1="50.8" x2="21.59" y2="49.53" width="0.1524" layer="91"/> +<junction x="45.72" y="49.53"/> +<junction x="36.83" y="49.53"/> +<junction x="29.21" y="49.53"/> +<junction x="21.59" y="49.53"/> +<pinref part="C5V7" gate="C" pin="1"/> +<pinref part="C6V7" gate="C" pin="1"/> +<pinref part="C6V10" gate="C" pin="1"/> +<pinref part="P+12" gate="1" pin="VCC"/> +<pinref part="C4H3" gate="C" pin="2"/> +<pinref part="C4H4" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="118.11" y1="114.3" x2="102.87" y2="114.3" width="0.1524" layer="91"/> +<pinref part="P+13" gate="1" pin="VCC"/> +<pinref part="CON-ATX" gate="C" pin="19"/> +</segment> +<segment> +<wire x1="135.89" y1="114.3" x2="138.43" y2="114.3" width="0.1524" layer="91"/> +<pinref part="P+14" gate="1" pin="VCC"/> +<pinref part="CON-ATX" gate="C" pin="20"/> +</segment> +<segment> +<wire x1="135.89" y1="132.08" x2="151.13" y2="132.08" width="0.1524" layer="91"/> +<wire x1="151.13" y1="132.08" x2="151.13" y2="134.62" width="0.1524" layer="91"/> +<wire x1="151.13" y1="134.62" x2="151.13" y2="135.89" width="0.1524" layer="91"/> +<wire x1="135.89" y1="134.62" x2="151.13" y2="134.62" width="0.1524" layer="91"/> +<junction x="151.13" y="134.62"/> +<pinref part="P+15" gate="1" pin="VCC"/> +<pinref part="CON-ATX" gate="C" pin="4"/> +<pinref part="CON-ATX" gate="C" pin="6"/> +</segment> +</net> +<net name="VSBY5" class="0"> +<segment> +<wire x1="22.86" y1="85.09" x2="22.86" y2="93.98" width="0.1524" layer="91"/> +<wire x1="22.86" y1="93.98" x2="30.48" y2="93.98" width="0.1524" layer="91"/> +<wire x1="30.48" y1="93.98" x2="38.1" y2="93.98" width="0.1524" layer="91"/> +<wire x1="38.1" y1="93.98" x2="46.99" y2="93.98" width="0.1524" layer="91"/> +<wire x1="46.99" y1="93.98" x2="55.88" y2="93.98" width="0.1524" layer="91"/> +<wire x1="38.1" y1="93.98" x2="38.1" y2="85.09" width="0.1524" layer="91"/> +<wire x1="22.86" y1="96.52" x2="22.86" y2="93.98" width="0.1524" layer="91"/> +<junction x="38.1" y="93.98"/> +<junction x="22.86" y="93.98"/> +<pinref part="C6V3" gate="C" pin="1"/> +<pinref part="U$163" gate="VSBY5" pin="VSBY5"/> +<wire x1="118.11" y1="127" x2="105.41" y2="127" width="0.1524" layer="91"/> +<wire x1="105.41" y1="127" x2="105.41" y2="133.35" width="0.1524" layer="91"/> +<wire x1="105.41" y1="133.35" x2="76.2" y2="133.35" width="0.1524" layer="91"/> +<wire x1="105.41" y1="133.35" x2="105.41" y2="152.4" width="0.1524" layer="91"/> +<wire x1="105.41" y1="152.4" x2="189.23" y2="152.4" width="0.1524" layer="91"/> +<wire x1="189.23" y1="152.4" x2="190.5" y2="152.4" width="0.1524" layer="91"/> +<wire x1="190.5" y1="152.4" x2="190.5" y2="138.43" width="0.1524" layer="91"/> +<junction x="105.41" y="133.35"/> +<pinref part="CON-ATX" gate="C" pin="9"/> +<pinref part="R6V2" gate="R" pin="1"/> +<wire x1="55.88" y1="93.98" x2="55.88" y2="133.35" width="0.1524" layer="91"/> +<wire x1="55.88" y1="133.35" x2="76.2" y2="133.35" width="0.1524" layer="91"/> +<junction x="55.88" y="93.98"/> +<pinref part="U16" gate="U" pin="IN"/> +<wire x1="71.12" y1="93.98" x2="66.04" y2="93.98" width="0.1524" layer="91"/> +<pinref part="U16" gate="U" pin="EN"/> +<wire x1="66.04" y1="93.98" x2="55.88" y2="93.98" width="0.1524" layer="91"/> +<wire x1="71.12" y1="88.9" x2="66.04" y2="88.9" width="0.1524" layer="91"/> +<wire x1="66.04" y1="88.9" x2="66.04" y2="93.98" width="0.1524" layer="91"/> +<junction x="66.04" y="93.98"/> +<pinref part="C4H6" gate="C" pin="2"/> +</segment> +</net> +<net name="+12VPC" class="0"> +<segment> +<wire x1="134.62" y1="40.64" x2="134.62" y2="49.53" width="0.1524" layer="91"/> +<wire x1="134.62" y1="49.53" x2="142.24" y2="49.53" width="0.1524" layer="91"/> +<wire x1="142.24" y1="49.53" x2="149.86" y2="49.53" width="0.1524" layer="91"/> +<wire x1="149.86" y1="49.53" x2="157.48" y2="49.53" width="0.1524" layer="91"/> +<wire x1="157.48" y1="49.53" x2="165.1" y2="49.53" width="0.1524" layer="91"/> +<wire x1="165.1" y1="49.53" x2="165.1" y2="40.64" width="0.1524" layer="91"/> +<wire x1="157.48" y1="40.64" x2="157.48" y2="49.53" width="0.1524" layer="91"/> +<wire x1="149.86" y1="40.64" x2="149.86" y2="49.53" width="0.1524" layer="91"/> +<wire x1="142.24" y1="40.64" x2="142.24" y2="49.53" width="0.1524" layer="91"/> +<wire x1="134.62" y1="49.53" x2="134.62" y2="50.8" width="0.1524" layer="91"/> +<junction x="157.48" y="49.53"/> +<junction x="149.86" y="49.53"/> +<junction x="142.24" y="49.53"/> +<junction x="134.62" y="49.53"/> +<pinref part="C5V4" gate="C" pin="1"/> +<pinref part="C5V5" gate="C" pin="1"/> +<pinref part="C5V6" gate="C" pin="1"/> +<pinref part="U$151" gate="+12VPC" pin="+12VPC"/> +<pinref part="C4H7" gate="C" pin="2"/> +<pinref part="C5H2" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="135.89" y1="127" x2="170.18" y2="127" width="0.1524" layer="91"/> +<wire x1="170.18" y1="127" x2="170.18" y2="129.54" width="0.1524" layer="91"/> +<pinref part="U$164" gate="+12VPC" pin="+12VPC"/> +<pinref part="CON-ATX" gate="C" pin="10"/> +</segment> +</net> +<net name="GND" class="0"> +<segment> +<wire x1="22.86" y1="77.47" x2="22.86" y2="69.85" width="0.1524" layer="91"/> +<wire x1="22.86" y1="69.85" x2="30.48" y2="69.85" width="0.1524" layer="91"/> +<wire x1="30.48" y1="69.85" x2="38.1" y2="69.85" width="0.1524" layer="91"/> +<wire x1="38.1" y1="77.47" x2="38.1" y2="69.85" width="0.1524" layer="91"/> +<wire x1="22.86" y1="67.31" x2="22.86" y2="69.85" width="0.1524" layer="91"/> +<junction x="22.86" y="69.85"/> +<pinref part="C6V3" gate="C" pin="2"/> +<pinref part="U$156" gate="G$1" pin="GND"/> +<pinref part="C4H6" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="21.59" y1="31.75" x2="21.59" y2="24.13" width="0.1524" layer="91"/> +<wire x1="21.59" y1="24.13" x2="29.21" y2="24.13" width="0.1524" layer="91"/> +<wire x1="29.21" y1="24.13" x2="36.83" y2="24.13" width="0.1524" layer="91"/> +<wire x1="36.83" y1="24.13" x2="45.72" y2="24.13" width="0.1524" layer="91"/> +<wire x1="45.72" y1="24.13" x2="54.61" y2="24.13" width="0.1524" layer="91"/> +<wire x1="54.61" y1="24.13" x2="54.61" y2="34.29" width="0.1524" layer="91"/> +<wire x1="45.72" y1="34.29" x2="45.72" y2="24.13" width="0.1524" layer="91"/> +<wire x1="36.83" y1="34.29" x2="36.83" y2="24.13" width="0.1524" layer="91"/> +<wire x1="29.21" y1="31.75" x2="29.21" y2="24.13" width="0.1524" layer="91"/> +<wire x1="21.59" y1="24.13" x2="21.59" y2="21.59" width="0.1524" layer="91"/> +<junction x="29.21" y="24.13"/> +<junction x="36.83" y="24.13"/> +<junction x="45.72" y="24.13"/> +<junction x="21.59" y="24.13"/> +<pinref part="C6V10" gate="C" pin="2"/> +<pinref part="C5V7" gate="C" pin="2"/> +<pinref part="C6V7" gate="C" pin="2"/> +<pinref part="U$157" gate="G$1" pin="GND"/> +<pinref part="C4H3" gate="C" pin="1"/> +<pinref part="C4H4" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="165.1" y1="33.02" x2="165.1" y2="24.13" width="0.1524" layer="91"/> +<wire x1="165.1" y1="24.13" x2="157.48" y2="24.13" width="0.1524" layer="91"/> +<wire x1="157.48" y1="24.13" x2="149.86" y2="24.13" width="0.1524" layer="91"/> +<wire x1="149.86" y1="24.13" x2="142.24" y2="24.13" width="0.1524" layer="91"/> +<wire x1="142.24" y1="24.13" x2="134.62" y2="24.13" width="0.1524" layer="91"/> +<wire x1="134.62" y1="24.13" x2="134.62" y2="33.02" width="0.1524" layer="91"/> +<wire x1="142.24" y1="33.02" x2="142.24" y2="24.13" width="0.1524" layer="91"/> +<wire x1="149.86" y1="33.02" x2="149.86" y2="24.13" width="0.1524" layer="91"/> +<wire x1="157.48" y1="33.02" x2="157.48" y2="24.13" width="0.1524" layer="91"/> +<wire x1="134.62" y1="21.59" x2="134.62" y2="24.13" width="0.1524" layer="91"/> +<junction x="142.24" y="24.13"/> +<junction x="149.86" y="24.13"/> +<junction x="157.48" y="24.13"/> +<junction x="134.62" y="24.13"/> +<pinref part="C5V4" gate="C" pin="2"/> +<pinref part="C5V6" gate="C" pin="2"/> +<pinref part="C5V5" gate="C" pin="2"/> +<pinref part="U$160" gate="G$1" pin="GND"/> +<pinref part="C4H7" gate="C" pin="1"/> +<pinref part="C5H2" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="97.79" y1="31.75" x2="97.79" y2="24.13" width="0.1524" layer="91"/> +<wire x1="90.17" y1="31.75" x2="90.17" y2="24.13" width="0.1524" layer="91"/> +<wire x1="90.17" y1="24.13" x2="97.79" y2="24.13" width="0.1524" layer="91"/> +<wire x1="123.19" y1="24.13" x2="123.19" y2="34.29" width="0.1524" layer="91"/> +<wire x1="114.3" y1="24.13" x2="123.19" y2="24.13" width="0.1524" layer="91"/> +<wire x1="105.41" y1="24.13" x2="114.3" y2="24.13" width="0.1524" layer="91"/> +<wire x1="105.41" y1="34.29" x2="105.41" y2="24.13" width="0.1524" layer="91"/> +<wire x1="97.79" y1="24.13" x2="105.41" y2="24.13" width="0.1524" layer="91"/> +<wire x1="90.17" y1="24.13" x2="90.17" y2="21.59" width="0.1524" layer="91"/> +<junction x="97.79" y="24.13"/> +<junction x="105.41" y="24.13"/> +<junction x="90.17" y="24.13"/> +<pinref part="C6V9" gate="C" pin="2"/> +<pinref part="C6V5" gate="C" pin="2"/> +<pinref part="U$158" gate="G$1" pin="GND"/> +<pinref part="C3H5" gate="C" pin="2"/> +<pinref part="C4H2" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="80.01" y1="40.64" x2="80.01" y2="49.53" width="0.1524" layer="91"/> +<wire x1="80.01" y1="49.53" x2="72.39" y2="49.53" width="0.1524" layer="91"/> +<wire x1="72.39" y1="49.53" x2="64.77" y2="49.53" width="0.1524" layer="91"/> +<wire x1="64.77" y1="49.53" x2="64.77" y2="40.64" width="0.1524" layer="91"/> +<wire x1="72.39" y1="40.64" x2="72.39" y2="49.53" width="0.1524" layer="91"/> +<wire x1="80.01" y1="52.07" x2="80.01" y2="49.53" width="0.1524" layer="91"/> +<junction x="72.39" y="49.53"/> +<junction x="80.01" y="49.53"/> +<pinref part="C6V8" gate="C" pin="2"/> +<pinref part="C6V4" gate="C" pin="2"/> +<pinref part="U$159" gate="G$1" pin="GND"/> +<pinref part="C4H1" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="118.11" y1="134.62" x2="111.76" y2="134.62" width="0.1524" layer="91"/> +<wire x1="111.76" y1="134.62" x2="111.76" y2="132.08" width="0.1524" layer="91"/> +<wire x1="111.76" y1="132.08" x2="111.76" y2="129.54" width="0.1524" layer="91"/> +<wire x1="111.76" y1="129.54" x2="118.11" y2="129.54" width="0.1524" layer="91"/> +<wire x1="118.11" y1="132.08" x2="111.76" y2="132.08" width="0.1524" layer="91"/> +<wire x1="111.76" y1="134.62" x2="110.49" y2="134.62" width="0.1524" layer="91"/> +<junction x="111.76" y="132.08"/> +<junction x="111.76" y="134.62"/> +<pinref part="U$165" gate="G$1" pin="GND"/> +<pinref part="CON-ATX" gate="C" pin="3"/> +<pinref part="CON-ATX" gate="C" pin="5"/> +<pinref part="CON-ATX" gate="C" pin="7"/> +</segment> +<segment> +<wire x1="190.5" y1="87.63" x2="190.5" y2="97.79" width="0.1524" layer="91"/> +<pinref part="T1" gate="T" pin="S"/> +<pinref part="U$613" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="118.11" y1="116.84" x2="111.76" y2="116.84" width="0.1524" layer="91"/> +<wire x1="118.11" y1="119.38" x2="111.76" y2="119.38" width="0.1524" layer="91"/> +<wire x1="111.76" y1="119.38" x2="111.76" y2="116.84" width="0.1524" layer="91"/> +<wire x1="111.76" y1="119.38" x2="111.76" y2="121.92" width="0.1524" layer="91"/> +<wire x1="111.76" y1="121.92" x2="118.11" y2="121.92" width="0.1524" layer="91"/> +<wire x1="110.49" y1="121.92" x2="111.76" y2="121.92" width="0.1524" layer="91"/> +<junction x="111.76" y="119.38"/> +<junction x="111.76" y="121.92"/> +<pinref part="U$166" gate="G$1" pin="GND"/> +<pinref part="CON-ATX" gate="C" pin="13"/> +<pinref part="CON-ATX" gate="C" pin="15"/> +<pinref part="CON-ATX" gate="C" pin="17"/> +</segment> +<segment> +<wire x1="143.51" y1="119.38" x2="135.89" y2="119.38" width="0.1524" layer="91"/> +<pinref part="CON-ATX" gate="C" pin="16"/> +<pinref part="U$107" gate="G$1" pin="GND"/> +</segment> +<segment> +<pinref part="U16" gate="U" pin="DGND"/> +<pinref part="U$144" gate="G$1" pin="GND"/> +<wire x1="80.01" y1="68.58" x2="80.01" y2="69.85" width="0.1524" layer="91"/> +<pinref part="C2" gate="C" pin="1"/> +<wire x1="80.01" y1="69.85" x2="80.01" y2="77.47" width="0.1524" layer="91"/> +<wire x1="102.87" y1="77.47" x2="102.87" y2="69.85" width="0.1524" layer="91"/> +<wire x1="80.01" y1="69.85" x2="102.87" y2="69.85" width="0.1524" layer="91"/> +<junction x="80.01" y="69.85"/> +<pinref part="C6V11" gate="C" pin="1"/> +<wire x1="102.87" y1="69.85" x2="107.95" y2="69.85" width="0.1524" layer="91"/> +<wire x1="107.95" y1="69.85" x2="107.95" y2="77.47" width="0.1524" layer="91"/> +<junction x="102.87" y="69.85"/> +<pinref part="C6V12" gate="C" pin="1"/> +<wire x1="107.95" y1="69.85" x2="113.03" y2="69.85" width="0.1524" layer="91"/> +<wire x1="113.03" y1="69.85" x2="113.03" y2="77.47" width="0.1524" layer="91"/> +<junction x="107.95" y="69.85"/> +</segment> +<segment> +<pinref part="R6V1" gate="R" pin="2"/> +<pinref part="U$191" gate="G$1" pin="GND"/> +<wire x1="201.93" y1="88.9" x2="201.93" y2="87.63" width="0.1524" layer="91"/> +</segment> +</net> +<net name="-12VPC" class="0"> +<segment> +<wire x1="80.01" y1="24.13" x2="80.01" y2="33.02" width="0.1524" layer="91"/> +<wire x1="80.01" y1="24.13" x2="72.39" y2="24.13" width="0.1524" layer="91"/> +<wire x1="72.39" y1="24.13" x2="64.77" y2="24.13" width="0.1524" layer="91"/> +<wire x1="64.77" y1="24.13" x2="64.77" y2="33.02" width="0.1524" layer="91"/> +<wire x1="72.39" y1="33.02" x2="72.39" y2="24.13" width="0.1524" layer="91"/> +<wire x1="80.01" y1="24.13" x2="80.01" y2="19.05" width="0.1524" layer="91"/> +<junction x="72.39" y="24.13"/> +<junction x="80.01" y="24.13"/> +<pinref part="C6V8" gate="C" pin="1"/> +<pinref part="C6V4" gate="C" pin="1"/> +<pinref part="U$161" gate="-12VPC" pin="-12VPC"/> +<pinref part="C4H1" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="135.89" y1="124.46" x2="180.34" y2="124.46" width="0.1524" layer="91"/> +<wire x1="180.34" y1="124.46" x2="180.34" y2="127" width="0.1524" layer="91"/> +<pinref part="U$173" gate="-12VPC" pin="-12VPC"/> +<pinref part="CON-ATX" gate="C" pin="12"/> +</segment> +</net> +<net name="ATX-PWROK" class="0"> +<segment> +<wire x1="135.89" y1="129.54" x2="144.78" y2="129.54" width="0.1524" layer="91"/> +<pinref part="CON-ATX" gate="C" pin="8"/> +<label x="144.78" y="129.54" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="N$242" class="0"> +<segment> +<wire x1="190.5" y1="128.27" x2="190.5" y2="121.92" width="0.1524" layer="91"/> +<wire x1="190.5" y1="116.84" x2="190.5" y2="121.92" width="0.1524" layer="91"/> +<wire x1="190.5" y1="111.76" x2="190.5" y2="116.84" width="0.1524" layer="91"/> +<wire x1="190.5" y1="107.95" x2="190.5" y2="111.76" width="0.1524" layer="91"/> +<pinref part="R6V2" gate="R" pin="2"/> +<pinref part="T1" gate="T" pin="D"/> +<pinref part="CON-ATX" gate="C" pin="14"/> +<wire x1="135.89" y1="121.92" x2="190.5" y2="121.92" width="0.1524" layer="91"/> +<junction x="190.5" y="121.92"/> +</segment> +</net> +<net name="VSBY3-3" class="0"> +<segment> +<pinref part="U16" gate="U" pin="OUT"/> +<pinref part="U$138" gate="G$1" pin="VSBY3-3"/> +<wire x1="119.38" y1="96.52" x2="119.38" y2="93.98" width="0.1524" layer="91"/> +<wire x1="119.38" y1="93.98" x2="113.03" y2="93.98" width="0.1524" layer="91"/> +<pinref part="C2" gate="C" pin="2"/> +<wire x1="113.03" y1="93.98" x2="107.95" y2="93.98" width="0.1524" layer="91"/> +<wire x1="107.95" y1="93.98" x2="102.87" y2="93.98" width="0.1524" layer="91"/> +<wire x1="102.87" y1="93.98" x2="90.17" y2="93.98" width="0.1524" layer="91"/> +<wire x1="102.87" y1="85.09" x2="102.87" y2="93.98" width="0.1524" layer="91"/> +<junction x="102.87" y="93.98"/> +<pinref part="C6V11" gate="C" pin="2"/> +<wire x1="107.95" y1="85.09" x2="107.95" y2="93.98" width="0.1524" layer="91"/> +<junction x="107.95" y="93.98"/> +<pinref part="C6V12" gate="C" pin="2"/> +<wire x1="113.03" y1="85.09" x2="113.03" y2="93.98" width="0.1524" layer="91"/> +<junction x="113.03" y="93.98"/> +</segment> +</net> +<net name="CMDPWR" class="0"> +<segment> +<wire x1="210.82" y1="100.33" x2="201.93" y2="100.33" width="0.1524" layer="91"/> +<pinref part="T1" gate="T" pin="G"/> +<label x="210.82" y="100.33" size="1.778" layer="92" xref="yes"/> +<pinref part="R6V1" gate="R" pin="1"/> +<wire x1="201.93" y1="100.33" x2="198.12" y2="100.33" width="0.1524" layer="91"/> +<wire x1="201.93" y1="99.06" x2="201.93" y2="100.33" width="0.1524" layer="91"/> +<junction x="201.93" y="100.33"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="87.63" y="170.18" size="5.08" layer="94">5V to 2.5V</text> +<text x="38.1" y="50.8" size="2.1844" layer="94">Vout =0.6x (Rs+Ro)/Ro</text> +<circle x="124.46" y="102.87" radius="16.164459375" width="0.4064" layer="94"/> +<circle x="124.46" y="68.58" radius="17.643403125" width="0.4064" layer="94"/> +<text x="104.14" y="59.69" size="1.778" layer="94">Surement remplacer par SIR864DP</text> +</plain> +<instances> +<instance part="FRAME5" gate="G$1" x="0" y="0"/> +<instance part="FRAME5" gate="G$2" x="180.34" y="0"/> +<instance part="C4V6" gate="C" x="191.77" y="69.85" smashed="yes" rot="R180"> +<attribute name="NAME" x="192.0875" y="72.39" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="192.0875" y="70.1675" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="191.77" y="69.85" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="191.77" y="69.85" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="191.77" y="69.85" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6G15" gate="C" x="179.07" y="71.12" smashed="yes"> +<attribute name="NAME" x="178.7525" y="68.2625" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="178.7525" y="72.7075" size="1.778" layer="96" rot="R90"/> +<attribute name="ESR_R" x="179.07" y="71.12" size="1.778" layer="96" display="off"/> +<attribute name="VOLTAGE" x="179.07" y="71.12" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="179.07" y="71.12" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C4U8" gate="C" x="198.12" y="69.85" smashed="yes" rot="R180"> +<attribute name="NAME" x="198.4375" y="72.0725" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="198.4375" y="69.5325" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="198.12" y="69.85" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="198.12" y="69.85" size="1.778" layer="96" display="off"/> +</instance> +<instance part="Q7H5" gate="Q" x="124.46" y="64.77" smashed="yes"> +<attribute name="NAME" x="131.445" y="63.5" size="1.778" layer="95"/> +<attribute name="VALUE" x="131.445" y="60.96" size="1.778" layer="96"/> +</instance> +<instance part="U$16" gate="G$1" x="129.54" y="54.61"/> +<instance part="Q7H7" gate="Q" x="124.46" y="99.06" smashed="yes"> +<attribute name="NAME" x="131.445" y="100.33" size="1.778" layer="95"/> +<attribute name="VALUE" x="131.445" y="97.79" size="1.778" layer="96"/> +</instance> +<instance part="U7H1" gate="ISL6545" x="92.71" y="87.63" smashed="yes"> +<attribute name="NAME" x="80.9625" y="95.885" size="1.778" layer="95"/> +<attribute name="VALUE" x="95.25" y="95.885" size="1.778" layer="96"/> +</instance> +<instance part="C3V5" gate="C" x="62.23" y="109.22" rot="R90"> +<attribute name="VOLTAGE" x="62.23" y="109.22" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="62.23" y="109.22" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7G7" gate="C" x="62.23" y="115.57" rot="R90"> +<attribute name="VOLTAGE" x="62.23" y="115.57" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="62.23" y="115.57" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="62.23" y="115.57" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3V1" gate="R" x="76.2" y="129.54" rot="R270"> +<attribute name="POWER" x="76.2" y="129.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R7G1" gate="R" x="63.5" y="67.31" smashed="yes"> +<attribute name="NAME" x="59.69" y="63.5" size="1.778" layer="95"/> +<attribute name="VALUE" x="60.96" y="60.96" size="1.778" layer="96"/> +<attribute name="POWER" x="63.5" y="67.31" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="63.5" y="67.31" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7G8" gate="C" x="62.23" y="85.09" smashed="yes" rot="R270"> +<attribute name="NAME" x="59.69" y="80.9625" size="1.778" layer="95"/> +<attribute name="VALUE" x="60.96" y="90.17" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="62.23" y="85.09" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="62.23" y="85.09" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="62.23" y="85.09" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7G9" gate="C" x="52.07" y="77.47" rot="R180"> +<attribute name="VOLTAGE" x="52.07" y="77.47" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="52.07" y="77.47" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="52.07" y="77.47" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C3V6" gate="C" x="115.57" y="100.33" rot="R180"> +<attribute name="VOLTAGE" x="115.57" y="100.33" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="115.57" y="100.33" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="115.57" y="100.33" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6H9" gate="C" x="132.08" y="125.73" rot="R180"> +<attribute name="VOLTAGE" x="132.08" y="125.73" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="132.08" y="125.73" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="132.08" y="125.73" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7H2" gate="C" x="153.67" y="62.23" smashed="yes" rot="R180"> +<attribute name="NAME" x="152.7175" y="62.23" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="152.7175" y="66.675" size="1.778" layer="96" rot="R180"/> +<attribute name="VOLTAGE" x="153.67" y="62.23" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="153.67" y="62.23" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="153.67" y="62.23" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7G10" gate="C" x="17.78" y="128.27"> +<attribute name="VOLTAGE" x="17.78" y="128.27" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="17.78" y="128.27" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="17.78" y="128.27" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6H10" gate="C" x="111.76" y="125.73"> +<attribute name="VOLTAGE" x="111.76" y="125.73" size="1.778" layer="96" display="off"/> +<attribute name="ESR_R" x="111.76" y="125.73" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="111.76" y="125.73" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6J4" gate="C" x="121.92" y="125.73" smashed="yes" rot="R180"> +<attribute name="NAME" x="124.714" y="127.889" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="122.936" y="125.476" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="121.92" y="125.73" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="121.92" y="125.73" size="1.778" layer="96" display="off"/> +</instance> +<instance part="L6J3" gate="L" x="93.98" y="138.43"/> +<instance part="L6H3" gate="L" x="167.64" y="85.09"/> +<instance part="R7H1" gate="R" x="153.67" y="73.66" smashed="yes" rot="R270"> +<attribute name="NAME" x="151.765" y="73.025" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="151.766" y="75.9536" size="1.778" layer="96" rot="R180"/> +<attribute name="POWER" x="153.67" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="153.67" y="73.66" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R7G2" gate="R" x="17.78" y="104.14" rot="R90"> +<attribute name="POWER" x="17.78" y="104.14" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="17.78" y="104.14" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R7G3" gate="R" x="25.4" y="107.95" rot="R90"> +<attribute name="TOLERANCE" x="25.4" y="107.95" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="POWER" x="25.4" y="107.95" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R3V2" gate="R" x="114.3" y="68.58" rot="R270"> +<attribute name="POWER" x="114.3" y="68.58" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R7G5" gate="R" x="17.78" y="72.39" smashed="yes" rot="R90"> +<attribute name="NAME" x="16.51" y="71.4375" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="16.51" y="73.66" size="1.778" layer="96" rot="R90"/> +<attribute name="POWER" x="17.78" y="72.39" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="17.78" y="72.39" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="U$45" gate="G$1" x="50.8" y="105.41"/> +<instance part="U$57" gate="G$1" x="102.87" y="109.22"/> +<instance part="U$68" gate="G$1" x="153.67" y="53.34"/> +<instance part="U$71" gate="G$1" x="114.3" y="54.61"/> +<instance part="U$72" gate="G$1" x="76.2" y="77.47"/> +<instance part="P+3" gate="1" x="76.2" y="147.32"/> +<instance part="U$73" gate="G$1" x="17.78" y="62.23"/> +<instance part="U$74" gate="G$1" x="179.07" y="52.07"/> +<instance part="TP4" gate="TP" x="198.12" y="106.68"> +<attribute name="DNP" x="203.2" y="110.49" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="C6H8" gate="C" x="140.97" y="125.73" rot="R180"> +<attribute name="VOLTAGE" x="140.97" y="125.73" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="140.97" y="125.73" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="140.97" y="125.73" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6G5" gate="R" x="208.28" y="85.09"> +<attribute name="POWER" x="208.28" y="85.09" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="208.28" y="85.09" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$77" gate="G$1" x="227.33" y="92.71"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="129.54" y1="55.88" x2="129.54" y2="57.15" width="0.1524" layer="91"/> +<wire x1="129.54" y1="57.15" x2="129.54" y2="59.69" width="0.1524" layer="91"/> +<wire x1="129.54" y1="57.15" x2="128.27" y2="57.15" width="0.1524" layer="91"/> +<wire x1="128.27" y1="57.15" x2="127" y2="57.15" width="0.1524" layer="91"/> +<wire x1="127" y1="57.15" x2="127" y2="59.69" width="0.1524" layer="91"/> +<wire x1="128.27" y1="57.15" x2="128.27" y2="59.69" width="0.1524" layer="91"/> +<wire x1="129.54" y1="57.15" x2="128.27" y2="57.15" width="0.1524" layer="91"/> +<junction x="129.54" y="57.15"/> +<junction x="128.27" y="57.15"/> +<pinref part="Q7H5" gate="Q" pin="S@3"/> +<pinref part="U$16" gate="G$1" pin="GND"/> +<pinref part="Q7H5" gate="Q" pin="S@1"/> +<pinref part="Q7H5" gate="Q" pin="S@2"/> +</segment> +<segment> +<wire x1="59.69" y1="115.57" x2="50.8" y2="115.57" width="0.1524" layer="91"/> +<wire x1="50.8" y1="115.57" x2="50.8" y2="109.22" width="0.1524" layer="91"/> +<wire x1="50.8" y1="109.22" x2="59.69" y2="109.22" width="0.1524" layer="91"/> +<wire x1="50.8" y1="106.68" x2="50.8" y2="109.22" width="0.1524" layer="91"/> +<junction x="50.8" y="109.22"/> +<pinref part="C7G7" gate="C" pin="2"/> +<pinref part="C3V5" gate="C" pin="2"/> +<pinref part="U$45" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="140.97" y1="123.19" x2="140.97" y2="111.76" width="0.1524" layer="91"/> +<wire x1="140.97" y1="111.76" x2="132.08" y2="111.76" width="0.1524" layer="91"/> +<wire x1="132.08" y1="111.76" x2="121.92" y2="111.76" width="0.1524" layer="91"/> +<wire x1="121.92" y1="111.76" x2="111.76" y2="111.76" width="0.1524" layer="91"/> +<wire x1="111.76" y1="111.76" x2="102.87" y2="111.76" width="0.1524" layer="91"/> +<wire x1="111.76" y1="120.65" x2="111.76" y2="111.76" width="0.1524" layer="91"/> +<wire x1="121.92" y1="123.19" x2="121.92" y2="111.76" width="0.1524" layer="91"/> +<wire x1="132.08" y1="123.19" x2="132.08" y2="111.76" width="0.1524" layer="91"/> +<wire x1="102.87" y1="111.76" x2="102.87" y2="110.49" width="0.1524" layer="91"/> +<junction x="132.08" y="111.76"/> +<junction x="121.92" y="111.76"/> +<junction x="111.76" y="111.76"/> +<pinref part="C6H10" gate="C" pin="C-"/> +<pinref part="C6J4" gate="C" pin="2"/> +<pinref part="C6H9" gate="C" pin="2"/> +<pinref part="U$57" gate="G$1" pin="GND"/> +<pinref part="C6H8" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="114.3" y1="63.5" x2="114.3" y2="55.88" width="0.1524" layer="91"/> +<pinref part="R3V2" gate="R" pin="2"/> +<pinref part="U$71" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="153.67" y1="54.61" x2="153.67" y2="59.69" width="0.1524" layer="91"/> +<pinref part="C7H2" gate="C" pin="2"/> +<pinref part="U$68" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="76.2" y1="78.74" x2="76.2" y2="81.28" width="0.1524" layer="91"/> +<wire x1="76.2" y1="81.28" x2="77.47" y2="81.28" width="0.1524" layer="91"/> +<pinref part="U7H1" gate="ISL6545" pin="GND"/> +<pinref part="U$72" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="17.78" y1="63.5" x2="17.78" y2="67.31" width="0.1524" layer="91"/> +<pinref part="R7G5" gate="R" pin="1"/> +<pinref part="U$73" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="198.12" y1="67.31" x2="198.12" y2="55.88" width="0.1524" layer="91"/> +<wire x1="198.12" y1="55.88" x2="191.77" y2="55.88" width="0.1524" layer="91"/> +<wire x1="191.77" y1="67.31" x2="191.77" y2="55.88" width="0.1524" layer="91"/> +<wire x1="191.77" y1="55.88" x2="185.42" y2="55.88" width="0.1524" layer="91"/> +<wire x1="185.42" y1="55.88" x2="179.07" y2="55.88" width="0.1524" layer="91"/> +<wire x1="179.07" y1="66.04" x2="179.07" y2="55.88" width="0.1524" layer="91"/> +<wire x1="179.07" y1="55.88" x2="179.07" y2="53.34" width="0.1524" layer="91"/> +<junction x="191.77" y="55.88"/> +<junction x="179.07" y="55.88"/> +<pinref part="C4U8" gate="C" pin="2"/> +<pinref part="C4V6" gate="C" pin="2"/> +<pinref part="C6G15" gate="C" pin="C-"/> +<pinref part="U$74" gate="G$1" pin="GND"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<wire x1="120.65" y1="62.23" x2="121.92" y2="62.23" width="0.1524" layer="91"/> +<wire x1="107.95" y1="81.28" x2="114.3" y2="81.28" width="0.1524" layer="91"/> +<wire x1="114.3" y1="81.28" x2="120.65" y2="81.28" width="0.1524" layer="91"/> +<wire x1="120.65" y1="81.28" x2="120.65" y2="62.23" width="0.1524" layer="91"/> +<wire x1="114.3" y1="81.28" x2="114.3" y2="73.66" width="0.1524" layer="91"/> +<junction x="114.3" y="81.28"/> +<pinref part="Q7H5" gate="Q" pin="G"/> +<pinref part="U7H1" gate="ISL6545" pin="LGATE/OCSET"/> +<pinref part="R3V2" gate="R" pin="1"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<wire x1="120.65" y1="96.52" x2="121.92" y2="96.52" width="0.1524" layer="91"/> +<wire x1="107.95" y1="88.9" x2="120.65" y2="88.9" width="0.1524" layer="91"/> +<wire x1="120.65" y1="88.9" x2="120.65" y2="96.52" width="0.1524" layer="91"/> +<pinref part="Q7H7" gate="Q" pin="G"/> +<pinref part="U7H1" gate="ISL6545" pin="UGATE"/> +</segment> +</net> +<net name="N$33" class="0"> +<segment> +<wire x1="67.31" y1="115.57" x2="76.2" y2="115.57" width="0.1524" layer="91"/> +<wire x1="76.2" y1="115.57" x2="76.2" y2="109.22" width="0.1524" layer="91"/> +<wire x1="76.2" y1="109.22" x2="67.31" y2="109.22" width="0.1524" layer="91"/> +<wire x1="76.2" y1="124.46" x2="76.2" y2="115.57" width="0.1524" layer="91"/> +<wire x1="77.47" y1="92.71" x2="76.2" y2="92.71" width="0.1524" layer="91"/> +<wire x1="76.2" y1="92.71" x2="76.2" y2="109.22" width="0.1524" layer="91"/> +<junction x="76.2" y="115.57"/> +<junction x="76.2" y="109.22"/> +<pinref part="C7G7" gate="C" pin="1"/> +<pinref part="C3V5" gate="C" pin="1"/> +<pinref part="R3V1" gate="R" pin="2"/> +<pinref part="U7H1" gate="ISL6545" pin="VCC"/> +</segment> +</net> +<net name="N$43" class="0"> +<segment> +<wire x1="77.47" y1="85.09" x2="72.39" y2="85.09" width="0.1524" layer="91"/> +<wire x1="72.39" y1="85.09" x2="64.77" y2="85.09" width="0.1524" layer="91"/> +<wire x1="68.58" y1="67.31" x2="72.39" y2="67.31" width="0.1524" layer="91"/> +<wire x1="72.39" y1="67.31" x2="72.39" y2="85.09" width="0.1524" layer="91"/> +<junction x="72.39" y="85.09"/> +<junction x="72.39" y="85.09"/> +<pinref part="U7H1" gate="ISL6545" pin="COMP/SD"/> +<pinref part="C7G8" gate="C" pin="2"/> +<pinref part="R7G1" gate="R" pin="2"/> +</segment> +</net> +<net name="N$89" class="0"> +<segment> +<wire x1="109.22" y1="107.95" x2="109.22" y2="92.71" width="0.1524" layer="91"/> +<wire x1="109.22" y1="92.71" x2="107.95" y2="92.71" width="0.1524" layer="91"/> +<wire x1="115.57" y1="105.41" x2="115.57" y2="107.95" width="0.1524" layer="91"/> +<wire x1="115.57" y1="107.95" x2="109.22" y2="107.95" width="0.1524" layer="91"/> +<pinref part="U7H1" gate="ISL6545" pin="BOOT"/> +<pinref part="C3V6" gate="C" pin="1"/> +</segment> +</net> +<net name="N$91" class="0"> +<segment> +<wire x1="153.67" y1="67.31" x2="153.67" y2="68.58" width="0.1524" layer="91"/> +<pinref part="C7H2" gate="C" pin="1"/> +<pinref part="R7H1" gate="R" pin="2"/> +</segment> +</net> +<net name="N$93" class="0"> +<segment> +<wire x1="17.78" y1="109.22" x2="17.78" y2="123.19" width="0.1524" layer="91"/> +<pinref part="R7G2" gate="R" pin="2"/> +<pinref part="C7G10" gate="C" pin="1"/> +</segment> +</net> +<net name="N$94" class="0"> +<segment> +<wire x1="151.13" y1="107.95" x2="152.4" y2="107.95" width="0.1524" layer="91"/> +<wire x1="149.86" y1="107.95" x2="151.13" y2="107.95" width="0.1524" layer="91"/> +<wire x1="148.59" y1="107.95" x2="149.86" y2="107.95" width="0.1524" layer="91"/> +<wire x1="130.81" y1="107.95" x2="148.59" y2="107.95" width="0.1524" layer="91"/> +<wire x1="130.81" y1="104.14" x2="130.81" y2="107.95" width="0.1524" layer="91"/> +<wire x1="129.54" y1="107.95" x2="130.81" y2="107.95" width="0.1524" layer="91"/> +<wire x1="129.54" y1="104.14" x2="129.54" y2="107.95" width="0.1524" layer="91"/> +<wire x1="127" y1="104.14" x2="127" y2="107.95" width="0.1524" layer="91"/> +<wire x1="127" y1="107.95" x2="128.27" y2="107.95" width="0.1524" layer="91"/> +<wire x1="128.27" y1="107.95" x2="129.54" y2="107.95" width="0.1524" layer="91"/> +<wire x1="128.27" y1="104.14" x2="128.27" y2="107.95" width="0.1524" layer="91"/> +<wire x1="152.4" y1="107.95" x2="152.4" y2="138.43" width="0.1524" layer="91"/> +<wire x1="140.97" y1="138.43" x2="140.97" y2="130.81" width="0.1524" layer="91"/> +<wire x1="132.08" y1="138.43" x2="140.97" y2="138.43" width="0.1524" layer="91"/> +<wire x1="121.92" y1="130.81" x2="121.92" y2="138.43" width="0.1524" layer="91"/> +<wire x1="102.87" y1="138.43" x2="111.76" y2="138.43" width="0.1524" layer="91"/> +<wire x1="111.76" y1="128.27" x2="111.76" y2="138.43" width="0.1524" layer="91"/> +<wire x1="111.76" y1="138.43" x2="121.92" y2="138.43" width="0.1524" layer="91"/> +<wire x1="121.92" y1="138.43" x2="132.08" y2="138.43" width="0.1524" layer="91"/> +<wire x1="132.08" y1="130.81" x2="132.08" y2="138.43" width="0.1524" layer="91"/> +<wire x1="152.4" y1="138.43" x2="140.97" y2="138.43" width="0.1524" layer="91"/> +<wire x1="99.06" y1="138.43" x2="102.87" y2="138.43" width="0.1524" layer="91"/> +<junction x="130.81" y="107.95"/> +<junction x="129.54" y="107.95"/> +<junction x="128.27" y="107.95"/> +<junction x="140.97" y="138.43"/> +<junction x="111.76" y="138.43"/> +<junction x="121.92" y="138.43"/> +<junction x="132.08" y="138.43"/> +<pinref part="Q7H7" gate="Q" pin="D@4"/> +<pinref part="Q7H7" gate="Q" pin="D@3"/> +<pinref part="Q7H7" gate="Q" pin="D@1"/> +<pinref part="Q7H7" gate="Q" pin="D@2"/> +<pinref part="C6J4" gate="C" pin="1"/> +<pinref part="C6H10" gate="C" pin="C+"/> +<pinref part="C6H9" gate="C" pin="1"/> +<pinref part="L6J3" gate="L" pin="1"/> +<pinref part="C6H8" gate="C" pin="1"/> +</segment> +</net> +<net name="N$95" class="0"> +<segment> +<wire x1="52.07" y1="74.93" x2="52.07" y2="67.31" width="0.1524" layer="91"/> +<wire x1="52.07" y1="67.31" x2="58.42" y2="67.31" width="0.1524" layer="91"/> +<pinref part="R7G1" gate="R" pin="1"/> +<pinref part="C7G9" gate="C" pin="2"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<wire x1="76.2" y1="144.78" x2="76.2" y2="138.43" width="0.1524" layer="91"/> +<wire x1="76.2" y1="138.43" x2="76.2" y2="134.62" width="0.1524" layer="91"/> +<wire x1="85.09" y1="138.43" x2="76.2" y2="138.43" width="0.1524" layer="91"/> +<wire x1="85.09" y1="138.43" x2="87.63" y2="138.43" width="0.1524" layer="91"/> +<junction x="76.2" y="138.43"/> +<pinref part="P+3" gate="1" pin="VCC"/> +<pinref part="R3V1" gate="R" pin="1"/> +<pinref part="L6J3" gate="L" pin="2"/> +</segment> +</net> +<net name="V2P5" class="0"> +<segment> +<wire x1="213.36" y1="85.09" x2="227.33" y2="85.09" width="0.1524" layer="91"/> +<wire x1="227.33" y1="85.09" x2="227.33" y2="91.44" width="0.1524" layer="91"/> +<pinref part="R6G5" gate="R" pin="2"/> +<pinref part="U$77" gate="G$1" pin="V2P5"/> +</segment> +</net> +<net name="V2P5-CONTROL" class="0"> +<segment> +<wire x1="25.4" y1="113.03" x2="25.4" y2="133.35" width="0.1524" layer="91"/> +<wire x1="17.78" y1="130.81" x2="17.78" y2="133.35" width="0.1524" layer="91"/> +<wire x1="25.4" y1="133.35" x2="17.78" y2="133.35" width="0.1524" layer="91"/> +<wire x1="25.4" y1="133.35" x2="31.75" y2="133.35" width="0.1524" layer="91"/> +<junction x="25.4" y="133.35"/> +<pinref part="R7G3" gate="R" pin="2"/> +<pinref part="C7G10" gate="C" pin="2"/> +<label x="31.75" y="133.35" size="1.778" layer="92" xref="yes"/> +</segment> +<segment> +<wire x1="198.12" y1="101.6" x2="187.96" y2="101.6" width="0.1524" layer="91"/> +<wire x1="198.12" y1="85.09" x2="198.12" y2="74.93" width="0.1524" layer="91"/> +<wire x1="198.12" y1="85.09" x2="198.12" y2="101.6" width="0.1524" layer="91"/> +<wire x1="198.12" y1="101.6" x2="198.12" y2="104.14" width="0.1524" layer="91"/> +<wire x1="198.12" y1="85.09" x2="203.2" y2="85.09" width="0.1524" layer="91"/> +<wire x1="191.77" y1="85.09" x2="191.77" y2="74.93" width="0.1524" layer="91"/> +<wire x1="191.77" y1="85.09" x2="198.12" y2="85.09" width="0.1524" layer="91"/> +<wire x1="179.07" y1="85.09" x2="191.77" y2="85.09" width="0.1524" layer="91"/> +<wire x1="179.07" y1="85.09" x2="179.07" y2="73.66" width="0.1524" layer="91"/> +<wire x1="172.72" y1="85.09" x2="179.07" y2="85.09" width="0.1524" layer="91"/> +<junction x="198.12" y="85.09"/> +<junction x="191.77" y="85.09"/> +<junction x="179.07" y="85.09"/> +<junction x="198.12" y="101.6"/> +<pinref part="R6G5" gate="R" pin="1"/> +<pinref part="TP4" gate="TP" pin="1"/> +<pinref part="C4U8" gate="C" pin="1"/> +<pinref part="C4V6" gate="C" pin="1"/> +<pinref part="C6G15" gate="C" pin="C+"/> +<pinref part="L6H3" gate="L" pin="1"/> +<label x="187.96" y="101.6" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FB-PW2.5" class="0"> +<segment> +<wire x1="77.47" y1="88.9" x2="57.15" y2="88.9" width="0.1524" layer="91"/> +<wire x1="57.15" y1="88.9" x2="57.15" y2="85.09" width="0.1524" layer="91"/> +<wire x1="57.15" y1="88.9" x2="52.07" y2="88.9" width="0.1524" layer="91"/> +<wire x1="52.07" y1="88.9" x2="52.07" y2="82.55" width="0.1524" layer="91"/> +<wire x1="52.07" y1="88.9" x2="30.48" y2="88.9" width="0.1524" layer="91"/> +<wire x1="30.48" y1="88.9" x2="25.4" y2="88.9" width="0.1524" layer="91"/> +<wire x1="25.4" y1="88.9" x2="17.78" y2="88.9" width="0.1524" layer="91"/> +<wire x1="17.78" y1="88.9" x2="17.78" y2="86.36" width="0.1524" layer="91"/> +<wire x1="17.78" y1="77.47" x2="17.78" y2="86.36" width="0.1524" layer="91"/> +<wire x1="17.78" y1="88.9" x2="17.78" y2="99.06" width="0.1524" layer="91"/> +<wire x1="25.4" y1="102.87" x2="25.4" y2="88.9" width="0.1524" layer="91"/> +<junction x="57.15" y="88.9"/> +<junction x="52.07" y="88.9"/> +<junction x="17.78" y="88.9"/> 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part="U$10" gate="PW-V1P2" x="16.51" y="91.44"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="138.43" y1="102.87" x2="138.43" y2="104.14" width="0.1524" layer="91"/> +<wire x1="138.43" y1="104.14" x2="138.43" y2="105.41" width="0.1524" layer="91"/> +<wire x1="138.43" y1="104.14" x2="137.16" y2="104.14" width="0.1524" layer="91"/> +<wire x1="137.16" y1="104.14" x2="135.89" y2="104.14" width="0.1524" layer="91"/> +<wire x1="135.89" y1="104.14" x2="135.89" y2="105.41" width="0.1524" layer="91"/> +<wire x1="137.16" y1="104.14" x2="137.16" y2="105.41" width="0.1524" layer="91"/> +<wire x1="138.43" y1="104.14" x2="137.16" y2="104.14" width="0.1524" layer="91"/> +<junction x="138.43" y="104.14"/> +<junction x="137.16" y="104.14"/> +<pinref part="Q5H3" gate="Q" pin="S@3"/> +<pinref part="U$1" gate="G$1" pin="GND"/> +<pinref part="Q5H3" gate="Q" pin="S@1"/> +<pinref part="Q5H3" gate="Q" pin="S@2"/> +</segment> +<segment> +<wire x1="153.67" y1="102.87" x2="153.67" y2="104.14" width="0.1524" layer="91"/> +<wire x1="153.67" y1="104.14" x2="153.67" y2="105.41" width="0.1524" layer="91"/> +<wire x1="153.67" y1="104.14" x2="152.4" y2="104.14" width="0.1524" layer="91"/> +<wire x1="152.4" y1="104.14" x2="151.13" y2="104.14" width="0.1524" layer="91"/> +<wire x1="151.13" y1="104.14" x2="151.13" y2="105.41" width="0.1524" layer="91"/> +<wire x1="152.4" y1="104.14" x2="152.4" y2="105.41" width="0.1524" layer="91"/> +<junction x="153.67" y="104.14"/> +<junction x="152.4" y="104.14"/> +<pinref part="Q5H1" gate="Q" pin="S@3"/> +<pinref part="U$2" gate="G$1" pin="GND"/> +<pinref part="Q5H1" gate="Q" pin="S@1"/> +<pinref part="Q5H1" gate="Q" pin="S@2"/> +</segment> +<segment> +<wire x1="17.78" y1="128.27" x2="17.78" y2="123.19" width="0.1524" layer="91"/> +<wire x1="17.78" y1="123.19" x2="22.86" y2="123.19" width="0.1524" layer="91"/> +<wire x1="22.86" y1="123.19" x2="22.86" y2="128.27" width="0.1524" layer="91"/> +<wire x1="22.86" y1="120.65" x2="22.86" y2="123.19" width="0.1524" layer="91"/> +<wire x1="29.21" y1="123.19" x2="22.86" y2="123.19" width="0.1524" layer="91"/> +<junction x="22.86" y="123.19"/> +<pinref part="C5V1" gate="C" pin="2"/> +<pinref part="C5H1" gate="C" pin="2"/> +<pinref part="R4V8" gate="R" pin="2"/> +<pinref part="U$9" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="85.09" y1="113.03" x2="85.09" y2="115.57" width="0.1524" layer="91"/> +<wire x1="85.09" y1="115.57" x2="86.36" y2="115.57" width="0.1524" layer="91"/> +<pinref part="U5H1" gate="ISL6545" pin="GND"/> +<pinref part="U$5" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="163.83" y1="95.25" x2="163.83" y2="99.06" width="0.1524" layer="91"/> +<pinref part="C5H3" gate="C" pin="2"/> +<pinref part="U$6" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="237.49" y1="102.87" x2="237.49" y2="93.98" width="0.1524" layer="91"/> +<wire x1="237.49" y1="93.98" x2="237.49" y2="92.71" width="0.1524" layer="91"/> +<wire x1="237.49" y1="93.98" x2="231.14" y2="93.98" width="0.1524" layer="91"/> +<wire x1="231.14" y1="93.98" x2="224.79" y2="93.98" width="0.1524" layer="91"/> +<wire x1="224.79" y1="93.98" x2="218.44" y2="93.98" width="0.1524" layer="91"/> +<wire x1="218.44" y1="93.98" x2="212.09" y2="93.98" width="0.1524" layer="91"/> +<wire x1="212.09" y1="93.98" x2="205.74" y2="93.98" width="0.1524" layer="91"/> +<wire x1="205.74" y1="93.98" x2="199.39" y2="93.98" width="0.1524" layer="91"/> +<wire x1="199.39" y1="93.98" x2="199.39" y2="100.33" width="0.1524" layer="91"/> +<wire x1="205.74" y1="93.98" x2="205.74" y2="100.33" width="0.1524" layer="91"/> +<wire x1="212.09" y1="93.98" x2="212.09" y2="100.33" width="0.1524" layer="91"/> +<wire x1="218.44" y1="93.98" x2="218.44" y2="100.33" width="0.1524" layer="91"/> +<wire x1="224.79" y1="93.98" x2="224.79" y2="102.87" width="0.1524" layer="91"/> +<wire x1="231.14" y1="93.98" x2="231.14" y2="102.87" width="0.1524" layer="91"/> +<junction x="237.49" y="93.98"/> +<junction x="205.74" y="93.98"/> +<junction x="212.09" y="93.98"/> +<junction x="218.44" y="93.98"/> +<junction x="224.79" y="93.98"/> +<junction x="231.14" y="93.98"/> +<pinref part="C4U6" gate="C" pin="2"/> +<pinref part="C5U5" gate="C" pin="C-"/> +<pinref part="C6G8" gate="C" pin="C-"/> +<pinref part="C6G13" gate="C" pin="C-"/> +<pinref part="C5G5" gate="C" pin="C-"/> +<pinref part="C4U7" gate="C" pin="2"/> +<pinref part="C4V2" gate="C" pin="2"/> +<pinref part="U$7" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="81.28" y1="31.75" x2="81.28" y2="50.8" width="0.1524" layer="91"/> +<pinref part="Q5U1" gate="T" pin="S"/> +<pinref part="U$48" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="222.25" y1="151.13" x2="222.25" y2="142.24" width="0.1524" layer="91"/> +<wire x1="222.25" y1="142.24" x2="215.9" y2="142.24" width="0.1524" layer="91"/> +<wire x1="215.9" y1="142.24" x2="209.55" y2="142.24" width="0.1524" layer="91"/> +<wire x1="209.55" y1="142.24" x2="203.2" y2="142.24" width="0.1524" layer="91"/> +<wire x1="203.2" y1="142.24" x2="196.85" y2="142.24" width="0.1524" layer="91"/> +<wire x1="196.85" y1="142.24" x2="190.5" y2="142.24" width="0.1524" layer="91"/> +<wire x1="190.5" y1="142.24" x2="184.15" y2="142.24" width="0.1524" layer="91"/> +<wire x1="184.15" y1="142.24" x2="177.8" y2="142.24" width="0.1524" layer="91"/> +<wire x1="177.8" y1="142.24" x2="171.45" y2="142.24" width="0.1524" layer="91"/> +<wire x1="171.45" y1="142.24" x2="165.1" y2="142.24" width="0.1524" layer="91"/> +<wire x1="165.1" y1="142.24" x2="165.1" y2="148.59" width="0.1524" layer="91"/> +<wire x1="171.45" y1="148.59" x2="171.45" y2="142.24" width="0.1524" layer="91"/> +<wire x1="177.8" y1="148.59" x2="177.8" y2="142.24" width="0.1524" layer="91"/> +<wire x1="184.15" y1="148.59" x2="184.15" y2="142.24" width="0.1524" layer="91"/> +<wire x1="190.5" y1="151.13" x2="190.5" y2="142.24" width="0.1524" layer="91"/> +<wire x1="196.85" y1="151.13" x2="196.85" y2="142.24" width="0.1524" layer="91"/> +<wire x1="203.2" y1="151.13" x2="203.2" y2="142.24" width="0.1524" layer="91"/> +<wire x1="209.55" y1="151.13" x2="209.55" y2="142.24" width="0.1524" layer="91"/> +<wire x1="215.9" y1="151.13" x2="215.9" y2="142.24" width="0.1524" layer="91"/> +<wire x1="222.25" y1="142.24" x2="222.25" y2="140.97" width="0.1524" layer="91"/> +<junction x="215.9" y="142.24"/> +<junction x="209.55" y="142.24"/> +<junction x="203.2" y="142.24"/> +<junction x="196.85" y="142.24"/> +<junction x="190.5" y="142.24"/> +<junction x="184.15" y="142.24"/> +<junction x="177.8" y="142.24"/> +<junction x="171.45" y="142.24"/> +<junction x="222.25" y="142.24"/> +<pinref part="C6H3" gate="C" pin="2"/> +<pinref part="C6H6" gate="C" pin="C-"/> +<pinref part="C5J3" gate="C" pin="C-"/> +<pinref part="C5J2" gate="C" pin="C-"/> +<pinref part="C5J1" gate="C" pin="C-"/> +<pinref part="C6H4" gate="C" pin="2"/> +<pinref part="C4V4" gate="C" pin="2"/> +<pinref part="C4V5" gate="C" pin="2"/> +<pinref part="C4V3" gate="C" pin="2"/> +<pinref part="C6H2" gate="C" pin="2"/> +<pinref part="U$3" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="100.33" y1="107.95" x2="107.95" y2="107.95" width="0.1524" layer="91"/> +<pinref part="R5V2" gate="R" pin="2"/> +<pinref part="U$65" gate="G$1" pin="GND"/> +</segment> +</net> +<net name="N$10" class="0"> +<segment> +<wire x1="118.11" y1="149.86" x2="118.11" y2="144.78" width="0.1524" layer="91"/> +<wire x1="118.11" y1="144.78" x2="118.11" y2="127" width="0.1524" layer="91"/> +<wire x1="118.11" y1="127" x2="116.84" y2="127" width="0.1524" layer="91"/> +<wire x1="123.19" y1="140.97" x2="123.19" y2="144.78" width="0.1524" layer="91"/> +<wire x1="123.19" y1="144.78" x2="118.11" y2="144.78" width="0.1524" layer="91"/> +<junction x="118.11" y="144.78"/> +<pinref part="U5H1" gate="ISL6545" pin="BOOT"/> +<pinref part="C5V3" gate="C" pin="1"/> +<pinref part="CR5H1" gate="DIODE" pin="C"/> +</segment> +</net> +<net name="N$6" class="0"> +<segment> +<wire x1="163.83" y1="106.68" x2="163.83" y2="107.95" width="0.1524" layer="91"/> +<pinref part="C5H3" gate="C" pin="1"/> +<pinref part="R5H3" gate="R" pin="2"/> +</segment> +</net> +<net name="N$9" class="0"> +<segment> +<wire x1="34.29" y1="101.6" x2="34.29" y2="87.63" width="0.1524" layer="91"/> +<wire x1="45.72" y1="88.9" x2="45.72" y2="87.63" width="0.1524" layer="91"/> +<wire x1="45.72" y1="87.63" x2="34.29" y2="87.63" width="0.1524" layer="91"/> +<wire x1="34.29" y1="87.63" x2="31.75" y2="87.63" width="0.1524" layer="91"/> +<wire x1="34.29" y1="87.63" x2="45.72" y2="87.63" width="0.1524" layer="91"/> +<wire x1="45.72" y1="87.63" x2="102.87" y2="87.63" width="0.1524" layer="91"/> +<junction x="34.29" y="87.63"/> +<junction x="45.72" y="87.63"/> +<pinref part="R5U17" gate="R" pin="2"/> +<pinref part="C5U6" gate="C" pin="2"/> +<pinref part="R5U11" gate="R" pin="1"/> +<pinref part="R5U13" gate="R" pin="1"/> +</segment> +</net> +<net name="N$11" class="0"> +<segment> +<wire x1="45.72" y1="101.6" x2="45.72" y2="96.52" width="0.1524" layer="91"/> +<pinref part="R5U16" gate="R" pin="2"/> +<pinref part="C5U6" gate="C" pin="1"/> +</segment> +</net> +<net name="V1P2-CORE-EN-N" class="0"> +<segment> +<wire x1="68.58" y1="53.34" x2="52.07" y2="53.34" width="0.1524" layer="91"/> +<label x="52.07" y="53.34" size="1.778" layer="92" rot="R180" xref="yes"/> +<wire x1="73.66" y1="53.34" x2="68.58" y2="53.34" width="0.1524" layer="91"/> +<wire x1="68.58" y1="57.15" x2="68.58" y2="53.34" width="0.1524" layer="91"/> +<pinref part="Q5U1" gate="T" pin="G"/> +<pinref part="R5U14" gate="R" pin="1"/> +<junction x="68.58" y="53.34"/> +</segment> +</net> +<net name="N$40" class="0"> +<segment> +<wire x1="86.36" y1="119.38" x2="81.28" y2="119.38" width="0.1524" layer="91"/> +<wire x1="81.28" y1="119.38" x2="68.58" y2="119.38" width="0.1524" layer="91"/> +<wire x1="81.28" y1="96.52" x2="81.28" y2="119.38" width="0.1524" layer="91"/> +<wire x1="76.2" y1="96.52" x2="81.28" y2="96.52" width="0.1524" layer="91"/> +<wire x1="81.28" y1="96.52" x2="81.28" y2="60.96" width="0.1524" layer="91"/> +<junction x="81.28" y="119.38"/> +<junction x="81.28" y="96.52"/> +<pinref part="C5U7" gate="C" pin="1"/> +<pinref part="U5H1" gate="ISL6545" pin="COMP/SD"/> +<pinref part="R5V1" gate="R" pin="2"/> +<pinref part="Q5U1" gate="T" pin="D"/> +</segment> +</net> +<net name="N$8" class="0"> +<segment> +<wire x1="66.04" y1="96.52" x2="54.61" y2="96.52" width="0.1524" layer="91"/> +<wire x1="54.61" y1="96.52" x2="54.61" y2="101.6" width="0.1524" layer="91"/> +<pinref part="R5V1" gate="R" pin="1"/> +<pinref part="C5V2" gate="C" pin="2"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<wire x1="91.44" y1="168.91" x2="91.44" y2="166.37" width="0.1524" layer="91"/> +<wire x1="91.44" y1="166.37" x2="99.06" y2="166.37" width="0.1524" layer="91"/> +<pinref part="P+1" gate="1" pin="VCC"/> +<pinref part="L6J2" gate="L" pin="2"/> +</segment> +<segment> +<wire x1="17.78" y1="151.13" x2="17.78" y2="152.4" width="0.1524" layer="91"/> +<pinref part="R5G1" gate="R" pin="1"/> +<pinref part="P+9" gate="1" pin="VCC"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="68.58" y1="69.85" x2="68.58" y2="67.31" width="0.1524" layer="91"/> +<pinref part="R5U14" gate="R" pin="2"/> +<pinref part="U$8" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="V1P2" class="0"> +<segment> +<wire x1="237.49" y1="110.49" x2="237.49" y2="119.38" width="0.1524" layer="91"/> +<wire x1="199.39" y1="107.95" x2="199.39" y2="119.38" width="0.1524" layer="91"/> +<wire x1="199.39" y1="119.38" x2="205.74" y2="119.38" width="0.1524" layer="91"/> +<wire x1="205.74" y1="107.95" x2="205.74" y2="119.38" width="0.1524" layer="91"/> +<wire x1="205.74" y1="119.38" x2="212.09" y2="119.38" width="0.1524" layer="91"/> +<wire x1="212.09" y1="107.95" x2="212.09" y2="119.38" width="0.1524" layer="91"/> +<wire x1="212.09" y1="119.38" x2="218.44" y2="119.38" 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layer="91"/> +<junction x="199.39" y="119.38"/> +<junction x="205.74" y="119.38"/> +<junction x="212.09" y="119.38"/> +<junction x="218.44" y="119.38"/> +<junction x="224.79" y="119.38"/> +<junction x="231.14" y="119.38"/> +<junction x="190.5" y="119.38"/> +<pinref part="L6H1" gate="L" pin="2"/> +<pinref part="C4U6" gate="C" pin="1"/> +<pinref part="R5U13" gate="R" pin="2"/> +<pinref part="C5U5" gate="C" pin="C+"/> +<pinref part="C6G8" gate="C" pin="C+"/> +<pinref part="C6G13" gate="C" pin="C+"/> +<pinref part="C5G5" gate="C" pin="C+"/> +<pinref part="C4U7" gate="C" pin="1"/> +<pinref part="C4V2" gate="C" pin="1"/> +<pinref part="U$13" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="21.59" y1="87.63" x2="16.51" y2="87.63" width="0.1524" layer="91"/> +<wire x1="16.51" y1="87.63" x2="16.51" y2="88.9" width="0.1524" layer="91"/> +<pinref part="R5U11" gate="R" pin="2"/> +<pinref part="U$10" gate="PW-V1P2" pin="V1P2"/> +</segment> +</net> +<net name="UGATE1-2" class="0"> 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gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="168.91" y1="96.52" x2="168.91" y2="97.79" width="0.1524" layer="91"/> +<pinref part="C7H1" gate="C" pin="2"/> +<pinref part="U$184" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="76.2" y1="111.76" x2="76.2" y2="114.3" width="0.1524" layer="91"/> +<wire x1="76.2" y1="114.3" x2="77.47" y2="114.3" width="0.1524" layer="91"/> +<pinref part="U7H2" gate="ISL6545" pin="GND"/> +<pinref part="U$187" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="72.39" y1="53.34" x2="72.39" y2="41.91" width="0.1524" layer="91"/> +<pinref part="Q3U5" gate="T" pin="S"/> +<pinref part="U$586" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="8.89" y1="121.92" x2="12.7" y2="121.92" width="0.1524" layer="91"/> +<pinref part="R7G14" gate="R" pin="1"/> +<pinref part="U$19" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="233.68" y1="102.87" x2="233.68" y2="93.98" width="0.1524" layer="91"/> +<wire x1="233.68" y1="93.98" x2="227.33" y2="93.98" width="0.1524" layer="91"/> +<wire x1="227.33" y1="102.87" x2="227.33" y2="93.98" width="0.1524" layer="91"/> +<wire x1="227.33" y1="93.98" x2="220.98" y2="93.98" width="0.1524" layer="91"/> +<wire x1="220.98" y1="102.87" x2="220.98" y2="93.98" width="0.1524" layer="91"/> +<wire x1="220.98" y1="93.98" x2="214.63" y2="93.98" width="0.1524" layer="91"/> +<wire x1="214.63" y1="101.6" x2="214.63" y2="93.98" width="0.1524" layer="91"/> +<wire x1="214.63" y1="93.98" x2="208.28" y2="93.98" width="0.1524" layer="91"/> +<wire x1="208.28" y1="101.6" x2="208.28" y2="93.98" width="0.1524" layer="91"/> +<wire x1="208.28" y1="93.98" x2="201.93" y2="93.98" width="0.1524" layer="91"/> +<wire x1="201.93" y1="93.98" x2="201.93" y2="101.6" width="0.1524" layer="91"/> +<wire x1="201.93" y1="90.17" x2="201.93" y2="93.98" width="0.1524" layer="91"/> +<junction x="227.33" y="93.98"/> +<junction x="220.98" y="93.98"/> +<junction x="214.63" y="93.98"/> +<junction x="208.28" y="93.98"/> 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y2="106.68" width="0.1524" layer="91"/> +<junction x="120.65" y="102.87"/> +<junction x="114.3" y="114.3"/> +<pinref part="Q7H2" gate="Q" pin="G"/> +<pinref part="Q7H4" gate="Q" pin="G"/> +<pinref part="U7H2" gate="ISL6545" pin="LGATE/OCSET"/> +<pinref part="R3V13" gate="R" pin="1"/> +</segment> +</net> +<net name="N$18" class="0"> +<segment> +<wire x1="120.65" y1="129.54" x2="121.92" y2="129.54" width="0.1524" layer="91"/> +<wire x1="107.95" y1="121.92" x2="120.65" y2="121.92" width="0.1524" layer="91"/> +<wire x1="120.65" y1="121.92" x2="120.65" y2="129.54" width="0.1524" layer="91"/> +<wire x1="143.51" y1="129.54" x2="135.89" y2="129.54" width="0.1524" layer="91"/> +<wire x1="135.89" y1="129.54" x2="135.89" y2="121.92" width="0.1524" layer="91"/> +<wire x1="135.89" y1="121.92" x2="120.65" y2="121.92" width="0.1524" layer="91"/> +<junction x="120.65" y="121.92"/> +<pinref part="Q7H1" gate="Q" pin="G"/> +<pinref part="U7H2" gate="ISL6545" pin="UGATE"/> +<pinref part="Q7H3" gate="Q" pin="G"/> +</segment> +</net> +<net name="N$21" class="0"> +<segment> +<wire x1="67.31" y1="144.78" x2="76.2" y2="144.78" width="0.1524" layer="91"/> +<wire x1="76.2" y1="144.78" x2="76.2" y2="138.43" width="0.1524" layer="91"/> +<wire x1="76.2" y1="138.43" x2="67.31" y2="138.43" width="0.1524" layer="91"/> +<wire x1="76.2" y1="153.67" x2="76.2" y2="144.78" width="0.1524" layer="91"/> +<wire x1="77.47" y1="125.73" x2="76.2" y2="125.73" width="0.1524" layer="91"/> +<wire x1="76.2" y1="125.73" x2="76.2" y2="138.43" width="0.1524" layer="91"/> +<junction x="76.2" y="144.78"/> +<junction x="76.2" y="138.43"/> +<pinref part="C7G4" gate="C" pin="1"/> +<pinref part="C3V1" gate="C" pin="1"/> +<pinref part="R3V6" gate="R" pin="2"/> +<pinref part="U7H2" gate="ISL6545" pin="VCC"/> +</segment> +</net> +<net name="N$22" class="0"> +<segment> +<wire x1="77.47" y1="118.11" x2="72.39" y2="118.11" width="0.1524" layer="91"/> +<wire x1="72.39" y1="118.11" x2="64.77" y2="118.11" width="0.1524" layer="91"/> +<wire x1="68.58" y1="100.33" x2="72.39" y2="100.33" width="0.1524" layer="91"/> +<wire x1="72.39" y1="100.33" x2="72.39" y2="118.11" width="0.1524" layer="91"/> +<wire x1="72.39" y1="100.33" x2="72.39" y2="63.5" width="0.1524" layer="91"/> +<junction x="72.39" y="118.11"/> +<junction x="72.39" y="118.11"/> +<junction x="72.39" y="100.33"/> +<pinref part="U7H2" gate="ISL6545" pin="COMP/SD"/> +<pinref part="C7G5" gate="C" pin="2"/> +<pinref part="R7G25" gate="R" pin="2"/> +<pinref part="Q3U5" gate="T" pin="D"/> +</segment> +</net> +<net name="N$24" class="0"> +<segment> +<wire x1="85.09" y1="146.05" x2="85.09" y2="140.97" width="0.1524" layer="91"/> +<wire x1="85.09" y1="140.97" x2="109.22" y2="140.97" width="0.1524" layer="91"/> +<wire x1="109.22" y1="140.97" x2="109.22" y2="125.73" width="0.1524" layer="91"/> +<wire x1="109.22" y1="125.73" x2="107.95" y2="125.73" width="0.1524" layer="91"/> +<wire x1="115.57" y1="138.43" x2="115.57" y2="140.97" width="0.1524" layer="91"/> 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layer="91"/> +<junction x="29.21" y="85.09"/> +<junction x="43.18" y="85.09"/> +<pinref part="R7G23" gate="R" pin="2"/> +<pinref part="C7G6" gate="C" pin="2"/> +<pinref part="R3U12" gate="R" pin="1"/> +<pinref part="R7G18" gate="R" pin="1"/> +</segment> +</net> +<net name="N$28" class="0"> +<segment> +<wire x1="43.18" y1="102.87" x2="43.18" y2="99.06" width="0.1524" layer="91"/> +<pinref part="R7G26" gate="R" pin="2"/> +<pinref part="C7G6" gate="C" pin="1"/> +</segment> +</net> +<net name="FB-VCC-CPU" class="0"> +<segment> +<wire x1="77.47" y1="121.92" x2="57.15" y2="121.92" width="0.1524" layer="91"/> +<wire x1="57.15" y1="121.92" x2="57.15" y2="118.11" width="0.1524" layer="91"/> +<wire x1="57.15" y1="121.92" x2="52.07" y2="121.92" width="0.1524" layer="91"/> +<wire x1="52.07" y1="121.92" x2="52.07" y2="115.57" width="0.1524" layer="91"/> +<wire x1="52.07" y1="121.92" x2="43.18" y2="121.92" width="0.1524" layer="91"/> +<wire x1="43.18" y1="121.92" x2="43.18" y2="113.03" width="0.1524" layer="91"/> +<wire x1="43.18" y1="121.92" x2="29.21" y2="121.92" width="0.1524" layer="91"/> +<wire x1="29.21" y1="121.92" x2="29.21" y2="110.49" width="0.1524" layer="91"/> +<wire x1="22.86" y1="121.92" x2="29.21" y2="121.92" width="0.1524" layer="91"/> +<junction x="57.15" y="121.92"/> +<junction x="52.07" y="121.92"/> +<junction x="43.18" y="121.92"/> +<junction x="29.21" y="121.92"/> +<label x="34.3535" y="123.8885" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7G23" gate="R" pin="1"/> +<pinref part="R7G26" gate="R" pin="1"/> +<pinref part="C7G3" gate="C" pin="1"/> +<pinref part="C7G5" gate="C" pin="1"/> +<pinref part="U7H2" gate="ISL6545" pin="FB"/> +<pinref part="R7G14" gate="R" pin="2"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="62.23" y1="76.2" x2="62.23" y2="71.12" width="0.1524" layer="91"/> +<pinref part="R3U13" gate="R" pin="2"/> +<pinref part="U$330" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="N$23" class="0"> +<segment> +<wire x1="152.4" y1="140.97" x2="152.4" y2="137.16" width="0.1524" layer="91"/> +<wire x1="151.13" y1="140.97" x2="152.4" y2="140.97" width="0.1524" layer="91"/> +<wire x1="151.13" y1="137.16" x2="151.13" y2="140.97" width="0.1524" layer="91"/> +<wire x1="149.86" y1="140.97" x2="151.13" y2="140.97" width="0.1524" layer="91"/> +<wire x1="149.86" y1="137.16" x2="149.86" y2="140.97" width="0.1524" layer="91"/> +<wire x1="148.59" y1="140.97" x2="149.86" y2="140.97" width="0.1524" layer="91"/> +<wire x1="148.59" y1="137.16" x2="148.59" y2="140.97" width="0.1524" layer="91"/> +<wire x1="130.81" y1="140.97" x2="148.59" y2="140.97" width="0.1524" layer="91"/> +<wire x1="130.81" y1="137.16" x2="130.81" y2="140.97" width="0.1524" layer="91"/> +<wire x1="129.54" y1="140.97" x2="130.81" y2="140.97" width="0.1524" layer="91"/> +<wire x1="129.54" y1="137.16" x2="129.54" y2="140.97" width="0.1524" layer="91"/> +<wire x1="127" y1="137.16" x2="127" y2="140.97" width="0.1524" layer="91"/> +<wire x1="127" y1="140.97" x2="128.27" y2="140.97" width="0.1524" layer="91"/> +<wire x1="128.27" y1="140.97" x2="129.54" y2="140.97" width="0.1524" layer="91"/> +<wire x1="128.27" y1="137.16" x2="128.27" y2="140.97" width="0.1524" layer="91"/> +<wire x1="152.4" y1="140.97" x2="152.4" y2="171.45" width="0.1524" layer="91"/> +<wire x1="140.97" y1="171.45" x2="140.97" y2="163.83" width="0.1524" layer="91"/> +<wire x1="132.08" y1="171.45" x2="140.97" y2="171.45" width="0.1524" layer="91"/> +<wire x1="121.92" y1="163.83" x2="121.92" y2="171.45" width="0.1524" layer="91"/> +<wire x1="102.87" y1="161.29" x2="102.87" y2="171.45" width="0.1524" layer="91"/> +<wire x1="102.87" y1="171.45" x2="111.76" y2="171.45" width="0.1524" layer="91"/> +<wire x1="111.76" y1="161.29" x2="111.76" y2="171.45" width="0.1524" layer="91"/> +<wire x1="111.76" y1="171.45" x2="121.92" y2="171.45" width="0.1524" layer="91"/> +<wire x1="121.92" y1="171.45" x2="132.08" y2="171.45" width="0.1524" layer="91"/> +<wire x1="132.08" y1="163.83" x2="132.08" y2="171.45" width="0.1524" layer="91"/> +<wire x1="152.4" y1="171.45" x2="140.97" y2="171.45" width="0.1524" layer="91"/> +<wire x1="99.06" y1="171.45" x2="102.87" y2="171.45" width="0.1524" layer="91"/> +<junction x="151.13" y="140.97"/> +<junction x="149.86" y="140.97"/> +<junction x="148.59" y="140.97"/> +<junction x="130.81" y="140.97"/> +<junction x="129.54" y="140.97"/> +<junction x="128.27" y="140.97"/> +<junction x="140.97" y="171.45"/> +<junction x="111.76" y="171.45"/> +<junction x="121.92" y="171.45"/> +<junction x="132.08" y="171.45"/> +<junction x="152.4" y="140.97"/> +<junction x="102.87" y="171.45"/> +<pinref part="Q7H3" gate="Q" pin="D@4"/> +<pinref part="Q7H3" gate="Q" pin="D@3"/> +<pinref part="Q7H3" gate="Q" pin="D@2"/> +<pinref part="Q7H3" gate="Q" pin="D@1"/> +<pinref part="Q7H1" gate="Q" pin="D@4"/> +<pinref part="Q7H1" gate="Q" pin="D@3"/> +<pinref part="Q7H1" gate="Q" pin="D@1"/> +<pinref part="Q7H1" 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y="137.16" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="144.78" y="137.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C9C3" gate="C" x="149.86" y="137.16" rot="R180"> +<attribute name="VOLTAGE" x="149.86" y="137.16" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="149.86" y="137.16" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="149.86" y="137.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C9C4" gate="C" x="154.94" y="137.16" rot="R180"> +<attribute name="VOLTAGE" x="154.94" y="137.16" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="154.94" y="137.16" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="154.94" y="137.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C9C7" gate="C" x="160.02" y="137.16" rot="R180"> +<attribute name="VOLTAGE" x="160.02" y="137.16" size="1.778" layer="96" display="off"/> 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part="C1N1" gate="C" x="17.78" y="86.36" rot="R180"> +<attribute name="VOLTAGE" x="17.78" y="86.36" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="17.78" y="86.36" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="17.78" y="86.36" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C9B6" gate="C" x="20.32" y="111.76" rot="R180"> +<attribute name="VOLTAGE" x="20.32" y="111.76" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="20.32" y="111.76" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="20.32" y="111.76" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C9C2" gate="C" x="49.53" y="134.62" rot="R180"> +<attribute name="VOLTAGE" x="49.53" y="134.62" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="49.53" y="134.62" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="49.53" y="134.62" size="1.778" layer="96" display="off"/> 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size="1.778" layer="96" rot="MR0" display="off"/> +<attribute name="TYPE" x="209.55" y="158.75" size="1.778" layer="96" rot="MR0" display="off"/> +</instance> +<instance part="C8B1" gate="C" x="217.17" y="158.75" smashed="yes" rot="MR180"> +<attribute name="NAME" x="216.535" y="161.6075" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="216.154" y="158.496" size="1.778" layer="96" rot="MR270"/> +<attribute name="VOLTAGE" x="217.17" y="158.75" size="1.778" layer="96" rot="MR0" display="off"/> +<attribute name="TYPE" x="217.17" y="158.75" size="1.778" layer="96" rot="MR0" display="off"/> +</instance> +<instance part="C9C1" gate="C" x="224.79" y="158.75" smashed="yes" rot="MR180"> +<attribute name="NAME" x="224.155" y="161.29" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="223.774" y="158.496" size="1.778" layer="96" rot="MR270"/> +<attribute name="VOLTAGE" x="224.79" y="158.75" size="1.778" layer="96" rot="MR0" display="off"/> +<attribute name="TYPE" x="224.79" y="158.75" size="1.778" layer="96" rot="MR0" display="off"/> +</instance> +<instance part="C9B1" gate="C" x="232.41" y="158.75" smashed="yes" rot="MR180"> +<attribute name="NAME" x="231.775" y="161.29" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="231.394" y="158.496" size="1.778" layer="96" rot="MR270"/> +<attribute name="VOLTAGE" x="232.41" y="158.75" size="1.778" layer="96" rot="MR0" display="off"/> +<attribute name="TYPE" x="232.41" y="158.75" size="1.778" layer="96" rot="MR0" display="off"/> +</instance> +<instance part="C9B4" gate="C" x="242.57" y="158.75" smashed="yes"> +<attribute name="NAME" x="241.935" y="155.2575" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="241.8715" y="160.401" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="242.57" y="158.75" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="242.57" y="158.75" size="1.778" layer="96" display="off"/> +<attribute name="ESR_R" x="242.57" y="158.75" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C9B3" gate="C" x="248.92" y="158.75" smashed="yes"> +<attribute name="NAME" x="248.285" y="155.2575" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="248.2215" y="160.401" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="248.92" y="158.75" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="248.92" y="158.75" size="1.778" layer="96" display="off"/> +<attribute name="ESR_R" x="248.92" y="158.75" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C9B2" gate="C" x="255.27" y="158.75" smashed="yes"> +<attribute name="NAME" x="254.635" y="155.2575" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="254.5715" y="160.401" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="255.27" y="158.75" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="255.27" y="158.75" size="1.778" layer="96" display="off"/> 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y="114.3"/> +<instance part="P+11" gate="1" x="60.96" y="149.86"/> +<instance part="R1N5" gate="R" x="50.8" y="80.01" smashed="yes" rot="MR90"> +<attribute name="NAME" x="48.26" y="81.28" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="48.26" y="77.47" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="50.8" y="80.01" size="1.778" layer="96" rot="MR90" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="186.69" y1="102.87" x2="186.69" y2="106.68" width="0.1524" layer="91"/> +<wire x1="186.69" y1="106.68" x2="186.69" y2="107.95" width="0.1524" layer="91"/> +<wire x1="186.69" y1="106.68" x2="185.42" y2="106.68" width="0.1524" layer="91"/> +<wire x1="185.42" y1="106.68" x2="184.15" y2="106.68" width="0.1524" layer="91"/> +<wire x1="184.15" y1="106.68" x2="184.15" y2="107.95" width="0.1524" layer="91"/> +<wire x1="185.42" y1="106.68" x2="185.42" y2="107.95" width="0.1524" layer="91"/> +<wire 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pin="GND"/> +</segment> +<segment> +<wire x1="55.88" y1="76.2" x2="55.88" y2="72.39" width="0.1524" layer="91"/> +<pinref part="C8C3" gate="C" pin="2"/> +<pinref part="U$413" gate="G$1" pin="GND"/> +<pinref part="R1N5" gate="R" pin="1"/> +<wire x1="55.88" y1="72.39" x2="55.88" y2="69.85" width="0.1524" layer="91"/> +<wire x1="50.8" y1="74.93" x2="50.8" y2="72.39" width="0.1524" layer="91"/> +<wire x1="50.8" y1="72.39" x2="55.88" y2="72.39" width="0.1524" layer="91"/> +<junction x="55.88" y="72.39"/> +</segment> +<segment> +<wire x1="17.78" y1="83.82" x2="17.78" y2="73.66" width="0.1524" layer="91"/> +<wire x1="17.78" y1="73.66" x2="26.67" y2="73.66" width="0.1524" layer="91"/> +<wire x1="26.67" y1="73.66" x2="26.67" y2="81.28" width="0.1524" layer="91"/> +<junction x="26.67" y="73.66"/> +<pinref part="C1N1" gate="C" pin="2"/> +<pinref part="C2M14" gate="C" pin="C-"/> +<pinref part="U$416" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="49.53" y1="132.08" x2="49.53" y2="127" width="0.1524" layer="91"/> +<pinref part="C9C2" gate="C" pin="2"/> +<pinref part="U$418" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="69.85" y1="132.08" x2="69.85" y2="127" width="0.1524" layer="91"/> +<pinref part="C8C1" gate="C" pin="2"/> +<pinref part="U$419" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="80.01" y1="127" x2="80.01" y2="132.08" width="0.1524" layer="91"/> +<pinref part="U$420" gate="G$1" pin="GND"/> +<pinref part="C1N3" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="242.57" y1="153.67" x2="242.57" y2="147.32" width="0.1524" layer="91"/> +<wire x1="242.57" y1="147.32" x2="248.92" y2="147.32" width="0.1524" layer="91"/> +<wire x1="248.92" y1="147.32" x2="248.92" y2="153.67" width="0.1524" layer="91"/> +<wire x1="248.92" y1="147.32" x2="255.27" y2="147.32" width="0.1524" layer="91"/> +<wire x1="255.27" y1="147.32" x2="255.27" y2="153.67" width="0.1524" layer="91"/> +<wire x1="255.27" y1="147.32" x2="255.27" y2="146.05" width="0.1524" layer="91"/> +<junction x="248.92" y="147.32"/> +<junction x="255.27" y="147.32"/> +<pinref part="C9B4" gate="C" pin="C-"/> +<pinref part="C9B3" gate="C" pin="C-"/> +<pinref part="C9B2" gate="C" pin="C-"/> +<pinref part="U$423" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="232.41" y1="156.21" x2="232.41" y2="147.32" width="0.1524" layer="91"/> +<wire x1="232.41" y1="147.32" x2="224.79" y2="147.32" width="0.1524" layer="91"/> +<wire x1="224.79" y1="147.32" x2="217.17" y2="147.32" width="0.1524" layer="91"/> +<wire x1="217.17" y1="147.32" x2="209.55" y2="147.32" width="0.1524" layer="91"/> +<wire x1="209.55" y1="147.32" x2="209.55" y2="156.21" width="0.1524" layer="91"/> +<wire x1="217.17" y1="156.21" x2="217.17" y2="147.32" width="0.1524" layer="91"/> +<wire x1="224.79" y1="156.21" x2="224.79" y2="147.32" width="0.1524" layer="91"/> +<wire x1="232.41" y1="147.32" x2="232.41" y2="146.05" width="0.1524" layer="91"/> +<junction x="217.17" y="147.32"/> +<junction x="224.79" y="147.32"/> +<junction x="232.41" y="147.32"/> +<pinref part="C9B1" gate="C" pin="2"/> +<pinref part="C9B5" gate="C" pin="2"/> +<pinref part="C8B1" gate="C" pin="2"/> +<pinref part="C9C1" gate="C" pin="2"/> +<pinref part="U$424" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="234.95" y1="29.21" x2="234.95" y2="26.67" width="0.1524" layer="91"/> +<pinref part="R8C1" gate="R" pin="2"/> +<pinref part="U$426" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="208.28" y1="93.98" x2="208.28" y2="92.71" width="0.1524" layer="91"/> +<pinref part="U$400" gate="G$1" pin="GND"/> +<pinref part="R1N1" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="105.41" y1="86.36" x2="107.95" y2="86.36" width="0.1524" layer="91"/> +<wire x1="107.95" y1="86.36" x2="107.95" y2="83.82" width="0.1524" layer="91"/> +<wire x1="107.95" y1="83.82" x2="107.95" y2="81.28" width="0.1524" layer="91"/> +<wire x1="105.41" y1="83.82" x2="107.95" y2="83.82" width="0.1524" layer="91"/> +<wire x1="105.41" y1="81.28" x2="107.95" y2="81.28" width="0.1524" layer="91"/> +<wire x1="107.95" y1="86.36" x2="127" y2="86.36" width="0.1524" layer="91"/> +<wire x1="127" y1="86.36" x2="134.62" y2="86.36" width="0.1524" layer="91"/> +<wire x1="127" y1="80.01" x2="127" y2="86.36" width="0.1524" layer="91"/> +<junction x="107.95" y="83.82"/> +<junction x="107.95" y="86.36"/> +<junction x="127" y="86.36"/> +<pinref part="U9C1" gate="ISL6532" pin="GND@1"/> +<pinref part="U9C1" gate="ISL6532" pin="GND@2"/> +<pinref part="U9C1" gate="ISL6532" pin="GND@3"/> +<pinref part="C8C2" gate="C" pin="2"/> +<pinref part="U$406" gate="G$1" pin="GND"/> +</segment> +</net> +<net name="N$368" class="0"> +<segment> +<wire x1="175.26" y1="110.49" x2="179.07" y2="110.49" width="0.1524" layer="91"/> +<wire x1="175.26" y1="110.49" x2="175.26" y2="96.52" width="0.1524" layer="91"/> +<wire x1="175.26" y1="96.52" x2="193.04" y2="96.52" width="0.1524" layer="91"/> +<wire x1="193.04" y1="96.52" x2="193.04" y2="110.49" width="0.1524" layer="91"/> +<wire x1="105.41" y1="90.17" x2="137.16" y2="90.17" width="0.1524" layer="91"/> +<wire x1="137.16" y1="90.17" x2="137.16" y2="110.49" width="0.1524" layer="91"/> +<wire x1="137.16" y1="110.49" x2="175.26" y2="110.49" width="0.1524" layer="91"/> +<junction x="175.26" y="110.49"/> +<pinref part="Q9C3" gate="Q" pin="G"/> +<pinref part="Q9C2" gate="Q" pin="G"/> +<pinref part="U9C1" gate="ISL6532" pin="LGATE"/> +</segment> +</net> +<net name="N$369" class="0"> +<segment> +<wire x1="175.26" y1="138.43" x2="179.07" y2="138.43" width="0.1524" layer="91"/> +<wire x1="175.26" y1="129.54" x2="175.26" y2="138.43" width="0.1524" layer="91"/> +<wire x1="194.31" y1="138.43" x2="193.04" y2="138.43" width="0.1524" layer="91"/> +<wire x1="193.04" y1="138.43" x2="193.04" y2="129.54" width="0.1524" layer="91"/> +<wire x1="193.04" y1="129.54" x2="175.26" y2="129.54" width="0.1524" layer="91"/> +<wire x1="124.46" y1="93.98" x2="133.35" y2="93.98" width="0.1524" layer="91"/> +<wire x1="133.35" y1="93.98" x2="133.35" y2="120.65" width="0.1524" layer="91"/> +<wire x1="133.35" y1="120.65" x2="175.26" y2="120.65" width="0.1524" layer="91"/> +<wire x1="175.26" y1="120.65" x2="175.26" y2="129.54" width="0.1524" layer="91"/> +<junction x="175.26" y="129.54"/> +<pinref part="Q9C1" gate="Q" pin="G"/> +<pinref part="Q9C4" gate="Q" pin="G"/> +<pinref part="R9C1" gate="R" pin="2"/> +</segment> +</net> +<net name="N$372" class="0"> +<segment> +<wire x1="114.3" y1="93.98" x2="105.41" y2="93.98" width="0.1524" layer="91"/> +<pinref part="R9C1" gate="R" pin="1"/> +<pinref part="U9C1" gate="ISL6532" pin="UGATE"/> +</segment> +</net> +<net name="V1P8-DDR" class="0"> +<segment> +<wire x1="228.6" y1="129.54" x2="228.6" y2="124.46" width="0.1524" layer="91"/> +<wire x1="228.6" y1="124.46" x2="228.6" y2="86.36" width="0.1524" layer="91"/> +<wire x1="228.6" y1="86.36" x2="228.6" y2="80.01" width="0.1524" layer="91"/> +<wire x1="228.6" y1="124.46" x2="224.79" y2="124.46" width="0.1524" layer="91"/> +<wire x1="181.61" y1="86.36" x2="228.6" y2="86.36" width="0.1524" layer="91"/> +<junction x="228.6" y="124.46"/> +<junction x="228.6" y="86.36"/> +<pinref part="C8C4" gate="C" pin="1"/> +<pinref part="U$401" gate="V1P8-DDR" pin="V1P8-DDR"/> +<pinref part="R1N3" gate="R" pin="1"/> +<pinref part="L9C1" gate="L" pin="2"/> +<wire x1="241.3" y1="86.36" x2="241.3" y2="80.01" width="0.1524" layer="91"/> +<pinref part="R1N4" gate="R" pin="1"/> +<wire x1="241.3" y1="86.36" x2="228.6" y2="86.36" width="0.1524" layer="91"/> +</segment> +<segment> +<wire x1="69.85" y1="105.41" x2="67.31" y2="105.41" width="0.1524" layer="91"/> +<wire x1="67.31" y1="105.41" x2="67.31" y2="107.95" width="0.1524" layer="91"/> +<wire x1="67.31" y1="107.95" x2="67.31" y2="111.76" width="0.1524" layer="91"/> +<wire x1="67.31" y1="107.95" x2="69.85" y2="107.95" width="0.1524" layer="91"/> +<junction x="67.31" y="107.95"/> +<pinref part="U9C1" gate="ISL6532" pin="VDDQ@2"/> +<pinref part="U$412" gate="V1P8-DDR" pin="V1P8-DDR"/> +<pinref part="U9C1" gate="ISL6532" pin="VDDQ@1"/> +</segment> +<segment> +<wire x1="30.48" y1="123.19" x2="30.48" y2="114.3" width="0.1524" layer="91"/> +<wire x1="20.32" y1="116.84" x2="20.32" y2="123.19" width="0.1524" layer="91"/> +<wire x1="20.32" y1="123.19" x2="20.32" y2="127" width="0.1524" layer="91"/> +<wire x1="30.48" y1="123.19" x2="20.32" y2="123.19" width="0.1524" layer="91"/> +<junction x="20.32" y="123.19"/> +<pinref part="C9B6" gate="C" pin="1"/> +<pinref part="C2M13" gate="C" pin="C+"/> +<pinref part="U$414" gate="V1P8-DDR" pin="V1P8-DDR"/> +</segment> +<segment> +<wire x1="255.27" y1="161.29" x2="255.27" y2="168.91" width="0.1524" layer="91"/> +<wire x1="255.27" y1="168.91" x2="248.92" y2="168.91" width="0.1524" layer="91"/> +<wire x1="248.92" y1="168.91" x2="242.57" y2="168.91" width="0.1524" layer="91"/> +<wire x1="242.57" y1="168.91" x2="242.57" y2="171.45" width="0.1524" layer="91"/> +<wire x1="242.57" y1="168.91" x2="242.57" y2="161.29" width="0.1524" layer="91"/> +<wire x1="248.92" y1="168.91" x2="248.92" y2="161.29" width="0.1524" layer="91"/> +<junction x="242.57" y="168.91"/> +<junction x="248.92" y="168.91"/> +<pinref part="C9B2" gate="C" pin="C+"/> +<pinref part="C9B4" gate="C" pin="C+"/> +<pinref part="C9B3" gate="C" pin="C+"/> +<pinref part="U$422" gate="V1P8-DDR" pin="V1P8-DDR"/> +</segment> +<segment> +<wire x1="232.41" y1="163.83" x2="232.41" y2="168.91" width="0.1524" layer="91"/> +<wire x1="232.41" y1="168.91" x2="224.79" y2="168.91" width="0.1524" layer="91"/> +<wire x1="224.79" y1="168.91" x2="217.17" y2="168.91" width="0.1524" layer="91"/> +<wire x1="217.17" y1="168.91" x2="209.55" y2="168.91" width="0.1524" layer="91"/> +<wire x1="209.55" y1="168.91" x2="209.55" y2="163.83" width="0.1524" layer="91"/> +<wire x1="217.17" y1="163.83" x2="217.17" y2="168.91" width="0.1524" layer="91"/> +<wire x1="224.79" y1="163.83" x2="224.79" y2="168.91" width="0.1524" layer="91"/> +<wire x1="209.55" y1="168.91" x2="209.55" y2="171.45" width="0.1524" layer="91"/> +<junction x="209.55" y="168.91"/> +<junction x="217.17" y="168.91"/> +<junction x="224.79" y="168.91"/> +<pinref part="C9B1" gate="C" pin="1"/> +<pinref part="C9B5" gate="C" pin="1"/> +<pinref part="C8B1" gate="C" pin="1"/> +<pinref part="C9C1" gate="C" pin="1"/> +<pinref part="U$425" gate="V1P8-DDR" pin="V1P8-DDR"/> +</segment> +<segment> +<wire x1="166.37" y1="67.31" x2="180.34" y2="67.31" width="0.1524" layer="91"/> +<wire x1="180.34" y1="67.31" x2="180.34" y2="72.39" width="0.1524" layer="91"/> +<pinref part="R6L5" gate="R" pin="1"/> +<pinref part="U$571" gate="V1P8-DDR" pin="V1P8-DDR"/> +</segment> +</net> +<net name="N$374" class="0"> +<segment> +<wire x1="241.3" y1="69.85" x2="241.3" y2="67.31" width="0.1524" layer="91"/> +<wire x1="241.3" y1="67.31" x2="241.3" y2="64.77" width="0.1524" layer="91"/> +<wire x1="228.6" y1="69.85" x2="228.6" y2="67.31" width="0.1524" layer="91"/> +<wire x1="228.6" y1="67.31" x2="228.6" y2="64.77" width="0.1524" layer="91"/> +<wire x1="228.6" y1="67.31" x2="241.3" y2="67.31" width="0.1524" layer="91"/> +<junction x="228.6" y="67.31"/> +<junction x="241.3" y="67.31"/> +<pinref part="R1N4" gate="R" pin="2"/> +<pinref part="R9C3" gate="R" pin="1"/> +<pinref part="R1N3" gate="R" pin="2"/> +<pinref part="R9C2" gate="R" pin="1"/> +</segment> +</net> +<net name="N$375" class="0"> +<segment> +<pinref part="R9C3" gate="R" pin="2"/> +<pinref part="C9C6" gate="C" pin="1"/> +</segment> +</net> +<net name="N$376" class="0"> +<segment> +<wire x1="69.85" y1="81.28" x2="64.77" y2="81.28" width="0.1524" layer="91"/> +<wire x1="64.77" y1="81.28" x2="64.77" y2="31.75" width="0.1524" layer="91"/> +<wire x1="64.77" y1="31.75" x2="125.73" y2="31.75" width="0.1524" layer="91"/> +<wire x1="125.73" y1="35.56" x2="113.03" y2="35.56" width="0.1524" layer="91"/> +<wire x1="241.3" y1="41.91" x2="241.3" y2="46.99" width="0.1524" layer="91"/> +<wire x1="234.95" y1="41.91" x2="241.3" y2="41.91" width="0.1524" layer="91"/> +<wire x1="234.95" y1="39.37" x2="234.95" y2="41.91" width="0.1524" layer="91"/> +<wire x1="125.73" y1="41.91" x2="228.6" y2="41.91" width="0.1524" layer="91"/> +<wire x1="228.6" y1="41.91" x2="234.95" y2="41.91" width="0.1524" layer="91"/> +<wire x1="91.44" y1="41.91" x2="125.73" y2="41.91" width="0.1524" layer="91"/> +<wire x1="125.73" y1="41.91" x2="125.73" y2="35.56" width="0.1524" layer="91"/> +<wire x1="125.73" y1="31.75" x2="125.73" y2="35.56" width="0.1524" layer="91"/> +<wire x1="228.6" y1="54.61" x2="228.6" y2="41.91" width="0.1524" layer="91"/> +<junction x="234.95" y="41.91"/> +<junction x="125.73" y="41.91"/> +<junction x="125.73" y="35.56"/> +<junction x="228.6" y="41.91"/> +<pinref part="U9C1" gate="ISL6532" pin="FB"/> +<pinref part="R1N2" gate="R" pin="2"/> +<pinref part="C9C6" gate="C" pin="2"/> +<pinref part="R8C1" gate="R" pin="1"/> +<pinref part="R9C2" gate="R" pin="2"/> +<pinref part="C9C5" gate="C" pin="2"/> +</segment> +</net> +<net name="N$377" class="0"> +<segment> +<wire x1="102.87" y1="35.56" x2="88.9" y2="35.56" width="0.1524" layer="91"/> +<pinref part="C9C9" gate="C" pin="2"/> +<pinref part="R1N2" gate="R" pin="1"/> +</segment> +</net> +<net name="N$378" class="0"> +<segment> +<wire x1="81.28" y1="35.56" x2="71.12" y2="35.56" width="0.1524" layer="91"/> +<wire x1="71.12" y1="35.56" x2="71.12" y2="41.91" width="0.1524" layer="91"/> +<wire x1="71.12" y1="41.91" x2="83.82" y2="41.91" width="0.1524" layer="91"/> +<wire x1="71.12" y1="35.56" x2="68.58" y2="35.56" width="0.1524" layer="91"/> +<wire x1="68.58" y1="35.56" x2="68.58" y2="69.85" width="0.1524" layer="91"/> +<wire x1="68.58" y1="69.85" x2="69.85" y2="69.85" width="0.1524" layer="91"/> +<junction x="71.12" y="35.56"/> +<pinref part="C9C9" gate="C" pin="1"/> +<pinref part="C9C5" gate="C" pin="1"/> +<pinref part="U9C1" gate="ISL6532" pin="COMP"/> +</segment> +</net> +<net name="P1V8-PGOOD" class="0"> +<segment> +<wire x1="105.41" y1="67.31" x2="142.24" y2="67.31" width="0.1524" layer="91"/> +<wire x1="142.24" y1="53.34" x2="142.24" y2="67.31" width="0.1524" layer="91"/> +<pinref part="U9C1" gate="ISL6532" pin="PGOOD"/> +<wire x1="142.24" y1="53.34" x2="138.43" y2="53.34" width="0.1524" layer="91"/> +<label x="138.43" y="53.34" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="R6L5" gate="R" pin="2"/> +<wire x1="156.21" y1="67.31" x2="142.24" y2="67.31" width="0.1524" layer="91"/> +<junction x="142.24" y="67.31"/> +</segment> +</net> +<net name="N$379" class="0"> +<segment> +<wire x1="105.41" y1="71.12" x2="149.86" y2="71.12" width="0.1524" layer="91"/> +<wire x1="149.86" y1="71.12" x2="149.86" y2="86.36" width="0.1524" layer="91"/> +<wire x1="149.86" y1="86.36" x2="142.24" y2="86.36" width="0.1524" layer="91"/> +<wire x1="173.99" y1="86.36" x2="149.86" y2="86.36" width="0.1524" layer="91"/> +<junction x="149.86" y="86.36"/> +<pinref part="U9C1" gate="ISL6532" pin="VREF-OUT"/> +<pinref part="C8C2" gate="C" pin="1"/> +<pinref part="C8C4" gate="C" pin="2"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<wire x1="97.79" y1="163.83" x2="111.76" y2="163.83" width="0.1524" layer="91"/> +<pinref part="P+27" gate="1" pin="VCC"/> +<pinref part="R9D1" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="49.53" y1="139.7" x2="49.53" y2="143.51" width="0.1524" layer="91"/> +<wire x1="49.53" y1="143.51" x2="49.53" y2="144.78" width="0.1524" layer="91"/> +<wire x1="49.53" y1="144.78" x2="60.96" y2="144.78" width="0.1524" layer="91"/> +<wire x1="60.96" y1="144.78" x2="69.85" y2="144.78" width="0.1524" layer="91"/> +<wire x1="69.85" y1="144.78" x2="69.85" y2="143.51" width="0.1524" layer="91"/> +<wire x1="69.85" y1="143.51" x2="69.85" y2="139.7" width="0.1524" layer="91"/> +<wire x1="60.96" y1="144.78" x2="60.96" y2="147.32" width="0.1524" layer="91"/> +<junction x="60.96" y="144.78"/> +<pinref part="C9C2" gate="C" pin="1"/> +<pinref part="C8C1" gate="C" pin="1"/> +<pinref part="P+11" gate="1" pin="VCC"/> +</segment> +<segment> +<wire x1="105.41" y1="105.41" x2="106.68" y2="105.41" width="0.1524" layer="91"/> +<wire x1="106.68" y1="105.41" x2="106.68" y2="107.95" width="0.1524" layer="91"/> +<wire x1="106.68" y1="107.95" x2="105.41" y2="107.95" width="0.1524" layer="91"/> +<wire x1="106.68" y1="107.95" x2="106.68" y2="111.76" width="0.1524" layer="91"/> +<junction x="106.68" y="107.95"/> +<pinref part="U9C1" gate="ISL6532" pin="P5VSBY"/> +<pinref part="U9C1" gate="ISL6532" pin="5VSBY"/> +<pinref part="P+8" gate="1" pin="VCC"/> +</segment> +</net> +<net name="+12VPC" class="0"> +<segment> +<wire x1="97.79" y1="157.48" x2="97.79" y2="153.67" width="0.1524" layer="91"/> +<wire x1="97.79" y1="153.67" x2="97.79" y2="148.59" width="0.1524" layer="91"/> +<wire x1="104.14" y1="153.67" x2="97.79" y2="153.67" width="0.1524" layer="91"/> +<junction x="97.79" y="153.67"/> +<pinref part="U$408" gate="+12VPC" pin="+12VPC"/> +<pinref part="C1P1" gate="C" pin="1"/> +<pinref part="R1P1" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="105.41" y1="101.6" x2="111.76" y2="101.6" width="0.1524" layer="91"/> +<wire x1="111.76" y1="101.6" x2="111.76" y2="118.11" width="0.1524" layer="91"/> +<pinref part="U9C1" gate="ISL6532" pin="P12V"/> +<pinref part="U$410" gate="+12VPC" pin="+12VPC"/> +</segment> +<segment> +<wire x1="80.01" y1="147.32" x2="80.01" y2="139.7" width="0.1524" layer="91"/> +<pinref part="U$421" gate="+12VPC" pin="+12VPC"/> +<pinref part="C1N3" gate="C" pin="1"/> +</segment> +</net> +<net name="N$384" class="0"> +<segment> +<wire x1="69.85" y1="85.09" x2="55.88" y2="85.09" width="0.1524" layer="91"/> +<wire x1="55.88" y1="85.09" x2="55.88" y2="83.82" width="0.1524" layer="91"/> +<pinref part="U9C1" gate="ISL6532" pin="VREF-IN"/> +<pinref part="C8C3" gate="C" pin="1"/> +</segment> +</net> +<net name="DDR2-VTT" class="0"> +<segment> +<wire x1="20.32" y1="99.06" x2="26.67" y2="99.06" width="0.1524" layer="91"/> +<wire x1="26.67" y1="99.06" x2="30.48" y2="99.06" width="0.1524" layer="91"/> +<wire x1="30.48" y1="99.06" x2="67.31" y2="99.06" width="0.1524" layer="91"/> +<wire x1="69.85" y1="96.52" x2="67.31" y2="96.52" width="0.1524" layer="91"/> +<wire x1="67.31" y1="96.52" x2="67.31" y2="99.06" width="0.1524" layer="91"/> +<wire x1="67.31" y1="99.06" x2="67.31" y2="101.6" width="0.1524" layer="91"/> +<wire x1="67.31" y1="101.6" x2="69.85" y2="101.6" width="0.1524" layer="91"/> +<wire x1="67.31" y1="99.06" x2="69.85" y2="99.06" width="0.1524" layer="91"/> +<wire x1="20.32" y1="109.22" x2="20.32" y2="99.06" width="0.1524" layer="91"/> +<wire x1="30.48" y1="106.68" x2="30.48" y2="99.06" width="0.1524" layer="91"/> +<wire x1="26.67" y1="99.06" x2="26.67" y2="88.9" width="0.1524" layer="91"/> +<wire x1="12.7" y1="99.06" x2="12.7" y2="107.95" width="0.1524" layer="91"/> +<wire x1="20.32" y1="99.06" x2="17.78" y2="99.06" width="0.1524" layer="91"/> +<wire x1="17.78" y1="99.06" x2="12.7" y2="99.06" width="0.1524" layer="91"/> +<wire x1="17.78" y1="91.44" x2="17.78" y2="99.06" width="0.1524" layer="91"/> +<junction x="67.31" y="99.06"/> +<junction x="20.32" y="99.06"/> +<junction x="26.67" y="99.06"/> +<junction x="30.48" y="99.06"/> +<junction x="17.78" y="99.06"/> +<pinref part="U9C1" gate="ISL6532" pin="VTTSNS"/> +<pinref part="U9C1" gate="ISL6532" pin="VTT@1"/> +<pinref part="U9C1" gate="ISL6532" pin="VTT@2"/> +<pinref part="C9B6" gate="C" pin="2"/> +<pinref part="C1N1" gate="C" pin="1"/> +<pinref part="C2M14" gate="C" pin="C+"/> +<pinref part="C2M13" gate="C" pin="C-"/> +<pinref part="U$415" gate="DDR2-VTT" pin="DDR2-VTT"/> +</segment> +</net> +<net name="DDR2-NCH-5V" class="0"> +<segment> +<wire x1="203.2" y1="151.13" x2="203.2" y2="146.05" width="0.1524" layer="91"/> +<wire x1="201.93" y1="151.13" x2="203.2" y2="151.13" width="0.1524" layer="91"/> +<wire x1="201.93" y1="146.05" x2="201.93" y2="151.13" width="0.1524" layer="91"/> +<wire x1="200.66" y1="151.13" x2="201.93" y2="151.13" width="0.1524" layer="91"/> +<wire x1="200.66" y1="146.05" x2="200.66" y2="151.13" width="0.1524" layer="91"/> +<wire x1="199.39" y1="151.13" x2="200.66" y2="151.13" width="0.1524" layer="91"/> +<wire x1="199.39" y1="146.05" x2="199.39" y2="151.13" width="0.1524" layer="91"/> +<wire x1="187.96" y1="151.13" x2="199.39" y2="151.13" width="0.1524" layer="91"/> +<wire x1="187.96" y1="146.05" x2="187.96" y2="151.13" width="0.1524" layer="91"/> +<wire x1="186.69" y1="151.13" x2="187.96" y2="151.13" width="0.1524" layer="91"/> +<wire x1="186.69" y1="146.05" x2="186.69" y2="151.13" width="0.1524" layer="91"/> +<wire x1="184.15" y1="146.05" x2="184.15" y2="151.13" width="0.1524" layer="91"/> +<wire x1="184.15" y1="151.13" x2="185.42" y2="151.13" width="0.1524" layer="91"/> +<wire x1="185.42" y1="151.13" x2="186.69" y2="151.13" width="0.1524" layer="91"/> +<wire x1="185.42" y1="146.05" x2="185.42" y2="151.13" width="0.1524" layer="91"/> +<wire x1="184.15" y1="151.13" x2="184.15" y2="157.48" width="0.1524" layer="91"/> +<wire x1="184.15" y1="157.48" x2="184.15" y2="163.83" width="0.1524" layer="91"/> +<wire x1="129.54" y1="151.13" x2="134.62" y2="151.13" width="0.1524" layer="91"/> +<wire x1="134.62" y1="151.13" x2="139.7" y2="151.13" width="0.1524" layer="91"/> +<wire x1="139.7" y1="151.13" x2="144.78" y2="151.13" width="0.1524" layer="91"/> +<wire x1="144.78" y1="151.13" x2="149.86" y2="151.13" width="0.1524" layer="91"/> +<wire x1="149.86" y1="151.13" x2="154.94" y2="151.13" width="0.1524" layer="91"/> +<wire x1="154.94" y1="151.13" x2="160.02" y2="151.13" width="0.1524" layer="91"/> +<wire x1="160.02" y1="142.24" x2="160.02" y2="151.13" width="0.1524" layer="91"/> +<wire x1="154.94" y1="142.24" x2="154.94" y2="151.13" width="0.1524" layer="91"/> +<wire x1="149.86" y1="142.24" x2="149.86" y2="151.13" width="0.1524" layer="91"/> +<wire x1="144.78" y1="142.24" x2="144.78" y2="151.13" width="0.1524" layer="91"/> +<wire x1="139.7" y1="139.7" x2="139.7" y2="151.13" width="0.1524" layer="91"/> +<wire x1="134.62" y1="139.7" x2="134.62" y2="151.13" width="0.1524" layer="91"/> +<wire x1="129.54" y1="139.7" x2="129.54" y2="151.13" width="0.1524" layer="91"/> +<wire x1="184.15" y1="151.13" x2="160.02" y2="151.13" width="0.1524" layer="91"/> +<wire x1="171.45" y1="163.83" x2="184.15" y2="163.83" width="0.1524" layer="91"/> +<junction x="201.93" y="151.13"/> +<junction x="200.66" y="151.13"/> +<junction x="199.39" y="151.13"/> +<junction x="187.96" y="151.13"/> +<junction x="186.69" y="151.13"/> +<junction x="185.42" y="151.13"/> +<junction x="134.62" y="151.13"/> +<junction x="139.7" y="151.13"/> +<junction x="144.78" y="151.13"/> +<junction x="149.86" y="151.13"/> +<junction x="154.94" y="151.13"/> +<junction x="160.02" y="151.13"/> +<junction x="184.15" y="151.13"/> +<label x="163.5125" y="151.765" size="1.778" layer="92"/> +<pinref part="Q9C4" gate="Q" pin="D@4"/> +<pinref part="Q9C4" gate="Q" pin="D@3"/> +<pinref part="Q9C4" gate="Q" pin="D@2"/> +<pinref part="Q9C4" gate="Q" pin="D@1"/> +<pinref part="Q9C1" gate="Q" pin="D@4"/> +<pinref part="Q9C1" gate="Q" pin="D@3"/> +<pinref part="Q9C1" gate="Q" pin="D@1"/> +<pinref part="Q9C1" gate="Q" pin="D@2"/> +<pinref part="C9C7" gate="C" pin="1"/> +<pinref part="C9C4" gate="C" pin="1"/> +<pinref part="C9C3" gate="C" pin="1"/> +<pinref part="C9C8" gate="C" pin="1"/> +<pinref part="C9C10" gate="C" pin="C+"/> +<pinref part="C9C12" gate="C" pin="C+"/> +<pinref part="C9C11" gate="C" pin="C+"/> +<pinref part="L9D1" gate="L" pin="2"/> +</segment> +</net> +<net name="N$7" class="0"> +<segment> +<wire x1="208.28" y1="115.57" x2="208.28" y2="104.14" width="0.1524" layer="91"/> +<pinref part="R1N1" gate="R" pin="1"/> +<pinref part="C1N2" gate="C" pin="1"/> +</segment> +</net> +<net name="DDR2-NODE" class="0"> +<segment> +<wire x1="184.15" y1="118.11" x2="184.15" y2="124.46" width="0.1524" layer="91"/> +<wire x1="184.15" y1="124.46" x2="185.42" y2="124.46" width="0.1524" layer="91"/> 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x1="186.69" y1="132.08" x2="185.42" y2="132.08" width="0.1524" layer="91"/> +<wire x1="186.69" y1="132.08" x2="199.39" y2="132.08" width="0.1524" layer="91"/> +<wire x1="186.69" y1="132.08" x2="186.69" y2="135.89" width="0.1524" layer="91"/> +<wire x1="201.93" y1="124.46" x2="201.93" y2="132.08" width="0.1524" layer="91"/> +<wire x1="208.28" y1="123.19" x2="208.28" y2="124.46" width="0.1524" layer="91"/> +<junction x="185.42" y="124.46"/> +<junction x="186.69" y="124.46"/> +<junction x="187.96" y="124.46"/> +<junction x="198.12" y="124.46"/> +<junction x="199.39" y="124.46"/> +<junction x="200.66" y="124.46"/> +<junction x="200.66" y="132.08"/> +<junction x="199.39" y="132.08"/> +<junction x="185.42" y="132.08"/> +<junction x="186.69" y="132.08"/> +<junction x="201.93" y="124.46"/> +<junction x="201.93" y="132.08"/> +<junction x="208.28" y="124.46"/> +<pinref part="Q9C2" gate="Q" pin="D@4"/> +<pinref part="Q9C3" gate="Q" pin="D@1"/> +<pinref part="Q9C3" gate="Q" pin="D@2"/> +<pinref part="Q9C3" gate="Q" pin="D@3"/> +<pinref part="Q9C3" gate="Q" pin="D@4"/> +<pinref part="Q9C2" gate="Q" pin="D@1"/> +<pinref part="Q9C2" gate="Q" pin="D@2"/> +<pinref part="Q9C2" gate="Q" pin="D@3"/> +<pinref part="L9C1" gate="L" pin="1"/> +<pinref part="Q9C4" gate="Q" pin="S@1"/> +<pinref part="Q9C4" gate="Q" pin="S@2"/> +<pinref part="Q9C4" gate="Q" pin="S@3"/> +<pinref part="Q9C1" gate="Q" pin="S@2"/> +<pinref part="Q9C1" gate="Q" pin="S@1"/> +<pinref part="Q9C1" gate="Q" pin="S@3"/> +<pinref part="C1N2" gate="C" pin="2"/> +</segment> +</net> +<net name="DDR2-NCH-5V-R" class="0"> +<segment> +<wire x1="134.62" y1="163.83" x2="121.92" y2="163.83" width="0.1524" layer="91"/> +<pinref part="R9D1" gate="R" pin="2"/> +<pinref part="Q9D1" gate="T" pin="S"/> +</segment> +</net> +<net name="DDR2-NCH-5V-L" class="0"> +<segment> +<wire x1="144.78" y1="163.83" x2="160.02" y2="163.83" width="0.1524" layer="91"/> +<pinref part="L9D1" gate="L" pin="1"/> +<pinref part="Q9D1" gate="T" pin="D"/> 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x="138.43" y="170.18"/> +<junction x="146.05" y="170.18"/> +<junction x="153.67" y="170.18"/> +<junction x="161.29" y="170.18"/> +<junction x="168.91" y="170.18"/> +<junction x="176.53" y="170.18"/> +<junction x="184.15" y="170.18"/> +<junction x="191.77" y="170.18"/> +<junction x="199.39" y="170.18"/> +<junction x="207.01" y="170.18"/> +<junction x="214.63" y="170.18"/> +<junction x="222.25" y="170.18"/> +<junction x="229.87" y="170.18"/> +<junction x="237.49" y="170.18"/> +<junction x="245.11" y="170.18"/> +<junction x="252.73" y="170.18"/> +<pinref part="C4P21" gate="C" pin="C+"/> +<pinref part="C4P1" gate="C" pin="C+"/> +<pinref part="C5P4" gate="C" pin="C+"/> +<pinref part="C4P2" gate="C" pin="C+"/> +<pinref part="C4P6" gate="C" pin="1"/> +<pinref part="C5P13" gate="C" pin="1"/> +<pinref part="C5P21" gate="C" pin="1"/> +<pinref part="C5P10" gate="C" pin="1"/> +<pinref part="C5P15" gate="C" pin="1"/> +<pinref part="C5P12" gate="C" pin="1"/> +<pinref part="C5P14" gate="C" pin="1"/> +<pinref part="C4T1" gate="C" pin="1"/> +<pinref part="C4T2" gate="C" pin="1"/> +<pinref part="C5P1" gate="C" pin="1"/> +<pinref part="C5P2" gate="C" pin="1"/> +<pinref part="C5P11" gate="C" pin="1"/> +<pinref part="C5P22" gate="C" pin="1"/> +<pinref part="C5P18" gate="C" pin="1"/> +<pinref part="C4P7" gate="C" pin="1"/> +<wire x1="123.19" y1="170.18" x2="93.98" y2="170.18" width="0.1524" layer="91"/> +<junction x="123.19" y="170.18"/> +<junction x="93.98" y="170.18"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="99.06" y="125.73" size="3.81" layer="94">More Power Decoupling</text> +</plain> +<instances> +<instance part="FRAME11" gate="G$1" x="0" y="0"/> +<instance part="FRAME11" gate="G$2" x="180.34" y="0"/> +<instance part="C5U1" gate="C" x="116.84" y="90.17" smashed="yes" rot="R180"> +<attribute name="NAME" x="117.1575" y="92.3925" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="117.1575" y="89.8525" size="1.778" layer="96" rot="R270"/> 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x="101.9175" y="89.8525" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="101.6" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="101.6" y="90.17" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7F2" gate="C" x="135.89" y="91.44" smashed="yes" rot="R180"> +<attribute name="NAME" x="136.2075" y="93.6625" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="136.2075" y="91.1225" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="135.89" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="135.89" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="135.89" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7F3" gate="C" x="143.51" y="91.44" smashed="yes" rot="R180"> +<attribute name="NAME" x="143.8275" y="93.6625" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="143.8275" y="91.1225" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="143.51" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="143.51" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="143.51" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7E3" gate="C" x="195.58" y="91.44" smashed="yes" rot="R180"> +<attribute name="NAME" x="195.8975" y="93.6625" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="195.8975" y="91.1225" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="195.58" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="195.58" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="195.58" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7E4" gate="C" x="187.96" y="91.44" smashed="yes" rot="R180"> +<attribute name="NAME" x="188.2775" y="93.6625" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="188.2775" y="91.1225" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="187.96" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="187.96" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="187.96" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7F1" gate="C" x="128.27" y="91.44" smashed="yes" rot="R180"> +<attribute name="NAME" x="128.5875" y="93.6625" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="128.5875" y="91.1225" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="128.27" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="128.27" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="128.27" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7E5" gate="C" x="180.34" y="91.44" smashed="yes" rot="R180"> +<attribute name="NAME" x="180.6575" y="93.6625" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="180.6575" y="91.1225" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="180.34" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="180.34" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="180.34" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7E6" gate="C" x="172.72" y="91.44" smashed="yes" rot="R180"> +<attribute name="NAME" x="173.0375" y="93.6625" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="173.0375" y="91.1225" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="172.72" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="172.72" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="172.72" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$385" gate="G$1" x="101.6" y="74.93"/> +<instance part="U$452" gate="G$1" x="128.27" y="77.47"/> +<instance part="U$456" gate="G$1" x="172.72" y="77.47"/> +<instance part="U$78" gate="G$1" x="135.89" y="109.22"/> +<instance part="P+17" gate="1" x="101.6" y="106.68"/> +<instance part="C2P1" gate="C" x="74.93" y="90.17" rot="R180"> +<attribute name="VOLTAGE" x="74.93" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="74.93" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="74.93" y="90.17" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2P2" gate="C" x="68.58" y="90.17" rot="R180"> +<attribute name="VOLTAGE" x="68.58" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="68.58" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="68.58" y="90.17" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7D4" gate="C" x="62.23" y="90.17" rot="R180"> +<attribute name="VOLTAGE" x="62.23" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="62.23" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="62.23" y="90.17" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7D3" gate="C" x="55.88" y="90.17" rot="R180"> +<attribute name="VOLTAGE" x="55.88" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="55.88" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="55.88" y="90.17" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7D2" gate="C" x="49.53" y="90.17" rot="R180"> +<attribute name="VOLTAGE" x="49.53" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="49.53" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="49.53" y="90.17" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7D1" gate="C" x="43.18" y="90.17" rot="R180"> +<attribute name="VOLTAGE" x="43.18" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="43.18" y="90.17" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="43.18" y="90.17" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$76" gate="G$1" x="74.93" y="76.2" rot="MR0"/> +<instance part="U$18" gate="G$1" x="36.83" y="105.41"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="101.6" y1="76.2" x2="101.6" y2="78.74" width="0.1524" layer="91"/> +<wire x1="101.6" y1="78.74" x2="109.22" y2="78.74" width="0.1524" layer="91"/> +<wire x1="109.22" y1="78.74" x2="116.84" y2="78.74" width="0.1524" layer="91"/> +<wire x1="116.84" y1="78.74" x2="116.84" y2="87.63" width="0.1524" layer="91"/> +<wire x1="109.22" y1="87.63" x2="109.22" y2="78.74" width="0.1524" layer="91"/> +<wire x1="101.6" y1="87.63" x2="101.6" y2="78.74" width="0.1524" layer="91"/> +<junction x="109.22" y="78.74"/> +<junction x="101.6" y="78.74"/> +<pinref part="C5U1" gate="C" pin="2"/> +<pinref part="C5U2" gate="C" pin="2"/> +<pinref part="C5T6" gate="C" pin="2"/> +<pinref part="U$385" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="128.27" y1="88.9" x2="128.27" y2="80.01" width="0.1524" layer="91"/> +<wire x1="128.27" y1="80.01" x2="135.89" y2="80.01" width="0.1524" layer="91"/> +<wire x1="135.89" y1="80.01" x2="143.51" y2="80.01" width="0.1524" layer="91"/> +<wire x1="143.51" y1="80.01" x2="143.51" y2="88.9" width="0.1524" layer="91"/> +<wire x1="135.89" y1="80.01" x2="135.89" y2="88.9" width="0.1524" layer="91"/> +<wire x1="128.27" y1="78.74" x2="128.27" y2="80.01" width="0.1524" layer="91"/> +<junction x="135.89" y="80.01"/> +<junction x="128.27" y="80.01"/> +<pinref part="C7F1" gate="C" pin="2"/> +<pinref part="C7F3" gate="C" pin="2"/> +<pinref part="C7F2" gate="C" pin="2"/> +<pinref part="U$452" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="172.72" y1="88.9" x2="172.72" y2="80.01" width="0.1524" layer="91"/> +<wire x1="172.72" y1="80.01" x2="180.34" y2="80.01" width="0.1524" layer="91"/> +<wire x1="180.34" y1="80.01" x2="187.96" y2="80.01" width="0.1524" layer="91"/> +<wire x1="187.96" y1="80.01" x2="195.58" y2="80.01" width="0.1524" layer="91"/> +<wire x1="195.58" y1="80.01" x2="195.58" y2="88.9" width="0.1524" layer="91"/> +<wire x1="187.96" y1="88.9" x2="187.96" y2="80.01" width="0.1524" layer="91"/> +<wire x1="180.34" y1="88.9" x2="180.34" y2="80.01" width="0.1524" layer="91"/> +<wire x1="172.72" y1="78.74" x2="172.72" y2="80.01" width="0.1524" layer="91"/> +<junction x="187.96" y="80.01"/> +<junction x="180.34" y="80.01"/> +<junction x="172.72" y="80.01"/> +<pinref part="C7E6" gate="C" pin="2"/> +<pinref part="C7E3" gate="C" pin="2"/> +<pinref part="C7E4" gate="C" pin="2"/> +<pinref part="C7E5" gate="C" pin="2"/> +<pinref part="U$456" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="43.18" y1="87.63" x2="43.18" y2="78.74" width="0.1524" layer="91"/> +<wire x1="43.18" y1="78.74" x2="49.53" y2="78.74" width="0.1524" layer="91"/> +<wire x1="49.53" y1="78.74" x2="55.88" y2="78.74" width="0.1524" layer="91"/> +<wire x1="55.88" y1="78.74" x2="62.23" y2="78.74" width="0.1524" layer="91"/> +<wire x1="62.23" y1="78.74" x2="68.58" y2="78.74" width="0.1524" layer="91"/> +<wire x1="68.58" y1="78.74" x2="74.93" y2="78.74" width="0.1524" layer="91"/> +<wire x1="74.93" y1="78.74" x2="74.93" y2="87.63" width="0.1524" layer="91"/> +<wire x1="68.58" y1="87.63" x2="68.58" y2="78.74" width="0.1524" layer="91"/> +<wire x1="62.23" y1="87.63" x2="62.23" y2="78.74" width="0.1524" layer="91"/> +<wire x1="55.88" y1="87.63" x2="55.88" y2="78.74" width="0.1524" layer="91"/> +<wire x1="49.53" y1="87.63" x2="49.53" y2="78.74" width="0.1524" layer="91"/> +<wire x1="74.93" y1="77.47" x2="74.93" y2="78.74" width="0.1524" layer="91"/> +<junction x="74.93" y="78.74"/> +<junction x="68.58" y="78.74"/> +<junction x="62.23" y="78.74"/> +<junction x="55.88" y="78.74"/> +<junction x="49.53" y="78.74"/> +<pinref part="C7D1" gate="C" pin="2"/> +<pinref part="C2P1" gate="C" pin="2"/> +<pinref part="C2P2" gate="C" pin="2"/> +<pinref part="C7D4" gate="C" pin="2"/> +<pinref part="C7D3" gate="C" pin="2"/> +<pinref part="C7D2" gate="C" pin="2"/> +<pinref part="U$76" gate="G$1" pin="GND"/> +</segment> +</net> +<net name="V2P5" class="0"> +<segment> +<wire x1="128.27" y1="96.52" x2="128.27" y2="102.87" width="0.1524" layer="91"/> +<wire x1="128.27" y1="102.87" x2="135.89" y2="102.87" width="0.1524" layer="91"/> +<wire x1="135.89" y1="102.87" x2="143.51" y2="102.87" width="0.1524" layer="91"/> +<wire x1="143.51" y1="102.87" x2="143.51" y2="96.52" width="0.1524" layer="91"/> +<wire x1="135.89" y1="96.52" x2="135.89" y2="102.87" width="0.1524" layer="91"/> +<wire x1="135.89" y1="102.87" x2="135.89" y2="107.95" width="0.1524" layer="91"/> +<junction x="135.89" y="102.87"/> +<pinref part="C7F1" gate="C" pin="1"/> +<pinref part="C7F3" gate="C" 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size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="43.18" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="43.18" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="43.18" y="129.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C5P19" gate="C" x="43.18" y="156.21" smashed="yes" rot="R180"> +<attribute name="NAME" x="41.91" y="148.59" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="42.164" y="159.004" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="43.18" y="156.21" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="43.18" y="156.21" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="43.18" y="156.21" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C5E4" gate="C" x="63.5" y="71.12" smashed="yes" rot="R180"> +<attribute name="NAME" x="62.23" y="63.5" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="62.23" y="73.66" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="63.5" y="71.12" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="63.5" y="71.12" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C5D5" gate="C" x="50.8" y="130.81" smashed="yes" rot="R180"> +<attribute name="NAME" x="49.53" y="124.46" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="49.53" y="133.35" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="50.8" y="130.81" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="50.8" y="130.81" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C5P23" gate="C" x="50.8" y="157.48" smashed="yes" rot="R180"> +<attribute name="NAME" x="49.53" y="149.86" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="49.784" y="160.274" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="50.8" y="157.48" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="50.8" y="157.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R5E14" gate="R" x="29.21" y="82.55" smashed="yes"> +<attribute name="NAME" x="32.8666" y="85.7906" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="28.574" y="78.9864" size="1.778" layer="96"/> +<attribute name="POWER" x="29.21" y="82.55" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R5D6" gate="R" x="19.05" y="143.51"> +<attribute name="POWER" x="19.05" y="143.51" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R5P8" gate="R" x="17.78" y="168.91"> +<attribute name="POWER" x="17.78" y="168.91" size="1.778" layer="96" display="off"/> +</instance> +<instance part="L5E3" gate="L" x="43.18" y="82.55" smashed="yes" rot="R180"> +<attribute name="NAME" x="39.37" y="83.82" size="1.778" layer="95"/> +<attribute name="VALUE" x="46.99" y="83.82" size="1.778" layer="96"/> +</instance> +<instance part="L5D2" gate="L" x="33.02" y="143.51" smashed="yes" rot="R180"> +<attribute name="NAME" x="27.94" y="144.145" size="1.778" layer="95"/> +<attribute name="VALUE" x="35.56" y="144.145" size="1.778" layer="96"/> +</instance> +<instance part="L5P1" gate="L" x="30.48" y="168.91" smashed="yes" rot="R180"> +<attribute name="NAME" x="25.4" y="169.545" size="1.778" layer="95"/> +<attribute name="VALUE" x="34.29" y="169.545" size="1.778" layer="96"/> +</instance> +<instance part="U$230" gate="G$1" x="48.26" y="62.23" rot="R270"/> +<instance part="U$233" gate="G$1" x="53.34" y="121.92" rot="R90"/> +<instance part="U$234" gate="G$1" x="53.34" y="147.32" rot="R90"/> +<instance part="U6E1" gate="PWR-GBE" x="222.25" y="27.94"/> +<instance part="U6E1" gate="PWR-MIS" x="129.54" y="128.27" rot="R90"/> +<instance part="U6E1" gate="PWR-PCI" x="73.66" y="104.14" rot="R90"/> +<instance part="U6E1" gate="PWR-SATA" x="255.27" y="132.08" rot="R90"/> +<instance part="U6E1" gate="PWR-USB" x="191.77" y="130.81" rot="R90"/> +<instance part="U$527" gate="G$1" x="186.69" y="52.07"/> +<instance part="C8V10" gate="C" x="107.95" y="38.1" smashed="yes" rot="R180"> +<attribute name="NAME" x="108.585" y="40.64" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="108.585" y="38.1" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="107.95" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="107.95" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="107.95" y="38.1" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$501" gate="G$1" x="101.6" y="22.86"/> +<instance part="C8V9" gate="C" x="101.6" y="38.1" smashed="yes" rot="R180"> +<attribute name="NAME" x="102.235" y="40.64" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="102.235" y="38.1" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="101.6" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="101.6" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="101.6" y="38.1" size="1.778" layer="96" display="off"/> +</instance> +<instance part="XB1H1" gate="G$1" x="62.23" y="35.56" smashed="yes"> +<attribute name="NAME" x="67.31" y="38.1" size="1.778" layer="95"/> +<attribute name="VALUE" x="64.77" y="33.02" size="1.778" layer="96"/> +</instance> +<instance part="U$17" gate="AGND" x="154.94" y="140.97"/> +<instance part="U$21" gate="AGND" x="97.79" y="107.95"/> +<instance part="U$135" gate="PW-VCC3" x="78.74" y="57.15"/> +<instance part="U$82" gate="G$1" x="218.44" y="43.18"/> +<instance part="U$252" gate="PW-VCC3" x="191.77" y="44.45"/> +<instance part="U$145" gate="PW-V1P2" x="109.22" y="121.92"/> +<instance part="U$27" gate="PW-V1P2" x="201.93" y="121.92"/> +<instance part="U$174" gate="PW-V1P2" x="201.93" y="137.16"/> +<instance part="U$223" gate="PW-V1P2" x="201.93" y="165.1"/> +<instance part="U$224" gate="PW-V1P2" x="83.82" y="148.59"/> +<instance part="U$225" gate="PW-V1P2" x="86.36" y="114.3"/> +<instance part="U$237" gate="PW-V1P2" x="152.4" y="127"/> +<instance part="U$198" gate="PW-V1P2" x="207.01" y="101.6"/> +<instance part="U$199" gate="PW-V1P2" x="16.51" y="119.38"/> +<instance part="U$201" gate="PW-V1P2" x="10.16" y="175.26"/> +<instance part="U$203" gate="PW-V1P2" x="59.69" y="171.45"/> +<instance part="U$205" gate="PW-V1P2" x="168.91" y="128.27"/> +<instance part="U$219" gate="PW-V1P2" x="167.64" y="142.24"/> +<instance part="U$26" gate="V1P8-DDR" x="100.33" y="151.13"/> +<instance part="U$42" gate="PW-VCC3" x="16.51" y="88.9"/> +<instance part="U$47" gate="PW-VCC3" x="143.51" y="167.64"/> +<instance part="U$49" gate="PW-VCC3" x="201.93" y="151.13"/> +<instance part="U$50" gate="PW-VCC3" x="207.01" y="93.98"/> +<instance part="U$67" gate="PW-VCC3" x="100.33" y="142.24"/> +<instance part="SW3" gate="PB" x="127" y="20.32" smashed="yes" rot="R180"> +<attribute name="NAME" x="121.92" y="24.384" size="1.778" layer="95" rot="R180"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="146.05" y1="8.89" x2="149.86" y2="8.89" width="0.1524" layer="91"/> +<wire x1="149.86" y1="8.89" x2="149.86" y2="19.05" width="0.1524" layer="91"/> +<wire x1="149.86" y1="8.89" x2="149.86" y2="7.62" width="0.1524" layer="91"/> +<junction x="149.86" y="8.89"/> +<pinref part="R7W8" gate="R" pin="2"/> +<pinref part="C7W1" gate="C" pin="2"/> +<pinref part="U$282" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="62.23" y1="33.02" x2="62.23" y2="30.48" width="0.1524" layer="91"/> +<pinref part="U$288" gate="G$1" pin="GND"/> +<pinref part="XB1H1" gate="G$1" pin="M"/> +</segment> +<segment> +<wire x1="219.71" y1="62.23" x2="219.71" y2="53.34" width="0.1524" layer="91"/> +<wire x1="219.71" y1="53.34" x2="227.33" y2="53.34" width="0.1524" layer="91"/> +<wire x1="227.33" y1="53.34" x2="228.6" y2="53.34" width="0.1524" layer="91"/> +<wire x1="228.6" y1="53.34" x2="228.6" y2="62.23" width="0.1524" layer="91"/> +<wire x1="228.6" y1="53.34" x2="238.76" y2="53.34" width="0.1524" layer="91"/> +<junction x="228.6" y="53.34"/> +<pinref part="C5T8" gate="C" pin="2"/> +<pinref part="C5T11" gate="C" pin="2"/> +<pinref part="U$458" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="162.56" y1="153.67" x2="153.67" y2="153.67" width="0.1524" layer="91"/> +<wire x1="153.67" y1="153.67" x2="153.67" y2="148.59" width="0.1524" layer="91"/> +<wire x1="153.67" y1="148.59" x2="162.56" y2="148.59" width="0.1524" layer="91"/> +<wire x1="153.67" y1="153.67" x2="152.4" y2="153.67" width="0.1524" layer="91"/> +<junction x="153.67" y="153.67"/> +<pinref part="C4E3" gate="C" pin="2"/> +<pinref part="C5E5" gate="C" pin="2"/> +<pinref part="U$207" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="167.64" y1="92.71" x2="167.64" y2="85.09" width="0.1524" layer="91"/> +<wire x1="167.64" y1="85.09" x2="172.72" y2="85.09" width="0.1524" layer="91"/> +<wire x1="172.72" y1="85.09" x2="172.72" y2="92.71" width="0.1524" layer="91"/> +<wire x1="167.64" y1="83.82" x2="167.64" y2="85.09" width="0.1524" layer="91"/> +<junction x="167.64" y="85.09"/> +<pinref part="C5E12" gate="C" pin="2"/> +<pinref part="C5E6" gate="C" pin="2"/> +<pinref part="U$208" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="224.79" y1="109.22" x2="217.17" y2="109.22" width="0.1524" layer="91"/> +<wire x1="217.17" y1="109.22" x2="217.17" y2="102.87" width="0.1524" layer="91"/> +<wire x1="217.17" y1="102.87" x2="224.79" y2="102.87" width="0.1524" layer="91"/> +<wire x1="214.63" y1="109.22" x2="217.17" y2="109.22" width="0.1524" layer="91"/> +<junction x="217.17" y="109.22"/> +<pinref part="C5D8" gate="C" pin="2"/> +<pinref part="C5E2" gate="C" pin="2"/> +<pinref part="U$209" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="228.6" y1="121.92" x2="228.6" y2="118.11" width="0.1524" layer="91"/> +<wire x1="228.6" y1="118.11" x2="236.22" y2="118.11" width="0.1524" layer="91"/> +<wire x1="236.22" y1="118.11" x2="236.22" y2="121.92" width="0.1524" layer="91"/> +<wire x1="236.22" y1="118.11" x2="237.49" y2="118.11" width="0.1524" layer="91"/> +<junction x="236.22" y="118.11"/> +<pinref part="C5E13" gate="C" pin="2"/> +<pinref part="C5E7" gate="C" pin="2"/> +<pinref part="U$210" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="228.6" y1="137.16" x2="228.6" y2="135.89" width="0.1524" layer="91"/> +<wire x1="228.6" y1="135.89" x2="236.22" y2="135.89" width="0.1524" layer="91"/> +<wire x1="236.22" y1="135.89" x2="236.22" y2="137.16" width="0.1524" layer="91"/> +<wire x1="236.22" y1="135.89" x2="237.49" y2="135.89" width="0.1524" layer="91"/> +<junction x="236.22" y="135.89"/> +<pinref part="C5R2" gate="C" pin="2"/> +<pinref part="C5R6" gate="C" pin="2"/> +<pinref part="U$211" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="237.49" y1="149.86" x2="236.22" y2="149.86" width="0.1524" layer="91"/> +<wire x1="236.22" y1="149.86" x2="228.6" y2="149.86" width="0.1524" layer="91"/> +<wire x1="236.22" y1="149.86" x2="236.22" y2="151.13" width="0.1524" layer="91"/> +<junction x="236.22" y="149.86"/> +<pinref part="C5E1" gate="C" pin="2"/> +<pinref part="C5E3" gate="C" pin="2"/> +<pinref part="U$212" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="93.98" y1="82.55" x2="93.98" y2="73.66" width="0.1524" layer="91"/> +<wire x1="93.98" y1="73.66" x2="101.6" y2="73.66" width="0.1524" layer="91"/> +<wire x1="101.6" y1="73.66" x2="109.22" y2="73.66" width="0.1524" layer="91"/> +<wire x1="109.22" y1="73.66" x2="109.22" y2="82.55" width="0.1524" layer="91"/> +<wire x1="101.6" y1="82.55" x2="101.6" y2="73.66" width="0.1524" layer="91"/> +<wire x1="93.98" y1="73.66" x2="93.98" y2="72.39" width="0.1524" layer="91"/> +<junction x="101.6" y="73.66"/> +<junction x="93.98" y="73.66"/> +<pinref part="C5P17" gate="C" pin="2"/> +<pinref part="C5P20" gate="C" pin="2"/> +<pinref part="C5P16" gate="C" pin="2"/> +<pinref part="U$218" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="146.05" y1="128.27" x2="146.05" y2="125.73" width="0.1524" layer="91"/> +<pinref part="R5D3" gate="R" pin="1"/> +<pinref part="U$221" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="33.02" y1="99.06" x2="33.02" y2="95.25" width="0.1524" layer="91"/> +<wire x1="33.02" y1="95.25" x2="40.64" y2="95.25" width="0.1524" layer="91"/> +<wire x1="40.64" y1="95.25" x2="48.26" y2="95.25" width="0.1524" layer="91"/> +<wire x1="48.26" y1="95.25" x2="55.88" y2="95.25" width="0.1524" layer="91"/> +<wire x1="55.88" y1="95.25" x2="55.88" y2="99.06" width="0.1524" layer="91"/> +<wire x1="48.26" y1="99.06" x2="48.26" y2="95.25" width="0.1524" layer="91"/> +<wire x1="40.64" y1="99.06" x2="40.64" y2="95.25" width="0.1524" layer="91"/> +<wire x1="33.02" y1="93.98" x2="33.02" y2="95.25" width="0.1524" layer="91"/> +<junction x="40.64" y="95.25"/> +<junction x="48.26" y="95.25"/> +<junction x="33.02" y="95.25"/> +<pinref part="C5P9" gate="C" pin="2"/> +<pinref part="C5P8" gate="C" pin="2"/> +<pinref part="C5P5" gate="C" pin="2"/> +<pinref part="C5P7" gate="C" pin="2"/> +<pinref part="U$228" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="63.5" y1="68.58" x2="63.5" y2="62.23" width="0.1524" layer="91"/> +<wire x1="63.5" y1="62.23" x2="55.88" y2="62.23" width="0.1524" layer="91"/> +<wire x1="55.88" y1="62.23" x2="55.88" y2="68.58" width="0.1524" layer="91"/> +<wire x1="55.88" y1="62.23" x2="49.53" y2="62.23" width="0.1524" layer="91"/> +<junction x="55.88" y="62.23"/> +<pinref part="C5E4" gate="C" pin="2"/> +<pinref part="C5E11" gate="C" pin="2"/> +<pinref part="U$230" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="43.18" y1="153.67" x2="43.18" y2="147.32" width="0.1524" layer="91"/> +<wire x1="43.18" y1="147.32" x2="50.8" y2="147.32" width="0.1524" layer="91"/> +<wire x1="50.8" y1="147.32" x2="50.8" y2="154.94" width="0.1524" layer="91"/> +<wire x1="50.8" y1="147.32" x2="52.07" y2="147.32" width="0.1524" layer="91"/> +<junction x="50.8" y="147.32"/> +<pinref part="C5P19" gate="C" pin="2"/> +<pinref part="C5P23" gate="C" pin="2"/> +<pinref part="U$234" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="50.8" y1="128.27" x2="50.8" y2="121.92" width="0.1524" layer="91"/> +<wire x1="50.8" y1="121.92" x2="43.18" y2="121.92" width="0.1524" layer="91"/> +<wire x1="43.18" y1="121.92" x2="43.18" y2="127" width="0.1524" layer="91"/> +<wire x1="50.8" y1="121.92" x2="52.07" y2="121.92" width="0.1524" layer="91"/> +<junction x="50.8" y="121.92"/> +<pinref part="C5D5" gate="C" pin="2"/> +<pinref part="C5D7" gate="C" pin="2"/> +<pinref part="U$233" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="193.04" y1="59.69" x2="193.04" y2="53.34" width="0.1524" layer="91"/> +<wire x1="193.04" y1="53.34" x2="200.66" y2="53.34" width="0.1524" layer="91"/> +<wire x1="200.66" y1="53.34" x2="200.66" y2="59.69" width="0.1524" layer="91"/> +<wire x1="193.04" y1="53.34" x2="189.23" y2="53.34" width="0.1524" layer="91"/> +<wire x1="189.23" y1="53.34" x2="186.69" y2="53.34" width="0.1524" layer="91"/> +<junction x="193.04" y="53.34"/> +<pinref part="C5T9" gate="C" pin="2"/> +<pinref part="C5T12" gate="C" pin="2"/> +<pinref part="U$527" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="101.6" y1="24.13" x2="101.6" y2="26.67" width="0.1524" layer="91"/> +<wire x1="101.6" y1="26.67" x2="101.6" y2="35.56" width="0.1524" layer="91"/> +<wire x1="101.6" y1="26.67" x2="107.95" y2="26.67" width="0.1524" layer="91"/> +<wire x1="107.95" y1="26.67" x2="107.95" y2="35.56" width="0.1524" layer="91"/> +<junction x="101.6" y="26.67"/> +<pinref part="U$501" gate="G$1" pin="GND"/> +<pinref part="C8V10" gate="C" pin="2"/> +<pinref part="C8V9" gate="C" pin="2"/> +</segment> +</net> +<net name="N$224" class="0"> +<segment> +<wire x1="60.96" y1="44.45" x2="60.96" y2="46.99" width="0.1524" layer="91"/> +<wire x1="60.96" y1="46.99" x2="63.5" y2="46.99" width="0.1524" layer="91"/> +<wire x1="63.5" y1="46.99" x2="63.5" y2="44.45" width="0.1524" layer="91"/> +<wire x1="63.5" y1="46.99" x2="67.31" y2="46.99" width="0.1524" layer="91"/> +<junction x="63.5" y="46.99"/> +<pinref part="R8V6" gate="R" pin="2"/> +<pinref part="XB1H1" gate="G$1" pin="P@1"/> +<pinref part="XB1H1" gate="G$1" pin="P@2"/> +</segment> +</net> +<net name="V-3P0-BAT-VREG" class="0"> +<segment> +<wire x1="95.25" y1="49.53" x2="101.6" y2="49.53" width="0.1524" layer="91"/> +<wire x1="101.6" y1="49.53" x2="106.68" y2="49.53" width="0.1524" layer="91"/> +<wire x1="106.68" y1="49.53" x2="107.95" y2="49.53" width="0.1524" layer="91"/> +<wire x1="107.95" y1="49.53" x2="115.57" y2="49.53" width="0.1524" layer="91"/> +<wire x1="115.57" y1="49.53" x2="138.43" y2="49.53" width="0.1524" layer="91"/> +<wire x1="138.43" y1="49.53" x2="138.43" y2="48.26" width="0.1524" layer="91"/> +<wire x1="138.43" y1="49.53" x2="143.51" y2="49.53" width="0.1524" layer="91"/> +<wire x1="101.6" y1="43.18" x2="101.6" y2="49.53" width="0.1524" layer="91"/> +<wire x1="107.95" y1="43.18" x2="107.95" y2="49.53" width="0.1524" layer="91"/> +<junction x="138.43" y="49.53"/> +<junction x="101.6" y="49.53"/> +<junction x="107.95" y="49.53"/> +<pinref part="CR8V1" gate="D" pin="K"/> +<pinref part="R7W11" gate="R" pin="1"/> +<pinref part="C8V10" gate="C" pin="1"/> +<pinref part="C8V9" gate="C" pin="1"/> +<label x="143.51" y="49.53" size="1.778" layer="92" xref="yes"/> +</segment> +<segment> +<wire x1="189.23" y1="76.2" x2="193.04" y2="76.2" width="0.1524" layer="91"/> +<wire x1="193.04" y1="67.31" x2="193.04" y2="76.2" width="0.1524" layer="91"/> +<wire x1="193.04" y1="76.2" x2="200.66" y2="76.2" width="0.1524" layer="91"/> +<wire x1="200.66" y1="67.31" x2="200.66" y2="76.2" width="0.1524" layer="91"/> +<wire x1="200.66" y1="76.2" x2="205.74" y2="76.2" width="0.1524" layer="91"/> +<junction x="200.66" y="76.2"/> +<junction x="193.04" y="76.2"/> +<pinref part="C5T9" gate="C" pin="1"/> +<pinref part="C5T12" gate="C" pin="1"/> +<pinref part="R5U1" gate="R" pin="1"/> +<label x="189.23" y="76.2" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$228" class="0"> +<segment> +<wire x1="127" y1="8.89" x2="129.54" y2="8.89" width="0.1524" layer="91"/> +<pinref part="R7W8" gate="R" pin="1"/> +<pinref part="SW3" gate="PB" pin="3"/> +<wire x1="129.54" y1="8.89" x2="135.89" y2="8.89" width="0.1524" layer="91"/> +<wire x1="124.46" y1="16.51" x2="124.46" y2="8.89" width="0.1524" layer="91"/> +<wire x1="124.46" y1="8.89" x2="127" y2="8.89" width="0.1524" layer="91"/> +<pinref part="SW3" gate="PB" pin="4"/> +<wire x1="129.54" y1="16.51" x2="129.54" y2="8.89" width="0.1524" layer="91"/> +<junction x="129.54" y="8.89"/> +</segment> +</net> +<net name="IMCH-RTCRST-N" class="0"> +<segment> +<wire x1="138.43" y1="38.1" x2="138.43" y2="35.56" width="0.1524" layer="91"/> +<wire x1="138.43" y1="35.56" x2="149.86" y2="35.56" width="0.1524" layer="91"/> +<wire x1="149.86" y1="35.56" x2="154.94" y2="35.56" width="0.1524" layer="91"/> +<wire x1="149.86" y1="26.67" x2="149.86" y2="35.56" width="0.1524" layer="91"/> +<junction x="149.86" y="35.56"/> +<pinref part="R7W11" gate="R" pin="2"/> +<pinref part="C7W1" gate="C" pin="1"/> +<label x="154.94" y="35.56" size="1.778" layer="92" xref="yes"/> +<pinref part="SW3" gate="PB" pin="1"/> +<wire x1="138.43" y1="35.56" x2="129.54" y2="35.56" width="0.1524" layer="91"/> +<wire x1="129.54" y1="35.56" x2="129.54" y2="31.75" width="0.1524" layer="91"/> +<junction x="138.43" y="35.56"/> +<pinref part="SW3" gate="PB" pin="2"/> +<wire x1="129.54" y1="35.56" x2="124.46" y2="35.56" width="0.1524" layer="91"/> +<wire x1="124.46" y1="35.56" x2="124.46" y2="31.75" width="0.1524" layer="91"/> +<junction x="129.54" y="35.56"/> +</segment> +</net> +<net name="V-3P0-BAT-VREG-R" class="0"> +<segment> +<wire x1="215.9" y1="76.2" x2="219.71" y2="76.2" width="0.1524" layer="91"/> +<wire x1="219.71" y1="76.2" x2="219.71" y2="69.85" width="0.1524" layer="91"/> +<wire x1="219.71" y1="76.2" x2="228.6" y2="76.2" width="0.1524" layer="91"/> +<wire x1="228.6" y1="76.2" x2="228.6" y2="69.85" width="0.1524" layer="91"/> +<wire x1="228.6" y1="76.2" x2="237.49" y2="76.2" width="0.1524" layer="91"/> +<junction x="219.71" y="76.2"/> +<junction x="228.6" y="76.2"/> +<pinref part="R5U1" gate="R" pin="2"/> +<pinref part="C5T8" gate="C" pin="1"/> +<pinref part="C5T11" gate="C" pin="1"/> +<label x="237.49" y="76.2" size="1.778" layer="92" xref="yes"/> +</segment> +<segment> +<wire x1="123.19" y1="157.48" x2="119.38" y2="157.48" width="0.1524" layer="91"/> +<wire x1="119.38" y1="157.48" x2="119.38" y2="163.83" width="0.1524" layer="91"/> +<wire x1="119.38" y1="163.83" x2="109.22" y2="163.83" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCPRTC"/> +<label x="109.22" y="163.83" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$153" class="0"> +<segment> +<wire x1="214.63" y1="132.08" x2="217.17" y2="132.08" width="0.1524" layer="91"/> +<pinref part="R5E15" gate="R" pin="2"/> +<pinref part="L5E4" gate="L" pin="1"/> +</segment> +</net> +<net name="N$157" class="0"> +<segment> +<wire x1="236.22" y1="129.54" x2="236.22" y2="132.08" width="0.1524" layer="91"/> +<wire x1="236.22" y1="132.08" x2="242.57" y2="132.08" width="0.1524" layer="91"/> +<wire x1="228.6" y1="132.08" x2="236.22" y2="132.08" width="0.1524" layer="91"/> +<wire x1="228.6" y1="129.54" x2="228.6" y2="132.08" width="0.1524" layer="91"/> +<wire x1="246.38" y1="132.08" x2="242.57" y2="132.08" width="0.1524" layer="91"/> +<wire x1="242.57" y1="132.08" x2="242.57" y2="129.54" width="0.1524" layer="91"/> +<wire x1="246.38" y1="129.54" x2="242.57" y2="129.54" width="0.1524" layer="91"/> +<wire x1="242.57" y1="129.54" x2="242.57" y2="127" width="0.1524" layer="91"/> +<wire x1="246.38" y1="127" x2="242.57" y2="127" width="0.1524" layer="91"/> +<junction x="242.57" y="129.54"/> +<junction x="242.57" y="132.08"/> +<junction x="228.6" y="132.08"/> +<junction x="236.22" y="132.08"/> +<pinref part="C5E7" gate="C" pin="1"/> +<pinref part="L5E4" gate="L" pin="2"/> +<pinref part="C5E13" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCARX@1"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCARX@2"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCARX@3"/> +</segment> +</net> +<net name="N$158" class="0"> +<segment> +<wire x1="214.63" y1="160.02" x2="215.9" y2="160.02" width="0.1524" layer="91"/> +<pinref part="R5D7" gate="R" pin="2"/> +<pinref part="L5E2" gate="L" pin="1"/> +</segment> +</net> +<net name="N$161" class="0"> +<segment> +<wire x1="227.33" y1="160.02" x2="228.6" y2="160.02" width="0.1524" layer="91"/> +<wire x1="228.6" y1="160.02" x2="236.22" y2="160.02" width="0.1524" layer="91"/> +<wire x1="236.22" y1="158.75" x2="236.22" y2="160.02" width="0.1524" layer="91"/> +<wire x1="236.22" y1="160.02" x2="240.03" y2="160.02" width="0.1524" layer="91"/> +<wire x1="240.03" y1="160.02" x2="246.38" y2="160.02" width="0.1524" layer="91"/> +<wire x1="240.03" y1="160.02" x2="240.03" y2="157.48" width="0.1524" layer="91"/> +<wire x1="240.03" y1="157.48" x2="240.03" y2="154.94" width="0.1524" layer="91"/> +<wire x1="240.03" y1="154.94" x2="246.38" y2="154.94" width="0.1524" layer="91"/> +<wire x1="246.38" y1="157.48" x2="240.03" y2="157.48" width="0.1524" layer="91"/> +<wire x1="228.6" y1="157.48" x2="228.6" y2="160.02" width="0.1524" layer="91"/> +<junction x="240.03" y="157.48"/> +<junction x="240.03" y="160.02"/> +<junction x="236.22" y="160.02"/> +<junction x="228.6" y="160.02"/> +<pinref part="L5E2" gate="L" pin="2"/> +<pinref part="C5E1" gate="C" pin="1"/> +<pinref part="C5E3" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCATX@1"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCATX@2"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCATX@3"/> +</segment> +</net> +<net name="N$154" class="0"> +<segment> +<wire x1="214.63" y1="146.05" x2="217.17" y2="146.05" width="0.1524" layer="91"/> +<pinref part="R5P11" gate="R" pin="2"/> +<pinref part="L5P2" gate="L" pin="1"/> +</segment> +</net> +<net name="N$163" class="0"> +<segment> +<wire x1="228.6" y1="146.05" x2="236.22" y2="146.05" width="0.1524" layer="91"/> +<wire x1="228.6" y1="144.78" x2="228.6" y2="146.05" width="0.1524" layer="91"/> +<wire x1="236.22" y1="144.78" x2="236.22" y2="146.05" width="0.1524" layer="91"/> +<wire x1="236.22" y1="146.05" x2="242.57" y2="146.05" width="0.1524" layer="91"/> +<wire x1="242.57" y1="146.05" x2="246.38" y2="146.05" width="0.1524" layer="91"/> +<junction x="228.6" y="146.05"/> +<junction x="236.22" y="146.05"/> +<pinref part="L5P2" gate="L" pin="2"/> +<pinref part="C5R2" gate="C" pin="1"/> +<pinref part="C5R6" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCASATABG3P3"/> +</segment> +</net> +<net name="N$164" class="0"> +<segment> +<wire x1="214.63" y1="114.3" x2="219.71" y2="114.3" width="0.1524" layer="91"/> +<pinref part="R5E2" gate="R" pin="2"/> +<pinref part="L5E1" gate="L" pin="1"/> +</segment> +</net> +<net name="N$166" class="0"> +<segment> +<wire x1="231.14" y1="114.3" x2="237.49" y2="114.3" width="0.1524" layer="91"/> +<wire x1="237.49" y1="114.3" x2="237.49" y2="109.22" width="0.1524" layer="91"/> +<wire x1="232.41" y1="102.87" x2="237.49" y2="102.87" width="0.1524" layer="91"/> +<wire x1="237.49" y1="102.87" x2="237.49" y2="109.22" width="0.1524" layer="91"/> +<wire x1="237.49" y1="109.22" x2="246.38" y2="109.22" width="0.1524" layer="91"/> +<wire x1="232.41" y1="109.22" x2="237.49" y2="109.22" width="0.1524" layer="91"/> +<junction x="237.49" y="109.22"/> +<pinref part="L5E1" gate="L" pin="2"/> +<pinref part="C5D8" gate="C" pin="1"/> +<pinref part="C5E2" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCAPLL"/> +</segment> +</net> +<net name="N$168" class="0"> +<segment> +<wire x1="153.67" y1="106.68" x2="156.21" y2="106.68" width="0.1524" layer="91"/> +<wire x1="153.67" y1="106.68" x2="152.4" y2="106.68" width="0.1524" layer="91"/> +<wire x1="152.4" y1="106.68" x2="152.4" y2="109.22" width="0.1524" layer="91"/> +<pinref part="L5E5" gate="L" pin="1"/> +<pinref part="R5E16" gate="R" pin="2"/> +</segment> +</net> +<net name="N$170" class="0"> +<segment> +<wire x1="167.64" y1="106.68" x2="172.72" y2="106.68" width="0.1524" layer="91"/> +<wire x1="167.64" y1="100.33" x2="167.64" y2="106.68" width="0.1524" layer="91"/> +<wire x1="172.72" y1="100.33" x2="172.72" y2="106.68" width="0.1524" layer="91"/> +<wire x1="172.72" y1="106.68" x2="179.07" y2="106.68" width="0.1524" layer="91"/> +<wire x1="179.07" y1="106.68" x2="182.88" y2="106.68" width="0.1524" layer="91"/> +<wire x1="182.88" y1="101.6" x2="179.07" y2="101.6" width="0.1524" layer="91"/> +<wire x1="179.07" y1="101.6" x2="179.07" y2="104.14" width="0.1524" layer="91"/> +<wire x1="179.07" y1="104.14" x2="179.07" y2="106.68" width="0.1524" layer="91"/> +<wire x1="179.07" y1="104.14" x2="182.88" y2="104.14" width="0.1524" layer="91"/> +<junction x="179.07" y="106.68"/> +<junction x="179.07" y="104.14"/> +<junction x="167.64" y="106.68"/> +<junction x="172.72" y="106.68"/> +<pinref part="L5E5" gate="L" pin="2"/> +<pinref part="C5E12" gate="C" pin="1"/> +<pinref part="C5E6" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCAUSB12@1"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCAUSB12@2"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCAUSB12@3"/> +</segment> +</net> +<net name="N$171" class="0"> +<segment> +<wire x1="158.75" y1="158.75" x2="156.21" y2="158.75" width="0.1524" layer="91"/> +<pinref part="R4E9" gate="R" pin="2"/> +<pinref part="L4E1" gate="L" pin="1"/> +</segment> +</net> +<net name="N$173" class="0"> +<segment> +<wire x1="170.18" y1="158.75" x2="177.8" y2="158.75" width="0.1524" layer="91"/> +<wire x1="170.18" y1="148.59" x2="177.8" y2="148.59" width="0.1524" layer="91"/> +<wire x1="177.8" y1="148.59" x2="177.8" y2="153.67" width="0.1524" layer="91"/> +<wire x1="177.8" y1="153.67" x2="177.8" y2="158.75" width="0.1524" layer="91"/> +<wire x1="170.18" y1="153.67" x2="177.8" y2="153.67" width="0.1524" layer="91"/> +<wire x1="182.88" y1="158.75" x2="177.8" y2="158.75" width="0.1524" layer="91"/> +<junction x="177.8" y="153.67"/> +<junction x="177.8" y="158.75"/> +<pinref part="L4E1" gate="L" pin="2"/> +<pinref part="C5E5" gate="C" pin="1"/> +<pinref part="C4E3" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCABG3P3_USB"/> +</segment> +</net> +<net name="N$155" class="0"> +<segment> +<wire x1="113.03" y1="147.32" x2="123.19" y2="147.32" width="0.1524" layer="91"/> +<pinref part="R4P6" gate="R" pin="1"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCTMP18"/> +</segment> +</net> +<net name="VCCA" class="0"> +<segment> +<wire x1="109.22" y1="90.17" x2="109.22" y2="96.52" width="0.1524" layer="91"/> +<wire x1="109.22" y1="96.52" x2="101.6" y2="96.52" width="0.1524" layer="91"/> +<wire x1="101.6" y1="96.52" x2="93.98" y2="96.52" width="0.1524" layer="91"/> +<wire x1="93.98" y1="96.52" x2="93.98" y2="90.17" width="0.1524" layer="91"/> +<wire x1="101.6" y1="90.17" x2="101.6" y2="96.52" width="0.1524" layer="91"/> +<wire x1="109.22" y1="96.52" x2="116.84" y2="96.52" width="0.1524" layer="91"/> +<wire x1="116.84" y1="96.52" x2="123.19" y2="96.52" width="0.1524" layer="91"/> +<wire x1="116.84" y1="96.52" x2="116.84" y2="93.98" width="0.1524" layer="91"/> +<wire x1="116.84" y1="93.98" x2="123.19" y2="93.98" width="0.1524" layer="91"/> +<wire x1="93.98" y1="96.52" x2="86.36" y2="96.52" width="0.1524" layer="91"/> +<wire x1="86.36" y1="96.52" x2="86.36" y2="99.06" width="0.1524" layer="91"/> +<junction x="101.6" y="96.52"/> +<junction x="116.84" y="96.52"/> +<junction x="109.22" y="96.52"/> +<junction x="93.98" y="96.52"/> +<pinref part="C5P20" gate="C" pin="1"/> +<pinref part="C5P17" gate="C" pin="1"/> +<pinref part="C5P16" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCA[1]"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCA[2]"/> +<pinref part="R5D2" gate="R" pin="2"/> +</segment> +</net> +<net name="N$159" class="0"> +<segment> +<wire x1="83.82" y1="133.35" x2="83.82" y2="128.27" width="0.1524" layer="91"/> +<wire x1="83.82" y1="128.27" x2="86.36" y2="128.27" width="0.1524" layer="91"/> +<pinref part="R5D8" gate="R" pin="2"/> +<pinref part="L5D3" gate="L" pin="1"/> +</segment> +</net> +<net name="N$165" class="0"> +<segment> +<wire x1="97.79" y1="128.27" x2="102.87" y2="128.27" width="0.1524" layer="91"/> +<wire x1="97.79" y1="124.46" x2="97.79" y2="128.27" width="0.1524" layer="91"/> +<wire x1="102.87" y1="124.46" x2="102.87" y2="128.27" width="0.1524" layer="91"/> +<wire x1="123.19" y1="128.27" x2="116.84" y2="128.27" width="0.1524" layer="91"/> +<wire x1="116.84" y1="128.27" x2="115.57" y2="128.27" width="0.1524" layer="91"/> +<wire x1="115.57" y1="128.27" x2="102.87" y2="128.27" width="0.1524" layer="91"/> +<junction x="97.79" y="128.27"/> +<junction x="102.87" y="128.27"/> +<pinref part="L5D3" gate="L" pin="2"/> +<pinref part="C5D1" gate="C" pin="1"/> +<pinref part="C5D3" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCAHPLL"/> +</segment> +</net> +<net name="N$172" class="0"> +<segment> +<wire x1="33.02" y1="106.68" x2="33.02" y2="114.3" width="0.1524" layer="91"/> +<wire x1="33.02" y1="114.3" x2="40.64" y2="114.3" width="0.1524" layer="91"/> +<wire x1="40.64" y1="114.3" x2="48.26" y2="114.3" width="0.1524" layer="91"/> +<wire x1="48.26" y1="114.3" x2="55.88" y2="114.3" width="0.1524" layer="91"/> +<wire x1="55.88" y1="114.3" x2="55.88" y2="106.68" width="0.1524" layer="91"/> +<wire x1="48.26" y1="106.68" x2="48.26" y2="114.3" width="0.1524" layer="91"/> +<wire x1="40.64" y1="106.68" x2="40.64" y2="114.3" width="0.1524" layer="91"/> +<wire x1="27.94" y1="114.3" x2="33.02" y2="114.3" width="0.1524" layer="91"/> +<wire x1="66.04" y1="88.9" x2="59.69" y2="88.9" width="0.1524" layer="91"/> +<wire x1="59.69" y1="88.9" x2="59.69" y2="91.44" width="0.1524" layer="91"/> +<wire x1="59.69" y1="91.44" x2="59.69" y2="93.98" width="0.1524" layer="91"/> +<wire x1="59.69" y1="93.98" x2="59.69" y2="96.52" width="0.1524" layer="91"/> +<wire x1="59.69" y1="96.52" x2="59.69" y2="99.06" width="0.1524" layer="91"/> +<wire x1="59.69" y1="99.06" x2="59.69" y2="101.6" width="0.1524" layer="91"/> +<wire x1="59.69" y1="101.6" x2="59.69" y2="104.14" width="0.1524" layer="91"/> +<wire x1="59.69" y1="104.14" x2="59.69" y2="106.68" width="0.1524" layer="91"/> +<wire x1="59.69" y1="106.68" x2="59.69" y2="109.22" width="0.1524" layer="91"/> +<wire x1="59.69" y1="109.22" x2="59.69" y2="111.76" width="0.1524" layer="91"/> +<wire x1="59.69" y1="111.76" x2="59.69" y2="114.3" width="0.1524" layer="91"/> +<wire x1="59.69" y1="114.3" x2="59.69" y2="116.84" width="0.1524" layer="91"/> +<wire x1="59.69" y1="116.84" x2="66.04" y2="116.84" width="0.1524" layer="91"/> +<wire x1="59.69" y1="114.3" x2="66.04" y2="114.3" width="0.1524" layer="91"/> +<wire x1="59.69" y1="111.76" x2="66.04" y2="111.76" width="0.1524" layer="91"/> +<wire x1="59.69" y1="109.22" x2="66.04" y2="109.22" width="0.1524" layer="91"/> +<wire x1="59.69" y1="106.68" x2="66.04" y2="106.68" width="0.1524" layer="91"/> +<wire x1="59.69" y1="104.14" x2="66.04" y2="104.14" width="0.1524" layer="91"/> +<wire x1="59.69" y1="101.6" x2="66.04" y2="101.6" width="0.1524" layer="91"/> +<wire x1="59.69" y1="99.06" x2="66.04" y2="99.06" width="0.1524" layer="91"/> +<wire x1="59.69" y1="96.52" x2="66.04" y2="96.52" width="0.1524" layer="91"/> +<wire x1="59.69" y1="93.98" x2="66.04" y2="93.98" width="0.1524" layer="91"/> +<wire x1="59.69" y1="91.44" x2="66.04" y2="91.44" width="0.1524" layer="91"/> +<wire x1="55.88" y1="114.3" x2="59.69" y2="114.3" width="0.1524" layer="91"/> +<junction x="40.64" y="114.3"/> +<junction x="48.26" y="114.3"/> +<junction x="33.02" y="114.3"/> +<junction x="59.69" y="91.44"/> +<junction x="59.69" y="93.98"/> +<junction x="59.69" y="96.52"/> +<junction x="59.69" y="99.06"/> +<junction x="59.69" y="101.6"/> +<junction x="59.69" y="104.14"/> +<junction x="59.69" y="106.68"/> +<junction x="59.69" y="109.22"/> +<junction x="59.69" y="111.76"/> +<junction x="59.69" y="114.3"/> +<junction x="55.88" y="114.3"/> +<pinref part="C5P9" gate="C" pin="1"/> +<pinref part="C5P8" gate="C" pin="1"/> +<pinref part="C5P5" gate="C" pin="1"/> +<pinref part="C5P7" gate="C" pin="1"/> +<pinref part="R5D1" gate="R" pin="2"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@1"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@2"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@3"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@4"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@5"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@6"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@7"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@8"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@9"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@10"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@11"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE@12"/> +</segment> +</net> +<net name="N$169" class="0"> +<segment> +<wire x1="54.61" y1="143.51" x2="54.61" y2="125.73" width="0.1524" layer="91"/> +<wire x1="54.61" y1="125.73" x2="66.04" y2="125.73" width="0.1524" layer="91"/> +<wire x1="39.37" y1="143.51" x2="43.18" y2="143.51" width="0.1524" layer="91"/> +<wire x1="43.18" y1="143.51" x2="50.8" y2="143.51" width="0.1524" layer="91"/> +<wire x1="50.8" y1="143.51" x2="54.61" y2="143.51" width="0.1524" layer="91"/> +<wire x1="43.18" y1="134.62" x2="43.18" y2="143.51" width="0.1524" layer="91"/> +<wire x1="50.8" y1="135.89" x2="50.8" y2="143.51" width="0.1524" layer="91"/> +<junction x="43.18" y="143.51"/> +<junction x="50.8" y="143.51"/> +<pinref part="L5D2" gate="L" pin="2"/> +<pinref part="C5D7" gate="C" pin="1"/> +<pinref part="C5D5" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE0PLL12@1"/> +</segment> +</net> +<net name="N$174" class="0"> +<segment> +<wire x1="49.53" y1="82.55" x2="55.88" y2="82.55" width="0.1524" layer="91"/> +<wire x1="55.88" y1="82.55" x2="63.5" y2="82.55" width="0.1524" layer="91"/> +<wire x1="63.5" y1="82.55" x2="63.5" y2="76.2" width="0.1524" layer="91"/> +<wire x1="63.5" y1="82.55" x2="66.04" y2="82.55" width="0.1524" layer="91"/> +<wire x1="55.88" y1="76.2" x2="55.88" y2="82.55" width="0.1524" layer="91"/> +<junction x="63.5" y="82.55"/> +<junction x="55.88" y="82.55"/> +<pinref part="L5E3" gate="L" pin="2"/> +<pinref part="C5E11" gate="C" pin="1"/> +<pinref part="C5E4" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCABGP033"/> +</segment> +</net> +<net name="N$176" class="0"> +<segment> +<wire x1="34.29" y1="82.55" x2="38.1" y2="82.55" width="0.1524" layer="91"/> +<pinref part="R5E14" gate="R" pin="2"/> +<pinref part="L5E3" gate="L" pin="1"/> +</segment> +</net> +<net name="N$177" class="0"> +<segment> +<wire x1="36.83" y1="168.91" x2="43.18" y2="168.91" width="0.1524" layer="91"/> +<wire x1="43.18" y1="168.91" x2="50.8" y2="168.91" width="0.1524" layer="91"/> +<wire x1="50.8" y1="168.91" x2="57.15" y2="168.91" width="0.1524" layer="91"/> +<wire x1="50.8" y1="162.56" x2="50.8" y2="168.91" width="0.1524" layer="91"/> +<wire x1="43.18" y1="161.29" x2="43.18" y2="168.91" width="0.1524" layer="91"/> +<wire x1="66.04" y1="128.27" x2="57.15" y2="128.27" width="0.1524" layer="91"/> +<wire x1="57.15" y1="168.91" x2="57.15" y2="128.27" width="0.1524" layer="91"/> +<wire x1="43.18" y1="168.91" x2="50.8" y2="168.91" width="0.1524" layer="91"/> +<junction x="43.18" y="168.91"/> +<junction x="50.8" y="168.91"/> +<pinref part="L5P1" gate="L" pin="2"/> +<pinref part="C5P23" gate="C" pin="1"/> +<pinref part="C5P19" gate="C" pin="1"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCAPE0PLL12@2"/> +</segment> +</net> +<net name="N$179" class="0"> +<segment> +<wire x1="25.4" y1="168.91" x2="22.86" y2="168.91" width="0.1524" layer="91"/> +<pinref part="L5P1" gate="L" pin="1"/> +<pinref part="R5P8" gate="R" pin="2"/> +</segment> +</net> +<net name="N$180" class="0"> +<segment> +<wire x1="24.13" y1="143.51" x2="27.94" y2="143.51" width="0.1524" layer="91"/> +<pinref part="R5D6" gate="R" pin="2"/> +<pinref part="L5D2" gate="L" pin="1"/> +</segment> +</net> +<net name="AGND" class="0"> +<segment> +<wire x1="140.97" y1="146.05" x2="146.05" y2="146.05" width="0.1524" layer="91"/> +<wire x1="146.05" y1="146.05" x2="146.05" y2="138.43" width="0.1524" layer="91"/> +<wire x1="146.05" y1="146.05" x2="154.94" y2="146.05" width="0.1524" layer="91"/> +<wire x1="154.94" y1="146.05" x2="154.94" y2="140.97" width="0.1524" layer="91"/> +<junction x="146.05" y="146.05"/> +<pinref part="R5D3" gate="R" pin="2"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VSSA"/> +<pinref part="U$17" gate="AGND" pin="AGND"/> +</segment> +<segment> +<wire x1="97.79" y1="116.84" x2="97.79" y2="110.49" width="0.1524" layer="91"/> +<wire x1="97.79" y1="110.49" x2="102.87" y2="110.49" width="0.1524" layer="91"/> +<wire x1="102.87" y1="110.49" x2="102.87" y2="116.84" width="0.1524" layer="91"/> +<wire x1="97.79" y1="107.95" x2="97.79" y2="110.49" width="0.1524" layer="91"/> +<junction x="97.79" y="110.49"/> +<pinref part="C5D1" gate="C" pin="2"/> +<pinref part="C5D3" gate="C" pin="2"/> +<pinref part="U$21" gate="AGND" pin="AGND"/> +</segment> +</net> +<net name="N$225" class="0"> +<segment> +<wire x1="83.82" y1="46.99" x2="77.47" y2="46.99" width="0.1524" layer="91"/> +<pinref part="CR8V1" gate="D" pin="A1"/> +<pinref part="R8V6" gate="R" pin="1"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="78.74" y1="52.07" x2="78.74" y2="54.61" width="0.1524" layer="91"/> +<wire x1="83.82" y1="52.07" x2="78.74" y2="52.07" width="0.1524" layer="91"/> +<pinref part="CR8V1" gate="D" pin="A2"/> +<pinref part="U$135" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="191.77" y1="34.29" x2="191.77" y2="39.37" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCCGBE33"/> +<pinref part="U$252" gate="PW-VCC3" pin="VCC3"/> +<wire x1="191.77" y1="39.37" x2="191.77" y2="41.91" width="0.1524" layer="91"/> +<wire x1="204.47" y1="34.29" x2="204.47" y2="39.37" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCCGBEPSUS"/> +<wire x1="191.77" y1="39.37" x2="204.47" y2="39.37" width="0.1524" layer="91"/> +<junction x="191.77" y="39.37"/> +</segment> +<segment> +<wire x1="24.13" y1="82.55" x2="16.51" y2="82.55" width="0.1524" layer="91"/> +<wire x1="16.51" y1="82.55" x2="16.51" y2="86.36" width="0.1524" layer="91"/> +<pinref part="R5E14" gate="R" pin="1"/> +<pinref part="U$42" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="143.51" y1="158.75" x2="146.05" y2="158.75" width="0.1524" layer="91"/> +<wire x1="143.51" y1="158.75" x2="143.51" y2="165.1" width="0.1524" layer="91"/> +<pinref part="R4E9" gate="R" pin="1"/> +<pinref part="U$47" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="201.93" y1="148.59" x2="201.93" y2="146.05" width="0.1524" layer="91"/> +<wire x1="201.93" y1="146.05" x2="204.47" y2="146.05" width="0.1524" layer="91"/> +<pinref part="R5P11" gate="R" pin="1"/> +<pinref part="U$49" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="246.38" y1="93.98" x2="243.84" y2="93.98" width="0.1524" layer="91"/> +<wire x1="243.84" y1="93.98" x2="243.84" y2="91.44" width="0.1524" layer="91"/> +<wire x1="243.84" y1="91.44" x2="242.57" y2="91.44" width="0.1524" layer="91"/> +<wire x1="242.57" y1="91.44" x2="207.01" y2="91.44" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCSATA33"/> +<pinref part="U$50" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="123.19" y1="139.7" x2="105.41" y2="139.7" width="0.1524" layer="91"/> +<wire x1="105.41" y1="139.7" x2="105.41" y2="137.16" width="0.1524" layer="91"/> +<wire x1="105.41" y1="137.16" x2="105.41" y2="134.62" width="0.1524" layer="91"/> +<wire x1="105.41" y1="137.16" x2="123.19" y2="137.16" width="0.1524" layer="91"/> +<wire x1="105.41" y1="134.62" x2="123.19" y2="134.62" width="0.1524" layer="91"/> +<wire x1="105.41" y1="139.7" x2="100.33" y2="139.7" width="0.1524" layer="91"/> +<junction x="105.41" y="137.16"/> +<junction x="105.41" y="139.7"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCPSUS@1"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCPSUS@2"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCPSUS@3"/> +<pinref part="U$67" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="V2P5" class="0"> +<segment> +<wire x1="218.44" y1="34.29" x2="218.44" y2="38.1" width="0.1524" layer="91"/> +<wire x1="218.44" y1="38.1" x2="220.98" y2="38.1" width="0.1524" layer="91"/> +<wire x1="220.98" y1="38.1" x2="223.52" y2="38.1" width="0.1524" layer="91"/> +<wire x1="223.52" y1="38.1" x2="226.06" y2="38.1" width="0.1524" layer="91"/> +<wire x1="226.06" y1="38.1" x2="226.06" y2="34.29" width="0.1524" layer="91"/> +<wire x1="223.52" y1="34.29" x2="223.52" y2="38.1" width="0.1524" layer="91"/> +<wire x1="220.98" y1="34.29" x2="220.98" y2="38.1" width="0.1524" layer="91"/> +<junction x="220.98" y="38.1"/> +<junction x="223.52" y="38.1"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCC25@1"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCC25@2"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCC25@3"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCC25@4"/> +<wire x1="237.49" y1="34.29" x2="237.49" y2="38.1" width="0.1524" layer="91"/> +<wire x1="245.11" y1="38.1" x2="245.11" y2="34.29" width="0.1524" layer="91"/> +<wire x1="242.57" y1="38.1" x2="245.11" y2="38.1" width="0.1524" layer="91"/> +<wire x1="242.57" y1="34.29" x2="242.57" y2="38.1" width="0.1524" layer="91"/> +<wire x1="240.03" y1="38.1" x2="242.57" y2="38.1" width="0.1524" layer="91"/> +<wire x1="240.03" y1="34.29" x2="240.03" y2="38.1" width="0.1524" layer="91"/> +<wire x1="237.49" y1="38.1" x2="240.03" y2="38.1" width="0.1524" layer="91"/> +<junction x="242.57" y="38.1"/> +<junction x="240.03" y="38.1"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCCSUS25@1"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCCSUS25@2"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCCSUS25@3"/> +<pinref part="U6E1" gate="PWR-GBE" pin="VCCSUS25@4"/> +<wire x1="226.06" y1="38.1" x2="237.49" y2="38.1" width="0.1524" layer="91"/> +<junction x="226.06" y="38.1"/> +<junction x="237.49" y="38.1"/> +<pinref part="U$82" gate="G$1" pin="V2P5"/> +<wire x1="218.44" y1="38.1" x2="218.44" y2="41.91" width="0.1524" layer="91"/> +<junction x="218.44" y="38.1"/> +</segment> +</net> +<net name="V1P2" class="0"> +<segment> +<wire x1="114.3" y1="110.49" x2="109.22" y2="110.49" width="0.1524" layer="91"/> +<wire x1="123.19" y1="102.87" x2="116.84" y2="102.87" width="0.1524" layer="91"/> +<wire x1="116.84" y1="102.87" x2="116.84" y2="105.41" width="0.1524" layer="91"/> +<wire x1="116.84" y1="105.41" x2="116.84" y2="107.95" width="0.1524" layer="91"/> +<wire x1="116.84" y1="107.95" x2="116.84" y2="110.49" width="0.1524" layer="91"/> +<wire x1="116.84" y1="110.49" x2="123.19" y2="110.49" width="0.1524" layer="91"/> +<wire x1="123.19" y1="107.95" x2="116.84" y2="107.95" width="0.1524" layer="91"/> +<wire x1="116.84" y1="105.41" x2="123.19" y2="105.41" width="0.1524" layer="91"/> +<wire x1="116.84" y1="110.49" x2="114.3" y2="110.49" width="0.1524" layer="91"/> +<wire x1="109.22" y1="110.49" x2="109.22" y2="119.38" width="0.1524" layer="91"/> +<junction x="116.84" y="110.49"/> +<junction x="116.84" y="107.95"/> +<junction x="116.84" y="105.41"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCSUS1@1"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCSUS1@2"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCSUS1@3"/> +<pinref part="U6E1" gate="PWR-MIS" pin="VCCSUS1@4"/> +<pinref part="U$145" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="246.38" y1="104.14" x2="240.03" y2="104.14" width="0.1524" layer="91"/> +<wire x1="240.03" y1="104.14" x2="240.03" y2="101.6" width="0.1524" layer="91"/> +<wire x1="240.03" y1="101.6" x2="240.03" y2="99.06" width="0.1524" layer="91"/> +<wire x1="240.03" y1="99.06" x2="234.95" y2="99.06" width="0.1524" layer="91"/> +<wire x1="234.95" y1="99.06" x2="207.01" y2="99.06" width="0.1524" layer="91"/> +<wire x1="240.03" y1="101.6" x2="246.38" y2="101.6" width="0.1524" layer="91"/> +<junction x="240.03" y="101.6"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCSATA@1"/> +<pinref part="U6E1" gate="PWR-SATA" pin="VCCSATA@2"/> +<pinref part="U$198" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="201.93" y1="119.38" x2="201.93" y2="114.3" width="0.1524" layer="91"/> +<wire x1="201.93" y1="114.3" x2="204.47" y2="114.3" width="0.1524" layer="91"/> +<pinref part="R5E2" gate="R" pin="1"/> +<pinref part="U$27" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="201.93" y1="134.62" x2="201.93" y2="132.08" width="0.1524" layer="91"/> +<wire x1="201.93" y1="132.08" x2="204.47" y2="132.08" width="0.1524" layer="91"/> +<pinref part="R5E15" gate="R" pin="1"/> +<pinref part="U$174" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="201.93" y1="162.56" x2="201.93" y2="160.02" width="0.1524" layer="91"/> +<wire x1="201.93" y1="160.02" x2="204.47" y2="160.02" width="0.1524" layer="91"/> +<pinref part="R5D7" gate="R" pin="1"/> +<pinref part="U$223" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="83.82" y1="146.05" x2="83.82" y2="143.51" width="0.1524" layer="91"/> +<pinref part="R5D8" gate="R" pin="1"/> +<pinref part="U$224" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="86.36" y1="109.22" x2="86.36" y2="111.76" width="0.1524" layer="91"/> +<pinref part="R5D2" gate="R" pin="1"/> +<pinref part="U$225" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="152.4" y1="124.46" x2="152.4" y2="119.38" width="0.1524" layer="91"/> +<pinref part="R5E16" gate="R" pin="1"/> +<pinref part="U$237" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="13.97" y1="143.51" x2="10.16" y2="143.51" width="0.1524" layer="91"/> +<wire x1="10.16" y1="143.51" x2="10.16" y2="168.91" width="0.1524" layer="91"/> +<wire x1="12.7" y1="168.91" x2="10.16" y2="168.91" width="0.1524" layer="91"/> +<wire x1="10.16" y1="168.91" x2="10.16" y2="172.72" width="0.1524" layer="91"/> +<junction x="10.16" y="168.91"/> +<pinref part="R5D6" gate="R" pin="1"/> +<pinref part="R5P8" gate="R" pin="1"/> +<pinref part="U$201" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="59.69" y1="168.91" x2="59.69" y2="161.29" width="0.1524" layer="91"/> +<wire x1="59.69" y1="161.29" x2="59.69" y2="158.75" width="0.1524" layer="91"/> +<wire x1="59.69" y1="158.75" x2="59.69" y2="156.21" width="0.1524" layer="91"/> +<wire x1="59.69" y1="156.21" x2="59.69" y2="153.67" width="0.1524" layer="91"/> +<wire x1="59.69" y1="153.67" x2="59.69" y2="151.13" width="0.1524" layer="91"/> +<wire x1="59.69" y1="151.13" x2="59.69" y2="148.59" width="0.1524" layer="91"/> +<wire x1="59.69" y1="148.59" x2="59.69" y2="146.05" width="0.1524" layer="91"/> +<wire x1="59.69" y1="146.05" x2="59.69" y2="143.51" width="0.1524" layer="91"/> +<wire x1="59.69" y1="143.51" x2="66.04" y2="143.51" width="0.1524" layer="91"/> +<wire x1="59.69" y1="161.29" x2="66.04" y2="161.29" width="0.1524" layer="91"/> +<wire x1="59.69" y1="158.75" x2="66.04" y2="158.75" width="0.1524" layer="91"/> +<wire x1="59.69" y1="156.21" x2="66.04" y2="156.21" width="0.1524" layer="91"/> +<wire x1="59.69" y1="153.67" x2="66.04" y2="153.67" width="0.1524" layer="91"/> +<wire x1="59.69" y1="151.13" x2="66.04" y2="151.13" width="0.1524" layer="91"/> +<wire x1="59.69" y1="148.59" x2="66.04" y2="148.59" width="0.1524" layer="91"/> +<wire x1="59.69" y1="146.05" x2="66.04" y2="146.05" width="0.1524" layer="91"/> +<junction x="59.69" y="146.05"/> +<junction x="59.69" y="148.59"/> +<junction x="59.69" y="151.13"/> +<junction x="59.69" y="153.67"/> +<junction x="59.69" y="156.21"/> +<junction x="59.69" y="158.75"/> +<junction x="59.69" y="161.29"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCRPE@1"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCRPE@2"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCRPE@3"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCRPE@4"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCRPE@5"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCRPE@6"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCRPE@7"/> +<pinref part="U6E1" gate="PWR-PCI" pin="VCCRPE@8"/> +<pinref part="U$203" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="16.51" y1="114.3" x2="17.78" y2="114.3" width="0.1524" layer="91"/> +<wire x1="16.51" y1="114.3" x2="16.51" y2="116.84" width="0.1524" layer="91"/> +<pinref part="R5D1" gate="R" pin="1"/> +<pinref part="U$199" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="182.88" y1="138.43" x2="179.07" y2="138.43" width="0.1524" layer="91"/> +<wire x1="179.07" y1="138.43" x2="167.64" y2="138.43" width="0.1524" layer="91"/> +<wire x1="167.64" y1="138.43" x2="167.64" y2="139.7" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCC1P2_USBSUS"/> +<pinref part="U$219" gate="PW-V1P2" pin="V1P2"/> +</segment> +<segment> +<wire x1="168.91" y1="125.73" x2="168.91" y2="121.92" width="0.1524" layer="91"/> +<wire x1="182.88" y1="132.08" x2="179.07" y2="132.08" width="0.1524" layer="91"/> +<wire x1="179.07" y1="129.54" x2="179.07" y2="132.08" width="0.1524" layer="91"/> +<wire x1="179.07" y1="129.54" x2="182.88" y2="129.54" width="0.1524" layer="91"/> +<wire x1="179.07" y1="127" x2="179.07" y2="129.54" width="0.1524" layer="91"/> +<wire x1="179.07" y1="127" x2="182.88" y2="127" width="0.1524" layer="91"/> +<wire x1="179.07" y1="124.46" x2="179.07" y2="127" width="0.1524" layer="91"/> +<wire x1="179.07" y1="124.46" x2="182.88" y2="124.46" width="0.1524" layer="91"/> +<wire x1="182.88" y1="116.84" x2="179.07" y2="116.84" width="0.1524" layer="91"/> +<wire x1="179.07" y1="116.84" x2="179.07" y2="119.38" width="0.1524" layer="91"/> +<wire x1="179.07" y1="119.38" x2="182.88" y2="119.38" width="0.1524" layer="91"/> +<wire x1="179.07" y1="119.38" x2="179.07" y2="121.92" width="0.1524" layer="91"/> +<wire x1="179.07" y1="121.92" x2="179.07" y2="124.46" width="0.1524" layer="91"/> +<wire x1="179.07" y1="121.92" x2="182.88" y2="121.92" width="0.1524" layer="91"/> +<wire x1="179.07" y1="121.92" x2="168.91" y2="121.92" width="0.1524" layer="91"/> +<junction x="179.07" y="129.54"/> +<junction x="179.07" y="127"/> +<junction x="179.07" y="124.46"/> +<junction x="179.07" y="119.38"/> +<junction x="179.07" y="121.92"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCUSB12@3"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCUSB12@4"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCUSB12@5"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCUSB12@6"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCUSB12@7"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCUSB12@2"/> +<pinref part="U6E1" gate="PWR-USB" pin="VCCUSB12@1"/> +<pinref part="U$205" gate="PW-V1P2" pin="V1P2"/> +</segment> +</net> +<net name="V1P8-DDR" class="0"> +<segment> +<wire x1="100.33" y1="149.86" x2="100.33" y2="147.32" width="0.1524" layer="91"/> +<wire x1="100.33" y1="147.32" x2="102.87" y2="147.32" width="0.1524" layer="91"/> +<pinref part="R4P6" gate="R" pin="2"/> +<pinref part="U$26" gate="V1P8-DDR" pin="V1P8-DDR"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="114.3" y="170.18" size="3.81" layer="94">DDR2 CONN</text> +</plain> +<instances> +<instance part="FRAME22" gate="G$1" x="0" y="0"/> +<instance part="FRAME22" gate="G$2" x="180.34" y="0"/> +<instance part="R3M2" gate="R" x="31.75" y="125.73" smashed="yes" rot="R270"> +<attribute name="DNP" x="30.48" y="123.19" size="1.778" layer="96" rot="R90"/> +<attribute name="POWER" x="31.75" y="125.73" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="31.4325" y="129.2225" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="31.4325" y="122.555" size="1.778" layer="96" rot="MR270"/> +</instance> +<instance part="U$386" gate="G$1" x="31.75" y="71.12"/> +<instance part="R2M20" gate="R" x="36.83" y="125.73" rot="R270"> +<attribute name="POWER" x="36.83" y="125.73" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3M1" gate="R" x="41.91" y="125.73" smashed="yes" rot="R270"> +<attribute name="DNP" x="40.64" y="123.19" size="1.778" layer="96" rot="R90"/> +<attribute name="POWER" x="41.91" y="125.73" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="41.5925" y="129.2225" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="41.5925" y="122.555" size="1.778" layer="96" rot="MR270"/> +</instance> +<instance part="R3M3" gate="R" x="31.75" y="87.63" rot="R270"> +<attribute name="POWER" x="31.75" y="87.63" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2M22" gate="R" x="36.83" y="87.63" smashed="yes" rot="R270"> +<attribute name="DNP" x="35.56" y="85.09" size="1.778" layer="96" rot="R90"/> +<attribute name="POWER" x="36.83" y="87.63" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="36.5125" y="91.1225" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="36.5125" y="84.455" size="1.778" layer="96" rot="MR270"/> +</instance> +<instance part="R2M23" gate="R" x="41.91" y="87.63" rot="R270"> +<attribute name="POWER" x="41.91" y="87.63" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6M1" gate="C" x="93.98" y="66.04" smashed="yes" rot="MR0"> +<attribute name="NAME" x="93.6625" y="66.04" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="93.6625" y="63.8175" size="1.778" layer="96" rot="MR270"/> +<attribute name="VOLTAGE" x="93.98" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="93.98" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="93.98" y="66.04" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$387" gate="G$1" x="93.98" y="49.53"/> +<instance part="P+21" gate="1" x="54.61" y="96.52"/> +<instance part="R6N2" gate="R" x="54.61" y="82.55" smashed="yes" rot="MR90"> +<attribute name="NAME" x="51.435" y="82.2325" size="1.778" layer="95" rot="R270"/> +<attribute name="VALUE" x="51.435" y="83.185" size="1.778" layer="96" rot="MR90"/> +<attribute name="POWER" x="54.61" y="82.55" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="54.61" y="82.55" size="1.778" layer="96" rot="MR90" display="off"/> +</instance> +<instance part="R6N3" gate="R" x="54.61" y="63.5" smashed="yes" rot="MR90"> +<attribute name="NAME" x="51.1175" y="63.5" size="1.778" layer="95" rot="R270"/> +<attribute name="VALUE" x="51.1175" y="64.4525" size="1.778" layer="96" rot="MR90"/> +<attribute name="POWER" x="54.61" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="54.61" y="63.5" size="1.778" layer="96" rot="MR90" display="off"/> +</instance> +<instance part="U$388" gate="G$1" x="54.61" y="50.8"/> +<instance part="R6N1" gate="R" x="76.2" y="74.93" smashed="yes" rot="MR0"> +<attribute name="NAME" x="77.47" y="76.2" size="1.778" layer="95"/> +<attribute name="VALUE" x="74.295" y="76.2" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="76.2" y="74.93" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6M2" gate="C" x="86.36" y="62.23" smashed="yes" rot="R180"> +<attribute name="NAME" x="85.725" y="61.9125" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="85.725" y="64.77" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="86.36" y="62.23" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="86.36" y="62.23" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="86.36" y="62.23" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6N1" gate="C" x="67.31" y="62.23" smashed="yes" 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layer="94">DDR2 TERMINATION</text> +<text x="102.87" y="172.72" size="3.81" layer="94">DDR2 POWER</text> +<text x="87.63" y="128.27" size="1.778" layer="94">Limited @ Single Side chip on DDR2</text> +</plain> +<instances> +<instance part="FRAME23" gate="G$1" x="0" y="0"/> +<instance part="FRAME23" gate="G$2" x="180.34" y="0"/> +<instance part="U$389" gate="G$1" x="76.2" y="130.81"/> +<instance part="C6B4" gate="C" x="120.65" y="107.95" smashed="yes" rot="R270"> +<attribute name="NAME" x="118.364" y="108.331" size="1.6764" layer="95" rot="MR0"/> +<attribute name="VALUE" x="120.65" y="108.2675" size="1.6764" layer="96"/> +<attribute name="VOLTAGE" x="120.65" y="107.95" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="120.65" y="107.95" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="120.65" y="107.95" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C6B14" gate="C" x="107.95" y="105.41" smashed="yes" rot="R270"> +<attribute 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layer="91"/> +<wire x1="137.16" y1="76.2" x2="185.42" y2="76.2" width="0.1524" layer="91"/> +<label x="138.43" y="76.5175" size="1.778" layer="92"/> +<pinref part="RP4M3" gate="C" pin="2"/> +</segment> +</net> +<net name="DDR-MA0" class="0"> +<segment> +<wire x1="78.74" y1="73.66" x2="80.01" y2="72.39" width="0.1524" layer="91"/> +<wire x1="80.01" y1="72.39" x2="115.57" y2="72.39" width="0.1524" layer="91"/> +<label x="81.28" y="72.7075" size="1.778" layer="92"/> +<pinref part="C6B11" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="135.89" y1="72.39" x2="137.16" y2="71.12" width="0.1524" layer="91"/> +<wire x1="137.16" y1="71.12" x2="185.42" y2="71.12" width="0.1524" layer="91"/> +<label x="138.43" y="71.4375" size="1.778" layer="92"/> +<pinref part="RP4M2" gate="A" pin="2"/> +</segment> +</net> +<net name="DDR-BA2" class="0"> +<segment> +<wire x1="12.7" y1="83.82" x2="13.97" y2="82.55" width="0.1524" layer="91"/> +<wire x1="13.97" y1="82.55" x2="31.75" y2="82.55" width="0.1524" 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x2="208.28" y2="88.9" width="0.1524" layer="91"/> +<wire x1="234.95" y1="83.82" x2="208.28" y2="83.82" width="0.1524" layer="91"/> +<wire x1="208.28" y1="83.82" x2="208.28" y2="86.36" width="0.1524" layer="91"/> +<wire x1="217.17" y1="81.28" x2="208.28" y2="81.28" width="0.1524" layer="91"/> +<wire x1="208.28" y1="81.28" x2="208.28" y2="83.82" width="0.1524" layer="91"/> +<wire x1="234.95" y1="78.74" x2="208.28" y2="78.74" width="0.1524" layer="91"/> +<wire x1="217.17" y1="76.2" x2="208.28" y2="76.2" width="0.1524" layer="91"/> +<wire x1="234.95" y1="73.66" x2="208.28" y2="73.66" width="0.1524" layer="91"/> +<wire x1="208.28" y1="73.66" x2="208.28" y2="76.2" width="0.1524" layer="91"/> +<wire x1="208.28" y1="76.2" x2="208.28" y2="78.74" width="0.1524" layer="91"/> +<wire x1="208.28" y1="78.74" x2="208.28" y2="81.28" width="0.1524" layer="91"/> +<wire x1="208.28" y1="106.68" x2="203.2" y2="106.68" width="0.1524" layer="91"/> +<junction x="203.2" y="106.68"/> +<junction x="203.2" y="104.14"/> +<junction x="203.2" y="101.6"/> +<junction x="203.2" y="99.06"/> +<junction x="203.2" y="96.52"/> +<junction x="203.2" y="93.98"/> +<junction x="203.2" y="91.44"/> +<junction x="203.2" y="88.9"/> +<junction x="203.2" y="86.36"/> +<junction x="203.2" y="83.82"/> +<junction x="203.2" y="81.28"/> +<junction x="203.2" y="73.66"/> +<junction x="203.2" y="76.2"/> +<junction x="203.2" y="78.74"/> +<junction x="208.28" y="104.14"/> +<junction x="208.28" y="101.6"/> +<junction x="208.28" y="99.06"/> +<junction x="208.28" y="96.52"/> +<junction x="208.28" y="93.98"/> +<junction x="208.28" y="91.44"/> +<junction x="208.28" y="88.9"/> +<junction x="208.28" y="86.36"/> +<junction x="208.28" y="83.82"/> +<junction x="208.28" y="81.28"/> +<junction x="208.28" y="76.2"/> +<junction x="208.28" y="78.74"/> +<junction x="208.28" y="106.68"/> +<pinref part="P+24" gate="1" pin="DDR2-VTT"/> +<pinref part="RP4M4" gate="B" pin="1"/> +<pinref part="RP4M4" gate="C" pin="1"/> +<pinref part="RP4M4" gate="D" pin="1"/> +<pinref part="RPT4M2" gate="B" pin="1"/> +<pinref part="RP4M3" gate="A" pin="1"/> +<pinref part="RP4M3" gate="B" pin="1"/> +<pinref part="RPT4M1" gate="C" pin="1"/> +<pinref part="RP4M4" gate="A" pin="1"/> +<pinref part="RPT4M2" gate="A" pin="1"/> +<pinref part="RPT4M2" gate="C" pin="1"/> +<pinref part="RPT4M2" gate="D" pin="1"/> +<pinref part="RP4M3" gate="C" pin="1"/> +<pinref part="RP4M2" gate="A" pin="1"/> +<pinref part="RP4M2" gate="B" pin="1"/> +<pinref part="RP5M1" gate="D" pin="1"/> +<pinref part="C5M2" gate="C" pin="1"/> +<pinref part="C4M4" gate="C" pin="2"/> +<pinref part="C4M3" gate="C" pin="2"/> +<pinref part="C4M5" gate="C" pin="2"/> +<pinref part="C4M6" gate="C" pin="2"/> +<pinref part="C4M15" gate="C" pin="1"/> +<pinref part="C4M7" gate="C" pin="2"/> +<pinref part="C4M8" gate="C" pin="1"/> +<pinref part="C4M9" gate="C" pin="1"/> +<pinref part="C4M10" gate="C" pin="1"/> +<pinref part="C4M11" gate="C" pin="1"/> +<pinref part="C4M12" gate="C" pin="1"/> +<pinref part="C4M13" gate="C" pin="1"/> +<pinref part="C4M14" gate="C" pin="1"/> +</segment> +</net> +<net name="DDR-CKE0" class="0"> +<segment> +<wire x1="12.7" y1="35.56" x2="13.97" y2="34.29" width="0.1524" layer="91"/> +<wire x1="13.97" y1="34.29" x2="39.37" y2="34.29" width="0.1524" layer="91"/> +<label x="15.24" y="34.6075" size="1.778" layer="92"/> +<pinref part="RP5M1" gate="B" pin="2"/> +</segment> +</net> +<net name="DDR-CKE1" class="0"> +<segment> +<wire x1="12.7" y1="31.75" x2="13.97" y2="30.48" width="0.1524" layer="91"/> +<wire x1="13.97" y1="30.48" x2="39.37" y2="30.48" width="0.1524" layer="91"/> +<label x="15.24" y="30.7975" size="1.778" layer="92"/> +<pinref part="RP5M1" gate="A" pin="2"/> +</segment> +</net> +<net name="DDR-MA1" class="0"> +<segment> +<wire x1="135.89" y1="74.93" x2="137.16" y2="73.66" width="0.1524" layer="91"/> +<wire x1="137.16" y1="73.66" x2="162.56" y2="73.66" width="0.1524" layer="91"/> +<label x="138.43" y="73.9775" size="1.778" layer="92"/> +<pinref part="RP4M3" gate="B" pin="2"/> +</segment> +<segment> +<wire x1="78.74" y1="76.2" x2="80.01" y2="74.93" width="0.1524" layer="91"/> +<wire x1="80.01" y1="74.93" x2="102.87" y2="74.93" width="0.1524" layer="91"/> +<label x="81.28" y="75.2475" size="1.778" layer="92"/> +<pinref part="C6B10" gate="C" pin="1"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="232.41" y1="172.72" x2="232.41" y2="165.1" width="0.1524" layer="91"/> +<pinref part="DIMMA0" gate="PWR" pin="VDDSPD"/> +<pinref part="U$217" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="12.7" y="168.91" size="3.81" layer="94">DDR2 CPU</text> +</plain> +<instances> +<instance part="FRAME24" gate="G$1" x="0" y="0"/> +<instance part="FRAME24" gate="G$2" x="180.34" y="0"/> +<instance part="R4P2" gate="R" x="60.96" y="33.02" rot="MR180"> +<attribute name="POWER" x="60.96" y="33.02" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="TOLERANCE" x="60.96" y="33.02" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="R4P5" gate="R" x="60.96" y="26.67" rot="MR180"> +<attribute name="POWER" x="60.96" y="26.67" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="TOLERANCE" x="60.96" y="26.67" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="R3P1" gate="R" x="20.32" y="24.13" rot="MR180"> +<attribute name="POWER" x="20.32" y="24.13" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="TOLERANCE" x="20.32" y="24.13" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="R4P3" gate="R" x="60.96" y="20.32" rot="MR180"> +<attribute name="POWER" x="60.96" y="20.32" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="TOLERANCE" x="60.96" y="20.32" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="R4P4" gate="R" x="60.96" y="16.51" rot="MR180"> +<attribute name="POWER" x="60.96" y="16.51" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="TOLERANCE" x="60.96" y="16.51" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="C3P2" gate="C" x="39.37" y="16.51" smashed="yes" rot="R180"> +<attribute name="NAME" x="38.481" y="16.764" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="38.7985" y="20.8915" size="1.778" layer="96" rot="R180"/> +<attribute name="VOLTAGE" x="39.37" y="16.51" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="39.37" y="16.51" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="39.37" y="16.51" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$434" gate="G$1" x="33.02" y="26.67" rot="R270"/> +<instance part="U$435" gate="G$1" x="39.37" y="11.43"/> +<instance part="U6E1" gate="DDR2ACCESS" x="167.64" y="76.2"/> +<instance part="U6E1" gate="DDR2CLK" x="237.49" y="46.99"/> +<instance part="U6E1" gate="DDR2CMP" x="88.9" y="78.74"/> +<instance part="U6E1" gate="DDR2DATA" x="85.09" y="160.02" rot="R90"/> +<instance part="U$28" gate="V1P8-DDR" x="6.35" y="33.02"/> +</instances> +<busses> +<bus name="DDR-DQ[0..63],DDR-DM[0..8]"> +<segment> +<wire x1="39.37" y1="124.46" x2="39.37" y2="127" width="0.4064" layer="92"/> +<wire x1="39.37" y1="127" x2="43.18" y2="127" width="0.4064" layer="92"/> +<wire x1="43.18" y1="127" x2="43.18" y2="124.46" width="0.4064" layer="92"/> +<wire x1="43.18" y1="124.46" x2="237.49" y2="124.46" width="0.4064" layer="92"/> +<label x="43.18" y="121.92" size="1.778" layer="92"/> +</segment> +</bus> +<bus name="DDR-ODT[0..1],DDR-DQSP[0..8],DDR-DQSN[0..8],DDRA-ECC[0..7]"> +<segment> +<wire x1="48.26" y1="36.83" x2="48.26" y2="114.3" width="0.4064" layer="92"/> +<wire x1="48.26" y1="114.3" x2="13.97" y2="114.3" width="0.4064" layer="92"/> +<wire x1="13.97" y1="114.3" x2="13.97" y2="116.84" width="0.4064" layer="92"/> +<wire x1="13.97" y1="116.84" x2="10.16" y2="116.84" width="0.4064" layer="92"/> +<wire x1="10.16" y1="116.84" x2="10.16" y2="114.3" width="0.4064" layer="92"/> +<label x="14.478" y="114.808" size="1.778" layer="92"/> +</segment> +</bus> +<bus name="DDR-BA[0..2],DDR-CKE[0..1],DDR-CS[0..1],DDR-WE,DDR-RAS,DDR-CAS,DDR-MA[0..14]"> +<segment> +<wire x1="132.08" y1="21.59" x2="132.08" y2="93.98" width="0.4064" layer="92"/> +<wire x1="132.08" y1="93.98" x2="110.49" y2="93.98" width="0.4064" layer="92"/> +<wire x1="110.49" y1="93.98" x2="110.49" y2="96.52" width="0.4064" layer="92"/> +<wire x1="110.49" y1="96.52" x2="106.68" y2="96.52" width="0.4064" layer="92"/> +<wire x1="106.68" y1="96.52" x2="106.68" y2="93.98" width="0.4064" layer="92"/> +<label x="111.252" y="94.742" size="1.778" layer="92"/> +</segment> +</bus> +<bus name="DDR-CKN[0..5],DDR-CKP[0..5]"> +<segment> +<wire x1="203.2" y1="27.94" x2="203.2" y2="63.5" width="0.4064" layer="92"/> +<wire x1="203.2" y1="63.5" x2="186.69" y2="63.5" width="0.4064" layer="92"/> +<wire x1="186.69" y1="63.5" x2="186.69" y2="66.04" width="0.4064" layer="92"/> +<wire x1="186.69" y1="66.04" x2="182.88" y2="66.04" width="0.4064" layer="92"/> +<wire x1="182.88" y1="66.04" x2="182.88" y2="63.5" width="0.4064" layer="92"/> +<label x="187.198" y="64.008" size="1.778" layer="92"/> +</segment> +</bus> +</busses> +<nets> +<net name="DDR-DQ0" class="0"> +<segment> +<wire x1="49.53" y1="124.46" x2="50.8" y2="125.73" width="0.1524" layer="91"/> +<wire x1="50.8" y1="125.73" x2="50.8" y2="143.51" width="0.1524" layer="91"/> +<label x="48.5775" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[0]"/> +</segment> +</net> +<net name="DDR-DQ2" class="0"> +<segment> +<wire x1="54.61" y1="124.46" x2="55.88" y2="125.73" width="0.1524" layer="91"/> +<wire x1="55.88" y1="125.73" x2="55.88" y2="143.51" width="0.1524" layer="91"/> +<label x="53.6575" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[2]"/> +</segment> +</net> +<net name="DDR-DQ3" class="0"> +<segment> +<wire x1="57.15" y1="124.46" x2="58.42" y2="125.73" width="0.1524" layer="91"/> +<wire x1="58.42" y1="125.73" x2="58.42" y2="143.51" width="0.1524" layer="91"/> +<label x="56.1975" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[3]"/> +</segment> +</net> +<net name="DDR-DQ4" class="0"> +<segment> +<wire x1="59.69" y1="124.46" x2="60.96" y2="125.73" width="0.1524" layer="91"/> +<wire x1="60.96" y1="125.73" x2="60.96" y2="143.51" width="0.1524" layer="91"/> +<label x="58.7375" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[4]"/> +</segment> +</net> +<net name="DDR-DQ5" class="0"> +<segment> +<wire x1="62.23" y1="124.46" x2="63.5" y2="125.73" width="0.1524" layer="91"/> +<wire x1="63.5" y1="125.73" x2="63.5" y2="143.51" width="0.1524" layer="91"/> +<label x="61.2775" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[5]"/> +</segment> +</net> +<net name="DDR-DQ6" class="0"> +<segment> +<wire x1="64.77" y1="124.46" x2="66.04" y2="125.73" width="0.1524" layer="91"/> +<wire x1="66.04" y1="125.73" x2="66.04" y2="143.51" width="0.1524" layer="91"/> +<label x="63.8175" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[6]"/> +</segment> +</net> +<net name="DDR-DQ7" class="0"> +<segment> +<wire x1="67.31" y1="124.46" x2="68.58" y2="125.73" width="0.1524" layer="91"/> +<wire x1="68.58" y1="125.73" x2="68.58" y2="143.51" width="0.1524" layer="91"/> +<label x="66.3575" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[7]"/> +</segment> +</net> +<net name="DDR-DQ8" class="0"> +<segment> +<wire x1="69.85" y1="124.46" x2="71.12" y2="125.73" width="0.1524" layer="91"/> +<wire x1="71.12" y1="125.73" x2="71.12" y2="143.51" width="0.1524" layer="91"/> +<label x="68.8975" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[8]"/> +</segment> +</net> +<net name="DDR-DQ9" class="0"> +<segment> +<wire x1="72.39" y1="124.46" x2="73.66" y2="125.73" width="0.1524" layer="91"/> +<wire x1="73.66" y1="125.73" x2="73.66" y2="143.51" width="0.1524" layer="91"/> +<label x="71.4375" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[9]"/> +</segment> +</net> +<net name="DDR-DQ10" class="0"> +<segment> +<wire x1="74.93" y1="124.46" x2="76.2" y2="125.73" width="0.1524" layer="91"/> +<wire x1="76.2" y1="125.73" x2="76.2" y2="143.51" width="0.1524" layer="91"/> +<label x="73.9775" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[10]"/> +</segment> +</net> +<net name="DDR-DQ11" class="0"> +<segment> +<wire x1="77.47" y1="124.46" x2="78.74" y2="125.73" width="0.1524" layer="91"/> +<wire x1="78.74" y1="125.73" x2="78.74" y2="143.51" width="0.1524" layer="91"/> +<label x="76.5175" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[11]"/> +</segment> +</net> +<net name="DDR-DQ12" class="0"> +<segment> +<wire x1="80.01" y1="124.46" x2="81.28" y2="125.73" width="0.1524" layer="91"/> +<wire x1="81.28" y1="125.73" x2="81.28" y2="143.51" width="0.1524" layer="91"/> +<label x="79.0575" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[12]"/> +</segment> +</net> +<net name="DDR-DQ13" class="0"> +<segment> +<wire x1="82.55" y1="124.46" x2="83.82" y2="125.73" width="0.1524" layer="91"/> +<wire x1="83.82" y1="125.73" x2="83.82" y2="143.51" width="0.1524" layer="91"/> +<label x="81.5975" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[13]"/> +</segment> +</net> +<net name="DDR-DQ14" class="0"> +<segment> +<wire x1="85.09" y1="124.46" x2="86.36" y2="125.73" width="0.1524" layer="91"/> +<wire x1="86.36" y1="125.73" x2="86.36" y2="143.51" width="0.1524" layer="91"/> +<label x="84.1375" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[14]"/> +</segment> +</net> +<net name="DDR-DQ15" class="0"> +<segment> +<wire x1="87.63" y1="124.46" x2="88.9" y2="125.73" width="0.1524" layer="91"/> +<wire x1="88.9" y1="125.73" x2="88.9" y2="143.51" width="0.1524" layer="91"/> +<label x="86.6775" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[15]"/> +</segment> +</net> +<net name="DDR-DQ16" class="0"> +<segment> +<wire x1="90.17" y1="124.46" x2="91.44" y2="125.73" width="0.1524" layer="91"/> +<wire x1="91.44" y1="125.73" x2="91.44" y2="143.51" width="0.1524" layer="91"/> +<label x="89.2175" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[16]"/> +</segment> +</net> +<net name="DDR-DQ17" class="0"> +<segment> +<wire x1="92.71" y1="124.46" x2="93.98" y2="125.73" width="0.1524" layer="91"/> +<wire x1="93.98" y1="125.73" x2="93.98" y2="143.51" width="0.1524" layer="91"/> +<label x="91.7575" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[17]"/> +</segment> +</net> +<net name="DDR-DQ18" class="0"> +<segment> +<wire x1="95.25" y1="124.46" x2="96.52" y2="125.73" width="0.1524" layer="91"/> +<wire x1="96.52" y1="125.73" x2="96.52" y2="143.51" width="0.1524" layer="91"/> +<label x="94.2975" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[18]"/> +</segment> +</net> +<net name="DDR-DQ19" class="0"> +<segment> +<wire x1="97.79" y1="124.46" x2="99.06" y2="125.73" width="0.1524" layer="91"/> +<wire x1="99.06" y1="125.73" x2="99.06" y2="143.51" width="0.1524" layer="91"/> +<label x="96.8375" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[19]"/> +</segment> +</net> +<net name="DDR-DQ20" class="0"> +<segment> +<wire x1="100.33" y1="124.46" x2="101.6" y2="125.73" width="0.1524" layer="91"/> +<wire x1="101.6" y1="125.73" x2="101.6" y2="143.51" width="0.1524" layer="91"/> +<label x="99.3775" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[20]"/> +</segment> +</net> +<net name="DDR-DQ21" class="0"> +<segment> +<wire x1="102.87" y1="124.46" x2="104.14" y2="125.73" width="0.1524" layer="91"/> +<wire x1="104.14" y1="125.73" x2="104.14" y2="143.51" width="0.1524" layer="91"/> +<label x="101.9175" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[21]"/> +</segment> +</net> +<net name="DDR-DQ22" class="0"> +<segment> +<wire x1="105.41" y1="124.46" x2="106.68" y2="125.73" width="0.1524" layer="91"/> +<wire x1="106.68" y1="125.73" x2="106.68" y2="143.51" width="0.1524" layer="91"/> +<label x="104.4575" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[22]"/> +</segment> +</net> +<net name="DDR-DQ23" class="0"> +<segment> +<wire x1="107.95" y1="124.46" x2="109.22" y2="125.73" width="0.1524" layer="91"/> +<wire x1="109.22" y1="125.73" x2="109.22" y2="143.51" width="0.1524" layer="91"/> +<label x="106.9975" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[23]"/> +</segment> +</net> +<net name="DDR-DQ24" class="0"> +<segment> +<wire x1="110.49" y1="124.46" x2="111.76" y2="125.73" width="0.1524" layer="91"/> +<wire x1="111.76" y1="125.73" x2="111.76" y2="143.51" width="0.1524" layer="91"/> +<label x="109.5375" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[24]"/> +</segment> +</net> +<net name="DDR-DQ25" class="0"> +<segment> +<wire x1="113.03" y1="124.46" x2="114.3" y2="125.73" width="0.1524" layer="91"/> +<wire x1="114.3" y1="125.73" x2="114.3" y2="143.51" width="0.1524" layer="91"/> +<label x="112.0775" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[25]"/> +</segment> +</net> +<net name="DDR-DQ26" class="0"> +<segment> +<wire x1="115.57" y1="124.46" x2="116.84" y2="125.73" width="0.1524" layer="91"/> +<wire x1="116.84" y1="125.73" x2="116.84" y2="143.51" width="0.1524" layer="91"/> +<label x="114.6175" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[26]"/> +</segment> +</net> +<net name="DDR-DQ27" class="0"> +<segment> +<wire x1="118.11" y1="124.46" x2="119.38" y2="125.73" width="0.1524" layer="91"/> +<wire x1="119.38" y1="125.73" x2="119.38" y2="143.51" width="0.1524" layer="91"/> +<label x="117.1575" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[27]"/> +</segment> +</net> +<net name="DDR-DQ28" class="0"> +<segment> +<wire x1="120.65" y1="124.46" x2="121.92" y2="125.73" width="0.1524" layer="91"/> +<wire x1="121.92" y1="125.73" x2="121.92" y2="143.51" width="0.1524" layer="91"/> +<label x="119.6975" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[28]"/> +</segment> +</net> +<net name="DDR-DQ29" class="0"> +<segment> +<wire x1="123.19" y1="124.46" x2="124.46" y2="125.73" width="0.1524" layer="91"/> +<wire x1="124.46" y1="125.73" x2="124.46" y2="143.51" width="0.1524" layer="91"/> +<label x="122.2375" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[29]"/> +</segment> +</net> +<net name="DDR-DQ30" class="0"> +<segment> +<wire x1="125.73" y1="124.46" x2="127" y2="125.73" width="0.1524" layer="91"/> +<wire x1="127" y1="125.73" x2="127" y2="143.51" width="0.1524" layer="91"/> +<label x="124.7775" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[30]"/> +</segment> +</net> +<net name="DDR-DQ31" class="0"> +<segment> +<wire x1="128.27" y1="124.46" x2="129.54" y2="125.73" width="0.1524" layer="91"/> +<wire x1="129.54" y1="125.73" x2="129.54" y2="143.51" width="0.1524" layer="91"/> +<label x="127.3175" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[31]"/> +</segment> +</net> +<net name="DDR-DQ1" class="0"> +<segment> +<wire x1="52.07" y1="124.46" x2="53.34" y2="125.73" width="0.1524" layer="91"/> +<wire x1="53.34" y1="125.73" x2="53.34" y2="143.51" width="0.1524" layer="91"/> +<label x="51.1175" y="140.335" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[1]"/> +</segment> +</net> +<net name="DDR-DQ32" class="0"> +<segment> +<wire x1="130.81" y1="124.46" x2="132.08" y2="125.73" width="0.1524" layer="91"/> +<wire x1="132.08" y1="125.73" x2="132.08" y2="143.51" width="0.1524" layer="91"/> +<label x="131.7625" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[32]"/> +</segment> +</net> +<net name="DDR-DQ33" class="0"> +<segment> +<wire x1="133.35" y1="124.46" x2="134.62" y2="125.73" width="0.1524" layer="91"/> +<wire x1="134.62" y1="125.73" x2="134.62" y2="143.51" width="0.1524" layer="91"/> +<label x="134.3025" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[33]"/> +</segment> +</net> +<net name="DDR-DQ34" class="0"> +<segment> +<wire x1="135.89" y1="124.46" x2="137.16" y2="125.73" width="0.1524" layer="91"/> +<wire x1="137.16" y1="125.73" x2="137.16" y2="143.51" width="0.1524" layer="91"/> +<label x="136.8425" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[34]"/> +</segment> +</net> +<net name="DDR-DQ35" class="0"> +<segment> +<wire x1="138.43" y1="124.46" x2="139.7" y2="125.73" width="0.1524" layer="91"/> +<wire x1="139.7" y1="125.73" x2="139.7" y2="143.51" width="0.1524" layer="91"/> +<label x="139.3825" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[35]"/> +</segment> +</net> +<net name="DDR-DQ36" class="0"> +<segment> +<wire x1="140.97" y1="124.46" x2="142.24" y2="125.73" width="0.1524" layer="91"/> +<wire x1="142.24" y1="125.73" x2="142.24" y2="143.51" width="0.1524" layer="91"/> +<label x="141.9225" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[36]"/> +</segment> +</net> +<net name="DDR-DQ37" class="0"> +<segment> +<wire x1="143.51" y1="124.46" x2="144.78" y2="125.73" width="0.1524" layer="91"/> +<wire x1="144.78" y1="125.73" x2="144.78" y2="143.51" width="0.1524" layer="91"/> +<label x="144.4625" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[37]"/> +</segment> +</net> +<net name="DDR-DQ38" class="0"> +<segment> +<wire x1="146.05" y1="124.46" x2="147.32" y2="125.73" width="0.1524" layer="91"/> +<wire x1="147.32" y1="125.73" x2="147.32" y2="143.51" width="0.1524" layer="91"/> +<label x="147.0025" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[38]"/> +</segment> +</net> +<net name="DDR-DQ39" class="0"> +<segment> +<wire x1="148.59" y1="124.46" x2="149.86" y2="125.73" width="0.1524" layer="91"/> +<wire x1="149.86" y1="125.73" x2="149.86" y2="143.51" width="0.1524" layer="91"/> +<label x="149.5425" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[39]"/> +</segment> +</net> +<net name="DDR-DQ40" class="0"> +<segment> +<wire x1="151.13" y1="124.46" x2="152.4" y2="125.73" width="0.1524" layer="91"/> +<wire x1="152.4" y1="125.73" x2="152.4" y2="143.51" width="0.1524" layer="91"/> +<label x="152.0825" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[40]"/> +</segment> +</net> +<net name="DDR-DQ41" class="0"> +<segment> +<wire x1="153.67" y1="124.46" x2="154.94" y2="125.73" width="0.1524" layer="91"/> +<wire x1="154.94" y1="125.73" x2="154.94" y2="143.51" width="0.1524" layer="91"/> +<label x="154.6225" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[41]"/> +</segment> +</net> +<net name="DDR-DQ42" class="0"> +<segment> +<wire x1="156.21" y1="124.46" x2="157.48" y2="125.73" width="0.1524" layer="91"/> +<wire x1="157.48" y1="125.73" x2="157.48" y2="143.51" width="0.1524" layer="91"/> +<label x="157.1625" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[42]"/> +</segment> +</net> +<net name="DDR-DQ43" class="0"> +<segment> +<wire x1="158.75" y1="124.46" x2="160.02" y2="125.73" width="0.1524" layer="91"/> +<wire x1="160.02" y1="125.73" x2="160.02" y2="143.51" width="0.1524" layer="91"/> +<label x="159.7025" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[43]"/> +</segment> +</net> +<net name="DDR-DQ44" class="0"> +<segment> +<wire x1="161.29" y1="124.46" x2="162.56" y2="125.73" width="0.1524" layer="91"/> +<wire x1="162.56" y1="125.73" x2="162.56" y2="143.51" width="0.1524" layer="91"/> +<label x="162.2425" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[44]"/> +</segment> +</net> +<net name="DDR-DQ45" class="0"> +<segment> +<wire x1="163.83" y1="124.46" x2="165.1" y2="125.73" width="0.1524" layer="91"/> +<wire x1="165.1" y1="125.73" x2="165.1" y2="143.51" width="0.1524" layer="91"/> +<label x="164.7825" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[45]"/> +</segment> +</net> +<net name="DDR-DQ46" class="0"> +<segment> +<wire x1="166.37" y1="124.46" x2="167.64" y2="125.73" width="0.1524" layer="91"/> +<wire x1="167.64" y1="125.73" x2="167.64" y2="143.51" width="0.1524" layer="91"/> +<label x="167.3225" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[46]"/> +</segment> +</net> +<net name="DDR-DQ47" class="0"> +<segment> +<wire x1="168.91" y1="124.46" x2="170.18" y2="125.73" width="0.1524" layer="91"/> +<wire x1="170.18" y1="125.73" x2="170.18" y2="143.51" width="0.1524" layer="91"/> +<label x="169.8625" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[47]"/> +</segment> +</net> +<net name="DDR-DQ48" class="0"> +<segment> +<wire x1="171.45" y1="124.46" x2="172.72" y2="125.73" width="0.1524" layer="91"/> +<wire x1="172.72" y1="125.73" x2="172.72" y2="143.51" width="0.1524" layer="91"/> +<label x="172.4025" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[48]"/> +</segment> +</net> +<net name="DDR-DQ49" class="0"> +<segment> +<wire x1="173.99" y1="124.46" x2="175.26" y2="125.73" width="0.1524" layer="91"/> +<wire x1="175.26" y1="125.73" x2="175.26" y2="143.51" width="0.1524" layer="91"/> +<label x="174.9425" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[49]"/> +</segment> +</net> +<net name="DDR-DQ50" class="0"> +<segment> +<wire x1="176.53" y1="124.46" x2="177.8" y2="125.73" width="0.1524" layer="91"/> +<wire x1="177.8" y1="125.73" x2="177.8" y2="143.51" width="0.1524" layer="91"/> +<label x="177.4825" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[50]"/> +</segment> +</net> +<net name="DDR-DQ51" class="0"> +<segment> +<wire x1="179.07" y1="124.46" x2="180.34" y2="125.73" width="0.1524" layer="91"/> +<wire x1="180.34" y1="125.73" x2="180.34" y2="143.51" width="0.1524" layer="91"/> +<label x="180.0225" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[51]"/> +</segment> +</net> +<net name="DDR-DQ52" class="0"> +<segment> +<wire x1="181.61" y1="124.46" x2="182.88" y2="125.73" width="0.1524" layer="91"/> +<wire x1="182.88" y1="125.73" x2="182.88" y2="143.51" width="0.1524" layer="91"/> +<label x="182.5625" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[52]"/> +</segment> +</net> +<net name="DDR-DQ53" class="0"> +<segment> +<wire x1="184.15" y1="124.46" x2="185.42" y2="125.73" width="0.1524" layer="91"/> +<wire x1="185.42" y1="125.73" x2="185.42" y2="143.51" width="0.1524" layer="91"/> +<label x="185.1025" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[53]"/> +</segment> +</net> +<net name="DDR-DQ54" class="0"> +<segment> +<wire x1="186.69" y1="124.46" x2="187.96" y2="125.73" width="0.1524" layer="91"/> +<wire x1="187.96" y1="125.73" x2="187.96" y2="143.51" width="0.1524" layer="91"/> +<label x="187.6425" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[54]"/> +</segment> +</net> +<net name="DDR-DQ55" class="0"> +<segment> +<wire x1="189.23" y1="124.46" x2="190.5" y2="125.73" width="0.1524" layer="91"/> +<wire x1="190.5" y1="125.73" x2="190.5" y2="143.51" width="0.1524" layer="91"/> +<label x="190.1825" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[55]"/> +</segment> +</net> +<net name="DDR-DQ56" class="0"> +<segment> +<wire x1="191.77" y1="124.46" x2="193.04" y2="125.73" width="0.1524" layer="91"/> +<wire x1="193.04" y1="125.73" x2="193.04" y2="143.51" width="0.1524" layer="91"/> +<label x="192.7225" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[56]"/> +</segment> +</net> +<net name="DDR-DQ57" class="0"> +<segment> +<wire x1="194.31" y1="124.46" x2="195.58" y2="125.73" width="0.1524" layer="91"/> +<wire x1="195.58" y1="125.73" x2="195.58" y2="143.51" width="0.1524" layer="91"/> +<label x="195.2625" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[57]"/> +</segment> +</net> +<net name="DDR-DQ58" class="0"> +<segment> +<wire x1="196.85" y1="124.46" x2="198.12" y2="125.73" width="0.1524" layer="91"/> +<wire x1="198.12" y1="125.73" x2="198.12" y2="143.51" width="0.1524" layer="91"/> +<label x="197.8025" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[58]"/> +</segment> +</net> +<net name="DDR-DQ59" class="0"> +<segment> +<wire x1="199.39" y1="124.46" x2="200.66" y2="125.73" width="0.1524" layer="91"/> +<wire x1="200.66" y1="125.73" x2="200.66" y2="143.51" width="0.1524" layer="91"/> +<label x="200.3425" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[59]"/> +</segment> +</net> +<net name="DDR-DQ60" class="0"> +<segment> +<wire x1="201.93" y1="124.46" x2="203.2" y2="125.73" width="0.1524" layer="91"/> +<wire x1="203.2" y1="125.73" x2="203.2" y2="143.51" width="0.1524" layer="91"/> +<label x="202.8825" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[60]"/> +</segment> +</net> +<net name="DDR-DQ61" class="0"> +<segment> +<wire x1="204.47" y1="124.46" x2="205.74" y2="125.73" width="0.1524" layer="91"/> +<wire x1="205.74" y1="125.73" x2="205.74" y2="143.51" width="0.1524" layer="91"/> +<label x="205.4225" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[61]"/> +</segment> +</net> +<net name="DDR-DQ62" class="0"> +<segment> +<wire x1="207.01" y1="124.46" x2="208.28" y2="125.73" width="0.1524" layer="91"/> +<wire x1="208.28" y1="125.73" x2="208.28" y2="143.51" width="0.1524" layer="91"/> +<label x="207.9625" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[62]"/> +</segment> +</net> +<net name="DDR-DQ63" class="0"> +<segment> +<wire x1="209.55" y1="124.46" x2="210.82" y2="125.73" width="0.1524" layer="91"/> +<wire x1="210.82" y1="125.73" x2="210.82" y2="143.51" width="0.1524" layer="91"/> +<label x="210.5025" y="127.635" size="1.778" layer="92" rot="R90"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DQ[63]"/> +</segment> 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part="U6E1" gate="DDR2DATA" pin="DDR_DM[4]"/> +</segment> +</net> +<net name="DDR-DM2" class="0"> +<segment> +<wire x1="218.44" y1="124.46" x2="219.71" y2="125.73" width="0.1524" layer="91"/> +<wire x1="219.71" y1="125.73" x2="219.71" y2="143.51" width="0.1524" layer="91"/> +<label x="217.4875" y="140.97" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DM[2]"/> +</segment> +</net> +<net name="DDR-DM3" class="0"> +<segment> +<wire x1="220.98" y1="124.46" x2="222.25" y2="125.73" width="0.1524" layer="91"/> +<wire x1="222.25" y1="125.73" x2="222.25" y2="143.51" width="0.1524" layer="91"/> +<label x="220.0275" y="140.97" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DM[3]"/> +</segment> +</net> +<net name="DDR-DM1" class="0"> +<segment> +<wire x1="215.9" y1="124.46" x2="217.17" y2="125.73" width="0.1524" layer="91"/> +<wire x1="217.17" y1="125.73" x2="217.17" y2="143.51" width="0.1524" layer="91"/> +<label x="214.9475" y="140.97" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DM[1]"/> +</segment> +</net> +<net name="DDR-DM0" class="0"> +<segment> +<wire x1="213.36" y1="124.46" x2="214.63" y2="125.73" width="0.1524" layer="91"/> +<wire x1="214.63" y1="125.73" x2="214.63" y2="143.51" width="0.1524" layer="91"/> +<label x="212.4075" y="140.97" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DM[0]"/> +</segment> +</net> +<net name="DDR-DM5" class="0"> +<segment> +<wire x1="226.06" y1="124.46" x2="227.33" y2="125.73" width="0.1524" layer="91"/> +<wire x1="227.33" y1="125.73" x2="227.33" y2="143.51" width="0.1524" layer="91"/> +<label x="225.1075" y="140.97" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DM[5]"/> +</segment> +</net> +<net name="DDR-DM8" class="0"> +<segment> +<wire x1="234.95" y1="143.51" x2="234.95" y2="125.73" width="0.1524" layer="91"/> +<wire x1="234.95" y1="125.73" x2="233.68" y2="124.46" width="0.1524" layer="91"/> +<label x="233.045" y="140.97" size="1.778" layer="92" rot="R270"/> +<pinref part="U6E1" gate="DDR2DATA" pin="DDR_DM[8]"/> +</segment> +</net> +<net name="DDR-BA2" class="0"> +<segment> +<wire x1="132.08" y1="68.58" x2="133.35" y2="67.31" width="0.1524" layer="91"/> +<wire x1="133.35" y1="67.31" x2="151.13" y2="67.31" width="0.1524" layer="91"/> +<label x="133.6675" y="69.215" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_BA[2]"/> +</segment> +</net> +<net name="DDR-BA1" class="0"> +<segment> +<wire x1="132.08" y1="71.12" x2="133.35" y2="69.85" width="0.1524" layer="91"/> +<wire x1="133.35" y1="69.85" x2="151.13" y2="69.85" width="0.1524" layer="91"/> +<label x="133.6675" y="71.755" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_BA[1]"/> +</segment> +</net> +<net name="DDR-BA0" class="0"> +<segment> +<wire x1="132.08" y1="73.66" x2="133.35" y2="72.39" width="0.1524" layer="91"/> +<wire x1="133.35" y1="72.39" x2="151.13" y2="72.39" width="0.1524" layer="91"/> +<label x="133.6675" y="74.295" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_BA[0]"/> +</segment> +</net> +<net name="DDR-CKN2" class="0"> +<segment> +<wire x1="203.2" y1="39.37" x2="204.47" y2="38.1" width="0.1524" layer="91"/> +<wire x1="204.47" y1="38.1" x2="222.25" y2="38.1" width="0.1524" layer="91"/> +<label x="205.74" y="38.4175" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CLK" pin="DDR_CK[2]#"/> +</segment> +</net> +<net name="DDR-CKP2" class="0"> +<segment> +<wire x1="203.2" y1="55.88" x2="204.47" y2="54.61" width="0.1524" layer="91"/> +<wire x1="204.47" y1="54.61" x2="222.25" y2="54.61" width="0.1524" layer="91"/> +<label x="205.74" y="54.9275" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CLK" pin="DDR_CK[2]"/> +</segment> +</net> +<net name="DDR-CKN1" class="0"> +<segment> +<wire x1="203.2" y1="41.91" x2="204.47" y2="40.64" width="0.1524" layer="91"/> +<wire x1="204.47" y1="40.64" x2="222.25" y2="40.64" width="0.1524" layer="91"/> +<label x="205.74" y="40.9575" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CLK" pin="DDR_CK[1]#"/> +</segment> +</net> +<net name="DDR-CKP1" class="0"> +<segment> +<wire x1="203.2" y1="58.42" x2="204.47" y2="57.15" width="0.1524" layer="91"/> +<wire x1="204.47" y1="57.15" x2="222.25" y2="57.15" width="0.1524" layer="91"/> +<label x="205.74" y="57.4675" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CLK" pin="DDR_CK[1]"/> +</segment> +</net> +<net name="DDR-CKN0" class="0"> +<segment> +<wire x1="203.2" y1="44.45" x2="204.47" y2="43.18" width="0.1524" layer="91"/> +<wire x1="204.47" y1="43.18" x2="222.25" y2="43.18" width="0.1524" layer="91"/> +<label x="205.74" y="43.4975" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CLK" pin="DDR_CK[0]#"/> +</segment> +</net> +<net name="DDR-CKP0" class="0"> +<segment> +<wire x1="203.2" y1="60.96" x2="204.47" y2="59.69" width="0.1524" layer="91"/> +<wire x1="204.47" y1="59.69" x2="222.25" y2="59.69" width="0.1524" layer="91"/> +<label x="205.74" y="60.0075" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CLK" pin="DDR_CK[0]"/> +</segment> +</net> +<net name="DDR-CKE1" class="0"> +<segment> +<wire x1="132.08" y1="22.86" x2="133.35" y2="21.59" width="0.1524" layer="91"/> +<wire x1="133.35" y1="21.59" x2="151.13" y2="21.59" width="0.1524" layer="91"/> +<label x="134.62" y="21.9075" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_CKE[1]"/> +</segment> +</net> +<net name="DDR-CKE0" class="0"> +<segment> +<wire x1="132.08" y1="25.4" x2="133.35" y2="24.13" width="0.1524" layer="91"/> +<wire x1="133.35" y1="24.13" x2="151.13" y2="24.13" width="0.1524" layer="91"/> +<label x="134.62" y="24.4475" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_CKE[0]"/> +</segment> +</net> +<net name="DDRA-ECC0" class="0"> +<segment> +<wire x1="73.66" y1="110.49" x2="49.53" y2="110.49" width="0.1524" layer="91"/> +<wire x1="49.53" y1="110.49" x2="48.26" y2="111.76" width="0.1524" layer="91"/> +<label x="50.4825" y="112.395" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ECC[0]"/> +</segment> +</net> +<net name="DDRA-ECC1" class="0"> +<segment> +<wire x1="73.66" y1="107.95" x2="49.53" y2="107.95" width="0.1524" layer="91"/> +<wire x1="49.53" y1="107.95" x2="48.26" y2="109.22" width="0.1524" layer="91"/> +<label x="50.4825" y="109.855" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ECC[1]"/> +</segment> +</net> +<net name="DDRA-ECC2" class="0"> +<segment> +<wire x1="73.66" y1="105.41" x2="49.53" y2="105.41" width="0.1524" layer="91"/> +<wire x1="49.53" y1="105.41" x2="48.26" y2="106.68" width="0.1524" layer="91"/> +<label x="50.4825" y="107.315" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ECC[2]"/> +</segment> +</net> +<net name="DDRA-ECC3" class="0"> +<segment> +<wire x1="73.66" y1="102.87" x2="49.53" y2="102.87" width="0.1524" layer="91"/> +<wire x1="49.53" y1="102.87" x2="48.26" y2="104.14" width="0.1524" layer="91"/> +<label x="50.4825" y="104.775" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ECC[3]"/> +</segment> +</net> +<net name="DDRA-ECC4" class="0"> +<segment> +<wire x1="73.66" y1="100.33" x2="49.53" y2="100.33" width="0.1524" layer="91"/> +<wire x1="49.53" y1="100.33" x2="48.26" y2="101.6" width="0.1524" layer="91"/> +<label x="50.4825" y="102.235" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ECC[4]"/> +</segment> +</net> +<net name="DDRA-ECC5" class="0"> +<segment> +<wire x1="73.66" y1="97.79" x2="49.53" y2="97.79" width="0.1524" layer="91"/> +<wire x1="49.53" y1="97.79" x2="48.26" y2="99.06" width="0.1524" layer="91"/> +<label x="50.4825" y="99.695" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ECC[5]"/> +</segment> +</net> +<net name="DDRA-ECC6" class="0"> +<segment> +<wire x1="73.66" y1="95.25" x2="49.53" y2="95.25" width="0.1524" layer="91"/> +<wire x1="49.53" y1="95.25" x2="48.26" y2="96.52" width="0.1524" layer="91"/> +<label x="50.4825" y="97.155" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ECC[6]"/> +</segment> +</net> +<net name="DDRA-ECC7" class="0"> +<segment> +<wire x1="73.66" y1="92.71" x2="49.53" y2="92.71" width="0.1524" layer="91"/> +<wire x1="49.53" y1="92.71" x2="48.26" y2="93.98" width="0.1524" layer="91"/> +<label x="50.4825" y="94.615" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ECC[7]"/> +</segment> +</net> +<net name="DDR-DQSN7" class="0"> +<segment> +<wire x1="48.26" y1="48.26" x2="49.53" y2="46.99" width="0.1524" layer="91"/> +<wire x1="49.53" y1="46.99" x2="73.66" y2="46.99" width="0.1524" layer="91"/> +<label x="50.8" y="47.3075" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[7]#"/> +</segment> +</net> +<net name="DDR-DQSP7" class="0"> +<segment> +<wire x1="48.26" y1="72.39" x2="49.53" y2="71.12" width="0.1524" layer="91"/> +<wire x1="49.53" y1="71.12" x2="73.66" y2="71.12" width="0.1524" layer="91"/> +<label x="50.8" y="71.4375" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[7]"/> +</segment> +</net> +<net name="DDR-DQSN6" class="0"> +<segment> +<wire x1="48.26" y1="50.8" x2="49.53" y2="49.53" width="0.1524" layer="91"/> +<wire x1="49.53" y1="49.53" x2="73.66" y2="49.53" width="0.1524" layer="91"/> +<label x="50.8" y="49.8475" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[6]#"/> +</segment> +</net> +<net name="DDR-DQSP6" class="0"> +<segment> +<wire x1="48.26" y1="74.93" x2="49.53" y2="73.66" width="0.1524" layer="91"/> +<wire x1="49.53" y1="73.66" x2="73.66" y2="73.66" width="0.1524" layer="91"/> +<label x="50.8" y="73.9775" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[6]"/> +</segment> +</net> +<net name="DDR-DQSN5" class="0"> +<segment> +<wire x1="48.26" y1="53.34" x2="49.53" y2="52.07" width="0.1524" layer="91"/> +<wire x1="49.53" y1="52.07" x2="73.66" y2="52.07" width="0.1524" layer="91"/> +<label x="50.8" y="52.3875" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[5]#"/> +</segment> +</net> +<net name="DDR-DQSP5" class="0"> +<segment> +<wire x1="48.26" y1="77.47" x2="49.53" y2="76.2" width="0.1524" layer="91"/> +<wire x1="49.53" y1="76.2" x2="73.66" y2="76.2" width="0.1524" layer="91"/> +<label x="50.8" y="76.5175" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[5]"/> +</segment> +</net> +<net name="DDR-DQSN4" class="0"> +<segment> +<wire x1="48.26" y1="55.88" x2="49.53" y2="54.61" width="0.1524" layer="91"/> +<wire x1="49.53" y1="54.61" x2="73.66" y2="54.61" width="0.1524" layer="91"/> +<label x="50.8" y="54.9275" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[4]#"/> +</segment> +</net> +<net name="DDR-DQSP4" class="0"> +<segment> +<wire x1="48.26" y1="80.01" x2="49.53" y2="78.74" width="0.1524" layer="91"/> +<wire x1="49.53" y1="78.74" x2="73.66" y2="78.74" width="0.1524" layer="91"/> +<label x="50.8" y="79.0575" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[4]"/> +</segment> +</net> +<net name="DDR-DQSN3" class="0"> +<segment> +<wire x1="48.26" y1="58.42" x2="49.53" y2="57.15" width="0.1524" layer="91"/> +<wire x1="49.53" y1="57.15" x2="73.66" y2="57.15" width="0.1524" layer="91"/> +<label x="50.8" y="57.4675" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[3]#"/> +</segment> +</net> +<net name="DDR-DQSP3" class="0"> +<segment> +<wire x1="48.26" y1="82.55" x2="49.53" y2="81.28" width="0.1524" layer="91"/> +<wire x1="49.53" y1="81.28" x2="73.66" y2="81.28" width="0.1524" layer="91"/> +<label x="50.8" y="81.5975" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[3]"/> +</segment> +</net> +<net name="DDR-DQSN2" class="0"> +<segment> +<wire x1="48.26" y1="60.96" x2="49.53" y2="59.69" width="0.1524" layer="91"/> +<wire x1="49.53" y1="59.69" x2="73.66" y2="59.69" width="0.1524" layer="91"/> +<label x="50.8" y="60.0075" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[2]#"/> +</segment> +</net> +<net name="DDR-DQSP2" class="0"> +<segment> +<wire x1="48.26" y1="85.09" x2="49.53" y2="83.82" width="0.1524" layer="91"/> +<wire x1="49.53" y1="83.82" x2="73.66" y2="83.82" width="0.1524" layer="91"/> +<label x="50.8" y="84.1375" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[2]"/> +</segment> +</net> +<net name="DDR-DQSN1" class="0"> +<segment> +<wire x1="48.26" y1="63.5" x2="49.53" y2="62.23" width="0.1524" layer="91"/> +<wire x1="49.53" y1="62.23" x2="73.66" y2="62.23" width="0.1524" layer="91"/> +<label x="50.8" y="62.5475" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[1]#"/> +</segment> +</net> +<net name="DDR-DQSP1" class="0"> +<segment> +<wire x1="48.26" y1="87.63" x2="49.53" y2="86.36" width="0.1524" layer="91"/> +<wire x1="49.53" y1="86.36" x2="73.66" y2="86.36" width="0.1524" layer="91"/> +<label x="50.8" y="86.6775" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[1]"/> +</segment> +</net> +<net name="DDR-DQSN0" class="0"> +<segment> +<wire x1="48.26" y1="66.04" x2="49.53" y2="64.77" width="0.1524" layer="91"/> +<wire x1="49.53" y1="64.77" x2="73.66" y2="64.77" width="0.1524" layer="91"/> +<label x="50.8" y="65.0875" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[0]#"/> +</segment> +</net> +<net name="DDR-DQSP0" class="0"> +<segment> +<wire x1="48.26" y1="90.17" x2="49.53" y2="88.9" width="0.1524" layer="91"/> +<wire x1="49.53" y1="88.9" x2="73.66" y2="88.9" width="0.1524" layer="91"/> +<label x="50.8" y="89.2175" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[0]"/> +</segment> +</net> +<net name="DDR-CS0" class="0"> +<segment> +<wire x1="132.08" y1="91.44" x2="133.35" y2="90.17" width="0.1524" layer="91"/> +<wire x1="133.35" y1="90.17" x2="151.13" y2="90.17" width="0.1524" layer="91"/> +<label x="134.62" y="90.4875" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_CS[0]#"/> +</segment> +</net> +<net name="DDR-CS1" class="0"> +<segment> +<wire x1="132.08" y1="88.9" x2="133.35" y2="87.63" width="0.1524" layer="91"/> +<wire x1="133.35" y1="87.63" x2="151.13" y2="87.63" width="0.1524" layer="91"/> +<label x="134.62" y="87.9475" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_CS[1]#"/> +</segment> +</net> +<net name="DDR-ODT0" class="0"> +<segment> +<wire x1="48.26" y1="41.91" x2="49.53" y2="40.64" width="0.1524" layer="91"/> +<wire x1="49.53" y1="40.64" x2="73.66" y2="40.64" width="0.1524" layer="91"/> +<label x="64.77" y="40.9575" size="1.778" layer="92" rot="MR0"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ODT0"/> +</segment> +</net> +<net name="DDR-ODT1" class="0"> +<segment> +<wire x1="48.26" y1="38.1" x2="49.53" y2="36.83" width="0.1524" layer="91"/> +<wire x1="49.53" y1="36.83" x2="73.66" y2="36.83" width="0.1524" layer="91"/> +<label x="64.77" y="37.1475" size="1.778" layer="92" rot="MR0"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_ODT1"/> +</segment> +</net> +<net name="N$388" class="0"> +<segment> +<wire x1="73.66" y1="16.51" x2="66.04" y2="16.51" width="0.1524" layer="91"/> +<pinref part="R4P4" gate="R" pin="2"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_SLEWCRES"/> +</segment> +</net> +<net name="N$389" class="0"> +<segment> +<wire x1="73.66" y1="20.32" x2="66.04" y2="20.32" width="0.1524" layer="91"/> +<pinref part="R4P3" gate="R" pin="2"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DRVCRES"/> +</segment> +</net> +<net name="N$390" class="0"> +<segment> +<wire x1="73.66" y1="24.13" x2="39.37" y2="24.13" width="0.1524" layer="91"/> +<wire x1="39.37" y1="24.13" x2="25.4" y2="24.13" width="0.1524" layer="91"/> +<wire x1="39.37" y1="24.13" x2="39.37" y2="21.59" width="0.1524" layer="91"/> +<junction x="39.37" y="24.13"/> +<pinref part="R3P1" gate="R" pin="2"/> +<pinref part="C3P2" gate="C" pin="1"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_CRES[2]"/> +</segment> +</net> +<net name="N$464" class="0"> +<segment> +<wire x1="66.04" y1="26.67" x2="73.66" y2="26.67" width="0.1524" layer="91"/> +<pinref part="R4P5" gate="R" pin="2"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_CRES[1]"/> +</segment> +</net> +<net name="N$468" class="0"> +<segment> +<wire x1="73.66" y1="33.02" x2="66.04" y2="33.02" width="0.1524" layer="91"/> +<pinref part="R4P2" gate="R" pin="2"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_RCOMPX"/> +</segment> +</net> +<net name="N$501" class="0"> +<segment> +<wire x1="55.88" y1="33.02" x2="48.26" y2="33.02" width="0.1524" layer="91"/> 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y2="13.97" width="0.1524" layer="91"/> +<pinref part="U$435" gate="G$1" pin="GND"/> +<pinref part="C3P2" gate="C" pin="2"/> +</segment> +</net> +<net name="DDR-DQSP8" class="0"> +<segment> +<wire x1="48.26" y1="69.85" x2="49.53" y2="68.58" width="0.1524" layer="91"/> +<wire x1="49.53" y1="68.58" x2="73.66" y2="68.58" width="0.1524" layer="91"/> +<label x="50.8" y="68.8975" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[8]"/> +</segment> +</net> +<net name="DDR-DQSN8" class="0"> +<segment> +<wire x1="48.26" y1="45.72" x2="49.53" y2="44.45" width="0.1524" layer="91"/> +<wire x1="49.53" y1="44.45" x2="73.66" y2="44.45" width="0.1524" layer="91"/> +<label x="50.8" y="44.7675" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2CMP" pin="DDR_DQS[8]#"/> +</segment> +</net> +<net name="DDR-WE" class="0"> +<segment> +<wire x1="132.08" y1="77.47" x2="133.35" y2="76.2" width="0.1524" layer="91"/> +<wire x1="133.35" y1="76.2" x2="151.13" y2="76.2" width="0.1524" layer="91"/> +<label x="134.62" y="76.5175" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_WE#"/> +</segment> +</net> +<net name="DDR-RAS" class="0"> +<segment> +<wire x1="132.08" y1="85.09" x2="133.35" y2="83.82" width="0.1524" layer="91"/> +<wire x1="133.35" y1="83.82" x2="151.13" y2="83.82" width="0.1524" layer="91"/> +<label x="134.62" y="84.1375" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_RAS#"/> +</segment> +</net> +<net name="DDR-CAS" class="0"> +<segment> +<wire x1="132.08" y1="81.28" x2="133.35" y2="80.01" width="0.1524" layer="91"/> +<wire x1="133.35" y1="80.01" x2="151.13" y2="80.01" width="0.1524" layer="91"/> +<label x="134.62" y="80.3275" size="1.778" layer="92"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_CAS#"/> +</segment> +</net> +<net name="DDR-MA14" class="0"> +<segment> +<wire x1="132.08" y1="29.21" x2="133.35" y2="27.94" width="0.1524" layer="91"/> +<wire x1="133.35" y1="27.94" x2="151.13" y2="27.94" width="0.1524" layer="91"/> +<label x="134.62" y="30.1625" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[14]"/> +</segment> +</net> +<net name="DDR-MA13" class="0"> +<segment> +<wire x1="132.08" y1="31.75" x2="133.35" y2="30.48" width="0.1524" layer="91"/> +<wire x1="133.35" y1="30.48" x2="151.13" y2="30.48" width="0.1524" layer="91"/> +<label x="134.62" y="32.7025" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[13]"/> +</segment> +</net> +<net name="DDR-MA12" class="0"> +<segment> +<wire x1="132.08" y1="34.29" x2="133.35" y2="33.02" width="0.1524" layer="91"/> +<wire x1="133.35" y1="33.02" x2="151.13" y2="33.02" width="0.1524" layer="91"/> +<label x="134.62" y="35.2425" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[12]"/> +</segment> +</net> +<net name="DDR-MA11" class="0"> +<segment> +<wire x1="132.08" y1="36.83" x2="133.35" y2="35.56" width="0.1524" layer="91"/> +<wire x1="133.35" y1="35.56" x2="151.13" y2="35.56" width="0.1524" layer="91"/> +<label x="134.62" y="37.7825" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[11]"/> +</segment> +</net> +<net name="DDR-MA10" class="0"> +<segment> +<wire x1="132.08" y1="39.37" x2="133.35" y2="38.1" width="0.1524" layer="91"/> +<wire x1="133.35" y1="38.1" x2="151.13" y2="38.1" width="0.1524" layer="91"/> +<label x="134.62" y="40.3225" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[10]"/> +</segment> +</net> +<net name="DDR-MA9" class="0"> +<segment> +<wire x1="132.08" y1="41.91" x2="133.35" y2="40.64" width="0.1524" layer="91"/> +<wire x1="133.35" y1="40.64" x2="151.13" y2="40.64" width="0.1524" layer="91"/> +<label x="134.62" y="42.8625" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[9]"/> +</segment> +</net> +<net name="DDR-MA8" class="0"> +<segment> +<wire x1="132.08" y1="44.45" x2="133.35" y2="43.18" width="0.1524" layer="91"/> +<wire x1="133.35" y1="43.18" x2="151.13" y2="43.18" width="0.1524" layer="91"/> +<label x="134.62" y="45.4025" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[8]"/> +</segment> +</net> +<net name="DDR-MA7" class="0"> +<segment> +<wire x1="132.08" y1="46.99" x2="133.35" y2="45.72" width="0.1524" layer="91"/> +<wire x1="133.35" y1="45.72" x2="151.13" y2="45.72" width="0.1524" layer="91"/> +<label x="134.62" y="47.9425" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[7]"/> +</segment> +</net> +<net name="DDR-MA6" class="0"> +<segment> +<wire x1="132.08" y1="49.53" x2="133.35" y2="48.26" width="0.1524" layer="91"/> +<wire x1="133.35" y1="48.26" x2="151.13" y2="48.26" width="0.1524" layer="91"/> +<label x="134.62" y="50.4825" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[6]"/> +</segment> +</net> +<net name="DDR-MA5" class="0"> +<segment> +<wire x1="132.08" y1="52.07" x2="133.35" y2="50.8" width="0.1524" layer="91"/> +<wire x1="133.35" y1="50.8" x2="151.13" y2="50.8" width="0.1524" layer="91"/> +<label x="134.62" y="53.0225" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[5]"/> +</segment> +</net> +<net name="DDR-MA4" class="0"> +<segment> +<wire x1="132.08" y1="54.61" x2="133.35" y2="53.34" width="0.1524" layer="91"/> +<wire x1="133.35" y1="53.34" x2="151.13" y2="53.34" width="0.1524" layer="91"/> +<label x="134.62" y="55.5625" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[4]"/> +</segment> +</net> +<net name="DDR-MA3" class="0"> +<segment> +<wire x1="132.08" y1="57.15" x2="133.35" y2="55.88" width="0.1524" layer="91"/> +<wire x1="133.35" y1="55.88" x2="151.13" y2="55.88" width="0.1524" layer="91"/> +<label x="134.62" y="58.1025" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[3]"/> +</segment> +</net> +<net name="DDR-MA2" class="0"> +<segment> +<wire x1="132.08" y1="59.69" x2="133.35" y2="58.42" width="0.1524" layer="91"/> +<wire x1="133.35" y1="58.42" x2="151.13" y2="58.42" width="0.1524" layer="91"/> +<label x="134.62" y="60.6425" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[2]"/> +</segment> +</net> +<net name="DDR-MA0" class="0"> +<segment> +<wire x1="132.08" y1="64.77" x2="133.35" y2="63.5" width="0.1524" layer="91"/> +<wire x1="133.35" y1="63.5" x2="151.13" y2="63.5" width="0.1524" layer="91"/> +<label x="134.62" y="65.7225" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[0]"/> +</segment> +</net> +<net name="DDR-MA1" class="0"> +<segment> +<wire x1="132.08" y1="62.23" x2="133.35" y2="60.96" width="0.1524" layer="91"/> +<wire x1="133.35" y1="60.96" x2="151.13" y2="60.96" width="0.1524" layer="91"/> +<label x="134.62" y="63.1825" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="DDR2ACCESS" pin="DDR_A[1]"/> +</segment> +</net> +<net name="V1P8-DDR" class="0"> +<segment> +<wire x1="15.24" y1="24.13" x2="6.35" y2="24.13" width="0.1524" layer="91"/> +<wire x1="6.35" y1="24.13" x2="6.35" y2="31.75" width="0.1524" layer="91"/> +<pinref part="R3P1" gate="R" pin="1"/> +<pinref part="U$28" gate="V1P8-DDR" pin="V1P8-DDR"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="96.52" y="162.56" size="1.778" layer="94">EP80579 : MDC/MDIO 2.5V IO driver (cf Page 209 PDG May 2010)</text> +<text x="96.52" y="160.02" size="1.778" layer="94">EP80579 : GBE RGMII v1.3 RX/TX_DATA 2.5V CMOS level (cf p1879 DS August 2009)</text> +<text x="104.14" y="170.18" size="3.81" layer="94">ETHERNET 1/5</text> +</plain> +<instances> +<instance part="R7E17" gate="R" x="204.47" y="104.14" smashed="yes" rot="MR180"> +<attribute name="NAME" x="198.12" y="105.41" size="1.778" layer="95"/> +<attribute name="VALUE" x="207.01" y="105.41" size="1.778" layer="96"/> +<attribute name="POWER" x="204.47" y="104.14" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="204.47" y="104.14" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$575" gate="G$1" x="222.25" y="102.87" rot="MR0"/> +<instance part="R5T6" gate="R" x="127" y="129.54" smashed="yes" rot="MR180"> +<attribute name="NAME" x="127" y="128.27" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="123.19" y="128.27" size="1.778" layer="96" rot="MR180"/> +<attribute name="POWER" x="127" y="129.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="FRAME15" gate="G$1" x="0" y="0"/> +<instance part="FRAME15" gate="G$2" x="180.34" y="0"/> +<instance part="U6E1" gate="GBE" x="172.72" y="96.52"/> +<instance part="R7E18" gate="R" x="217.17" y="134.62" rot="R270"> +<attribute name="POWER" x="217.17" y="134.62" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="217.17" y="134.62" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R7E19" gate="R" x="231.14" y="120.65" rot="R180"> +<attribute name="POWER" x="231.14" y="120.65" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="231.14" y="120.65" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$579" gate="G$1" x="243.84" y="120.65" rot="R90"/> +<instance part="R2R11" gate="R" x="146.05" y="69.85" smashed="yes"> +<attribute name="NAME" x="147.32" y="71.4375" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="147.955" y="71.4375" size="1.778" layer="96"/> +<attribute name="POWER" x="146.05" y="69.85" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3R16" gate="R" x="210.82" y="88.9" smashed="yes" rot="MR180"> +<attribute name="POWER" x="210.82" y="88.9" size="1.778" layer="96" display="off"/> +<attribute name="DNP" x="208.788" y="92.202" size="1.778" layer="96" rot="MR180"/> +<attribute name="NAME" x="207.3275" y="89.2175" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="213.995" y="89.2175" size="1.778" layer="96"/> +</instance> +<instance part="R3R22" gate="R" x="210.82" y="86.36" rot="MR180"> +<attribute name="POWER" x="210.82" y="86.36" size="1.778" layer="96" display="off"/> +</instance> +<instance part="Y8C1" gate="G$1" x="114.3" y="33.02" smashed="yes"> +<attribute name="NAME" x="110.49" y="35.306" size="1.778" layer="95"/> +<attribute name="VALUE" x="110.49" y="38.1" size="1.778" layer="96"/> +</instance> +<instance part="C8C5" gate="C" x="107.95" y="27.94" smashed="yes"> +<attribute name="NAME" x="109.22" y="27.94" size="1.778" layer="95"/> +<attribute name="VALUE" x="109.22" y="22.86" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="107.95" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="107.95" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="107.95" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C8D1" gate="C" x="121.92" y="27.94" smashed="yes"> +<attribute name="NAME" x="123.19" y="22.86" size="1.778" layer="95"/> +<attribute name="VALUE" x="123.19" y="27.94" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="121.92" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="121.92" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="121.92" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$34" gate="G$1" x="115.57" y="19.05"/> +<instance part="R8E26" gate="R" x="53.34" y="48.26" rot="MR180"> +<attribute name="POWER" x="53.34" y="48.26" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="R8E17" gate="R" x="146.05" y="41.91" rot="R270"> +<attribute name="POWER" x="146.05" y="41.91" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$141" gate="PW-VCC3" x="168.91" y="71.12"/> +<instance part="U$152" gate="G$1" x="146.05" y="21.59"/> +<instance part="R8E3" gate="R" x="152.4" y="41.91" rot="R270"> +<attribute name="DNP" x="152.4" y="41.91" size="1.778" layer="96"/> +<attribute name="POWER" x="152.4" y="41.91" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8E18" gate="R" x="154.94" y="62.23" rot="R180"> +<attribute name="POWER" x="154.94" y="62.23" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8E21" gate="R" x="154.94" y="59.69" rot="R180"> +<attribute name="POWER" x="154.94" y="59.69" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8E23" gate="R" x="154.94" y="64.77" rot="R180"> +<attribute name="POWER" x="154.94" y="64.77" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8C3" gate="R" x="68.58" y="60.96" smashed="yes"> +<attribute name="NAME" x="65.405" y="61.2775" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="71.755" y="61.2775" size="1.778" layer="96"/> +<attribute name="POWER" x="68.58" y="60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2N29" gate="R" x="68.58" y="58.42" smashed="yes"> +<attribute name="NAME" x="65.405" y="58.7375" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="71.755" y="58.7375" size="1.778" layer="96"/> +<attribute name="DNP" x="73.66" y="58.7375" size="1.778" layer="96"/> +<attribute name="POWER" x="68.58" y="58.42" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2N26" gate="R" x="68.58" y="55.88" smashed="yes"> +<attribute name="NAME" x="65.405" y="56.1975" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="71.755" y="56.1975" size="1.778" layer="96"/> +<attribute name="POWER" x="68.58" y="55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2N37" gate="R" x="68.58" y="53.34" smashed="yes"> +<attribute name="NAME" x="65.405" y="53.6575" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="71.755" y="53.6575" size="1.778" layer="96"/> +<attribute name="DNP" x="73.66" y="53.6575" size="1.778" layer="96"/> +<attribute name="POWER" x="68.58" y="53.34" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$153" gate="G$1" x="87.63" y="41.91"/> +<instance part="U8D1" gate="CORE" x="116.84" y="60.96"/> +<instance part="R2P3" gate="R" x="68.58" y="66.04"> +<attribute name="POWER" x="68.58" y="66.04" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2N34" gate="R" x="68.58" y="76.2" rot="MR180"> +<attribute name="POWER" x="68.58" y="76.2" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="U$377" gate="G$1" x="53.34" y="66.04"/> +<instance part="R8E2" gate="R" x="123.19" y="104.14" smashed="yes" rot="R180"> +<attribute name="DNP" x="120.9675" y="100.965" size="1.778" layer="96"/> +<attribute name="POWER" x="123.19" y="104.14" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="126.6825" y="104.4575" size="1.778" layer="95"/> +<attribute name="VALUE" x="120.015" y="104.4575" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="R7E20" gate="R" x="123.19" y="87.63" smashed="yes" rot="MR180"> +<attribute name="DNP" x="120.65" y="86.36" size="1.778" layer="96" rot="MR180"/> +<attribute name="POWER" x="123.19" y="87.63" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="NAME" x="119.6975" y="87.9475" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="126.365" y="87.9475" size="1.778" layer="96"/> +</instance> +<instance part="U$427" gate="G$1" x="104.14" y="86.36" rot="MR0"/> +<instance part="U$222" gate="G$1" x="217.17" y="149.86"/> +<instance part="U$86" gate="G$1" x="228.6" y="96.52"/> +<instance part="U$106" gate="G$1" x="52.07" y="78.74"/> +<instance part="U$109" gate="G$1" x="22.86" y="49.53"/> +<instance part="U$41" gate="G$1" x="101.6" y="109.22"/> +<instance part="R1N6" gate="R" x="146.05" y="116.84" smashed="yes" rot="MR90"> +<attribute name="NAME" x="143.51" y="118.11" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="143.51" y="114.3" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="146.05" y="116.84" size="1.778" layer="96" rot="MR90" display="off"/> +</instance> +<instance part="U$150" gate="G$1" x="146.05" y="106.68" rot="MR0"/> +<instance part="R8U25" gate="R" x="127" y="134.62" smashed="yes" rot="MR180"> +<attribute name="NAME" x="119.38" y="135.89" size="1.778" layer="95"/> +<attribute name="VALUE" x="134.62" y="135.89" size="1.778" layer="96" rot="MR0"/> +<attribute name="POWER" x="127" y="134.62" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="R3R18" gate="R" x="210.82" y="93.98" rot="MR180"> +<attribute name="POWER" x="210.82" y="93.98" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$134" gate="G$1" x="219.71" y="93.98" rot="MR270"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="236.22" y1="120.65" x2="242.57" y2="120.65" width="0.1524" layer="91"/> +<pinref part="R7E19" gate="R" pin="1"/> +<pinref part="U$579" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="222.25" y1="104.14" x2="209.55" y2="104.14" width="0.1524" layer="91"/> +<pinref part="R7E17" gate="R" pin="2"/> +<pinref part="U$575" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="107.95" y1="22.86" x2="107.95" y2="21.59" width="0.1524" layer="91"/> +<wire x1="107.95" y1="21.59" x2="115.57" y2="21.59" width="0.1524" layer="91"/> +<wire x1="115.57" y1="21.59" x2="121.92" y2="21.59" width="0.1524" layer="91"/> +<wire x1="121.92" y1="21.59" x2="121.92" y2="22.86" width="0.1524" layer="91"/> +<wire x1="115.57" y1="20.32" x2="115.57" y2="21.59" width="0.1524" layer="91"/> +<junction x="115.57" y="21.59"/> +<pinref part="C8C5" gate="C" pin="1"/> +<pinref part="C8D1" gate="C" pin="1"/> +<pinref part="U$34" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="146.05" y1="22.86" x2="146.05" y2="25.4" width="0.1524" layer="91"/> +<wire x1="146.05" y1="25.4" x2="146.05" y2="36.83" width="0.1524" layer="91"/> +<wire x1="152.4" y1="36.83" x2="152.4" y2="25.4" width="0.1524" layer="91"/> +<wire x1="152.4" y1="25.4" x2="146.05" y2="25.4" width="0.1524" layer="91"/> +<junction x="146.05" y="25.4"/> +<pinref part="R8E17" gate="R" pin="2"/> +<pinref part="U$152" gate="G$1" pin="GND"/> +<pinref part="R8E3" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="87.63" y1="43.18" x2="87.63" y2="44.45" width="0.1524" layer="91"/> +<pinref part="U$153" gate="G$1" pin="GND"/> +<pinref part="U8D1" gate="CORE" pin="VSSC"/> +</segment> +<segment> +<wire x1="104.14" y1="87.63" x2="118.11" y2="87.63" width="0.1524" layer="91"/> +<pinref part="R7E20" gate="R" pin="1"/> +<pinref part="U$427" gate="G$1" pin="GND"/> +</segment> +<segment> +<pinref part="R1N6" gate="R" pin="1"/> +<pinref part="U$150" gate="G$1" pin="GND"/> +<wire x1="146.05" y1="107.95" x2="146.05" y2="111.76" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="R3R18" gate="R" pin="2"/> +<pinref part="U$134" gate="G$1" pin="GND"/> +<wire x1="218.44" y1="93.98" x2="215.9" y2="93.98" width="0.1524" layer="91"/> +</segment> +</net> +<net name="GBE-RCOMPP" class="0"> +<segment> +<wire x1="226.06" y1="120.65" x2="215.9" y2="120.65" width="0.1524" layer="91"/> +<wire x1="215.9" y1="120.65" x2="195.58" y2="120.65" width="0.1524" layer="91"/> +<wire x1="195.58" y1="120.65" x2="191.77" y2="120.65" width="0.1524" layer="91"/> +<label x="195.58" y="122.682" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7E19" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE" pin="GBE_RCOMPP"/> +</segment> +</net> +<net name="GBE-RCOMPN" class="0"> +<segment> +<wire x1="217.17" y1="115.57" x2="195.58" y2="115.57" width="0.1524" layer="91"/> +<wire x1="217.17" y1="129.54" x2="217.17" y2="115.57" width="0.1524" layer="91"/> +<wire x1="195.58" y1="115.57" x2="191.77" y2="115.57" width="0.1524" layer="91"/> +<label x="195.58" y="117.602" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7E18" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE" pin="GBE_RCOMPN"/> +</segment> +</net> +<net name="P-PME-N" class="0"> +<segment> +<wire x1="121.92" y1="129.54" x2="93.98" y2="129.54" width="0.1524" layer="91"/> +<pinref part="R5T6" gate="R" pin="1"/> +<label x="93.98" y="129.54" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="SYS-PWR-OK-GBE" class="0"> +<segment> +<wire x1="153.67" y1="134.62" x2="146.05" y2="134.62" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE" pin="SYS_PWR_OK"/> +<pinref part="U6E1" gate="GBE" pin="GBE_AUX_PWR_GOOD"/> +<wire x1="146.05" y1="134.62" x2="132.08" y2="134.62" width="0.1524" layer="91"/> +<wire x1="153.67" y1="124.46" x2="146.05" y2="124.46" width="0.1524" layer="91"/> +<wire x1="146.05" y1="124.46" x2="146.05" y2="134.62" width="0.1524" layer="91"/> +<junction x="146.05" y="134.62"/> +<pinref part="R1N6" gate="R" pin="2"/> +<wire x1="146.05" y1="121.92" x2="146.05" y2="124.46" width="0.1524" layer="91"/> +<junction x="146.05" y="124.46"/> +<pinref part="R8U25" gate="R" pin="2"/> +</segment> +</net> +<net name="GBE_PME_WAKE_R" class="0"> +<segment> +<wire x1="153.67" y1="129.54" x2="132.08" y2="129.54" width="0.1524" layer="91"/> +<pinref part="R5T6" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE" pin="GBE_PME_WAKE"/> +</segment> +</net> +<net name="SYS-PWR-OK" class="0"> +<segment> +<wire x1="121.92" y1="134.62" x2="93.98" y2="134.62" width="0.1524" layer="91"/> +<label x="93.98" y="134.62" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="R8U25" gate="R" pin="1"/> +</segment> +</net> +<net name="N$116" class="0"> +<segment> +<wire x1="151.13" y1="69.85" x2="152.4" y2="69.85" width="0.1524" layer="91"/> +<wire x1="152.4" y1="69.85" x2="152.4" y2="86.36" width="0.1524" layer="91"/> +<wire x1="152.4" y1="86.36" x2="153.67" y2="86.36" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE" pin="GBE_REFCLK"/> +<pinref part="R2R11" gate="R" pin="2"/> +</segment> +</net> +<net name="N$125" class="0"> +<segment> +<wire x1="199.39" y1="104.14" x2="191.77" y2="104.14" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE" pin="GBE_REFCLK_RMII"/> +<pinref part="R7E17" gate="R" pin="1"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="160.02" y1="59.69" x2="168.91" y2="59.69" width="0.1524" layer="91"/> +<wire x1="168.91" y1="59.69" x2="168.91" y2="62.23" width="0.1524" layer="91"/> +<wire x1="168.91" y1="62.23" x2="168.91" y2="64.77" width="0.1524" layer="91"/> +<wire x1="168.91" y1="64.77" x2="168.91" y2="68.58" width="0.1524" layer="91"/> +<wire x1="160.02" y1="62.23" x2="168.91" y2="62.23" width="0.1524" layer="91"/> +<wire x1="160.02" y1="64.77" x2="168.91" y2="64.77" width="0.1524" layer="91"/> +<junction x="168.91" y="62.23"/> +<junction x="168.91" y="64.77"/> +<pinref part="R8E21" gate="R" pin="1"/> +<pinref part="U$141" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R8E18" gate="R" pin="1"/> +<pinref part="R8E23" gate="R" pin="1"/> +</segment> +</net> +<net name="N$81" class="0"> +<segment> +<wire x1="111.76" y1="33.02" x2="107.95" y2="33.02" width="0.1524" layer="91"/> +<wire x1="107.95" y1="33.02" x2="107.95" y2="36.83" width="0.1524" layer="91"/> +<wire x1="107.95" y1="30.48" x2="107.95" y2="33.02" width="0.1524" layer="91"/> +<junction x="107.95" y="33.02"/> +<pinref part="Y8C1" gate="G$1" pin="1"/> +<pinref part="C8C5" gate="C" pin="2"/> +<pinref part="U8D1" gate="CORE" pin="XTAL1"/> +</segment> +</net> +<net name="N$117" class="0"> +<segment> +<wire x1="116.84" y1="33.02" x2="121.92" y2="33.02" width="0.1524" layer="91"/> +<wire x1="121.92" y1="33.02" x2="121.92" y2="36.83" width="0.1524" layer="91"/> +<wire x1="121.92" y1="30.48" x2="121.92" y2="33.02" width="0.1524" layer="91"/> +<junction x="121.92" y="33.02"/> +<pinref part="Y8C1" gate="G$1" pin="2"/> +<pinref part="C8D1" gate="C" pin="2"/> +<pinref part="U8D1" gate="CORE" pin="XTAL2"/> +</segment> +</net> +<net name="N$138" class="0"> +<segment> +<wire x1="137.16" y1="54.61" x2="146.05" y2="54.61" width="0.1524" layer="91"/> +<wire x1="146.05" y1="54.61" x2="146.05" y2="46.99" width="0.1524" layer="91"/> +<pinref part="R8E17" gate="R" pin="1"/> +<pinref part="U8D1" gate="CORE" pin="TRSTN"/> +</segment> +</net> +<net name="N$203" class="0"> +<segment> +<wire x1="137.16" y1="57.15" x2="152.4" y2="57.15" width="0.1524" layer="91"/> +<wire x1="152.4" y1="57.15" x2="152.4" y2="46.99" width="0.1524" layer="91"/> +<pinref part="R8E3" gate="R" pin="1"/> +<pinref part="U8D1" gate="CORE" pin="TDO"/> +</segment> +</net> +<net name="N$205" class="0"> +<segment> +<wire x1="149.86" y1="62.23" x2="137.16" y2="62.23" width="0.1524" layer="91"/> +<pinref part="R8E18" gate="R" pin="2"/> +<pinref part="U8D1" gate="CORE" pin="TDI"/> +</segment> +</net> +<net name="N$206" class="0"> +<segment> +<wire x1="149.86" y1="59.69" x2="137.16" y2="59.69" width="0.1524" layer="91"/> +<pinref part="R8E21" gate="R" pin="2"/> +<pinref part="U8D1" gate="CORE" pin="TMS"/> +</segment> +</net> +<net name="N$207" class="0"> +<segment> +<wire x1="137.16" y1="64.77" x2="149.86" y2="64.77" width="0.1524" layer="91"/> +<pinref part="R8E23" gate="R" pin="2"/> +<pinref part="U8D1" gate="CORE" pin="TCK"/> +</segment> +</net> +<net name="N$208" class="0"> +<segment> +<wire x1="73.66" y1="60.96" x2="81.28" y2="60.96" width="0.1524" layer="91"/> +<wire x1="81.28" y1="60.96" x2="87.63" y2="60.96" width="0.1524" layer="91"/> +<wire x1="73.66" y1="58.42" x2="81.28" y2="58.42" width="0.1524" layer="91"/> +<wire x1="81.28" y1="58.42" x2="81.28" y2="60.96" width="0.1524" layer="91"/> +<junction x="81.28" y="60.96"/> +<pinref part="R8C3" gate="R" pin="2"/> +<pinref part="U8D1" gate="CORE" pin="GCONFIG0"/> +<pinref part="R2N29" gate="R" pin="2"/> +</segment> +</net> +<net name="N$209" class="0"> +<segment> +<wire x1="73.66" y1="53.34" x2="81.28" y2="53.34" width="0.1524" layer="91"/> +<wire x1="81.28" y1="53.34" x2="87.63" y2="53.34" width="0.1524" layer="91"/> +<wire x1="73.66" y1="55.88" x2="81.28" y2="55.88" width="0.1524" layer="91"/> +<wire x1="81.28" y1="55.88" x2="81.28" y2="53.34" width="0.1524" layer="91"/> +<junction x="81.28" y="53.34"/> +<pinref part="R2N37" gate="R" pin="2"/> +<pinref part="U8D1" gate="CORE" pin="GCONFIG1"/> +<pinref part="R2N26" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-LINK100" class="0"> +<segment> +<wire x1="63.5" y1="60.96" x2="46.99" y2="60.96" width="0.1524" layer="91"/> +<wire x1="46.99" y1="60.96" x2="46.99" y2="69.85" width="0.1524" layer="91"/> +<wire x1="46.99" y1="69.85" x2="34.29" y2="69.85" width="0.1524" layer="91"/> +<pinref part="R8C3" gate="R" pin="1"/> +<label x="34.29" y="69.85" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-LINK10" class="0"> +<segment> +<wire x1="63.5" y1="58.42" x2="44.45" y2="58.42" width="0.1524" layer="91"/> +<wire x1="44.45" y1="58.42" x2="44.45" y2="66.04" width="0.1524" layer="91"/> +<wire x1="44.45" y1="66.04" x2="34.29" y2="66.04" width="0.1524" layer="91"/> +<pinref part="R2N29" gate="R" pin="1"/> +<label x="34.29" y="66.04" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP3-LINK100" class="0"> +<segment> +<wire x1="63.5" y1="55.88" x2="41.91" y2="55.88" width="0.1524" layer="91"/> +<wire x1="41.91" y1="55.88" x2="41.91" y2="62.23" width="0.1524" layer="91"/> +<wire x1="41.91" y1="62.23" x2="35.56" y2="62.23" width="0.1524" layer="91"/> +<pinref part="R2N26" gate="R" pin="1"/> +<label x="35.56" y="62.23" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP3-LINK10" class="0"> +<segment> +<wire x1="63.5" y1="53.34" x2="39.37" y2="53.34" width="0.1524" layer="91"/> +<wire x1="39.37" y1="53.34" x2="39.37" y2="58.42" width="0.1524" layer="91"/> +<wire x1="39.37" y1="58.42" x2="34.29" y2="58.42" width="0.1524" layer="91"/> +<pinref part="R2N37" gate="R" pin="1"/> +<label x="34.29" y="58.42" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$124" class="0"> +<segment> +<wire x1="137.16" y1="69.85" x2="140.97" y2="69.85" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="CORE" pin="125CLK"/> +<pinref part="R2R11" gate="R" pin="1"/> +</segment> +</net> +<net name="AVDD" class="0"> +<segment> +<wire x1="53.34" y1="66.04" x2="63.5" y2="66.04" width="0.1524" layer="91"/> +<pinref part="R2P3" gate="R" pin="1"/> +<pinref part="U$377" gate="G$1" pin="AVDD"/> +</segment> +</net> +<net name="N$212" class="0"> +<segment> +<wire x1="81.28" y1="76.2" x2="73.66" y2="76.2" width="0.1524" layer="91"/> +<wire x1="87.63" y1="69.85" x2="81.28" y2="69.85" width="0.1524" layer="91"/> +<wire x1="81.28" y1="69.85" x2="81.28" y2="76.2" width="0.1524" layer="91"/> +<pinref part="R2N34" gate="R" pin="2"/> +<pinref part="U8D1" gate="CORE" pin="SEL_CLK"/> +</segment> +</net> +<net name="N$149" class="0"> +<segment> +<wire x1="87.63" y1="66.04" x2="73.66" y2="66.04" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="CORE" pin="SEL_25V"/> +<pinref part="R2P3" gate="R" pin="2"/> +</segment> +</net> +<net name="EP-MDIO" class="0"> +<segment> +<wire x1="128.27" y1="104.14" x2="139.7" y2="104.14" width="0.1524" layer="91"/> +<wire x1="139.7" y1="104.14" x2="139.7" y2="97.79" width="0.1524" layer="91"/> +<wire x1="139.7" y1="97.79" x2="115.57" y2="97.79" width="0.1524" layer="91"/> +<wire x1="139.7" y1="97.79" x2="142.24" y2="97.79" width="0.1524" layer="91"/> +<wire x1="115.57" y1="97.79" x2="114.3" y2="97.79" width="0.1524" layer="91"/> +<wire x1="142.24" y1="97.79" x2="153.67" y2="97.79" width="0.1524" layer="91"/> +<junction x="139.7" y="97.79"/> +<pinref part="R8E2" gate="R" pin="1"/> +<pinref part="U6E1" gate="GBE" pin="MDIO"/> +<label x="114.3" y="97.79" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP-MDC" class="0"> +<segment> +<wire x1="142.24" y1="95.25" x2="139.7" y2="95.25" width="0.1524" layer="91"/> +<wire x1="128.27" y1="87.63" x2="139.7" y2="87.63" width="0.1524" layer="91"/> +<wire x1="139.7" y1="87.63" x2="139.7" y2="93.98" width="0.1524" layer="91"/> +<wire x1="139.7" y1="93.98" x2="139.7" y2="95.25" width="0.1524" layer="91"/> +<wire x1="142.24" y1="95.25" x2="153.67" y2="95.25" width="0.1524" layer="91"/> +<pinref part="R7E20" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE" pin="MDC"/> +<label x="114.3" y="93.98" size="1.778" layer="92" rot="R180" xref="yes"/> +<wire x1="114.3" y1="93.98" x2="139.7" y2="93.98" width="0.1524" layer="91"/> +<junction x="139.7" y="93.98"/> +</segment> +</net> +<net name="M88E1141-RST-N" class="0"> +<segment> +<wire x1="68.58" y1="41.91" x2="41.91" y2="41.91" width="0.1524" layer="91"/> +<wire x1="58.42" y1="48.26" x2="68.58" y2="48.26" width="0.1524" layer="91"/> +<wire x1="68.58" y1="48.26" x2="87.63" y2="48.26" width="0.1524" layer="91"/> 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pin="EEDO"/> +<pinref part="R3R22" gate="R" pin="1"/> +</segment> +</net> +<net name="V2P5" class="0"> +<segment> +<wire x1="217.17" y1="148.59" x2="217.17" y2="139.7" width="0.1524" layer="91"/> +<pinref part="R7E18" gate="R" pin="1"/> +<pinref part="U$222" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="228.6" y1="86.36" x2="228.6" y2="88.9" width="0.1524" layer="91"/> +<wire x1="228.6" y1="88.9" x2="228.6" y2="95.25" width="0.1524" layer="91"/> +<wire x1="215.9" y1="88.9" x2="228.6" y2="88.9" width="0.1524" layer="91"/> +<wire x1="215.9" y1="86.36" x2="228.6" y2="86.36" width="0.1524" layer="91"/> +<junction x="228.6" y="88.9"/> +<pinref part="R3R16" gate="R" pin="2"/> +<pinref part="R3R22" gate="R" pin="2"/> +<pinref part="U$86" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="52.07" y1="77.47" x2="52.07" y2="76.2" width="0.1524" layer="91"/> +<wire x1="52.07" y1="76.2" x2="63.5" y2="76.2" width="0.1524" layer="91"/> +<pinref part="R2N34" gate="R" pin="1"/> +<pinref part="U$106" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="22.86" y1="48.26" x2="48.26" y2="48.26" width="0.1524" layer="91"/> +<pinref part="R8E26" gate="R" pin="1"/> +<pinref part="U$109" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="101.6" y1="107.95" x2="101.6" y2="104.14" width="0.1524" layer="91"/> +<wire x1="101.6" y1="104.14" x2="118.11" y2="104.14" width="0.1524" layer="91"/> +<pinref part="R8E2" gate="R" pin="2"/> +<pinref part="U$41" gate="G$1" pin="V2P5"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="114.3" y="172.72" size="3.81" layer="94">ETHERNET 2/5</text> +<text x="137.16" y="167.64" size="1.778" layer="94">EP80579 : MDC/MDIO 2.5V IO driver (cf Page 209 PDG May 2010)</text> +<text x="137.16" y="163.83" size="1.778" layer="94">EP80579 : GBE RGMII v1.3 RX/TX_DATA 2.5V CMOS level (cf p1879 DS August 2009)</text> +<text x="53.34" y="151.13" size="3.81" layer="94">Unused GBE3</text> +<text x="186.69" y="156.21" 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x="166.37" y="109.22"/> +<junction x="166.37" y="105.41"/> +<junction x="166.37" y="101.6"/> +<junction x="166.37" y="128.27"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDO@6"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDO@5"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDO@4"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDO@3"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDO@2"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDO@1"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDOH@4"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDOH@3"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDOH@2"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDOH@1"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDOX@2"/> +<pinref part="U8D1" gate="PW1/2" pin="VDDOX@1"/> +<pinref part="C2P24" gate="C" pin="1"/> +<pinref part="C2P22" gate="C" pin="1"/> +<pinref part="C3P10" gate="C" pin="1"/> +<pinref part="C3P1" gate="C" pin="1"/> +<pinref part="C3P8" gate="C" pin="1"/> +<pinref part="C2P3" gate="C" pin="1"/> +<pinref part="C2P23" gate="C" pin="1"/> +<pinref part="C2P9" gate="C" pin="1"/> +<pinref part="C2P4" gate="C" pin="1"/> +<pinref part="U$113" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="107.95" y1="110.49" x2="107.95" y2="107.95" width="0.1524" layer="91"/> +<wire x1="107.95" y1="107.95" x2="107.95" y2="100.33" width="0.1524" layer="91"/> +<wire x1="107.95" y1="107.95" x2="118.11" y2="107.95" width="0.1524" layer="91"/> +<wire x1="118.11" y1="107.95" x2="118.11" y2="100.33" width="0.1524" layer="91"/> +<wire x1="118.11" y1="107.95" x2="128.27" y2="107.95" width="0.1524" layer="91"/> +<wire x1="128.27" y1="107.95" x2="128.27" y2="100.33" width="0.1524" layer="91"/> +<junction x="107.95" y="107.95"/> +<junction x="118.11" y="107.95"/> +<pinref part="R2N5" gate="R" pin="1"/> +<pinref part="R2N8" gate="R" pin="1"/> +<pinref part="R2N7" gate="R" pin="1"/> +<pinref part="U$112" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="228.6" y1="59.69" x2="227.33" y2="59.69" width="0.1524" layer="91"/> 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name="NAME" x="234.95" y="72.39" size="1.778" layer="95"/> +</instance> +<instance part="EP0-CON" gate="LED1" x="236.22" y="68.58" smashed="yes" rot="R270"> +<attribute name="NAME" x="234.95" y="64.77" size="1.778" layer="95"/> +</instance> +<instance part="EP0-CON" gate="CORE" x="257.81" y="109.22" smashed="yes"> +<attribute name="NAME" x="236.22" y="130.556" size="1.778" layer="95"/> +<attribute name="VALUE" x="236.22" y="127.762" size="1.778" layer="96"/> +</instance> +<instance part="C2L8" gate="C" x="219.71" y="147.32" smashed="yes" rot="MR180"> +<attribute name="NAME" x="221.9325" y="157.48" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="220.0275" y="147.6375" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="219.71" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="219.71" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="219.71" y="147.32" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$311" gate="G$1" x="219.71" y="132.08" rot="MR0"/> +<instance part="U$526" gate="G$1" x="232.41" y="92.71"/> +<instance part="C2M3" gate="C" x="226.06" y="147.32" smashed="yes" rot="MR180"> +<attribute name="NAME" x="228.2825" y="157.48" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="226.3775" y="147.6375" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="226.06" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="226.06" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="226.06" y="147.32" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2L7" gate="C" x="232.41" y="147.32" smashed="yes" rot="MR180"> +<attribute name="NAME" x="234.6325" y="157.48" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="232.7275" y="147.6375" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="232.41" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="232.41" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="232.41" y="147.32" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2M4" gate="C" x="238.76" y="147.32" smashed="yes" rot="MR180"> +<attribute name="NAME" x="240.9825" y="157.48" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="239.0775" y="147.6375" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="238.76" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="238.76" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="238.76" y="147.32" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$253" gate="G$1" x="238.76" y="157.48"/> +<instance part="R2M4" gate="R" x="166.37" y="135.89" smashed="yes"> +<attribute name="NAME" x="163.5125" y="136.2075" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" 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x="60.96" y="148.59" smashed="yes" rot="R270"> +<attribute name="NAME" x="61.2775" y="151.765" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="61.2064" y="145.416" size="1.778" layer="96" rot="R270"/> +<attribute name="POWER" x="60.96" y="148.59" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8E9" gate="R" x="63.5" y="148.59" smashed="yes" rot="R270"> +<attribute name="NAME" x="63.8175" y="151.765" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="63.7464" y="145.416" size="1.778" layer="96" rot="R270"/> +<attribute name="POWER" x="63.5" y="148.59" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8E11" gate="R" x="92.71" y="148.59" smashed="yes" rot="R270"> +<attribute name="NAME" x="93.0275" y="151.765" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="92.9564" y="145.416" size="1.778" layer="96" rot="R270"/> +<attribute name="POWER" x="92.71" y="148.59" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8E7" gate="R" x="90.17" y="148.59" smashed="yes" rot="R270"> +<attribute name="NAME" x="90.4875" y="151.765" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="90.4164" y="145.416" size="1.778" layer="96" rot="R270"/> +<attribute name="POWER" x="90.17" y="148.59" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8E10" gate="R" x="87.63" y="148.59" smashed="yes" rot="R270"> +<attribute name="NAME" x="87.9475" y="151.765" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="87.8764" y="145.416" size="1.778" layer="96" rot="R270"/> +<attribute name="POWER" x="87.63" y="148.59" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8E8" gate="R" x="85.09" y="148.59" smashed="yes" rot="R270"> +<attribute name="NAME" x="85.4075" y="151.765" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="85.3364" y="145.416" size="1.778" layer="96" rot="R270"/> +<attribute name="POWER" x="85.09" y="148.59" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2R1" gate="R" x="121.92" y="149.86" smashed="yes" rot="R180"> +<attribute name="NAME" x="124.7775" y="149.5425" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="119.0625" y="149.5425" size="1.778" layer="96" rot="R180"/> +<attribute name="POWER" x="121.92" y="149.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="121.92" y="149.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$269" gate="G$1" x="132.08" y="149.86" rot="MR270"/> +<instance part="U$270" gate="G$1" x="96.52" y="101.6" rot="MR90"/> +<instance part="R8E1" gate="R" x="80.01" y="76.2"> +<attribute name="POWER" x="80.01" y="76.2" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U6E1" gate="GBE0" x="26.67" y="125.73" rot="MR0"/> +<instance part="U$335" gate="G$1" x="212.09" y="33.02"/> +<instance part="U$336" gate="G$1" x="187.96" y="33.02" rot="MR0"/> +<instance part="C2M2" gate="C" x="199.39" y="35.56" rot="R270"> +<attribute name="VOLTAGE" x="199.39" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="199.39" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="199.39" y="35.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="FB8B2" gate="F" x="198.12" y="40.64"/> +<instance part="R3N24" gate="R" x="132.08" y="29.21" smashed="yes" rot="R180"> +<attribute name="NAME" x="134.9375" y="28.8925" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="129.2225" y="28.8925" size="1.778" layer="96" rot="R180"/> +<attribute name="POWER" x="132.08" y="29.21" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3N20" gate="R" x="132.08" y="11.43" smashed="yes" rot="R180"> +<attribute name="NAME" x="134.9375" y="11.1125" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="129.2225" y="11.1125" size="1.778" layer="96" rot="R180"/> +<attribute name="POWER" x="132.08" y="11.43" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U8D1" gate="GB0" x="140.97" y="100.33"/> +<instance part="U$116" gate="G$1" x="48.26" y="166.37"/> +<instance part="U$117" gate="G$1" x="85.09" y="166.37"/> +<instance part="U$118" gate="G$1" x="68.58" y="81.28"/> +<instance part="U$119" gate="G$1" x="138.43" y="158.75"/> +<instance part="U$120" gate="G$1" x="208.28" y="90.17"/> +<instance part="U$130" gate="G$1" x="256.54" y="81.28"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="219.71" y1="133.35" x2="219.71" y2="134.62" width="0.1524" layer="91"/> +<wire x1="219.71" y1="144.78" x2="219.71" y2="134.62" width="0.1524" layer="91"/> +<wire x1="219.71" y1="134.62" x2="226.06" y2="134.62" width="0.1524" layer="91"/> +<wire x1="226.06" y1="134.62" x2="232.41" y2="134.62" width="0.1524" layer="91"/> +<wire x1="232.41" y1="134.62" x2="233.68" y2="134.62" width="0.1524" layer="91"/> +<wire x1="226.06" y1="144.78" x2="226.06" y2="134.62" width="0.1524" layer="91"/> +<wire x1="233.68" y1="134.62" x2="238.76" y2="134.62" width="0.1524" layer="91"/> +<wire x1="238.76" y1="134.62" x2="238.76" y2="144.78" width="0.1524" layer="91"/> +<wire x1="232.41" y1="144.78" x2="232.41" y2="134.62" width="0.1524" layer="91"/> +<junction x="219.71" y="134.62"/> +<junction x="226.06" y="134.62"/> +<junction x="232.41" y="134.62"/> +<pinref part="U$311" gate="G$1" pin="GND"/> +<pinref part="C2L8" gate="C" pin="2"/> +<pinref part="C2M3" gate="C" pin="2"/> +<pinref part="C2M4" gate="C" pin="2"/> +<pinref part="C2L7" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="191.77" y1="128.27" x2="196.85" y2="128.27" width="0.1524" layer="91"/> +<wire x1="196.85" y1="128.27" x2="196.85" y2="135.89" width="0.1524" layer="91"/> +<wire x1="196.85" y1="135.89" x2="189.23" y2="135.89" width="0.1524" layer="91"/> +<wire x1="198.12" y1="135.89" x2="196.85" y2="135.89" width="0.1524" layer="91"/> +<junction x="196.85" y="135.89"/> +<pinref part="C2M6" gate="C" pin="2"/> +<pinref part="C2M5" gate="C" pin="2"/> +<pinref part="U$262" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="189.23" y1="92.71" x2="196.85" y2="92.71" width="0.1524" layer="91"/> +<wire x1="196.85" y1="92.71" x2="196.85" y2="100.33" width="0.1524" layer="91"/> +<wire x1="196.85" y1="100.33" x2="191.77" y2="100.33" width="0.1524" layer="91"/> +<wire x1="198.12" y1="100.33" x2="196.85" y2="100.33" width="0.1524" layer="91"/> +<junction x="196.85" y="100.33"/> +<pinref part="C2M8" gate="C" pin="2"/> +<pinref part="C2M7" gate="C" pin="2"/> +<pinref part="U$263" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="186.69" y1="153.67" x2="199.39" y2="153.67" width="0.1524" layer="91"/> +<pinref part="U$265" gate="G$1" pin="GND"/> +<pinref part="R2P9" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="93.98" y1="120.65" x2="95.25" y2="120.65" width="0.1524" layer="91"/> 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part="R2R1" gate="R" pin="1"/> +<pinref part="U$269" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="97.79" y1="101.6" x2="99.06" y2="101.6" width="0.1524" layer="91"/> +<pinref part="U$270" gate="G$1" pin="GND"/> +<pinref part="U8D1" gate="GB0" pin="P0_TX_ER"/> +</segment> +<segment> +<wire x1="187.96" y1="34.29" x2="187.96" y2="35.56" width="0.1524" layer="91"/> +<wire x1="187.96" y1="35.56" x2="187.96" y2="40.64" width="0.1524" layer="91"/> +<wire x1="187.96" y1="40.64" x2="193.04" y2="40.64" width="0.1524" layer="91"/> +<wire x1="194.31" y1="35.56" x2="187.96" y2="35.56" width="0.1524" layer="91"/> +<junction x="187.96" y="35.56"/> +<pinref part="U$336" gate="G$1" pin="GND"/> +<pinref part="FB8B2" gate="F" pin="1"/> +<pinref part="C2M2" gate="C" pin="1"/> +</segment> +</net> +<net name="GND-CHASSIS" class="0"> +<segment> +<wire x1="232.41" y1="93.98" x2="232.41" y2="95.25" width="0.1524" layer="91"/> +<wire x1="232.41" y1="95.25" x2="236.22" y2="95.25" width="0.1524" layer="91"/> +<wire x1="236.22" y1="96.52" x2="232.41" y2="96.52" width="0.1524" layer="91"/> +<wire x1="232.41" y1="96.52" x2="232.41" y2="95.25" width="0.1524" layer="91"/> +<junction x="232.41" y="95.25"/> +<pinref part="U$526" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="EP0-CON" gate="CORE" pin="SHIELD#2"/> +<pinref part="EP0-CON" gate="CORE" pin="SHIELD#1"/> +</segment> +<segment> +<wire x1="203.2" y1="40.64" x2="212.09" y2="40.64" width="0.1524" layer="91"/> +<wire x1="212.09" y1="40.64" x2="212.09" y2="35.56" width="0.1524" layer="91"/> +<wire x1="212.09" y1="35.56" x2="212.09" y2="34.29" width="0.1524" layer="91"/> +<wire x1="201.93" y1="35.56" x2="212.09" y2="35.56" width="0.1524" layer="91"/> +<junction x="212.09" y="35.56"/> +<pinref part="FB8B2" gate="F" pin="2"/> +<pinref part="U$335" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="C2M2" gate="C" pin="2"/> +</segment> +</net> +<net name="AVDD" class="0"> +<segment> +<wire x1="219.71" y1="156.21" x2="219.71" y2="152.4" width="0.1524" layer="91"/> +<wire x1="226.06" y1="156.21" x2="219.71" y2="156.21" width="0.1524" layer="91"/> +<wire x1="226.06" y1="156.21" x2="226.06" y2="152.4" width="0.1524" layer="91"/> +<wire x1="233.68" y1="156.21" x2="232.41" y2="156.21" width="0.1524" layer="91"/> +<wire x1="232.41" y1="156.21" x2="226.06" y2="156.21" width="0.1524" layer="91"/> +<wire x1="233.68" y1="156.21" x2="238.76" y2="156.21" width="0.1524" layer="91"/> +<wire x1="219.71" y1="156.21" x2="214.63" y2="156.21" width="0.1524" layer="91"/> +<wire x1="214.63" y1="156.21" x2="214.63" y2="124.46" width="0.1524" layer="91"/> +<wire x1="214.63" y1="124.46" x2="220.98" y2="124.46" width="0.1524" layer="91"/> +<wire x1="232.41" y1="152.4" x2="232.41" y2="156.21" width="0.1524" layer="91"/> +<wire x1="238.76" y1="152.4" x2="238.76" y2="156.21" width="0.1524" layer="91"/> +<wire x1="220.98" y1="116.84" x2="214.63" y2="116.84" width="0.1524" layer="91"/> +<wire x1="214.63" y1="116.84" x2="214.63" y2="124.46" width="0.1524" layer="91"/> +<wire x1="220.98" y1="109.22" x2="214.63" y2="109.22" width="0.1524" layer="91"/> +<wire x1="214.63" y1="109.22" x2="214.63" y2="116.84" width="0.1524" layer="91"/> +<wire x1="220.98" y1="101.6" x2="214.63" y2="101.6" width="0.1524" layer="91"/> +<wire x1="214.63" y1="101.6" x2="214.63" y2="109.22" width="0.1524" layer="91"/> +<wire x1="238.76" y1="156.21" x2="238.76" y2="157.48" width="0.1524" layer="91"/> +<junction x="226.06" y="156.21"/> +<junction x="219.71" y="156.21"/> +<junction x="232.41" y="156.21"/> +<junction x="214.63" y="124.46"/> +<junction x="214.63" y="116.84"/> +<junction x="214.63" y="109.22"/> +<junction x="238.76" y="156.21"/> +<pinref part="EP0-CON" gate="CORE" pin="12"/> +<pinref part="C2L8" gate="C" pin="1"/> +<pinref part="C2M3" gate="C" pin="1"/> +<pinref part="C2L7" gate="C" pin="1"/> +<pinref part="C2M4" gate="C" pin="1"/> +<pinref part="EP0-CON" gate="CORE" pin="6"/> +<pinref part="EP0-CON" gate="CORE" pin="1"/> +<pinref part="EP0-CON" gate="CORE" pin="7"/> +<pinref part="U$253" gate="G$1" pin="AVDD"/> +</segment> +</net> +<net name="EP0-INT-N" class="0"> +<segment> +<wire x1="156.21" y1="153.67" x2="168.91" y2="153.67" width="0.1524" layer="91"/> +<wire x1="168.91" y1="153.67" x2="176.53" y2="153.67" width="0.1524" layer="91"/> +<wire x1="146.05" y1="139.7" x2="168.91" y2="139.7" width="0.1524" layer="91"/> +<wire x1="168.91" y1="139.7" x2="168.91" y2="153.67" width="0.1524" layer="91"/> +<wire x1="168.91" y1="153.67" x2="168.91" y2="163.83" width="0.1524" layer="91"/> +<wire x1="168.91" y1="163.83" x2="177.8" y2="163.83" width="0.1524" layer="91"/> +<junction x="168.91" y="153.67"/> +<label x="148.2725" y="140.0175" size="1.778" layer="92"/> +<pinref part="R2P9" gate="R" pin="1"/> +<pinref part="R2P6" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB0" pin="P0_INTN"/> +<label x="177.8" y="163.83" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP0-MDI0-P" class="0"> +<segment> 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y2="121.92" width="0.1524" layer="91"/> +<wire x1="146.05" y1="119.38" x2="154.94" y2="119.38" width="0.1524" layer="91"/> +<wire x1="154.94" y1="119.38" x2="172.72" y2="119.38" width="0.1524" layer="91"/> +<wire x1="172.72" y1="119.38" x2="207.01" y2="119.38" width="0.1524" layer="91"/> +<wire x1="161.29" y1="133.35" x2="154.94" y2="133.35" width="0.1524" layer="91"/> +<wire x1="154.94" y1="133.35" x2="154.94" y2="119.38" width="0.1524" layer="91"/> +<junction x="154.94" y="119.38"/> +<label x="184.4675" y="119.6975" size="1.778" layer="92"/> +<pinref part="EP0-CON" gate="CORE" pin="10"/> +<pinref part="R2M3" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_MDI[0]-"/> +</segment> +</net> +<net name="EP0-MDI1-P" class="0"> +<segment> +<wire x1="146.05" y1="116.84" x2="157.48" y2="116.84" width="0.1524" layer="91"/> +<wire x1="157.48" y1="116.84" x2="199.39" y2="116.84" width="0.1524" layer="91"/> +<wire x1="199.39" y1="116.84" x2="209.55" y2="116.84" width="0.1524" layer="91"/> +<wire x1="209.55" y1="116.84" x2="209.55" y2="119.38" width="0.1524" layer="91"/> +<wire x1="209.55" y1="119.38" x2="220.98" y2="119.38" width="0.1524" layer="91"/> +<wire x1="165.1" y1="128.27" x2="157.48" y2="128.27" width="0.1524" layer="91"/> +<wire x1="157.48" y1="128.27" x2="157.48" y2="116.84" width="0.1524" layer="91"/> +<junction x="157.48" y="116.84"/> +<label x="184.4675" y="117.1575" size="1.778" layer="92"/> +<pinref part="EP0-CON" gate="CORE" pin="4"/> +<pinref part="R2M6" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_MDI[1]+"/> +</segment> +</net> +<net name="EP0-MDI1-N" class="0"> +<segment> +<wire x1="146.05" y1="114.3" x2="160.02" y2="114.3" width="0.1524" layer="91"/> +<wire x1="160.02" y1="114.3" x2="189.23" y2="114.3" width="0.1524" layer="91"/> +<wire x1="189.23" y1="114.3" x2="220.98" y2="114.3" width="0.1524" layer="91"/> +<wire x1="165.1" y1="125.73" x2="160.02" y2="125.73" width="0.1524" layer="91"/> +<wire x1="160.02" y1="125.73" x2="160.02" y2="114.3" width="0.1524" layer="91"/> +<junction x="160.02" y="114.3"/> +<label x="184.4675" y="114.6175" size="1.778" layer="92"/> +<pinref part="EP0-CON" gate="CORE" pin="5"/> +<pinref part="R2M5" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_MDI[1]-"/> +</segment> +</net> +<net name="EP0-MDI2-P" class="0"> +<segment> +<wire x1="146.05" y1="111.76" x2="160.02" y2="111.76" width="0.1524" layer="91"/> +<wire x1="160.02" y1="111.76" x2="199.39" y2="111.76" width="0.1524" layer="91"/> +<wire x1="199.39" y1="111.76" x2="220.98" y2="111.76" width="0.1524" layer="91"/> +<wire x1="165.1" y1="100.33" x2="160.02" y2="100.33" width="0.1524" layer="91"/> +<wire x1="160.02" y1="100.33" x2="160.02" y2="111.76" width="0.1524" layer="91"/> +<junction x="160.02" y="111.76"/> +<label x="184.4675" y="112.0775" size="1.778" layer="92"/> +<pinref part="EP0-CON" gate="CORE" pin="3"/> +<pinref part="R2M8" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_MDI[2]+"/> +</segment> +</net> +<net name="EP0-MDI2-N" class="0"> +<segment> +<wire x1="212.09" y1="106.68" x2="220.98" y2="106.68" width="0.1524" layer="91"/> +<wire x1="212.09" y1="109.22" x2="212.09" y2="106.68" width="0.1524" layer="91"/> +<wire x1="146.05" y1="109.22" x2="157.48" y2="109.22" width="0.1524" layer="91"/> +<wire x1="157.48" y1="109.22" x2="189.23" y2="109.22" width="0.1524" layer="91"/> +<wire x1="189.23" y1="109.22" x2="212.09" y2="109.22" width="0.1524" layer="91"/> +<wire x1="165.1" y1="97.79" x2="157.48" y2="97.79" width="0.1524" layer="91"/> +<wire x1="157.48" y1="97.79" x2="157.48" y2="109.22" width="0.1524" layer="91"/> +<junction x="157.48" y="109.22"/> +<label x="184.4675" y="109.5375" size="1.778" layer="92"/> +<pinref part="EP0-CON" gate="CORE" pin="2"/> +<pinref part="R2M7" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_MDI[2]-"/> +</segment> +</net> +<net name="EP0-MDI3-P" class="0"> +<segment> +<wire x1="146.05" y1="106.68" x2="154.94" y2="106.68" width="0.1524" layer="91"/> +<wire x1="154.94" y1="106.68" x2="184.15" y2="106.68" width="0.1524" layer="91"/> +<wire x1="184.15" y1="106.68" x2="209.55" y2="106.68" width="0.1524" layer="91"/> +<wire x1="209.55" y1="106.68" x2="209.55" y2="104.14" width="0.1524" layer="91"/> +<wire x1="209.55" y1="104.14" x2="220.98" y2="104.14" width="0.1524" layer="91"/> +<wire x1="154.94" y1="92.71" x2="154.94" y2="106.68" width="0.1524" layer="91"/> +<wire x1="161.29" y1="92.71" x2="154.94" y2="92.71" width="0.1524" layer="91"/> +<junction x="154.94" y="106.68"/> +<label x="184.4675" y="106.9975" size="1.778" layer="92"/> +<pinref part="EP0-CON" gate="CORE" pin="8"/> +<pinref part="R2M10" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_MDI[3]+"/> +</segment> +</net> +<net name="EP0-MDI3-N" class="0"> +<segment> +<wire x1="146.05" y1="104.14" x2="152.4" y2="104.14" width="0.1524" layer="91"/> +<wire x1="152.4" y1="104.14" x2="172.72" y2="104.14" width="0.1524" layer="91"/> +<wire x1="172.72" y1="104.14" x2="207.01" y2="104.14" width="0.1524" layer="91"/> +<wire x1="207.01" y1="104.14" x2="207.01" y2="99.06" width="0.1524" layer="91"/> +<wire x1="207.01" y1="99.06" x2="220.98" y2="99.06" width="0.1524" layer="91"/> +<wire x1="152.4" y1="90.17" x2="152.4" y2="104.14" width="0.1524" layer="91"/> +<wire x1="161.29" y1="90.17" x2="152.4" y2="90.17" width="0.1524" layer="91"/> +<junction x="152.4" y="104.14"/> +<label x="184.4675" y="104.4575" size="1.778" layer="92"/> +<pinref part="EP0-CON" gate="CORE" pin="9"/> +<pinref part="R2M9" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_MDI[3]-"/> +</segment> +</net> +<net name="EP0-CONFIG1" class="0"> +<segment> +<wire x1="99.06" y1="62.23" x2="45.72" y2="62.23" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB0" pin="P0_CONFIG1"/> +<label x="45.72" y="62.23" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP0-CONFIG2" class="0"> +<segment> +<wire x1="99.06" y1="59.69" x2="88.9" y2="59.69" width="0.1524" layer="91"/> +<wire x1="88.9" y1="59.69" x2="88.9" y2="58.42" width="0.1524" layer="91"/> +<wire x1="88.9" y1="58.42" x2="45.72" y2="58.42" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB0" pin="P0_CONFIG2"/> +<label x="45.72" y="58.42" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP0-CONFIG3" class="0"> +<segment> +<wire x1="99.06" y1="57.15" x2="91.44" y2="57.15" width="0.1524" layer="91"/> +<wire x1="91.44" y1="57.15" x2="91.44" y2="54.61" width="0.1524" layer="91"/> +<wire x1="91.44" y1="54.61" x2="45.72" y2="54.61" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB0" pin="P0_CONFIG3"/> +<label x="45.72" y="54.61" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP0-CONFIG0" class="0"> +<segment> +<wire x1="127" y1="43.18" x2="93.98" y2="43.18" width="0.1524" layer="91"/> +<wire x1="93.98" y1="43.18" x2="93.98" y2="50.8" width="0.1524" layer="91"/> +<wire x1="93.98" y1="50.8" x2="45.72" y2="50.8" width="0.1524" layer="91"/> +<wire x1="99.06" y1="53.34" x2="93.98" y2="53.34" width="0.1524" layer="91"/> +<wire x1="93.98" y1="53.34" x2="93.98" y2="50.8" width="0.1524" layer="91"/> +<junction x="93.98" y="50.8"/> +<pinref part="R8C2" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB0" pin="P0_CONFIG0"/> +<label x="45.72" y="50.8" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP0-CONFIG4" class="0"> +<segment> +<wire x1="127" y1="40.64" x2="96.52" y2="40.64" width="0.1524" layer="91"/> +<wire x1="96.52" y1="40.64" x2="71.12" y2="40.64" width="0.1524" layer="91"/> +<wire x1="127" y1="24.13" x2="96.52" y2="24.13" width="0.1524" layer="91"/> +<wire x1="96.52" y1="24.13" x2="96.52" y2="40.64" width="0.1524" layer="91"/> +<wire x1="99.06" y1="50.8" x2="96.52" y2="50.8" width="0.1524" layer="91"/> +<wire x1="96.52" y1="50.8" x2="96.52" y2="40.64" width="0.1524" layer="91"/> +<junction x="96.52" y="40.64"/> +<pinref part="R2N25" gate="R" pin="2"/> +<pinref part="R3N15" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB0" pin="P0_CONFIG4"/> +<label x="71.12" y="40.64" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-CONFIG4" class="0"> +<segment> +<wire x1="127" y1="33.02" x2="93.98" y2="33.02" width="0.1524" layer="91"/> +<wire x1="93.98" y1="33.02" x2="71.12" y2="33.02" width="0.1524" layer="91"/> +<wire x1="127" y1="21.59" x2="93.98" y2="21.59" width="0.1524" layer="91"/> +<wire x1="93.98" y1="21.59" x2="93.98" y2="33.02" width="0.1524" layer="91"/> +<junction x="93.98" y="33.02"/> +<pinref part="R2N32" gate="R" pin="2"/> +<pinref part="R3N16" gate="R" pin="2"/> +<label x="71.12" y="33.02" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP1-CONFIG0" class="0"> +<segment> +<wire x1="127" y1="19.05" x2="71.12" y2="19.05" width="0.1524" layer="91"/> +<pinref part="R3N17" gate="R" pin="2"/> +<label x="71.12" y="19.05" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-CONFIG0" class="0"> +<segment> +<wire x1="127" y1="15.24" x2="71.12" y2="15.24" width="0.1524" layer="91"/> +<pinref part="R3N21" gate="R" pin="2"/> +<label x="71.12" y="15.24" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP0-RXD3" class="0"> +<segment> +<wire x1="48.26" y1="87.63" x2="44.45" y2="87.63" width="0.1524" layer="91"/> +<wire x1="48.26" y1="143.51" x2="48.26" y2="87.63" width="0.1524" layer="91"/> +<wire x1="48.26" y1="87.63" x2="73.66" y2="87.63" width="0.1524" layer="91"/> +<junction x="48.26" y="87.63"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_RXDATA[3]"/> +<pinref part="R2R5" gate="R" pin="2"/> +<pinref part="R7E15" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-RXD2" class="0"> +<segment> +<wire x1="50.8" y1="90.17" x2="44.45" y2="90.17" width="0.1524" layer="91"/> +<wire x1="50.8" y1="143.51" x2="50.8" y2="90.17" width="0.1524" layer="91"/> +<wire x1="50.8" y1="90.17" x2="73.66" y2="90.17" width="0.1524" layer="91"/> +<junction x="50.8" y="90.17"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_RXDATA[2]"/> +<pinref part="R2R4" gate="R" pin="2"/> +<pinref part="R6E3" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-RXD1" class="0"> +<segment> +<wire x1="53.34" y1="92.71" x2="44.45" y2="92.71" width="0.1524" layer="91"/> +<wire x1="53.34" y1="143.51" x2="53.34" y2="92.71" width="0.1524" layer="91"/> +<wire x1="53.34" y1="92.71" x2="73.66" y2="92.71" width="0.1524" layer="91"/> +<junction x="53.34" y="92.71"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_RXDATA[1]"/> +<pinref part="R2R3" gate="R" pin="2"/> +<pinref part="R7E16" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-RXD0" class="0"> +<segment> +<wire x1="55.88" y1="95.25" x2="44.45" y2="95.25" width="0.1524" layer="91"/> +<wire x1="55.88" y1="143.51" x2="55.88" y2="95.25" width="0.1524" layer="91"/> +<wire x1="55.88" y1="95.25" x2="73.66" y2="95.25" width="0.1524" layer="91"/> +<junction x="55.88" y="95.25"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_RXDATA[0]"/> +<pinref part="R2R2" gate="R" pin="2"/> +<pinref part="R7E11" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-RXCTL" class="0"> +<segment> +<wire x1="44.45" y1="104.14" x2="58.42" y2="104.14" width="0.1524" layer="91"/> +<wire x1="58.42" y1="104.14" x2="58.42" y2="143.51" width="0.1524" layer="91"/> +<wire x1="73.66" y1="104.14" x2="58.42" y2="104.14" width="0.1524" layer="91"/> +<junction x="58.42" y="104.14"/> +<pinref part="R7E14" gate="R" pin="2"/> +<pinref part="R2R7" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_RXCTL"/> +</segment> +</net> +<net name="EP0-RXCLK" class="0"> +<segment> +<wire x1="44.45" y1="111.76" x2="66.04" y2="111.76" width="0.1524" layer="91"/> +<wire x1="66.04" y1="111.76" x2="66.04" y2="143.51" width="0.1524" layer="91"/> +<wire x1="66.04" y1="111.76" x2="73.66" y2="111.76" width="0.1524" layer="91"/> +<junction x="66.04" y="111.76"/> +<pinref part="R7E13" gate="R" pin="2"/> +<pinref part="R2R6" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_RXCLK"/> +</segment> +</net> +<net name="EP0-TXD3" class="0"> +<segment> +<wire x1="44.45" y1="125.73" x2="73.66" y2="125.73" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_TXDATA[3]"/> +<pinref part="R3R23" gate="R" pin="1"/> +</segment> +</net> +<net name="EP0-TXD2" class="0"> +<segment> +<wire x1="44.45" y1="128.27" x2="73.66" y2="128.27" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_TXDATA[2]"/> +<pinref part="R3R20" gate="R" pin="1"/> +</segment> +</net> +<net name="EP0-TXD1" class="0"> +<segment> +<wire x1="44.45" y1="130.81" x2="73.66" y2="130.81" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_TXDATA[1]"/> +<pinref part="R3R14" gate="R" pin="1"/> +</segment> +</net> +<net name="EP0-TXD0" class="0"> +<segment> +<wire x1="44.45" y1="133.35" x2="73.66" y2="133.35" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_TXDATA[0]"/> +<pinref part="R3R19" gate="R" pin="1"/> +</segment> +</net> +<net name="EP0-RXCLK-R" class="0"> +<segment> +<wire x1="83.82" y1="111.76" x2="99.06" y2="111.76" width="0.1524" layer="91"/> +<pinref part="R2R6" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_RX_CLK"/> +</segment> +</net> +<net name="EP0-RXCTL-R" class="0"> +<segment> +<wire x1="99.06" y1="104.14" x2="83.82" y2="104.14" width="0.1524" layer="91"/> +<pinref part="R2R7" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_RX_DV"/> +</segment> +</net> +<net name="EP-MDIO" class="0"> +<segment> +<wire x1="85.09" y1="76.2" x2="91.44" y2="76.2" width="0.1524" layer="91"/> +<wire x1="91.44" y1="76.2" x2="91.44" y2="69.85" width="0.1524" layer="91"/> +<wire x1="91.44" y1="69.85" x2="45.72" y2="69.85" width="0.1524" layer="91"/> +<wire x1="91.44" y1="69.85" x2="99.06" y2="69.85" width="0.1524" layer="91"/> +<junction x="91.44" y="69.85"/> +<pinref part="R8E1" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB0" pin="P0_MDIO"/> +<label x="45.72" y="69.85" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP-MDC" class="0"> +<segment> +<wire x1="99.06" y1="67.31" x2="99.06" y2="66.04" width="0.1524" layer="91"/> +<wire x1="99.06" y1="66.04" x2="44.45" y2="66.04" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB0" pin="P0_MDC"/> +<label x="44.45" y="66.04" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP0-$3" class="0"> +<segment> +<wire x1="146.05" y1="63.5" x2="199.39" y2="63.5" width="0.1524" layer="91"/> +<wire x1="199.39" y1="63.5" x2="199.39" y2="67.31" width="0.1524" layer="91"/> +<pinref part="DS7C5" gate="LED" pin="K"/> +<pinref part="U8D1" gate="GB0" pin="P0_LED_RX"/> +</segment> +</net> +<net name="EP0-$4" class="0"> +<segment> +<wire x1="146.05" y1="60.96" x2="205.74" y2="60.96" width="0.1524" layer="91"/> +<wire x1="205.74" y1="60.96" x2="205.74" y2="76.2" width="0.1524" layer="91"/> +<wire x1="212.09" y1="76.2" x2="205.74" y2="76.2" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB0" pin="P0_LED_TX"/> +<pinref part="R2M2" gate="R" pin="1"/> +</segment> +</net> +<net name="EP0-$5" class="0"> +<segment> +<wire x1="137.16" y1="36.83" x2="149.86" y2="36.83" width="0.1524" layer="91"/> +<wire x1="189.23" y1="58.42" x2="189.23" y2="67.31" width="0.1524" layer="91"/> +<wire x1="146.05" y1="58.42" x2="149.86" y2="58.42" width="0.1524" layer="91"/> +<wire x1="149.86" y1="58.42" x2="189.23" y2="58.42" width="0.1524" layer="91"/> +<wire x1="149.86" y1="58.42" x2="149.86" y2="43.18" width="0.1524" layer="91"/> +<wire x1="149.86" y1="43.18" x2="137.16" y2="43.18" width="0.1524" layer="91"/> +<wire x1="137.16" y1="40.64" x2="149.86" y2="40.64" width="0.1524" layer="91"/> +<wire x1="149.86" y1="40.64" x2="149.86" y2="43.18" width="0.1524" layer="91"/> +<wire x1="149.86" y1="36.83" x2="149.86" y2="40.64" width="0.1524" layer="91"/> +<wire x1="137.16" y1="33.02" x2="149.86" y2="33.02" width="0.1524" layer="91"/> +<wire x1="149.86" y1="33.02" x2="149.86" y2="36.83" width="0.1524" layer="91"/> +<wire x1="137.16" y1="29.21" x2="149.86" y2="29.21" width="0.1524" layer="91"/> +<wire x1="149.86" y1="29.21" x2="149.86" y2="33.02" width="0.1524" layer="91"/> +<junction x="149.86" y="58.42"/> +<junction x="149.86" y="43.18"/> +<junction x="149.86" y="40.64"/> +<junction x="149.86" y="36.83"/> +<junction x="149.86" y="33.02"/> +<pinref part="R2N31" gate="R" pin="1"/> +<pinref part="DS7C4" gate="LED" pin="K"/> +<pinref part="R8C2" gate="R" pin="1"/> +<pinref part="R2N25" gate="R" pin="1"/> +<pinref part="R2N32" gate="R" pin="1"/> +<pinref part="R3N24" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_DUPLEX"/> +</segment> +</net> +<net name="EP0-$9" class="0"> +<segment> +<wire x1="181.61" y1="92.71" x2="176.53" y2="92.71" width="0.1524" layer="91"/> +<wire x1="176.53" y1="92.71" x2="171.45" y2="92.71" width="0.1524" layer="91"/> +<wire x1="171.45" y1="90.17" x2="176.53" y2="90.17" width="0.1524" layer="91"/> +<wire x1="176.53" y1="90.17" x2="176.53" y2="92.71" width="0.1524" layer="91"/> +<junction x="176.53" y="92.71"/> +<pinref part="R2M10" gate="R" pin="2"/> +<pinref part="C2M8" gate="C" pin="1"/> +<pinref part="R2M9" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-$10" class="0"> +<segment> +<wire x1="175.26" y1="97.79" x2="180.34" y2="97.79" width="0.1524" layer="91"/> +<wire x1="180.34" y1="97.79" x2="180.34" y2="100.33" width="0.1524" layer="91"/> +<wire x1="180.34" y1="100.33" x2="184.15" y2="100.33" width="0.1524" layer="91"/> +<wire x1="180.34" y1="100.33" x2="175.26" y2="100.33" width="0.1524" layer="91"/> +<junction x="180.34" y="100.33"/> +<pinref part="R2M7" gate="R" pin="2"/> +<pinref part="C2M7" gate="C" pin="1"/> +<pinref part="R2M8" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-$11" class="0"> +<segment> +<wire x1="175.26" y1="125.73" x2="181.61" y2="125.73" width="0.1524" layer="91"/> +<wire x1="181.61" y1="125.73" x2="181.61" y2="128.27" width="0.1524" layer="91"/> +<wire x1="181.61" y1="128.27" x2="184.15" y2="128.27" width="0.1524" layer="91"/> +<wire x1="181.61" y1="128.27" x2="175.26" y2="128.27" width="0.1524" layer="91"/> +<junction x="181.61" y="128.27"/> +<pinref part="R2M5" gate="R" pin="2"/> +<pinref part="C2M6" gate="C" pin="1"/> +<pinref part="R2M6" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-$12" class="0"> +<segment> +<wire x1="171.45" y1="135.89" x2="179.07" y2="135.89" width="0.1524" layer="91"/> +<wire x1="179.07" y1="135.89" x2="181.61" y2="135.89" width="0.1524" layer="91"/> +<wire x1="171.45" y1="133.35" x2="179.07" y2="133.35" width="0.1524" layer="91"/> +<wire x1="179.07" y1="133.35" x2="179.07" y2="135.89" width="0.1524" layer="91"/> +<junction x="179.07" y="135.89"/> +<pinref part="R2M4" gate="R" pin="2"/> +<pinref part="C2M5" gate="C" pin="1"/> +<pinref part="R2M3" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-$13" class="0"> +<segment> +<wire x1="160.02" y1="76.2" x2="160.02" y2="74.93" width="0.1524" layer="91"/> +<pinref part="DS7C1" gate="LED" pin="A"/> +<pinref part="R3N10" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-$14" class="0"> +<segment> +<wire x1="170.18" y1="76.2" x2="170.18" y2="74.93" width="0.1524" layer="91"/> +<pinref part="DS7C3" gate="LED" pin="A"/> +<pinref part="R3N8" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-$15" class="0"> +<segment> +<wire x1="180.34" y1="76.2" x2="180.34" y2="74.93" width="0.1524" layer="91"/> +<pinref part="DS7C2" gate="LED" pin="A"/> +<pinref part="R3N9" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-$16" class="0"> +<segment> +<wire x1="189.23" y1="76.2" x2="189.23" y2="74.93" width="0.1524" layer="91"/> +<pinref part="DS7C4" gate="LED" pin="A"/> +<pinref part="R3N7" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-$17" class="0"> +<segment> +<wire x1="199.39" y1="76.2" x2="199.39" y2="74.93" width="0.1524" layer="91"/> +<pinref part="DS7C5" gate="LED" pin="A"/> +<pinref part="R3N6" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-LINK100" class="0"> +<segment> +<wire x1="146.05" y1="53.34" x2="170.18" y2="53.34" width="0.1524" layer="91"/> +<wire x1="170.18" y1="53.34" x2="170.18" y2="67.31" width="0.1524" layer="91"/> +<wire x1="137.16" y1="15.24" x2="170.18" y2="15.24" width="0.1524" layer="91"/> +<wire x1="170.18" y1="15.24" x2="170.18" y2="53.34" width="0.1524" layer="91"/> +<wire x1="170.18" y1="53.34" x2="195.58" y2="53.34" width="0.1524" layer="91"/> +<junction x="170.18" y="53.34"/> +<pinref part="DS7C3" gate="LED" pin="K"/> +<pinref part="R3N21" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_LINK100"/> +<label x="195.58" y="53.34" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP0-LINK10" class="0"> +<segment> +<wire x1="180.34" y1="50.8" x2="180.34" y2="67.31" width="0.1524" layer="91"/> +<wire x1="180.34" y1="50.8" x2="234.95" y2="50.8" width="0.1524" layer="91"/> +<wire x1="173.99" y1="50.8" x2="180.34" y2="50.8" width="0.1524" layer="91"/> +<wire x1="173.99" y1="11.43" x2="173.99" y2="50.8" width="0.1524" layer="91"/> +<wire x1="137.16" y1="11.43" x2="173.99" y2="11.43" width="0.1524" layer="91"/> +<wire x1="173.99" y1="50.8" x2="146.05" y2="50.8" width="0.1524" layer="91"/> +<junction x="180.34" y="50.8"/> +<junction x="173.99" y="50.8"/> +<pinref part="DS7C2" gate="LED" pin="K"/> +<pinref part="R3N20" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_LINK10"/> +<label x="234.95" y="50.8" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP0-RST" class="0"> +<segment> +<wire x1="116.84" y1="149.86" x2="96.52" y2="149.86" width="0.1524" layer="91"/> +<wire x1="96.52" y1="149.86" x2="96.52" y2="137.16" width="0.1524" layer="91"/> +<wire x1="96.52" y1="137.16" x2="99.06" y2="137.16" width="0.1524" layer="91"/> +<label x="98.1075" y="150.1775" size="1.778" layer="92"/> +<pinref part="R2R1" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB0" pin="P0_RSET"/> +</segment> +</net> +<net name="EP3-CONFIG4" class="0"> +<segment> +<wire x1="127" y1="29.21" x2="71.12" y2="29.21" width="0.1524" layer="91"/> +<pinref part="R3N24" gate="R" pin="2"/> +<label x="71.12" y="29.21" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP3-CONFIG0" class="0"> +<segment> +<wire x1="127" y1="11.43" x2="71.12" y2="11.43" width="0.1524" layer="91"/> +<pinref part="R3N20" gate="R" pin="2"/> +<label x="71.12" y="11.43" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP0-LINK1000" class="0"> +<segment> +<wire x1="146.05" y1="55.88" x2="160.02" y2="55.88" width="0.1524" layer="91"/> +<wire x1="160.02" y1="55.88" x2="209.55" y2="55.88" width="0.1524" layer="91"/> +<wire x1="209.55" y1="55.88" x2="209.55" y2="68.58" width="0.1524" layer="91"/> +<wire x1="160.02" y1="55.88" x2="160.02" y2="67.31" width="0.1524" layer="91"/> +<wire x1="160.02" y1="24.13" x2="137.16" y2="24.13" width="0.1524" layer="91"/> +<wire x1="160.02" y1="19.05" x2="160.02" y2="21.59" width="0.1524" layer="91"/> +<wire x1="160.02" y1="21.59" x2="160.02" y2="24.13" width="0.1524" layer="91"/> +<wire x1="137.16" y1="19.05" x2="160.02" y2="19.05" width="0.1524" layer="91"/> +<wire x1="160.02" y1="24.13" x2="160.02" y2="26.67" width="0.1524" layer="91"/> +<wire x1="160.02" y1="26.67" x2="137.16" y2="26.67" width="0.1524" layer="91"/> +<wire x1="137.16" y1="21.59" x2="160.02" y2="21.59" width="0.1524" layer="91"/> +<wire x1="160.02" y1="26.67" x2="160.02" y2="55.88" width="0.1524" layer="91"/> +<wire x1="209.55" y1="55.88" x2="229.87" y2="55.88" width="0.1524" layer="91"/> +<wire x1="212.09" y1="68.58" x2="209.55" y2="68.58" width="0.1524" layer="91"/> +<junction x="160.02" y="55.88"/> +<junction x="160.02" y="24.13"/> +<junction x="160.02" y="21.59"/> +<junction x="160.02" y="26.67"/> +<junction x="209.55" y="55.88"/> +<pinref part="DS7C1" gate="LED" pin="K"/> +<pinref part="R3N15" gate="R" pin="1"/> +<pinref part="R3N17" gate="R" pin="1"/> +<pinref part="R3N14" gate="R" pin="1"/> +<pinref part="R3N16" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_LINK1000"/> +<pinref part="R2M1" gate="R" pin="1"/> +<label x="229.87" y="55.88" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP0-RXD0-R" class="0"> +<segment> +<wire x1="83.82" y1="95.25" x2="99.06" y2="95.25" width="0.1524" layer="91"/> +<pinref part="R2R2" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_RXD[0]"/> +</segment> +</net> +<net name="EP0-RXD1-R" class="0"> +<segment> +<wire x1="83.82" y1="92.71" x2="99.06" y2="92.71" width="0.1524" layer="91"/> +<pinref part="R2R3" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_RXD[1]"/> +</segment> +</net> +<net name="EP0-RXD2-R" class="0"> +<segment> +<wire x1="83.82" y1="90.17" x2="99.06" y2="90.17" width="0.1524" layer="91"/> +<pinref part="R2R4" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_RXD[2]"/> +</segment> +</net> +<net name="EP0-RXD3-R" class="0"> +<segment> +<wire x1="83.82" y1="87.63" x2="99.06" y2="87.63" width="0.1524" layer="91"/> +<pinref part="R2R5" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB0" pin="P0_RXD[3]"/> +</segment> +</net> +<net name="EP0-TXD0-R" class="0"> +<segment> +<wire x1="83.82" y1="133.35" x2="92.71" y2="133.35" width="0.1524" layer="91"/> +<wire x1="92.71" y1="133.35" x2="99.06" y2="133.35" width="0.1524" layer="91"/> +<wire x1="92.71" y1="143.51" x2="92.71" y2="133.35" width="0.1524" layer="91"/> +<junction x="92.71" y="133.35"/> +<pinref part="R3R19" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB0" pin="P0_TXD[0]"/> +<pinref part="R8E11" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-TXD1-R" class="0"> +<segment> +<wire x1="83.82" y1="130.81" x2="90.17" y2="130.81" width="0.1524" layer="91"/> +<wire x1="90.17" y1="130.81" x2="99.06" y2="130.81" width="0.1524" layer="91"/> +<wire x1="90.17" y1="143.51" x2="90.17" y2="130.81" width="0.1524" layer="91"/> +<junction x="90.17" y="130.81"/> +<pinref part="R3R14" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB0" pin="P0_TXD[1]"/> +<pinref part="R8E7" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-TXD2-R" class="0"> +<segment> +<wire x1="83.82" y1="128.27" x2="87.63" y2="128.27" width="0.1524" layer="91"/> +<wire x1="87.63" y1="128.27" x2="99.06" y2="128.27" width="0.1524" layer="91"/> +<wire x1="87.63" y1="143.51" x2="87.63" y2="128.27" width="0.1524" layer="91"/> +<junction x="87.63" y="128.27"/> +<pinref part="R3R20" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB0" pin="P0_TXD[2]"/> +<pinref part="R8E10" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-TXD3-R" class="0"> +<segment> +<wire x1="83.82" y1="125.73" x2="85.09" y2="125.73" width="0.1524" layer="91"/> +<wire x1="85.09" y1="125.73" x2="99.06" y2="125.73" width="0.1524" layer="91"/> +<wire x1="85.09" y1="143.51" x2="85.09" y2="125.73" width="0.1524" layer="91"/> +<junction x="85.09" y="125.73"/> +<pinref part="R3R23" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB0" pin="P0_TXD[3]"/> +<pinref part="R8E8" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-CONFIG4" class="0"> +<segment> +<wire x1="127" y1="36.83" x2="99.06" y2="36.83" width="0.1524" layer="91"/> +<wire x1="127" y1="26.67" x2="99.06" y2="26.67" width="0.1524" layer="91"/> +<wire x1="99.06" y1="26.67" x2="99.06" y2="36.83" width="0.1524" layer="91"/> +<wire x1="99.06" y1="36.83" x2="71.12" y2="36.83" width="0.1524" layer="91"/> +<junction x="99.06" y="36.83"/> +<pinref part="R2N31" gate="R" pin="2"/> +<pinref part="R3N14" gate="R" pin="2"/> +<label x="71.12" y="36.83" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP0-TXCLK-R" class="0"> +<segment> +<wire x1="83.82" y1="109.22" x2="86.36" y2="109.22" width="0.1524" layer="91"/> +<wire x1="86.36" y1="109.22" x2="99.06" y2="109.22" width="0.1524" layer="91"/> +<wire x1="86.36" y1="116.84" x2="86.36" y2="109.22" width="0.1524" layer="91"/> +<wire x1="63.5" y1="143.51" x2="63.5" y2="116.84" width="0.1524" layer="91"/> +<wire x1="63.5" y1="116.84" x2="86.36" y2="116.84" width="0.1524" layer="91"/> +<junction x="86.36" y="109.22"/> +<pinref part="U8D1" gate="GB0" pin="P0_GTX_CLK"/> +<pinref part="R3R21" gate="R" pin="2"/> +<pinref part="R8E9" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-TXCLK" class="0"> +<segment> +<wire x1="63.5" y1="109.22" x2="73.66" y2="109.22" width="0.1524" layer="91"/> +<wire x1="44.45" y1="109.22" x2="63.5" y2="109.22" width="0.1524" layer="91"/> +<pinref part="R3R21" gate="R" pin="1"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_TXCLK"/> +</segment> +</net> +<net name="EP0-TXCTL-R" class="0"> +<segment> +<wire x1="83.82" y1="106.68" x2="88.9" y2="106.68" width="0.1524" layer="91"/> +<wire x1="88.9" y1="106.68" x2="99.06" y2="106.68" width="0.1524" layer="91"/> +<wire x1="88.9" y1="119.38" x2="88.9" y2="106.68" width="0.1524" layer="91"/> +<wire x1="60.96" y1="143.51" x2="60.96" y2="119.38" width="0.1524" layer="91"/> +<wire x1="60.96" y1="119.38" x2="88.9" y2="119.38" width="0.1524" layer="91"/> +<junction x="88.9" y="106.68"/> +<pinref part="U8D1" gate="GB0" pin="P0_TX_EN"/> +<pinref part="R3R15" gate="R" pin="2"/> +<pinref part="R8E6" gate="R" pin="2"/> +</segment> +</net> +<net name="EP0-TXCTL" class="0"> +<segment> +<wire x1="60.96" y1="106.68" x2="73.66" y2="106.68" width="0.1524" layer="91"/> +<wire x1="44.45" y1="106.68" x2="60.96" y2="106.68" width="0.1524" layer="91"/> +<pinref part="R3R15" gate="R" pin="1"/> +<pinref part="U6E1" gate="GBE0" pin="GBE0_TXCTL"/> +</segment> +</net> +<net name="N$211" class="0"> +<segment> +<wire x1="233.68" y1="68.58" x2="222.25" y2="68.58" width="0.1524" layer="91"/> +<pinref part="R2M1" gate="R" pin="2"/> +<pinref part="EP0-CON" gate="LED1" pin="K"/> +</segment> +</net> +<net name="N$210" class="0"> +<segment> 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y2="162.56" width="0.1524" layer="91"/> +<wire x1="48.26" y1="162.56" x2="50.8" y2="162.56" width="0.1524" layer="91"/> +<wire x1="48.26" y1="162.56" x2="48.26" y2="165.1" width="0.1524" layer="91"/> +<wire x1="48.26" y1="153.67" x2="48.26" y2="162.56" width="0.1524" layer="91"/> +<wire x1="50.8" y1="153.67" x2="50.8" y2="162.56" width="0.1524" layer="91"/> +<wire x1="53.34" y1="153.67" x2="53.34" y2="162.56" width="0.1524" layer="91"/> +<wire x1="55.88" y1="153.67" x2="55.88" y2="162.56" width="0.1524" layer="91"/> +<junction x="63.5" y="162.56"/> +<junction x="60.96" y="162.56"/> +<junction x="58.42" y="162.56"/> +<junction x="48.26" y="162.56"/> +<junction x="50.8" y="162.56"/> +<junction x="53.34" y="162.56"/> +<junction x="55.88" y="162.56"/> +<pinref part="R7E14" gate="R" pin="1"/> +<pinref part="R7E13" gate="R" pin="1"/> +<pinref part="R8E9" gate="R" pin="1"/> +<pinref part="R8E6" gate="R" pin="1"/> +<pinref part="R7E15" gate="R" pin="1"/> +<pinref part="R6E3" gate="R" pin="1"/> +<pinref part="R7E16" gate="R" pin="1"/> +<pinref part="R7E11" gate="R" pin="1"/> +<pinref part="U$116" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="85.09" y1="165.1" x2="85.09" y2="162.56" width="0.1524" layer="91"/> +<wire x1="90.17" y1="162.56" x2="92.71" y2="162.56" width="0.1524" layer="91"/> +<wire x1="87.63" y1="162.56" x2="90.17" y2="162.56" width="0.1524" layer="91"/> +<wire x1="87.63" y1="162.56" x2="85.09" y2="162.56" width="0.1524" layer="91"/> +<wire x1="92.71" y1="153.67" x2="92.71" y2="162.56" width="0.1524" layer="91"/> +<wire x1="90.17" y1="153.67" x2="90.17" y2="162.56" width="0.1524" layer="91"/> +<wire x1="87.63" y1="153.67" x2="87.63" y2="162.56" width="0.1524" layer="91"/> +<wire x1="85.09" y1="153.67" x2="85.09" y2="162.56" width="0.1524" layer="91"/> +<junction x="90.17" y="162.56"/> +<junction x="87.63" y="162.56"/> +<junction x="85.09" y="162.56"/> +<pinref part="R8E11" gate="R" pin="1"/> +<pinref part="R8E7" gate="R" pin="1"/> +<pinref part="R8E10" gate="R" pin="1"/> +<pinref part="R8E8" gate="R" pin="1"/> +<pinref part="U$117" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="68.58" y1="80.01" x2="68.58" y2="76.2" width="0.1524" layer="91"/> +<wire x1="68.58" y1="76.2" x2="74.93" y2="76.2" width="0.1524" layer="91"/> +<pinref part="R8E1" gate="R" pin="1"/> +<pinref part="U$118" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="160.02" y1="86.36" x2="160.02" y2="87.63" width="0.1524" layer="91"/> +<wire x1="160.02" y1="87.63" x2="170.18" y2="87.63" width="0.1524" layer="91"/> +<wire x1="170.18" y1="87.63" x2="180.34" y2="87.63" width="0.1524" layer="91"/> +<wire x1="180.34" y1="87.63" x2="189.23" y2="87.63" width="0.1524" layer="91"/> +<wire x1="189.23" y1="87.63" x2="199.39" y2="87.63" width="0.1524" layer="91"/> +<wire x1="199.39" y1="87.63" x2="208.28" y2="87.63" width="0.1524" layer="91"/> +<wire x1="208.28" y1="87.63" x2="208.28" y2="88.9" width="0.1524" layer="91"/> +<wire x1="199.39" y1="86.36" x2="199.39" y2="87.63" width="0.1524" layer="91"/> +<wire x1="189.23" y1="86.36" x2="189.23" y2="87.63" width="0.1524" layer="91"/> +<wire x1="180.34" y1="86.36" x2="180.34" y2="87.63" width="0.1524" layer="91"/> +<wire x1="170.18" y1="86.36" x2="170.18" y2="87.63" width="0.1524" layer="91"/> +<junction x="199.39" y="87.63"/> +<junction x="189.23" y="87.63"/> +<junction x="180.34" y="87.63"/> +<junction x="170.18" y="87.63"/> +<pinref part="R3N10" gate="R" pin="1"/> +<pinref part="R3N6" gate="R" pin="1"/> +<pinref part="R3N7" gate="R" pin="1"/> +<pinref part="R3N9" gate="R" pin="1"/> +<pinref part="R3N8" gate="R" pin="1"/> +<pinref part="U$120" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="241.3" y1="68.58" x2="256.54" y2="68.58" width="0.1524" layer="91"/> +<wire x1="256.54" y1="68.58" x2="256.54" y2="76.2" width="0.1524" layer="91"/> +<wire x1="256.54" y1="76.2" x2="256.54" y2="80.01" width="0.1524" layer="91"/> +<wire x1="241.3" y1="76.2" x2="256.54" y2="76.2" width="0.1524" layer="91"/> +<junction x="256.54" y="76.2"/> +<pinref part="EP0-CON" gate="LED2" pin="A"/> +<pinref part="EP0-CON" gate="LED1" pin="A"/> +<pinref part="U$130" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="146.05" y1="153.67" x2="138.43" y2="153.67" width="0.1524" layer="91"/> +<wire x1="138.43" y1="153.67" x2="138.43" y2="157.48" width="0.1524" layer="91"/> +<pinref part="R2P6" gate="R" pin="1"/> +<pinref part="U$119" gate="G$1" pin="V2P5"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="102.87" y="167.64" size="3.81" layer="94">ETHERNET 4/5</text> +</plain> +<instances> +<instance part="FRAME20" gate="G$1" x="0" y="0"/> +<instance part="FRAME20" gate="G$2" x="180.34" y="0"/> +<instance part="EP1-CON" gate="LED2" x="236.22" y="72.39" smashed="yes" rot="R270"> +<attribute name="NAME" x="232.41" y="68.58" size="1.778" layer="95"/> +</instance> +<instance part="EP1-CON" gate="LED1" x="236.22" y="64.77" smashed="yes" rot="R270"> +<attribute name="NAME" x="232.41" y="60.96" size="1.778" layer="95"/> +</instance> +<instance part="EP1-CON" gate="CORE" x="257.81" y="104.14" smashed="yes"> +<attribute name="NAME" x="236.22" y="125.476" size="1.778" layer="95"/> +<attribute name="VALUE" x="236.22" y="122.682" size="1.778" layer="96"/> +</instance> +<instance part="C2L2" gate="C" x="219.71" y="142.24" smashed="yes" rot="MR180"> +<attribute name="NAME" x="221.9325" y="152.4" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="220.0275" y="142.5575" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="219.71" y="142.24" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="219.71" y="142.24" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="219.71" y="142.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$274" gate="G$1" x="219.71" y="127" rot="MR0"/> +<instance part="U$275" gate="G$1" x="232.41" y="87.63"/> +<instance part="C2L5" gate="C" x="226.06" y="142.24" smashed="yes" rot="MR180"> +<attribute name="NAME" x="228.2825" y="152.4" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="226.3775" y="142.5575" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="226.06" y="142.24" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="226.06" y="142.24" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="226.06" y="142.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2L4" gate="C" x="232.41" y="142.24" smashed="yes" rot="MR180"> +<attribute name="NAME" x="234.6325" y="152.4" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="232.7275" y="142.5575" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="232.41" y="142.24" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="232.41" y="142.24" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="232.41" y="142.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2L1" gate="C" x="238.76" y="142.24" smashed="yes" rot="MR180"> +<attribute name="NAME" x="240.9825" y="152.4" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="239.0775" y="142.5575" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="238.76" y="142.24" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="238.76" y="142.24" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="238.76" y="142.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$276" gate="G$1" x="238.76" y="154.94"/> +<instance part="R2M17" gate="R" x="168.91" y="130.81" smashed="yes"> +<attribute name="NAME" x="166.0525" y="131.1275" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="171.7675" y="131.1275" size="1.778" layer="96"/> +<attribute name="POWER" x="168.91" y="130.81" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="168.91" y="130.81" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2M11" gate="R" x="168.91" y="87.63" smashed="yes"> +<attribute name="NAME" x="166.0525" y="87.9475" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="171.7675" y="87.9475" size="1.778" layer="96"/> +<attribute name="POWER" x="168.91" y="87.63" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="168.91" y="87.63" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2M12" gate="R" x="168.91" y="85.09" smashed="yes"> +<attribute name="NAME" x="166.0525" y="85.4075" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="171.7675" y="85.4075" size="1.778" layer="96"/> +<attribute name="POWER" x="168.91" y="85.09" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="168.91" y="85.09" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2M18" gate="R" x="168.91" y="128.27" smashed="yes"> +<attribute name="NAME" x="166.0525" y="128.5875" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="171.7675" y="128.5875" size="1.778" layer="96"/> +<attribute name="POWER" x="168.91" y="128.27" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="168.91" y="128.27" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2M16" gate="R" x="172.72" y="120.65" smashed="yes"> +<attribute name="NAME" x="169.8625" y="120.9675" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="175.5775" y="120.9675" size="1.778" layer="96"/> +<attribute name="POWER" x="172.72" y="120.65" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="172.72" y="120.65" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2M15" gate="R" x="172.72" y="123.19" smashed="yes"> +<attribute name="NAME" x="169.8625" y="123.5075" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="175.5775" y="123.5075" size="1.778" layer="96"/> +<attribute name="POWER" x="172.72" y="123.19" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="172.72" y="123.19" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2M14" gate="R" x="172.72" y="92.71" smashed="yes"> +<attribute name="NAME" x="169.8625" y="93.0275" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="175.5775" y="93.0275" size="1.778" layer="96"/> +<attribute name="POWER" x="172.72" y="92.71" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="172.72" y="92.71" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2M13" gate="R" x="172.72" y="95.25" smashed="yes"> +<attribute name="NAME" x="169.8625" y="95.5675" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="175.5775" y="95.5675" size="1.778" layer="96"/> +<attribute name="POWER" x="172.72" y="95.25" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="172.72" y="95.25" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2M12" gate="C" x="190.5" y="130.81" smashed="yes" rot="MR90"> +<attribute name="NAME" x="187.96" y="131.1275" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="190.1825" y="131.1275" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="190.5" y="130.81" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="190.5" y="130.81" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="190.5" y="130.81" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2M11" gate="C" x="194.31" y="123.19" smashed="yes" rot="MR90"> +<attribute name="NAME" x="191.77" y="123.5075" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="193.9925" y="123.5075" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="194.31" y="123.19" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="194.31" y="123.19" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" 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y="67.31" size="1.778" layer="96"/> +<attribute name="POWER" x="48.26" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="44.7675" y="65.7225" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="51.435" y="65.7225" size="1.778" layer="96" rot="MR180"/> +</instance> +<instance part="R7E21" gate="R" x="48.26" y="60.96" smashed="yes"> +<attribute name="DNP" x="46.355" y="62.23" size="1.778" layer="96"/> +<attribute name="POWER" x="48.26" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="44.7675" y="60.6425" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="51.435" y="60.6425" size="1.778" layer="96" rot="MR180"/> +</instance> +<instance part="U$333" gate="G$1" x="205.74" y="27.94"/> +<instance part="U$334" gate="G$1" x="181.61" y="27.94" rot="MR0"/> +<instance part="C2M1" gate="C" x="193.04" y="30.48" rot="R270"> +<attribute name="VOLTAGE" x="193.04" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="193.04" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="193.04" y="30.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="FB8B1" gate="F" x="191.77" y="35.56"/> +<instance part="R3N18" gate="R" x="132.08" y="19.05" smashed="yes" rot="R180"> +<attribute name="NAME" x="134.9375" y="18.7325" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="129.2225" y="18.7325" size="1.778" layer="96" rot="R180"/> +<attribute name="POWER" x="132.08" y="19.05" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U8D1" gate="GB1" x="140.97" y="95.25"/> +<instance part="U$448" gate="G$1" x="85.09" y="158.75"/> +<instance part="U$131" gate="G$1" x="144.78" y="151.13"/> +<instance part="U$132" gate="G$1" x="256.54" y="77.47"/> +<instance part="U$133" gate="G$1" x="35.56" y="72.39"/> +<instance part="U$140" gate="G$1" x="208.28" y="85.09"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<wire x1="219.71" y1="128.27" x2="219.71" y2="129.54" width="0.1524" layer="91"/> +<wire x1="219.71" y1="139.7" x2="219.71" y2="129.54" width="0.1524" layer="91"/> +<wire x1="219.71" y1="129.54" x2="226.06" y2="129.54" width="0.1524" layer="91"/> +<wire x1="226.06" y1="129.54" x2="232.41" y2="129.54" width="0.1524" layer="91"/> +<wire x1="232.41" y1="129.54" x2="233.68" y2="129.54" width="0.1524" layer="91"/> +<wire x1="226.06" y1="139.7" x2="226.06" y2="129.54" width="0.1524" layer="91"/> +<wire x1="233.68" y1="129.54" x2="238.76" y2="129.54" width="0.1524" layer="91"/> +<wire x1="238.76" y1="129.54" x2="238.76" y2="139.7" width="0.1524" layer="91"/> +<wire x1="232.41" y1="139.7" x2="232.41" y2="129.54" width="0.1524" layer="91"/> +<junction x="219.71" y="129.54"/> +<junction x="226.06" y="129.54"/> +<junction x="232.41" y="129.54"/> +<pinref part="U$274" gate="G$1" pin="GND"/> +<pinref part="C2L2" gate="C" pin="2"/> +<pinref part="C2L5" gate="C" pin="2"/> +<pinref part="C2L1" gate="C" pin="2"/> +<pinref part="C2L4" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="196.85" y1="123.19" x2="201.93" y2="123.19" width="0.1524" layer="91"/> +<wire x1="201.93" y1="123.19" x2="201.93" y2="130.81" width="0.1524" layer="91"/> +<wire x1="201.93" y1="130.81" x2="193.04" y2="130.81" width="0.1524" layer="91"/> +<wire x1="205.74" y1="130.81" x2="201.93" y2="130.81" width="0.1524" layer="91"/> +<junction x="201.93" y="130.81"/> +<pinref part="C2M11" gate="C" pin="2"/> +<pinref part="C2M12" gate="C" pin="2"/> +<pinref part="U$277" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="194.31" y1="87.63" x2="200.66" y2="87.63" width="0.1524" layer="91"/> +<wire x1="200.66" y1="87.63" x2="200.66" y2="95.25" width="0.1524" layer="91"/> +<wire x1="200.66" y1="95.25" x2="195.58" y2="95.25" width="0.1524" layer="91"/> +<wire x1="201.93" y1="95.25" x2="200.66" y2="95.25" width="0.1524" layer="91"/> +<junction x="200.66" y="95.25"/> +<pinref part="C2M9" gate="C" pin="2"/> +<pinref part="C2M10" gate="C" pin="2"/> +<pinref part="U$287" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="190.5" y1="146.05" x2="204.47" y2="146.05" width="0.1524" layer="91"/> +<pinref part="U$291" gate="G$1" pin="GND"/> +<pinref part="R2P10" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="93.98" y1="115.57" x2="95.25" y2="115.57" width="0.1524" layer="91"/> +<wire x1="95.25" y1="115.57" x2="95.25" y2="118.11" width="0.1524" layer="91"/> +<wire x1="95.25" y1="118.11" x2="99.06" y2="118.11" width="0.1524" layer="91"/> +<wire x1="99.06" y1="115.57" x2="95.25" y2="115.57" width="0.1524" layer="91"/> +<wire x1="99.06" y1="113.03" x2="95.25" y2="113.03" width="0.1524" layer="91"/> +<wire x1="95.25" y1="113.03" x2="95.25" y2="115.57" width="0.1524" layer="91"/> +<wire x1="99.06" y1="110.49" x2="95.25" y2="110.49" width="0.1524" layer="91"/> +<wire x1="95.25" y1="110.49" x2="95.25" y2="113.03" width="0.1524" layer="91"/> +<junction x="95.25" y="115.57"/> +<junction x="95.25" y="113.03"/> +<pinref part="U$296" gate="G$1" pin="GND"/> +<pinref part="U8D1" gate="GB1" pin="P1_TXD[4]"/> +<pinref part="U8D1" gate="GB1" pin="P1_TXD[5]"/> +<pinref part="U8D1" gate="GB1" pin="P1_TXD[6]"/> +<pinref part="U8D1" gate="GB1" pin="P1_TXD[7]"/> +</segment> +<segment> +<wire x1="130.81" y1="144.78" x2="120.65" y2="144.78" width="0.1524" layer="91"/> +<pinref part="R2P5" gate="R" pin="1"/> +<pinref part="U$298" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="97.79" y1="96.52" x2="99.06" y2="96.52" width="0.1524" layer="91"/> +<pinref part="U$299" gate="G$1" pin="GND"/> +<pinref part="U8D1" gate="GB1" pin="P1_TX_ER"/> +</segment> +<segment> +<wire x1="35.56" y1="53.34" x2="35.56" y2="55.88" width="0.1524" layer="91"/> +<wire x1="35.56" y1="55.88" x2="43.18" y2="55.88" width="0.1524" layer="91"/> +<pinref part="U$326" gate="G$1" pin="GND"/> +<pinref part="R8E15" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="181.61" y1="29.21" x2="181.61" y2="30.48" width="0.1524" layer="91"/> +<wire x1="181.61" y1="30.48" x2="181.61" y2="35.56" width="0.1524" layer="91"/> +<wire x1="181.61" y1="35.56" x2="186.69" y2="35.56" width="0.1524" layer="91"/> +<wire x1="187.96" y1="30.48" x2="181.61" y2="30.48" width="0.1524" layer="91"/> +<junction x="181.61" y="30.48"/> +<pinref part="U$334" gate="G$1" pin="GND"/> +<pinref part="FB8B1" gate="F" pin="1"/> +<pinref part="C2M1" gate="C" pin="1"/> +</segment> +</net> +<net name="GND-CHASSIS" class="0"> +<segment> +<wire x1="232.41" y1="88.9" x2="232.41" y2="90.17" width="0.1524" layer="91"/> +<wire x1="232.41" y1="90.17" x2="236.22" y2="90.17" width="0.1524" layer="91"/> +<wire x1="236.22" y1="91.44" x2="232.41" y2="91.44" width="0.1524" layer="91"/> +<wire x1="232.41" y1="91.44" x2="232.41" y2="90.17" width="0.1524" layer="91"/> +<junction x="232.41" y="90.17"/> +<pinref part="U$275" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="EP1-CON" gate="CORE" pin="SHIELD#2"/> +<pinref part="EP1-CON" gate="CORE" pin="SHIELD#1"/> +</segment> +<segment> +<wire x1="196.85" y1="35.56" x2="205.74" y2="35.56" width="0.1524" layer="91"/> +<wire x1="205.74" y1="35.56" x2="205.74" y2="30.48" width="0.1524" layer="91"/> +<wire x1="205.74" y1="30.48" x2="205.74" y2="29.21" width="0.1524" layer="91"/> +<wire x1="195.58" y1="30.48" x2="205.74" y2="30.48" width="0.1524" layer="91"/> +<junction x="205.74" y="30.48"/> +<pinref part="FB8B1" gate="F" pin="2"/> +<pinref part="U$333" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="C2M1" gate="C" pin="2"/> +</segment> +</net> +<net name="AVDD" class="0"> +<segment> +<wire x1="219.71" y1="153.67" x2="219.71" y2="147.32" width="0.1524" layer="91"/> +<wire x1="226.06" y1="153.67" x2="219.71" y2="153.67" width="0.1524" layer="91"/> +<wire x1="226.06" y1="153.67" x2="226.06" y2="147.32" width="0.1524" layer="91"/> +<wire x1="233.68" y1="153.67" x2="232.41" y2="153.67" width="0.1524" layer="91"/> +<wire x1="232.41" y1="153.67" x2="226.06" y2="153.67" width="0.1524" layer="91"/> +<wire x1="233.68" y1="153.67" x2="238.76" y2="153.67" width="0.1524" layer="91"/> +<wire x1="219.71" y1="153.67" x2="214.63" y2="153.67" width="0.1524" layer="91"/> +<wire x1="214.63" y1="153.67" x2="214.63" y2="119.38" width="0.1524" layer="91"/> +<wire x1="214.63" y1="119.38" x2="220.98" y2="119.38" width="0.1524" layer="91"/> +<wire x1="232.41" y1="147.32" x2="232.41" y2="153.67" width="0.1524" layer="91"/> +<wire x1="238.76" y1="147.32" x2="238.76" y2="153.67" width="0.1524" layer="91"/> +<wire x1="220.98" y1="111.76" x2="214.63" y2="111.76" width="0.1524" layer="91"/> +<wire x1="214.63" y1="111.76" x2="214.63" y2="119.38" width="0.1524" layer="91"/> +<wire x1="220.98" y1="104.14" x2="214.63" y2="104.14" width="0.1524" layer="91"/> +<wire x1="214.63" y1="104.14" x2="214.63" y2="111.76" width="0.1524" layer="91"/> +<wire x1="220.98" y1="96.52" x2="214.63" y2="96.52" width="0.1524" layer="91"/> +<wire x1="214.63" y1="96.52" x2="214.63" y2="104.14" width="0.1524" layer="91"/> +<wire x1="238.76" y1="153.67" x2="238.76" y2="154.94" width="0.1524" layer="91"/> +<junction x="226.06" y="153.67"/> +<junction x="219.71" y="153.67"/> +<junction x="232.41" y="153.67"/> +<junction x="214.63" y="119.38"/> +<junction x="214.63" y="111.76"/> +<junction x="214.63" y="104.14"/> +<junction x="238.76" y="153.67"/> +<pinref part="EP1-CON" gate="CORE" pin="12"/> +<pinref part="C2L2" gate="C" pin="1"/> +<pinref part="C2L5" gate="C" pin="1"/> +<pinref part="C2L4" gate="C" pin="1"/> +<pinref part="C2L1" gate="C" pin="1"/> +<pinref part="EP1-CON" gate="CORE" pin="6"/> +<pinref part="EP1-CON" gate="CORE" pin="1"/> +<pinref part="EP1-CON" gate="CORE" pin="7"/> +<pinref part="U$276" gate="G$1" pin="AVDD"/> +</segment> +</net> +<net name="EP1-RXD3" class="0"> +<segment> +<wire x1="49.53" y1="82.55" x2="45.72" y2="82.55" width="0.1524" layer="91"/> +<wire x1="49.53" y1="138.43" x2="49.53" y2="82.55" width="0.1524" layer="91"/> +<wire x1="49.53" y1="82.55" x2="73.66" y2="82.55" width="0.1524" layer="91"/> +<junction x="49.53" y="82.55"/> +<pinref part="U6E1" gate="GBE1" pin="GBE1_RXDATA[3]"/> +<pinref part="R2R9" gate="R" pin="2"/> +<pinref part="R7E9" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-RXD1" class="0"> +<segment> +<wire x1="54.61" y1="87.63" x2="45.72" y2="87.63" width="0.1524" layer="91"/> +<wire x1="54.61" y1="138.43" x2="54.61" y2="87.63" width="0.1524" layer="91"/> +<wire x1="54.61" y1="87.63" x2="73.66" y2="87.63" width="0.1524" layer="91"/> +<junction x="54.61" y="87.63"/> +<pinref part="U6E1" gate="GBE1" pin="GBE1_RXDATA[1]"/> +<pinref part="R3R5" gate="R" pin="2"/> +<pinref part="R7E2" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-RXD0" class="0"> +<segment> +<wire x1="57.15" y1="90.17" x2="45.72" y2="90.17" width="0.1524" layer="91"/> +<wire x1="57.15" y1="138.43" x2="57.15" y2="90.17" width="0.1524" layer="91"/> +<wire x1="57.15" y1="90.17" x2="73.66" y2="90.17" width="0.1524" layer="91"/> +<junction x="57.15" y="90.17"/> +<pinref part="U6E1" gate="GBE1" pin="GBE1_RXDATA[0]"/> +<pinref part="R2R8" gate="R" pin="2"/> +<pinref part="R7E3" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-RXCTL" class="0"> +<segment> +<wire x1="45.72" y1="99.06" x2="59.69" y2="99.06" width="0.1524" layer="91"/> +<wire x1="59.69" y1="99.06" x2="59.69" y2="138.43" width="0.1524" layer="91"/> +<wire x1="73.66" y1="99.06" x2="59.69" y2="99.06" width="0.1524" layer="91"/> +<junction x="59.69" y="99.06"/> +<pinref part="R7E10" gate="R" pin="2"/> +<pinref part="R3R8" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE1" pin="GBE1_RXCTL"/> +</segment> +</net> +<net name="EP1-RXCLK" class="0"> +<segment> +<wire x1="45.72" y1="106.68" x2="67.31" y2="106.68" width="0.1524" layer="91"/> +<wire x1="67.31" y1="106.68" x2="67.31" y2="138.43" width="0.1524" layer="91"/> +<wire x1="67.31" y1="106.68" x2="73.66" y2="106.68" width="0.1524" layer="91"/> +<junction x="67.31" y="106.68"/> +<pinref part="R7E12" gate="R" pin="2"/> +<pinref part="R3R7" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE1" pin="GBE1_RXCLK"/> +</segment> +</net> +<net name="EP1-TXD3" class="0"> +<segment> +<wire x1="45.72" y1="120.65" x2="69.85" y2="120.65" width="0.1524" layer="91"/> +<wire x1="69.85" y1="120.65" x2="73.66" y2="120.65" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE1" pin="GBE1_TXDATA[3]"/> +<pinref part="R4R3" gate="R" pin="1"/> +</segment> +</net> +<net name="EP1-TXD2" class="0"> +<segment> +<wire x1="45.72" y1="123.19" x2="73.66" y2="123.19" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE1" pin="GBE1_TXDATA[2]"/> +<pinref part="R4R4" gate="R" pin="1"/> +</segment> +</net> +<net name="EP1-TXD1" class="0"> +<segment> +<wire x1="45.72" y1="125.73" x2="73.66" y2="125.73" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE1" pin="GBE1_TXDATA[1]"/> +<pinref part="R4R5" gate="R" pin="1"/> +</segment> +</net> +<net name="EP1-TXD0" class="0"> +<segment> +<wire x1="45.72" y1="128.27" x2="73.66" y2="128.27" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE1" pin="GBE1_TXDATA[0]"/> +<pinref part="R3R12" gate="R" pin="1"/> +</segment> +</net> +<net name="EP1-TXD0-R" class="0"> +<segment> +<wire x1="83.82" y1="128.27" x2="92.71" y2="128.27" width="0.1524" layer="91"/> +<wire x1="92.71" y1="128.27" x2="99.06" y2="128.27" width="0.1524" layer="91"/> +<wire x1="92.71" y1="138.43" x2="92.71" y2="128.27" width="0.1524" layer="91"/> +<junction x="92.71" y="128.27"/> +<pinref part="U8D1" gate="GB1" pin="P1_TXD[0]"/> +<pinref part="R3R12" gate="R" pin="2"/> +<pinref part="R7E8" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-TXD1-R" class="0"> +<segment> +<wire x1="83.82" y1="125.73" x2="90.17" y2="125.73" width="0.1524" layer="91"/> +<wire x1="90.17" y1="125.73" x2="99.06" y2="125.73" width="0.1524" layer="91"/> +<wire x1="90.17" y1="138.43" x2="90.17" y2="125.73" width="0.1524" layer="91"/> +<junction x="90.17" y="125.73"/> +<pinref part="U8D1" gate="GB1" pin="P1_TXD[1]"/> +<pinref part="R4R5" gate="R" pin="2"/> +<pinref part="R8E5" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-TXD2-R" class="0"> +<segment> +<wire x1="87.63" y1="123.19" x2="99.06" y2="123.19" width="0.1524" layer="91"/> +<wire x1="83.82" y1="123.19" x2="87.63" y2="123.19" width="0.1524" layer="91"/> +<wire x1="87.63" y1="138.43" x2="87.63" y2="123.19" width="0.1524" layer="91"/> +<junction x="87.63" y="123.19"/> +<pinref part="U8D1" gate="GB1" pin="P1_TXD[2]"/> +<pinref part="R4R4" gate="R" pin="2"/> +<pinref part="R7E6" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-TXD3-R" class="0"> +<segment> +<wire x1="83.82" y1="120.65" x2="85.09" y2="120.65" width="0.1524" layer="91"/> +<wire x1="85.09" y1="120.65" x2="99.06" y2="120.65" width="0.1524" layer="91"/> +<wire x1="85.09" y1="138.43" x2="85.09" y2="120.65" width="0.1524" layer="91"/> +<junction x="85.09" y="120.65"/> +<pinref part="U8D1" gate="GB1" pin="P1_TXD[3]"/> +<pinref part="R4R3" gate="R" pin="2"/> +<pinref part="R7E7" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-RXCLK-R" class="0"> +<segment> +<wire x1="83.82" y1="106.68" x2="99.06" y2="106.68" width="0.1524" layer="91"/> +<pinref part="R3R7" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_RX_CLK"/> +</segment> +</net> +<net name="EP1-RXCTL-R" class="0"> +<segment> +<wire x1="99.06" y1="99.06" x2="83.82" y2="99.06" width="0.1524" layer="91"/> +<pinref part="R3R8" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_RX_DV"/> +</segment> +</net> +<net name="EP1-RXD0-R" class="0"> +<segment> +<wire x1="83.82" y1="90.17" x2="99.06" y2="90.17" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB1" pin="P1_RXD[0]"/> +<pinref part="R2R8" gate="R" pin="1"/> +</segment> +</net> +<net name="EP1-RXD1-R" class="0"> +<segment> +<wire x1="83.82" y1="87.63" x2="99.06" y2="87.63" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB1" pin="P1_RXD[1]"/> +<pinref part="R3R5" gate="R" pin="1"/> +</segment> +</net> +<net name="EP1-RXD2-R" class="0"> +<segment> +<wire x1="83.82" y1="85.09" x2="99.06" y2="85.09" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB1" pin="P1_RXD[2]"/> +<pinref part="R3R6" gate="R" pin="1"/> +</segment> +</net> +<net name="EP1-RXD3-R" class="0"> +<segment> +<wire x1="83.82" y1="82.55" x2="99.06" y2="82.55" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB1" pin="P1_RXD[3]"/> +<pinref part="R2R9" gate="R" pin="1"/> +</segment> +</net> +<net name="EP1-MDIO" class="0"> +<segment> +<wire x1="53.34" y1="71.12" x2="60.96" y2="71.12" width="0.1524" layer="91"/> +<wire x1="60.96" y1="71.12" x2="60.96" y2="66.04" width="0.1524" layer="91"/> +<wire x1="60.96" y1="66.04" x2="60.96" y2="64.77" width="0.1524" layer="91"/> +<wire x1="60.96" y1="64.77" x2="99.06" y2="64.77" width="0.1524" layer="91"/> +<wire x1="53.34" y1="66.04" x2="60.96" y2="66.04" width="0.1524" layer="91"/> +<junction x="60.96" y="66.04"/> +<pinref part="R8E12" gate="R" pin="2"/> +<pinref part="R7E23" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB1" pin="P1_MDIO"/> +</segment> +</net> +<net name="EP1-MDC" class="0"> +<segment> +<wire x1="53.34" y1="55.88" x2="60.96" y2="55.88" width="0.1524" layer="91"/> +<wire x1="60.96" y1="55.88" x2="60.96" y2="60.96" width="0.1524" layer="91"/> +<wire x1="60.96" y1="60.96" x2="60.96" y2="62.23" width="0.1524" layer="91"/> +<wire x1="60.96" y1="62.23" x2="99.06" y2="62.23" width="0.1524" layer="91"/> +<wire x1="53.34" y1="60.96" x2="60.96" y2="60.96" width="0.1524" layer="91"/> +<junction x="60.96" y="60.96"/> +<pinref part="R8E15" gate="R" pin="2"/> +<pinref part="R7E21" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB1" pin="P1_MDC"/> +</segment> +</net> +<net name="EP1-CONFIG1" class="0"> +<segment> +<wire x1="99.06" y1="54.61" x2="80.01" y2="54.61" width="0.1524" layer="91"/> +<wire x1="80.01" y1="54.61" x2="80.01" y2="44.45" width="0.1524" layer="91"/> +<wire x1="80.01" y1="44.45" x2="73.66" y2="44.45" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB1" pin="P1_CONFIG1"/> +<label x="73.66" y="44.45" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP1-CONFIG2" class="0"> +<segment> +<wire x1="99.06" y1="52.07" x2="82.55" y2="52.07" width="0.1524" layer="91"/> +<wire x1="82.55" y1="52.07" x2="82.55" y2="39.37" width="0.1524" layer="91"/> +<wire x1="82.55" y1="39.37" x2="73.66" y2="39.37" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB1" pin="P1_CONFIG2"/> +<label x="73.66" y="39.37" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP1-CONFIG3" class="0"> +<segment> +<wire x1="127" y1="31.75" x2="110.49" y2="31.75" width="0.1524" layer="91"/> +<wire x1="110.49" y1="31.75" x2="110.49" y2="34.29" width="0.1524" layer="91"/> +<wire x1="110.49" y1="34.29" x2="110.49" y2="36.83" width="0.1524" layer="91"/> +<wire x1="110.49" y1="36.83" x2="127" y2="36.83" width="0.1524" layer="91"/> +<wire x1="127" y1="34.29" x2="110.49" y2="34.29" width="0.1524" layer="91"/> +<wire x1="110.49" y1="36.83" x2="95.25" y2="36.83" width="0.1524" layer="91"/> +<wire x1="95.25" y1="36.83" x2="95.25" y2="31.75" width="0.1524" layer="91"/> +<wire x1="95.25" y1="31.75" x2="73.66" y2="31.75" width="0.1524" layer="91"/> +<wire x1="99.06" y1="45.72" x2="95.25" y2="45.72" width="0.1524" layer="91"/> +<wire x1="95.25" y1="45.72" x2="95.25" y2="36.83" width="0.1524" layer="91"/> +<junction x="110.49" y="34.29"/> +<junction x="110.49" y="36.83"/> +<junction x="95.25" y="36.83"/> +<pinref part="R3N22" gate="R" pin="2"/> +<pinref part="R3N11" gate="R" pin="2"/> +<pinref part="R2N24" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB1" pin="P1_CONFIG3"/> +<label x="73.66" y="31.75" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP1-INT-N" class="0"> +<segment> +<wire x1="158.75" y1="146.05" x2="168.91" y2="146.05" width="0.1524" layer="91"/> +<wire x1="168.91" y1="146.05" x2="180.34" y2="146.05" width="0.1524" layer="91"/> +<wire x1="146.05" y1="134.62" x2="168.91" y2="134.62" width="0.1524" layer="91"/> +<wire x1="168.91" y1="134.62" x2="168.91" y2="146.05" width="0.1524" layer="91"/> +<junction x="168.91" y="146.05"/> +<label x="148.2725" y="135.255" size="1.778" layer="92"/> +<pinref part="R2P10" gate="R" pin="1"/> +<pinref part="R2P7" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB1" pin="P1_INTN"/> +</segment> +</net> +<net name="EP1-$1" class="0"> +<segment> +<wire x1="173.99" y1="130.81" x2="177.8" y2="130.81" width="0.1524" layer="91"/> +<wire x1="177.8" y1="130.81" x2="185.42" y2="130.81" width="0.1524" layer="91"/> +<wire x1="173.99" y1="128.27" x2="177.8" y2="128.27" width="0.1524" layer="91"/> +<wire x1="177.8" y1="128.27" x2="177.8" y2="130.81" width="0.1524" layer="91"/> +<junction x="177.8" y="130.81"/> +<pinref part="R2M17" gate="R" pin="2"/> +<pinref part="C2M12" gate="C" pin="1"/> +<pinref part="R2M18" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-$2" class="0"> +<segment> +<wire x1="177.8" y1="120.65" x2="184.15" y2="120.65" width="0.1524" layer="91"/> +<wire x1="184.15" y1="120.65" x2="184.15" y2="123.19" width="0.1524" layer="91"/> +<wire x1="184.15" y1="123.19" x2="189.23" y2="123.19" width="0.1524" layer="91"/> +<wire x1="184.15" y1="123.19" x2="177.8" y2="123.19" width="0.1524" layer="91"/> +<junction x="184.15" y="123.19"/> +<pinref part="R2M16" gate="R" pin="2"/> +<pinref part="C2M11" gate="C" pin="1"/> +<pinref part="R2M15" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-$3" class="0"> +<segment> +<wire x1="177.8" y1="92.71" x2="181.61" y2="92.71" width="0.1524" layer="91"/> +<wire x1="181.61" y1="92.71" x2="181.61" y2="95.25" width="0.1524" layer="91"/> +<wire x1="181.61" y1="95.25" x2="187.96" y2="95.25" width="0.1524" layer="91"/> +<wire x1="181.61" y1="95.25" x2="177.8" y2="95.25" width="0.1524" layer="91"/> +<junction x="181.61" y="95.25"/> +<pinref part="R2M14" gate="R" pin="2"/> +<pinref part="C2M10" gate="C" pin="1"/> +<pinref part="R2M13" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-$4" class="0"> +<segment> +<wire x1="186.69" y1="87.63" x2="181.61" y2="87.63" width="0.1524" layer="91"/> +<wire x1="181.61" y1="87.63" x2="173.99" y2="87.63" width="0.1524" layer="91"/> +<wire x1="173.99" y1="85.09" x2="181.61" y2="85.09" width="0.1524" layer="91"/> +<wire x1="181.61" y1="85.09" x2="181.61" y2="87.63" width="0.1524" layer="91"/> +<junction x="181.61" y="87.63"/> +<pinref part="R2M11" gate="R" pin="2"/> +<pinref part="C2M9" gate="C" pin="1"/> +<pinref part="R2M12" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-$7" class="0"> +<segment> +<wire x1="160.02" y1="71.12" x2="160.02" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS8C5" gate="LED" pin="A"/> +<pinref part="R2N12" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-$8" class="0"> +<segment> +<wire x1="170.18" y1="71.12" x2="170.18" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS7C7" gate="LED" pin="A"/> +<pinref part="R3N4" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-$9" class="0"> +<segment> +<wire x1="180.34" y1="71.12" x2="180.34" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS7C6" gate="LED" pin="A"/> +<pinref part="R3N5" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-$10" class="0"> +<segment> +<wire x1="189.23" y1="71.12" x2="189.23" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS8C1" gate="LED" pin="A"/> +<pinref part="R2N16" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-$11" class="0"> +<segment> +<wire x1="199.39" y1="71.12" x2="199.39" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS8C2" gate="LED" pin="A"/> +<pinref part="R2N15" gate="R" pin="2"/> +</segment> +</net> +<net name="EP1-LINK100" class="0"> +<segment> +<wire x1="146.05" y1="48.26" x2="152.4" y2="48.26" width="0.1524" layer="91"/> +<wire x1="152.4" y1="48.26" x2="170.18" y2="48.26" width="0.1524" layer="91"/> +<wire x1="170.18" y1="48.26" x2="170.18" y2="62.23" width="0.1524" layer="91"/> +<wire x1="170.18" y1="48.26" x2="185.42" y2="48.26" width="0.1524" layer="91"/> +<wire x1="152.4" y1="48.26" x2="152.4" y2="31.75" width="0.1524" layer="91"/> +<wire x1="152.4" y1="31.75" x2="137.16" y2="31.75" width="0.1524" layer="91"/> +<wire x1="152.4" y1="31.75" x2="152.4" y2="21.59" width="0.1524" layer="91"/> +<wire x1="152.4" y1="21.59" x2="152.4" y2="7.62" width="0.1524" layer="91"/> +<wire x1="152.4" y1="7.62" x2="137.16" y2="7.62" width="0.1524" layer="91"/> +<wire x1="137.16" y1="21.59" x2="152.4" y2="21.59" width="0.1524" layer="91"/> +<junction x="170.18" y="48.26"/> +<junction x="152.4" y="48.26"/> +<junction x="152.4" y="31.75"/> +<junction x="152.4" y="21.59"/> +<pinref part="DS7C7" gate="LED" pin="K"/> +<pinref part="R3N22" gate="R" pin="1"/> +<pinref part="R3N23" gate="R" pin="1"/> +<pinref part="R3N13" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_LINK100"/> +<label x="185.42" y="48.26" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP1-LINK10" class="0"> +<segment> +<wire x1="146.05" y1="45.72" x2="149.86" y2="45.72" width="0.1524" layer="91"/> +<wire x1="149.86" y1="45.72" x2="180.34" y2="45.72" width="0.1524" layer="91"/> +<wire x1="180.34" y1="45.72" x2="180.34" y2="62.23" width="0.1524" layer="91"/> +<wire x1="180.34" y1="45.72" x2="223.52" y2="45.72" width="0.1524" layer="91"/> +<wire x1="137.16" y1="36.83" x2="149.86" y2="36.83" width="0.1524" layer="91"/> +<wire x1="149.86" y1="36.83" x2="149.86" y2="45.72" width="0.1524" layer="91"/> +<wire x1="149.86" y1="36.83" x2="149.86" y2="26.67" width="0.1524" layer="91"/> +<wire x1="149.86" y1="26.67" x2="149.86" y2="19.05" width="0.1524" layer="91"/> +<wire x1="149.86" y1="19.05" x2="149.86" y2="12.7" width="0.1524" layer="91"/> +<wire x1="149.86" y1="12.7" x2="137.16" y2="12.7" width="0.1524" layer="91"/> +<wire x1="137.16" y1="26.67" x2="149.86" y2="26.67" width="0.1524" layer="91"/> +<wire x1="137.16" y1="19.05" x2="149.86" y2="19.05" width="0.1524" layer="91"/> +<junction x="180.34" y="45.72"/> +<junction x="149.86" y="45.72"/> +<junction x="149.86" y="36.83"/> +<junction x="149.86" y="26.67"/> +<junction x="149.86" y="19.05"/> +<pinref part="DS7C6" gate="LED" pin="K"/> +<pinref part="R3N11" gate="R" pin="1"/> +<pinref part="R3N12" gate="R" pin="1"/> +<pinref part="R3N19" gate="R" pin="1"/> +<pinref part="R3N18" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_LINK10"/> +<label x="223.52" y="45.72" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP1-MDI0-P" class="0"> +<segment> +<wire x1="146.05" y1="116.84" x2="152.4" y2="116.84" width="0.1524" layer="91"/> +<wire x1="152.4" y1="116.84" x2="185.42" y2="116.84" width="0.1524" layer="91"/> +<wire x1="185.42" y1="116.84" x2="207.01" y2="116.84" width="0.1524" layer="91"/> +<wire x1="220.98" y1="121.92" x2="207.01" y2="121.92" width="0.1524" layer="91"/> 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y2="128.27" width="0.1524" layer="91"/> +<wire x1="154.94" y1="128.27" x2="154.94" y2="114.3" width="0.1524" layer="91"/> +<junction x="154.94" y="114.3"/> +<label x="187.0075" y="114.6175" size="1.778" layer="92"/> +<pinref part="EP1-CON" gate="CORE" pin="10"/> +<pinref part="R2M18" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_MDI[0]-"/> +</segment> +</net> +<net name="EP1-MDI1-P" class="0"> +<segment> +<wire x1="146.05" y1="111.76" x2="157.48" y2="111.76" width="0.1524" layer="91"/> +<wire x1="157.48" y1="111.76" x2="201.93" y2="111.76" width="0.1524" layer="91"/> +<wire x1="201.93" y1="111.76" x2="212.09" y2="111.76" width="0.1524" layer="91"/> +<wire x1="212.09" y1="111.76" x2="212.09" y2="114.3" width="0.1524" layer="91"/> +<wire x1="212.09" y1="114.3" x2="220.98" y2="114.3" width="0.1524" layer="91"/> +<wire x1="167.64" y1="123.19" x2="157.48" y2="123.19" width="0.1524" layer="91"/> +<wire x1="157.48" y1="123.19" x2="157.48" y2="111.76" width="0.1524" layer="91"/> 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class="0"> +<segment> +<wire x1="146.05" y1="106.68" x2="160.02" y2="106.68" width="0.1524" layer="91"/> +<wire x1="160.02" y1="106.68" x2="201.93" y2="106.68" width="0.1524" layer="91"/> +<wire x1="201.93" y1="106.68" x2="220.98" y2="106.68" width="0.1524" layer="91"/> +<wire x1="167.64" y1="95.25" x2="160.02" y2="95.25" width="0.1524" layer="91"/> +<wire x1="160.02" y1="95.25" x2="160.02" y2="106.68" width="0.1524" layer="91"/> +<junction x="160.02" y="106.68"/> +<label x="187.0075" y="106.9975" size="1.778" layer="92"/> +<pinref part="EP1-CON" gate="CORE" pin="3"/> +<pinref part="R2M13" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_MDI[2]+"/> +</segment> +</net> +<net name="EP1-MDI2-N" class="0"> +<segment> +<wire x1="212.09" y1="101.6" x2="220.98" y2="101.6" width="0.1524" layer="91"/> +<wire x1="212.09" y1="104.14" x2="212.09" y2="101.6" width="0.1524" layer="91"/> +<wire x1="146.05" y1="104.14" x2="157.48" y2="104.14" width="0.1524" layer="91"/> +<wire x1="157.48" y1="104.14" x2="191.77" y2="104.14" width="0.1524" layer="91"/> +<wire x1="191.77" y1="104.14" x2="212.09" y2="104.14" width="0.1524" layer="91"/> +<wire x1="167.64" y1="92.71" x2="157.48" y2="92.71" width="0.1524" layer="91"/> +<wire x1="157.48" y1="92.71" x2="157.48" y2="104.14" width="0.1524" layer="91"/> +<junction x="157.48" y="104.14"/> +<label x="187.0075" y="104.4575" size="1.778" layer="92"/> +<pinref part="EP1-CON" gate="CORE" pin="2"/> +<pinref part="R2M14" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_MDI[2]-"/> +</segment> +</net> +<net name="EP1-MDI3-P" class="0"> +<segment> +<wire x1="146.05" y1="101.6" x2="154.94" y2="101.6" width="0.1524" layer="91"/> +<wire x1="154.94" y1="101.6" x2="186.69" y2="101.6" width="0.1524" layer="91"/> +<wire x1="186.69" y1="101.6" x2="209.55" y2="101.6" width="0.1524" layer="91"/> +<wire x1="209.55" y1="101.6" x2="209.55" y2="99.06" width="0.1524" layer="91"/> +<wire x1="209.55" y1="99.06" x2="220.98" y2="99.06" width="0.1524" layer="91"/> +<wire x1="154.94" y1="87.63" x2="154.94" y2="101.6" width="0.1524" layer="91"/> +<wire x1="163.83" y1="87.63" x2="154.94" y2="87.63" width="0.1524" layer="91"/> +<junction x="154.94" y="101.6"/> +<label x="187.0075" y="101.9175" size="1.778" layer="92"/> +<pinref part="EP1-CON" gate="CORE" pin="8"/> +<pinref part="R2M11" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_MDI[3]+"/> +</segment> +</net> +<net name="EP1-MDI3-N" class="0"> +<segment> +<wire x1="146.05" y1="99.06" x2="152.4" y2="99.06" width="0.1524" layer="91"/> +<wire x1="152.4" y1="99.06" x2="175.26" y2="99.06" width="0.1524" layer="91"/> +<wire x1="175.26" y1="99.06" x2="207.01" y2="99.06" width="0.1524" layer="91"/> +<wire x1="207.01" y1="99.06" x2="207.01" y2="93.98" width="0.1524" layer="91"/> +<wire x1="207.01" y1="93.98" x2="220.98" y2="93.98" width="0.1524" layer="91"/> +<wire x1="152.4" y1="85.09" x2="152.4" y2="99.06" width="0.1524" layer="91"/> +<wire x1="163.83" y1="85.09" x2="152.4" y2="85.09" width="0.1524" layer="91"/> +<junction x="152.4" y="99.06"/> +<label x="187.0075" y="99.3775" size="1.778" layer="92"/> +<pinref part="EP1-CON" gate="CORE" pin="9"/> +<pinref part="R2M12" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_MDI[3]-"/> +</segment> +</net> +<net name="EP1-RST" class="0"> +<segment> +<wire x1="110.49" y1="144.78" x2="95.25" y2="144.78" width="0.1524" layer="91"/> +<wire x1="95.25" y1="144.78" x2="95.25" y2="132.08" width="0.1524" layer="91"/> +<wire x1="95.25" y1="132.08" x2="99.06" y2="132.08" width="0.1524" layer="91"/> +<pinref part="R2P5" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB1" pin="P1_RSET"/> +</segment> +</net> +<net name="EP1-$19" class="0"> +<segment> +<wire x1="146.05" y1="55.88" x2="207.01" y2="55.88" width="0.1524" layer="91"/> +<wire x1="207.01" y1="55.88" x2="207.01" y2="72.39" width="0.1524" layer="91"/> +<wire x1="212.09" y1="72.39" x2="207.01" y2="72.39" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB1" pin="P1_LED_TX"/> +<pinref part="R2L2" gate="R" pin="1"/> +</segment> +</net> +<net name="EP1-$20" class="0"> +<segment> +<wire x1="189.23" y1="53.34" x2="189.23" y2="62.23" width="0.1524" layer="91"/> +<wire x1="146.05" y1="53.34" x2="149.86" y2="53.34" width="0.1524" layer="91"/> +<wire x1="149.86" y1="53.34" x2="156.21" y2="53.34" width="0.1524" layer="91"/> +<wire x1="156.21" y1="53.34" x2="189.23" y2="53.34" width="0.1524" layer="91"/> +<wire x1="156.21" y1="53.34" x2="156.21" y2="34.29" width="0.1524" layer="91"/> +<wire x1="156.21" y1="34.29" x2="156.21" y2="24.13" width="0.1524" layer="91"/> +<wire x1="156.21" y1="24.13" x2="156.21" y2="10.16" width="0.1524" layer="91"/> +<wire x1="156.21" y1="10.16" x2="137.16" y2="10.16" width="0.1524" layer="91"/> +<wire x1="137.16" y1="34.29" x2="156.21" y2="34.29" width="0.1524" layer="91"/> +<wire x1="137.16" y1="24.13" x2="156.21" y2="24.13" width="0.1524" layer="91"/> +<junction x="156.21" y="53.34"/> +<junction x="156.21" y="34.29"/> +<junction x="156.21" y="24.13"/> +<pinref part="DS8C1" gate="LED" pin="K"/> +<pinref part="R2N22" gate="R" pin="1"/> +<pinref part="R2N24" gate="R" pin="1"/> +<pinref part="R2N23" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB1" pin="P1_DUPLEX"/> +</segment> +</net> +<net name="EP1-$18" class="0"> +<segment> +<wire x1="146.05" y1="58.42" x2="199.39" y2="58.42" width="0.1524" layer="91"/> +<wire x1="199.39" y1="58.42" x2="199.39" y2="62.23" width="0.1524" layer="91"/> +<pinref part="DS8C2" gate="LED" pin="K"/> +<pinref part="U8D1" gate="GB1" pin="P1_LED_RX"/> +</segment> +</net> +<net name="V2P5" class="0"> +<segment> +<wire x1="64.77" y1="148.59" x2="64.77" y2="154.94" width="0.1524" layer="91"/> +<wire x1="67.31" y1="148.59" x2="67.31" y2="154.94" width="0.1524" layer="91"/> +<wire x1="67.31" y1="154.94" x2="64.77" y2="154.94" width="0.1524" layer="91"/> +<wire x1="64.77" y1="154.94" x2="62.23" y2="154.94" width="0.1524" layer="91"/> +<wire x1="62.23" y1="148.59" x2="62.23" y2="154.94" width="0.1524" layer="91"/> +<wire x1="62.23" y1="154.94" x2="59.69" y2="154.94" width="0.1524" layer="91"/> +<wire x1="59.69" y1="154.94" x2="59.69" y2="148.59" width="0.1524" layer="91"/> +<wire x1="57.15" y1="154.94" x2="59.69" y2="154.94" width="0.1524" layer="91"/> +<wire x1="57.15" y1="148.59" x2="57.15" y2="154.94" width="0.1524" layer="91"/> +<wire x1="54.61" y1="154.94" x2="57.15" y2="154.94" width="0.1524" layer="91"/> +<wire x1="54.61" y1="148.59" x2="54.61" y2="154.94" width="0.1524" layer="91"/> +<wire x1="52.07" y1="154.94" x2="54.61" y2="154.94" width="0.1524" layer="91"/> +<wire x1="52.07" y1="148.59" x2="52.07" y2="154.94" width="0.1524" layer="91"/> +<wire x1="49.53" y1="154.94" x2="52.07" y2="154.94" width="0.1524" layer="91"/> +<wire x1="49.53" y1="154.94" x2="49.53" y2="157.48" width="0.1524" layer="91"/> +<wire x1="49.53" y1="148.59" x2="49.53" y2="154.94" width="0.1524" layer="91"/> +<junction x="64.77" y="154.94"/> +<junction x="62.23" y="154.94"/> +<junction x="59.69" y="154.94"/> +<junction x="57.15" y="154.94"/> +<junction x="54.61" y="154.94"/> +<junction x="52.07" y="154.94"/> +<junction x="49.53" y="154.94"/> +<pinref part="U$279" gate="G$1" pin="V2P5"/> +<pinref part="R7E10" gate="R" pin="1"/> +<pinref part="R8E4" gate="R" pin="1"/> +<pinref part="R7E12" gate="R" pin="1"/> +<pinref part="R7E5" gate="R" pin="1"/> +<pinref part="R7E9" gate="R" pin="1"/> +<pinref part="R7E4" gate="R" pin="1"/> +<pinref part="R7E2" gate="R" pin="1"/> +<pinref part="R7E3" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="92.71" y1="154.94" x2="92.71" y2="148.59" width="0.1524" layer="91"/> +<wire x1="90.17" y1="154.94" x2="90.17" y2="148.59" width="0.1524" layer="91"/> +<wire x1="90.17" y1="154.94" x2="92.71" y2="154.94" width="0.1524" layer="91"/> +<wire x1="87.63" y1="148.59" x2="87.63" y2="154.94" width="0.1524" layer="91"/> +<wire x1="87.63" y1="154.94" x2="90.17" y2="154.94" width="0.1524" layer="91"/> +<wire x1="87.63" y1="154.94" x2="85.09" y2="154.94" width="0.1524" layer="91"/> +<wire x1="85.09" y1="154.94" x2="85.09" y2="148.59" width="0.1524" layer="91"/> +<wire x1="85.09" y1="154.94" x2="85.09" y2="157.48" width="0.1524" layer="91"/> +<junction x="90.17" y="154.94"/> +<junction x="87.63" y="154.94"/> +<junction x="85.09" y="154.94"/> +<pinref part="U$448" gate="G$1" pin="V2P5"/> +<pinref part="R7E8" gate="R" pin="1"/> +<pinref part="R8E5" gate="R" pin="1"/> +<pinref part="R7E6" gate="R" pin="1"/> +<pinref part="R7E7" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="35.56" y1="71.12" x2="43.18" y2="71.12" width="0.1524" layer="91"/> +<pinref part="R8E12" gate="R" pin="1"/> +<pinref part="U$133" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="160.02" y1="81.28" x2="160.02" y2="82.55" width="0.1524" layer="91"/> +<wire x1="160.02" y1="82.55" x2="170.18" y2="82.55" width="0.1524" layer="91"/> +<wire x1="170.18" y1="82.55" x2="180.34" y2="82.55" width="0.1524" layer="91"/> +<wire x1="180.34" y1="82.55" x2="189.23" y2="82.55" width="0.1524" layer="91"/> +<wire x1="189.23" y1="82.55" x2="199.39" y2="82.55" width="0.1524" layer="91"/> +<wire x1="199.39" y1="82.55" x2="208.28" y2="82.55" width="0.1524" layer="91"/> +<wire x1="208.28" y1="82.55" x2="208.28" y2="83.82" width="0.1524" layer="91"/> +<wire x1="199.39" y1="81.28" x2="199.39" y2="82.55" width="0.1524" layer="91"/> +<wire x1="189.23" y1="81.28" x2="189.23" y2="82.55" width="0.1524" layer="91"/> +<wire x1="180.34" y1="81.28" x2="180.34" y2="82.55" width="0.1524" layer="91"/> +<wire x1="170.18" y1="81.28" x2="170.18" y2="82.55" width="0.1524" layer="91"/> +<junction x="199.39" y="82.55"/> +<junction x="189.23" y="82.55"/> +<junction x="180.34" y="82.55"/> +<junction x="170.18" y="82.55"/> +<pinref part="R2N12" gate="R" pin="1"/> +<pinref part="R2N15" gate="R" pin="1"/> +<pinref part="R2N16" gate="R" pin="1"/> +<pinref part="R3N5" gate="R" pin="1"/> +<pinref part="R3N4" gate="R" pin="1"/> +<pinref part="U$140" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="241.3" y1="64.77" x2="256.54" y2="64.77" width="0.1524" layer="91"/> +<wire x1="256.54" y1="64.77" x2="256.54" y2="72.39" width="0.1524" layer="91"/> +<wire x1="256.54" y1="72.39" x2="256.54" y2="76.2" width="0.1524" layer="91"/> +<wire x1="241.3" y1="72.39" x2="256.54" y2="72.39" width="0.1524" layer="91"/> +<junction x="256.54" y="72.39"/> +<pinref part="EP1-CON" gate="LED2" pin="A"/> +<pinref part="EP1-CON" gate="LED1" pin="A"/> +<pinref part="U$132" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="148.59" y1="146.05" x2="144.78" y2="146.05" width="0.1524" layer="91"/> +<wire x1="144.78" y1="146.05" x2="144.78" y2="149.86" width="0.1524" layer="91"/> +<pinref part="R2P7" gate="R" pin="1"/> +<pinref part="U$131" gate="G$1" pin="V2P5"/> +</segment> +</net> +<net name="EP0-CONFIG3" class="0"> +<segment> +<wire x1="110.49" y1="12.7" x2="73.66" y2="12.7" width="0.1524" layer="91"/> +<wire x1="127" y1="7.62" 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+<pinref part="C3L7" gate="C" pin="2"/> +<pinref part="U$313" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="186.69" y1="139.7" x2="196.85" y2="139.7" width="0.1524" layer="91"/> +<pinref part="U$315" gate="G$1" pin="GND"/> +<pinref part="R2P11" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="93.98" y1="115.57" x2="95.25" y2="115.57" width="0.1524" layer="91"/> +<wire x1="95.25" y1="115.57" x2="95.25" y2="118.11" width="0.1524" layer="91"/> +<wire x1="95.25" y1="118.11" x2="99.06" y2="118.11" width="0.1524" layer="91"/> +<wire x1="99.06" y1="115.57" x2="95.25" y2="115.57" width="0.1524" layer="91"/> +<wire x1="99.06" y1="113.03" x2="95.25" y2="113.03" width="0.1524" layer="91"/> +<wire x1="95.25" y1="113.03" x2="95.25" y2="115.57" width="0.1524" layer="91"/> +<wire x1="99.06" y1="110.49" x2="95.25" y2="110.49" width="0.1524" layer="91"/> +<wire x1="95.25" y1="110.49" x2="95.25" y2="113.03" width="0.1524" layer="91"/> +<junction x="95.25" y="115.57"/> +<junction x="95.25" y="113.03"/> +<pinref part="U$319" gate="G$1" pin="GND"/> +<pinref part="U8D1" gate="GB2" pin="P2_TXD[4]"/> +<pinref part="U8D1" gate="GB2" pin="P2_TXD[5]"/> +<pinref part="U8D1" gate="GB2" pin="P2_TXD[6]"/> +<pinref part="U8D1" gate="GB2" pin="P2_TXD[7]"/> +</segment> +<segment> +<wire x1="132.08" y1="144.78" x2="121.92" y2="144.78" width="0.1524" layer="91"/> +<pinref part="R2P4" gate="R" pin="1"/> +<pinref part="U$322" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="97.79" y1="96.52" x2="99.06" y2="96.52" width="0.1524" layer="91"/> +<pinref part="U$323" gate="G$1" pin="GND"/> +<pinref part="U8D1" gate="GB2" pin="P2_TX_ER"/> +</segment> +<segment> +<wire x1="19.05" y1="53.34" x2="19.05" y2="55.88" width="0.1524" layer="91"/> +<wire x1="19.05" y1="55.88" x2="26.67" y2="55.88" width="0.1524" layer="91"/> +<pinref part="U$327" gate="G$1" pin="GND"/> +<pinref part="R8E16" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="200.66" y1="27.94" x2="200.66" y2="29.21" width="0.1524" layer="91"/> +<wire x1="200.66" y1="29.21" x2="200.66" y2="34.29" width="0.1524" layer="91"/> +<wire x1="200.66" y1="34.29" x2="205.74" y2="34.29" width="0.1524" layer="91"/> +<wire x1="207.01" y1="29.21" x2="200.66" y2="29.21" width="0.1524" layer="91"/> +<junction x="200.66" y="29.21"/> +<pinref part="U$332" gate="G$1" pin="GND"/> +<pinref part="FB9A1" gate="F" pin="1"/> +<pinref part="C9A3" gate="C" pin="1"/> +</segment> +</net> +<net name="GND-CHASSIS" class="0"> +<segment> +<wire x1="232.41" y1="88.9" x2="232.41" y2="90.17" width="0.1524" layer="91"/> +<wire x1="232.41" y1="90.17" x2="236.22" y2="90.17" width="0.1524" layer="91"/> +<wire x1="236.22" y1="91.44" x2="232.41" y2="91.44" width="0.1524" layer="91"/> +<wire x1="232.41" y1="91.44" x2="232.41" y2="90.17" width="0.1524" layer="91"/> +<junction x="232.41" y="90.17"/> +<pinref part="U$305" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="EP2-CON" gate="CORE" pin="SHIELD#2"/> +<pinref part="EP2-CON" gate="CORE" pin="SHIELD#1"/> +</segment> +<segment> +<wire x1="215.9" y1="34.29" x2="224.79" y2="34.29" width="0.1524" layer="91"/> +<wire x1="224.79" y1="34.29" x2="224.79" y2="29.21" width="0.1524" layer="91"/> +<wire x1="224.79" y1="29.21" x2="224.79" y2="27.94" width="0.1524" layer="91"/> +<wire x1="214.63" y1="29.21" x2="224.79" y2="29.21" width="0.1524" layer="91"/> +<junction x="224.79" y="29.21"/> +<pinref part="FB9A1" gate="F" pin="2"/> +<pinref part="U$328" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="C9A3" gate="C" pin="2"/> +</segment> +</net> +<net name="AVDD" class="0"> +<segment> +<wire x1="219.71" y1="152.4" x2="219.71" y2="144.78" width="0.1524" layer="91"/> +<wire x1="226.06" y1="152.4" x2="219.71" y2="152.4" width="0.1524" layer="91"/> +<wire x1="226.06" y1="152.4" x2="226.06" y2="144.78" width="0.1524" layer="91"/> +<wire x1="233.68" y1="152.4" x2="232.41" y2="152.4" width="0.1524" layer="91"/> +<wire x1="232.41" y1="152.4" x2="226.06" y2="152.4" width="0.1524" layer="91"/> +<wire x1="233.68" y1="152.4" x2="238.76" y2="152.4" width="0.1524" layer="91"/> +<wire x1="219.71" y1="152.4" x2="214.63" y2="152.4" width="0.1524" layer="91"/> +<wire x1="214.63" y1="152.4" x2="214.63" y2="119.38" width="0.1524" layer="91"/> +<wire x1="214.63" y1="119.38" x2="220.98" y2="119.38" width="0.1524" layer="91"/> +<wire x1="232.41" y1="144.78" x2="232.41" y2="152.4" width="0.1524" layer="91"/> +<wire x1="238.76" y1="144.78" x2="238.76" y2="152.4" width="0.1524" layer="91"/> +<wire x1="220.98" y1="111.76" x2="214.63" y2="111.76" width="0.1524" layer="91"/> +<wire x1="214.63" y1="111.76" x2="214.63" y2="119.38" width="0.1524" layer="91"/> +<wire x1="220.98" y1="104.14" x2="214.63" y2="104.14" width="0.1524" layer="91"/> +<wire x1="214.63" y1="104.14" x2="214.63" y2="111.76" width="0.1524" layer="91"/> +<wire x1="220.98" y1="96.52" x2="214.63" y2="96.52" width="0.1524" layer="91"/> +<wire x1="214.63" y1="96.52" x2="214.63" y2="104.14" width="0.1524" layer="91"/> +<wire x1="238.76" y1="152.4" x2="238.76" y2="153.67" width="0.1524" layer="91"/> +<junction x="226.06" y="152.4"/> +<junction x="219.71" y="152.4"/> +<junction x="232.41" y="152.4"/> +<junction x="214.63" y="119.38"/> +<junction x="214.63" y="111.76"/> +<junction x="214.63" y="104.14"/> +<junction x="238.76" y="152.4"/> +<pinref part="EP2-CON" gate="CORE" pin="12"/> +<pinref part="C3L2" gate="C" pin="1"/> +<pinref part="C2L3" gate="C" pin="1"/> +<pinref part="C3L4" gate="C" pin="1"/> +<pinref part="C2L6" gate="C" pin="1"/> +<pinref part="EP2-CON" gate="CORE" pin="6"/> +<pinref part="EP2-CON" gate="CORE" pin="1"/> +<pinref part="EP2-CON" gate="CORE" pin="7"/> +<pinref part="U$310" gate="G$1" pin="AVDD"/> +</segment> +</net> +<net name="EP1-CONFIG1" class="0"> +<segment> +<wire x1="67.31" y1="31.75" x2="127" y2="31.75" width="0.1524" layer="91"/> +<pinref part="R2N21" gate="R" pin="2"/> +<label x="67.31" y="31.75" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="V2P5" class="0"> +<segment> +<wire x1="60.96" y1="152.4" x2="60.96" y2="161.29" width="0.1524" layer="91"/> +<wire x1="63.5" y1="152.4" x2="63.5" y2="161.29" width="0.1524" layer="91"/> +<wire x1="63.5" y1="161.29" x2="60.96" y2="161.29" width="0.1524" layer="91"/> +<wire x1="60.96" y1="161.29" x2="58.42" y2="161.29" width="0.1524" layer="91"/> +<wire x1="58.42" y1="152.4" x2="58.42" y2="161.29" width="0.1524" layer="91"/> +<wire x1="58.42" y1="161.29" x2="55.88" y2="161.29" width="0.1524" layer="91"/> +<wire x1="55.88" y1="161.29" x2="55.88" y2="152.4" width="0.1524" layer="91"/> +<wire x1="53.34" y1="161.29" x2="55.88" y2="161.29" width="0.1524" layer="91"/> +<wire x1="53.34" y1="152.4" x2="53.34" y2="161.29" width="0.1524" layer="91"/> +<wire x1="50.8" y1="161.29" x2="53.34" y2="161.29" width="0.1524" layer="91"/> +<wire x1="50.8" y1="152.4" x2="50.8" y2="161.29" width="0.1524" layer="91"/> +<wire x1="48.26" y1="161.29" x2="50.8" y2="161.29" width="0.1524" layer="91"/> +<wire x1="48.26" y1="152.4" x2="48.26" y2="161.29" width="0.1524" layer="91"/> +<wire x1="45.72" y1="161.29" x2="48.26" y2="161.29" width="0.1524" layer="91"/> +<wire x1="45.72" y1="161.29" x2="45.72" y2="163.83" width="0.1524" layer="91"/> +<wire x1="45.72" y1="152.4" x2="45.72" y2="161.29" width="0.1524" layer="91"/> +<junction x="60.96" y="161.29"/> +<junction x="58.42" y="161.29"/> +<junction x="55.88" y="161.29"/> +<junction x="53.34" y="161.29"/> +<junction x="50.8" y="161.29"/> +<junction x="48.26" y="161.29"/> +<junction x="45.72" y="161.29"/> +<pinref part="U$325" gate="G$1" pin="V2P5"/> +<pinref part="R7E1" gate="R" pin="1"/> +<pinref part="R7D5" gate="R" pin="1"/> +<pinref part="R7D9" gate="R" pin="1"/> +<pinref part="R7D1" gate="R" pin="1"/> +<pinref part="R6E2" gate="R" pin="1"/> +<pinref part="R7D10" gate="R" pin="1"/> +<pinref part="R7D8" gate="R" pin="1"/> +<pinref part="R6E1" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="88.9" y1="161.29" x2="88.9" y2="152.4" width="0.1524" layer="91"/> +<wire x1="86.36" y1="161.29" x2="86.36" y2="152.4" width="0.1524" layer="91"/> +<wire x1="86.36" y1="161.29" x2="88.9" y2="161.29" width="0.1524" layer="91"/> +<wire x1="83.82" y1="152.4" x2="83.82" y2="161.29" width="0.1524" layer="91"/> +<wire x1="83.82" y1="161.29" x2="86.36" y2="161.29" width="0.1524" layer="91"/> +<wire x1="83.82" y1="161.29" x2="81.28" y2="161.29" width="0.1524" layer="91"/> +<wire x1="81.28" y1="161.29" x2="81.28" y2="152.4" width="0.1524" layer="91"/> +<wire x1="81.28" y1="161.29" x2="81.28" y2="163.83" width="0.1524" layer="91"/> +<junction x="86.36" y="161.29"/> +<junction x="83.82" y="161.29"/> +<junction x="81.28" y="161.29"/> +<pinref part="R7D6" gate="R" pin="1"/> +<pinref part="R7D3" gate="R" pin="1"/> +<pinref part="R7D4" gate="R" pin="1"/> +<pinref part="R7D2" gate="R" pin="1"/> +<pinref part="U$453" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="152.4" y1="139.7" x2="147.32" y2="139.7" width="0.1524" layer="91"/> +<wire x1="147.32" y1="139.7" x2="147.32" y2="143.51" width="0.1524" layer="91"/> +<pinref part="R2P8" gate="R" pin="1"/> +<pinref part="U$148" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="240.03" y1="63.5" x2="255.27" y2="63.5" width="0.1524" layer="91"/> +<wire x1="255.27" y1="63.5" x2="255.27" y2="71.12" width="0.1524" layer="91"/> +<wire x1="255.27" y1="71.12" x2="255.27" y2="74.93" width="0.1524" layer="91"/> +<wire x1="240.03" y1="71.12" x2="255.27" y2="71.12" width="0.1524" layer="91"/> +<junction x="255.27" y="71.12"/> +<pinref part="EP2-CON" gate="LED1" pin="A"/> +<pinref part="EP2-CON" gate="LED2" pin="A"/> +<pinref part="U$146" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="160.02" y1="81.28" x2="160.02" y2="82.55" width="0.1524" layer="91"/> +<wire x1="160.02" y1="82.55" x2="170.18" y2="82.55" width="0.1524" layer="91"/> +<wire x1="170.18" y1="82.55" x2="180.34" y2="82.55" width="0.1524" layer="91"/> +<wire x1="180.34" y1="82.55" x2="189.23" y2="82.55" width="0.1524" layer="91"/> +<wire x1="189.23" y1="82.55" x2="199.39" y2="82.55" width="0.1524" layer="91"/> +<wire x1="199.39" y1="82.55" x2="208.28" y2="82.55" width="0.1524" layer="91"/> +<wire x1="208.28" y1="82.55" x2="208.28" y2="83.82" width="0.1524" layer="91"/> +<wire x1="199.39" y1="81.28" x2="199.39" y2="82.55" width="0.1524" layer="91"/> +<wire x1="189.23" y1="81.28" x2="189.23" y2="82.55" width="0.1524" layer="91"/> +<wire x1="180.34" y1="81.28" x2="180.34" y2="82.55" width="0.1524" layer="91"/> +<wire x1="170.18" y1="81.28" x2="170.18" y2="82.55" width="0.1524" layer="91"/> +<junction x="199.39" y="82.55"/> +<junction x="189.23" y="82.55"/> +<junction x="180.34" y="82.55"/> +<junction x="170.18" y="82.55"/> +<pinref part="R2N13" gate="R" pin="1"/> +<pinref part="R2N9" gate="R" pin="1"/> +<pinref part="R2N10" gate="R" pin="1"/> +<pinref part="R2N11" gate="R" pin="1"/> +<pinref part="R2N14" gate="R" pin="1"/> +<pinref part="U$143" gate="G$1" pin="V2P5"/> +</segment> +<segment> +<wire x1="19.05" y1="71.12" x2="26.67" y2="71.12" width="0.1524" layer="91"/> +<pinref part="R2R10" gate="R" pin="1"/> +<pinref part="U$142" gate="G$1" pin="V2P5"/> +</segment> +</net> +<net name="EP-MDIO" class="0"> +<segment> +<wire x1="26.67" y1="66.04" x2="19.05" y2="66.04" width="0.1524" layer="91"/> +<pinref part="R7E24" gate="R" pin="1"/> +<label x="19.05" y="66.04" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP-MDC" class="0"> +<segment> +<wire x1="26.67" y1="60.96" x2="19.05" y2="60.96" width="0.1524" layer="91"/> +<pinref part="R7E22" gate="R" pin="1"/> +<label x="19.05" y="60.96" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-RST" class="0"> +<segment> +<wire x1="111.76" y1="144.78" x2="95.25" y2="144.78" width="0.1524" layer="91"/> +<wire x1="95.25" y1="144.78" x2="95.25" y2="132.08" width="0.1524" layer="91"/> +<wire x1="95.25" y1="132.08" x2="99.06" y2="132.08" width="0.1524" layer="91"/> +<pinref part="R2P4" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB2" pin="P2_RSET"/> +</segment> +</net> +<net name="EP2-INT-N" class="0"> +<segment> +<wire x1="162.56" y1="139.7" x2="172.72" y2="139.7" width="0.1524" layer="91"/> +<wire x1="172.72" y1="139.7" x2="176.53" y2="139.7" width="0.1524" layer="91"/> +<wire x1="146.05" y1="134.62" x2="172.72" y2="134.62" width="0.1524" layer="91"/> +<wire x1="172.72" y1="134.62" x2="172.72" y2="139.7" width="0.1524" layer="91"/> +<junction x="172.72" y="139.7"/> +<label x="148.2725" y="135.255" size="1.778" layer="92"/> +<pinref part="R2P11" gate="R" pin="1"/> +<pinref part="R2P8" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB2" pin="P2_INTN"/> +</segment> +</net> +<net name="EP2-MDI0-P" class="0"> +<segment> +<wire x1="146.05" y1="116.84" x2="152.4" y2="116.84" width="0.1524" layer="91"/> +<wire x1="152.4" y1="116.84" x2="185.42" y2="116.84" width="0.1524" layer="91"/> +<wire x1="185.42" y1="116.84" x2="207.01" y2="116.84" width="0.1524" layer="91"/> +<wire x1="220.98" y1="121.92" x2="207.01" y2="121.92" width="0.1524" layer="91"/> +<wire x1="207.01" y1="121.92" x2="207.01" y2="116.84" width="0.1524" layer="91"/> +<wire x1="163.83" y1="130.81" x2="152.4" y2="130.81" width="0.1524" layer="91"/> +<wire x1="152.4" y1="130.81" x2="152.4" y2="116.84" width="0.1524" layer="91"/> +<junction x="152.4" y="116.84"/> +<label x="187.0075" y="117.1575" size="1.778" layer="92"/> +<pinref part="EP2-CON" gate="CORE" pin="11"/> +<pinref part="R3L3" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDI[0]+"/> +</segment> +</net> +<net name="EP2-MDI0-N" class="0"> +<segment> +<wire x1="209.55" y1="116.84" x2="220.98" y2="116.84" width="0.1524" layer="91"/> +<wire x1="209.55" y1="114.3" x2="209.55" y2="116.84" width="0.1524" layer="91"/> +<wire x1="146.05" y1="114.3" x2="154.94" y2="114.3" width="0.1524" layer="91"/> +<wire x1="154.94" y1="114.3" x2="175.26" y2="114.3" width="0.1524" layer="91"/> +<wire x1="175.26" y1="114.3" x2="209.55" y2="114.3" width="0.1524" layer="91"/> +<wire x1="163.83" y1="128.27" x2="154.94" y2="128.27" width="0.1524" layer="91"/> +<wire x1="154.94" y1="128.27" x2="154.94" y2="114.3" width="0.1524" layer="91"/> +<junction x="154.94" y="114.3"/> +<label x="187.0075" y="114.6175" size="1.778" layer="92"/> +<pinref part="EP2-CON" gate="CORE" pin="10"/> +<pinref part="R3L2" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDI[0]-"/> +</segment> +</net> +<net name="EP2-MDI1-P" class="0"> +<segment> +<wire x1="146.05" y1="111.76" x2="157.48" y2="111.76" width="0.1524" layer="91"/> +<wire x1="157.48" y1="111.76" x2="201.93" y2="111.76" width="0.1524" layer="91"/> +<wire x1="201.93" y1="111.76" x2="212.09" y2="111.76" width="0.1524" layer="91"/> +<wire x1="212.09" y1="111.76" x2="212.09" y2="114.3" width="0.1524" layer="91"/> +<wire x1="212.09" y1="114.3" x2="220.98" y2="114.3" width="0.1524" layer="91"/> +<wire x1="167.64" y1="123.19" x2="157.48" y2="123.19" width="0.1524" layer="91"/> +<wire x1="157.48" y1="123.19" x2="157.48" y2="111.76" width="0.1524" layer="91"/> +<junction x="157.48" y="111.76"/> +<label x="187.0075" y="112.0775" size="1.778" layer="92"/> +<pinref part="EP2-CON" gate="CORE" pin="4"/> +<pinref part="R3L5" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDI[1]+"/> +</segment> +</net> +<net name="EP2-MDI1-N" class="0"> +<segment> +<wire x1="146.05" y1="109.22" x2="160.02" y2="109.22" width="0.1524" layer="91"/> +<wire x1="160.02" y1="109.22" x2="191.77" y2="109.22" width="0.1524" layer="91"/> +<wire x1="191.77" y1="109.22" x2="220.98" y2="109.22" width="0.1524" layer="91"/> +<wire x1="167.64" y1="120.65" x2="160.02" y2="120.65" width="0.1524" layer="91"/> +<wire x1="160.02" y1="120.65" x2="160.02" y2="109.22" width="0.1524" layer="91"/> +<junction x="160.02" y="109.22"/> +<label x="187.0075" y="109.5375" size="1.778" layer="92"/> +<pinref part="EP2-CON" gate="CORE" pin="5"/> +<pinref part="R3L4" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDI[1]-"/> +</segment> +</net> +<net name="EP2-MDI2-P" class="0"> +<segment> +<wire x1="146.05" y1="106.68" x2="160.02" y2="106.68" width="0.1524" layer="91"/> +<wire x1="160.02" y1="106.68" x2="201.93" y2="106.68" width="0.1524" layer="91"/> +<wire x1="201.93" y1="106.68" x2="220.98" y2="106.68" width="0.1524" layer="91"/> +<wire x1="167.64" y1="95.25" x2="160.02" y2="95.25" width="0.1524" layer="91"/> +<wire x1="160.02" y1="95.25" x2="160.02" y2="106.68" width="0.1524" layer="91"/> +<junction x="160.02" y="106.68"/> +<label x="187.0075" y="106.9975" size="1.778" layer="92"/> +<pinref part="EP2-CON" gate="CORE" pin="3"/> +<pinref part="R3L7" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDI[2]+"/> +</segment> +</net> +<net name="EP2-MDI2-N" class="0"> +<segment> +<wire x1="212.09" y1="101.6" x2="220.98" y2="101.6" width="0.1524" layer="91"/> +<wire x1="212.09" y1="104.14" x2="212.09" y2="101.6" width="0.1524" layer="91"/> +<wire x1="146.05" y1="104.14" x2="157.48" y2="104.14" width="0.1524" layer="91"/> +<wire x1="157.48" y1="104.14" x2="191.77" y2="104.14" width="0.1524" layer="91"/> +<wire x1="191.77" y1="104.14" x2="212.09" y2="104.14" width="0.1524" layer="91"/> +<wire x1="167.64" y1="92.71" x2="157.48" y2="92.71" width="0.1524" layer="91"/> +<wire x1="157.48" y1="92.71" x2="157.48" y2="104.14" width="0.1524" layer="91"/> +<junction x="157.48" y="104.14"/> +<label x="187.0075" y="104.4575" size="1.778" layer="92"/> +<pinref part="EP2-CON" gate="CORE" pin="2"/> +<pinref part="R3L6" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDI[2]-"/> +</segment> +</net> +<net name="EP2-MDI3-P" class="0"> +<segment> +<wire x1="146.05" y1="101.6" x2="154.94" y2="101.6" width="0.1524" layer="91"/> +<wire x1="154.94" y1="101.6" x2="186.69" y2="101.6" width="0.1524" layer="91"/> +<wire x1="186.69" y1="101.6" x2="209.55" y2="101.6" width="0.1524" layer="91"/> +<wire x1="209.55" y1="101.6" x2="209.55" y2="99.06" width="0.1524" layer="91"/> +<wire x1="209.55" y1="99.06" x2="220.98" y2="99.06" width="0.1524" layer="91"/> +<wire x1="154.94" y1="87.63" x2="154.94" y2="101.6" width="0.1524" layer="91"/> +<wire x1="163.83" y1="87.63" x2="154.94" y2="87.63" width="0.1524" layer="91"/> +<junction x="154.94" y="101.6"/> +<label x="187.0075" y="101.9175" size="1.778" layer="92"/> +<pinref part="EP2-CON" gate="CORE" pin="8"/> +<pinref part="R3L9" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDI[3]+"/> +</segment> +</net> +<net name="EP2-MDI3-N" class="0"> +<segment> +<wire x1="146.05" y1="99.06" x2="152.4" y2="99.06" width="0.1524" layer="91"/> +<wire x1="152.4" y1="99.06" x2="175.26" y2="99.06" width="0.1524" layer="91"/> +<wire x1="175.26" y1="99.06" x2="207.01" y2="99.06" width="0.1524" layer="91"/> +<wire x1="207.01" y1="99.06" x2="207.01" y2="93.98" width="0.1524" layer="91"/> +<wire x1="207.01" y1="93.98" x2="220.98" y2="93.98" width="0.1524" layer="91"/> +<wire x1="152.4" y1="85.09" x2="152.4" y2="99.06" width="0.1524" layer="91"/> +<wire x1="163.83" y1="85.09" x2="152.4" y2="85.09" width="0.1524" layer="91"/> +<junction x="152.4" y="99.06"/> +<label x="187.0075" y="99.3775" size="1.778" layer="92"/> +<pinref part="EP2-CON" gate="CORE" pin="9"/> +<pinref part="R3L8" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDI[3]-"/> +</segment> +</net> +<net name="EP2-$12" class="0"> +<segment> +<wire x1="173.99" y1="130.81" x2="181.61" y2="130.81" width="0.1524" layer="91"/> +<wire x1="181.61" y1="130.81" x2="185.42" y2="130.81" width="0.1524" layer="91"/> +<wire x1="173.99" y1="128.27" x2="181.61" y2="128.27" width="0.1524" layer="91"/> +<wire x1="181.61" y1="128.27" x2="181.61" y2="130.81" width="0.1524" layer="91"/> +<junction x="181.61" y="130.81"/> +<pinref part="R3L3" gate="R" pin="2"/> +<pinref part="C3L5" gate="C" pin="1"/> +<pinref part="R3L2" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-$13" class="0"> +<segment> +<wire x1="177.8" y1="120.65" x2="184.15" y2="120.65" width="0.1524" layer="91"/> +<wire x1="184.15" y1="120.65" x2="184.15" y2="123.19" width="0.1524" layer="91"/> +<wire x1="184.15" y1="123.19" x2="189.23" y2="123.19" width="0.1524" layer="91"/> +<wire x1="184.15" y1="123.19" x2="177.8" y2="123.19" width="0.1524" layer="91"/> +<junction x="184.15" y="123.19"/> +<pinref part="R3L4" gate="R" pin="2"/> +<pinref part="C3L6" gate="C" pin="1"/> +<pinref part="R3L5" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-$14" class="0"> +<segment> +<wire x1="177.8" y1="92.71" x2="181.61" y2="92.71" width="0.1524" layer="91"/> +<wire x1="181.61" y1="92.71" x2="181.61" y2="95.25" width="0.1524" layer="91"/> +<wire x1="181.61" y1="95.25" x2="187.96" y2="95.25" width="0.1524" layer="91"/> +<wire x1="181.61" y1="95.25" x2="177.8" y2="95.25" width="0.1524" layer="91"/> +<junction x="181.61" y="95.25"/> +<pinref part="R3L6" gate="R" pin="2"/> +<pinref part="C3L7" gate="C" pin="1"/> +<pinref part="R3L7" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-$15" class="0"> +<segment> +<wire x1="186.69" y1="87.63" x2="181.61" y2="87.63" width="0.1524" layer="91"/> +<wire x1="181.61" y1="87.63" x2="173.99" y2="87.63" width="0.1524" layer="91"/> +<wire x1="173.99" y1="85.09" x2="181.61" y2="85.09" width="0.1524" layer="91"/> +<wire x1="181.61" y1="85.09" x2="181.61" y2="87.63" width="0.1524" layer="91"/> +<junction x="181.61" y="87.63"/> +<pinref part="R3L9" gate="R" pin="2"/> +<pinref part="C3L8" gate="C" pin="1"/> +<pinref part="R3L8" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-$22" class="0"> +<segment> +<wire x1="160.02" y1="71.12" x2="160.02" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS8C4" gate="LED" pin="A"/> +<pinref part="R2N13" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-$23" class="0"> +<segment> +<wire x1="170.18" y1="71.12" x2="170.18" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS8C3" gate="LED" pin="A"/> +<pinref part="R2N14" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-$24" class="0"> +<segment> +<wire x1="180.34" y1="71.12" x2="180.34" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS8C6" gate="LED" pin="A"/> +<pinref part="R2N11" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-$25" class="0"> +<segment> +<wire x1="189.23" y1="71.12" x2="189.23" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS8C7" gate="LED" pin="A"/> +<pinref part="R2N10" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-$26" class="0"> +<segment> +<wire x1="199.39" y1="71.12" x2="199.39" y2="69.85" width="0.1524" layer="91"/> +<pinref part="DS8C8" gate="LED" pin="A"/> +<pinref part="R2N9" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-MDIO" class="0"> +<segment> +<wire x1="36.83" y1="71.12" x2="48.26" y2="71.12" width="0.1524" layer="91"/> +<wire x1="48.26" y1="71.12" x2="48.26" y2="66.04" width="0.1524" layer="91"/> +<wire x1="48.26" y1="66.04" x2="48.26" y2="64.77" width="0.1524" layer="91"/> +<wire x1="48.26" y1="64.77" x2="99.06" y2="64.77" width="0.1524" layer="91"/> +<wire x1="36.83" y1="66.04" x2="48.26" y2="66.04" width="0.1524" layer="91"/> +<junction x="48.26" y="66.04"/> +<pinref part="R2R10" gate="R" pin="2"/> +<pinref part="R7E24" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDIO"/> +</segment> +</net> +<net name="EP2-MDC" class="0"> +<segment> +<wire x1="99.06" y1="62.23" x2="48.26" y2="62.23" width="0.1524" layer="91"/> +<wire x1="36.83" y1="55.88" x2="48.26" y2="55.88" width="0.1524" layer="91"/> +<wire x1="48.26" y1="55.88" x2="48.26" y2="60.96" width="0.1524" layer="91"/> +<wire x1="48.26" y1="60.96" x2="48.26" y2="62.23" width="0.1524" layer="91"/> +<wire x1="36.83" y1="60.96" x2="48.26" y2="60.96" width="0.1524" layer="91"/> +<junction x="48.26" y="60.96"/> +<pinref part="R8E16" gate="R" pin="2"/> +<pinref part="R7E22" gate="R" pin="2"/> +<pinref part="U8D1" gate="GB2" pin="P2_MDC"/> +</segment> +</net> +<net name="EP2-LINK100" class="0"> +<segment> +<wire x1="146.05" y1="48.26" x2="170.18" y2="48.26" width="0.1524" layer="91"/> +<wire x1="170.18" y1="48.26" x2="170.18" y2="62.23" width="0.1524" layer="91"/> +<wire x1="170.18" y1="48.26" x2="190.5" y2="48.26" width="0.1524" layer="91"/> +<junction x="170.18" y="48.26"/> +<pinref part="DS8C3" gate="LED" pin="K"/> +<pinref part="U8D1" gate="GB2" pin="P2_LINK100"/> +<label x="190.5" y="48.26" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP2-LINK10" class="0"> +<segment> +<wire x1="152.4" y1="24.13" x2="137.16" y2="24.13" width="0.1524" layer="91"/> +<wire x1="146.05" y1="45.72" x2="152.4" y2="45.72" width="0.1524" layer="91"/> +<wire x1="152.4" y1="45.72" x2="180.34" y2="45.72" width="0.1524" layer="91"/> +<wire x1="180.34" y1="45.72" x2="180.34" y2="62.23" width="0.1524" layer="91"/> +<wire x1="180.34" y1="45.72" x2="227.33" y2="45.72" width="0.1524" layer="91"/> +<wire x1="152.4" y1="45.72" x2="152.4" y2="35.56" width="0.1524" layer="91"/> +<wire x1="152.4" y1="35.56" x2="152.4" y2="31.75" width="0.1524" layer="91"/> +<wire x1="152.4" y1="31.75" x2="152.4" y2="27.94" width="0.1524" layer="91"/> +<wire x1="152.4" y1="27.94" x2="137.16" y2="27.94" width="0.1524" layer="91"/> +<wire x1="152.4" y1="31.75" x2="137.16" y2="31.75" width="0.1524" layer="91"/> +<wire x1="137.16" y1="35.56" x2="152.4" y2="35.56" width="0.1524" layer="91"/> +<wire x1="152.4" y1="24.13" x2="152.4" y2="27.94" width="0.1524" layer="91"/> +<junction x="180.34" y="45.72"/> +<junction x="152.4" y="45.72"/> +<junction x="152.4" y="31.75"/> +<junction x="152.4" y="35.56"/> +<junction x="152.4" y="27.94"/> +<pinref part="R2N19" gate="R" pin="1"/> +<pinref part="DS8C6" gate="LED" pin="K"/> +<pinref part="R2N30" gate="R" pin="1"/> +<pinref part="R2N21" gate="R" pin="1"/> +<pinref part="R2N20" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_LINK10"/> +<label x="227.33" y="45.72" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP0-CONFIG1" class="0"> +<segment> +<wire x1="67.31" y1="27.94" x2="127" y2="27.94" width="0.1524" layer="91"/> +<pinref part="R2N30" gate="R" pin="2"/> +<label x="67.31" y="27.94" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-CONFIG1" class="0"> +<segment> +<wire x1="67.31" y1="35.56" x2="127" y2="35.56" width="0.1524" layer="91"/> +<pinref part="R2N20" gate="R" pin="2"/> +<label x="67.31" y="35.56" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="99.06" y1="53.34" x2="67.31" y2="53.34" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_CONFIG1"/> +<label x="67.31" y="53.34" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP3-CONFIG1" class="0"> +<segment> +<wire x1="67.31" y1="24.13" x2="127" y2="24.13" width="0.1524" layer="91"/> +<pinref part="R2N19" gate="R" pin="2"/> +<label x="67.31" y="24.13" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-CONFIG0" class="0"> +<segment> +<wire x1="99.06" y1="55.88" x2="93.98" y2="55.88" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_CONFIG0"/> +<label x="93.98" y="55.88" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-CONFIG2" class="0"> +<segment> +<wire x1="99.06" y1="50.8" x2="93.98" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_CONFIG2"/> +<label x="93.98" y="50.8" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-CONFIG3" class="0"> +<segment> +<wire x1="99.06" y1="48.26" x2="67.31" y2="48.26" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_CONFIG3"/> +<label x="67.31" y="48.26" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-CONFIG4" class="0"> +<segment> +<wire x1="99.06" y1="45.72" x2="93.98" y2="45.72" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_CONFIG4"/> +<label x="93.98" y="45.72" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EP2-LINK1000" class="0"> +<segment> +<wire x1="146.05" y1="50.8" x2="160.02" y2="50.8" width="0.1524" layer="91"/> +<wire x1="160.02" y1="50.8" x2="160.02" y2="62.23" width="0.1524" layer="91"/> +<wire x1="160.02" y1="50.8" x2="209.55" y2="50.8" width="0.1524" layer="91"/> +<wire x1="209.55" y1="50.8" x2="209.55" y2="63.5" width="0.1524" layer="91"/> +<wire x1="209.55" y1="50.8" x2="227.33" y2="50.8" width="0.1524" layer="91"/> +<wire x1="209.55" y1="63.5" x2="210.82" y2="63.5" width="0.1524" layer="91"/> +<junction x="160.02" y="50.8"/> +<junction x="209.55" y="50.8"/> +<pinref part="DS8C4" gate="LED" pin="K"/> +<pinref part="U8D1" gate="GB2" pin="P2_LINK1000"/> +<pinref part="R2L1" gate="R" pin="1"/> +<label x="227.33" y="50.8" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP2-RXD3" class="0"> +<segment> +<wire x1="45.72" y1="82.55" x2="41.91" y2="82.55" width="0.1524" layer="91"/> +<wire x1="45.72" y1="142.24" x2="45.72" y2="82.55" width="0.1524" layer="91"/> +<wire x1="68.58" y1="82.55" x2="45.72" y2="82.55" width="0.1524" layer="91"/> +<junction x="45.72" y="82.55"/> +<pinref part="R6E1" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_RXDATA[3]"/> +<pinref part="R3P7" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-RXD2" class="0"> +<segment> +<wire x1="48.26" y1="85.09" x2="41.91" y2="85.09" width="0.1524" layer="91"/> +<wire x1="48.26" y1="142.24" x2="48.26" y2="85.09" width="0.1524" layer="91"/> +<wire x1="68.58" y1="85.09" x2="48.26" y2="85.09" width="0.1524" layer="91"/> +<junction x="48.26" y="85.09"/> +<pinref part="R7D8" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_RXDATA[2]"/> +<pinref part="R3P5" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-RXD1" class="0"> +<segment> +<wire x1="50.8" y1="87.63" x2="41.91" y2="87.63" width="0.1524" layer="91"/> +<wire x1="50.8" y1="142.24" x2="50.8" y2="87.63" width="0.1524" layer="91"/> +<wire x1="68.58" y1="87.63" x2="50.8" y2="87.63" width="0.1524" layer="91"/> +<junction x="50.8" y="87.63"/> +<pinref part="R7D10" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_RXDATA[1]"/> +<pinref part="R3P3" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-RXD0" class="0"> +<segment> +<wire x1="53.34" y1="90.17" x2="41.91" y2="90.17" width="0.1524" layer="91"/> +<wire x1="53.34" y1="142.24" x2="53.34" y2="90.17" width="0.1524" layer="91"/> +<wire x1="68.58" y1="90.17" x2="53.34" y2="90.17" width="0.1524" layer="91"/> +<junction x="53.34" y="90.17"/> +<pinref part="R6E2" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_RXDATA[0]"/> +<pinref part="R3P8" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-TXD3" class="0"> +<segment> +<wire x1="41.91" y1="120.65" x2="66.04" y2="120.65" width="0.1524" layer="91"/> +<wire x1="68.58" y1="120.65" x2="66.04" y2="120.65" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_TXDATA[3]"/> +<pinref part="R4R1" gate="R" pin="1"/> +</segment> +</net> +<net name="EP2-TXD2" class="0"> +<segment> +<wire x1="41.91" y1="123.19" x2="68.58" y2="123.19" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_TXDATA[2]"/> +<pinref part="R3R2" gate="R" pin="1"/> +</segment> +</net> +<net name="EP2-TXD1" class="0"> +<segment> +<wire x1="41.91" y1="125.73" x2="68.58" y2="125.73" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_TXDATA[1]"/> +<pinref part="R3R3" gate="R" pin="1"/> +</segment> +</net> +<net name="EP2-TXD0" class="0"> +<segment> +<wire x1="41.91" y1="128.27" x2="68.58" y2="128.27" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_TXDATA[0]"/> +<pinref part="R3R4" gate="R" pin="1"/> +</segment> +</net> +<net name="EP2-RXCTL" class="0"> +<segment> +<wire x1="41.91" y1="99.06" x2="55.88" y2="99.06" width="0.1524" layer="91"/> +<wire x1="55.88" y1="99.06" x2="55.88" y2="142.24" width="0.1524" layer="91"/> +<wire x1="68.58" y1="99.06" x2="55.88" y2="99.06" width="0.1524" layer="91"/> +<junction x="55.88" y="99.06"/> +<pinref part="R7E1" gate="R" pin="2"/> +<pinref part="R3P6" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_RXCTL"/> +</segment> +</net> +<net name="EP2-RXCLK" class="0"> +<segment> +<wire x1="41.91" y1="106.68" x2="63.5" y2="106.68" width="0.1524" layer="91"/> +<wire x1="63.5" y1="106.68" x2="63.5" y2="142.24" width="0.1524" layer="91"/> +<wire x1="63.5" y1="106.68" x2="68.58" y2="106.68" width="0.1524" layer="91"/> +<junction x="63.5" y="106.68"/> +<pinref part="R7D9" gate="R" pin="2"/> +<pinref part="R3P4" gate="R" pin="2"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_RXCLK"/> +</segment> +</net> +<net name="EP2-RXD3-R" class="0"> +<segment> +<wire x1="78.74" y1="82.55" x2="99.06" y2="82.55" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_RXD[3]"/> +<pinref part="R3P7" gate="R" pin="1"/> +</segment> +</net> +<net name="EP2-RXD2-R" class="0"> +<segment> +<wire x1="78.74" y1="85.09" x2="99.06" y2="85.09" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_RXD[2]"/> +<pinref part="R3P5" gate="R" pin="1"/> +</segment> +</net> +<net name="EP2-RXD1-R" class="0"> +<segment> +<wire x1="78.74" y1="87.63" x2="99.06" y2="87.63" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_RXD[1]"/> +<pinref part="R3P3" gate="R" pin="1"/> +</segment> +</net> +<net name="EP2-RXD0-R" class="0"> +<segment> +<wire x1="78.74" y1="90.17" x2="99.06" y2="90.17" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_RXD[0]"/> +<pinref part="R3P8" gate="R" pin="1"/> +</segment> +</net> +<net name="EP2-RXCTL-R" class="0"> +<segment> +<wire x1="99.06" y1="99.06" x2="78.74" y2="99.06" width="0.1524" layer="91"/> +<pinref part="R3P6" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_RX_DV"/> +</segment> +</net> +<net name="EP2-RXCLK-R" class="0"> +<segment> +<wire x1="78.74" y1="106.68" x2="99.06" y2="106.68" width="0.1524" layer="91"/> +<pinref part="R3P4" gate="R" pin="1"/> +<pinref part="U8D1" gate="GB2" pin="P2_RX_CLK"/> +</segment> +</net> +<net name="EP2-TXD3-R" class="0"> +<segment> +<wire x1="78.74" y1="120.65" x2="81.28" y2="120.65" width="0.1524" layer="91"/> +<wire x1="81.28" y1="120.65" x2="99.06" y2="120.65" width="0.1524" layer="91"/> +<wire x1="81.28" y1="142.24" x2="81.28" y2="120.65" width="0.1524" layer="91"/> +<junction x="81.28" y="120.65"/> +<pinref part="U8D1" gate="GB2" pin="P2_TXD[3]"/> +<pinref part="R4R1" gate="R" pin="2"/> +<pinref part="R7D2" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-TXD2-R" class="0"> +<segment> +<wire x1="78.74" y1="123.19" x2="83.82" y2="123.19" width="0.1524" layer="91"/> +<wire x1="83.82" y1="123.19" x2="99.06" y2="123.19" width="0.1524" layer="91"/> +<wire x1="83.82" y1="142.24" x2="83.82" y2="123.19" width="0.1524" layer="91"/> +<junction x="83.82" y="123.19"/> +<pinref part="U8D1" gate="GB2" pin="P2_TXD[2]"/> +<pinref part="R3R2" gate="R" pin="2"/> +<pinref part="R7D4" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-TXD1-R" class="0"> +<segment> +<wire x1="78.74" y1="125.73" x2="86.36" y2="125.73" width="0.1524" layer="91"/> +<wire x1="86.36" y1="125.73" x2="99.06" y2="125.73" width="0.1524" layer="91"/> +<wire x1="86.36" y1="142.24" x2="86.36" y2="125.73" width="0.1524" layer="91"/> +<junction x="86.36" y="125.73"/> +<pinref part="U8D1" gate="GB2" pin="P2_TXD[1]"/> +<pinref part="R3R3" gate="R" pin="2"/> +<pinref part="R7D3" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-TXD0-R" class="0"> +<segment> +<wire x1="78.74" y1="128.27" x2="88.9" y2="128.27" width="0.1524" layer="91"/> +<wire x1="88.9" y1="128.27" x2="99.06" y2="128.27" width="0.1524" layer="91"/> +<wire x1="88.9" y1="142.24" x2="88.9" y2="128.27" width="0.1524" layer="91"/> +<junction x="88.9" y="128.27"/> +<pinref part="U8D1" gate="GB2" pin="P2_TXD[0]"/> +<pinref part="R3R4" gate="R" pin="2"/> +<pinref part="R7D6" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-$30" class="0"> +<segment> +<wire x1="146.05" y1="58.42" x2="199.39" y2="58.42" width="0.1524" layer="91"/> +<wire x1="199.39" y1="58.42" x2="199.39" y2="62.23" width="0.1524" layer="91"/> +<pinref part="DS8C8" gate="LED" pin="K"/> +<pinref part="U8D1" gate="GB2" pin="P2_LED_RX"/> +</segment> +</net> +<net name="EP2-$27" class="0"> +<segment> +<wire x1="146.05" y1="55.88" x2="207.01" y2="55.88" width="0.1524" layer="91"/> +<wire x1="207.01" y1="55.88" x2="207.01" y2="71.12" width="0.1524" layer="91"/> +<wire x1="207.01" y1="71.12" x2="210.82" y2="71.12" width="0.1524" layer="91"/> +<pinref part="U8D1" gate="GB2" pin="P2_LED_TX"/> +<pinref part="R3L1" gate="R" pin="1"/> +</segment> +</net> +<net name="EP2-$21" class="0"> +<segment> +<wire x1="189.23" y1="53.34" x2="189.23" y2="62.23" width="0.1524" layer="91"/> +<wire x1="156.21" y1="53.34" x2="189.23" y2="53.34" width="0.1524" layer="91"/> +<wire x1="149.86" y1="53.34" x2="156.21" y2="53.34" width="0.1524" layer="91"/> +<wire x1="146.05" y1="53.34" x2="149.86" y2="53.34" width="0.1524" layer="91"/> +<pinref part="DS8C7" gate="LED" pin="K"/> +<pinref part="U8D1" gate="GB2" pin="P2_DUPLEX"/> +</segment> +</net> +<net name="EP2-TXCLK-R" class="0"> +<segment> +<wire x1="78.74" y1="104.14" x2="81.28" y2="104.14" width="0.1524" layer="91"/> +<wire x1="81.28" y1="104.14" x2="99.06" y2="104.14" width="0.1524" layer="91"/> +<wire x1="81.28" y1="110.49" x2="81.28" y2="104.14" width="0.1524" layer="91"/> +<wire x1="60.96" y1="142.24" x2="60.96" y2="110.49" width="0.1524" layer="91"/> +<wire x1="60.96" y1="110.49" x2="81.28" y2="110.49" width="0.1524" layer="91"/> +<junction x="81.28" y="104.14"/> +<pinref part="U8D1" gate="GB2" pin="P2_GTX_CLK"/> +<pinref part="R3R1" gate="R" pin="2"/> +<pinref part="R7D5" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-TXCTL-R" class="0"> +<segment> +<wire x1="78.74" y1="101.6" x2="83.82" y2="101.6" width="0.1524" layer="91"/> +<wire x1="83.82" y1="101.6" x2="99.06" y2="101.6" width="0.1524" layer="91"/> +<wire x1="83.82" y1="113.03" x2="83.82" y2="101.6" width="0.1524" layer="91"/> +<wire x1="58.42" y1="142.24" x2="58.42" y2="113.03" width="0.1524" layer="91"/> +<wire x1="58.42" y1="113.03" x2="83.82" y2="113.03" width="0.1524" layer="91"/> +<junction x="83.82" y="101.6"/> +<pinref part="U8D1" gate="GB2" pin="P2_TX_EN"/> +<pinref part="R4R2" gate="R" pin="2"/> +<pinref part="R7D1" gate="R" pin="2"/> +</segment> +</net> +<net name="EP2-TXCLK" class="0"> +<segment> +<wire x1="60.96" y1="104.14" x2="68.58" y2="104.14" width="0.1524" layer="91"/> +<wire x1="41.91" y1="104.14" x2="60.96" y2="104.14" width="0.1524" layer="91"/> +<pinref part="R3R1" gate="R" pin="1"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_TXCLK"/> +</segment> +</net> +<net name="EP2-TXCTL" class="0"> +<segment> +<wire x1="58.42" y1="101.6" x2="68.58" y2="101.6" width="0.1524" layer="91"/> +<wire x1="41.91" y1="101.6" x2="58.42" y2="101.6" width="0.1524" layer="91"/> +<pinref part="R4R2" gate="R" pin="1"/> +<pinref part="U6E1" gate="GBE2" pin="GBE2_TXCTL"/> +</segment> +</net> +<net name="N$204" class="0"> +<segment> +<wire x1="232.41" y1="71.12" x2="220.98" y2="71.12" width="0.1524" layer="91"/> +<pinref part="R3L1" gate="R" pin="2"/> +<pinref part="EP2-CON" gate="LED2" pin="K"/> +</segment> +</net> +<net name="N$215" class="0"> +<segment> +<wire x1="232.41" y1="63.5" x2="220.98" y2="63.5" width="0.1524" layer="91"/> +<pinref part="R2L1" gate="R" pin="2"/> +<pinref part="EP2-CON" gate="LED1" pin="K"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="152.4" y="166.37" size="3.81" layer="94">LEB</text> +</plain> +<instances> +<instance part="FRAME16" gate="G$1" x="0" y="0"/> +<instance part="FRAME16" gate="G$2" x="180.34" y="0"/> +<instance part="R2V23" gate="R" x="111.76" y="95.25" smashed="yes" rot="MR0"> +<attribute name="NAME" x="108.585" y="95.5675" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="114.935" y="95.5675" size="1.778" layer="96"/> +<attribute name="POWER" x="111.76" y="95.25" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8H34" gate="R" x="111.76" y="92.71" smashed="yes" rot="MR0"> +<attribute name="NAME" x="108.2675" y="93.0275" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="114.6175" y="93.0275" size="1.778" layer="96"/> +<attribute name="POWER" x="111.76" y="92.71" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2V1" gate="R" x="111.4425" y="90.17" smashed="yes" rot="MR0"> +<attribute name="NAME" x="108.4316" y="90.4219" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="114.6185" y="90.4164" size="1.778" layer="96"/> +<attribute name="POWER" x="111.4425" y="90.17" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R8H33" gate="R" x="111.76" y="87.63" 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part="U$384" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R6W4" gate="R" pin="2"/> +<pinref part="R6Y6" gate="R" pin="1"/> +<pinref part="R6Y5" gate="R" pin="1"/> +<pinref part="R6Y4" gate="R" pin="1"/> +<pinref part="R6Y3" gate="R" pin="2"/> +<pinref part="R6Y2" gate="R" pin="2"/> +<pinref part="R6W5" gate="R" pin="2"/> +<pinref part="R4K3" gate="R" pin="2"/> +<pinref part="R6Y1" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="227.33" y1="106.68" x2="227.33" y2="100.33" width="0.1524" layer="91"/> +<wire x1="227.33" y1="100.33" x2="227.33" y2="97.79" width="0.1524" layer="91"/> +<wire x1="234.95" y1="87.63" x2="234.95" y2="100.33" width="0.1524" layer="91"/> +<wire x1="234.95" y1="100.33" x2="227.33" y2="100.33" width="0.1524" layer="91"/> +<wire x1="234.95" y1="100.33" x2="242.57" y2="100.33" width="0.1524" layer="91"/> +<wire x1="242.57" y1="100.33" x2="242.57" y2="77.47" width="0.1524" layer="91"/> +<junction x="227.33" y="100.33"/> +<junction x="234.95" y="100.33"/> +<pinref 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+<junction x="91.44" y="63.5"/> +<junction x="91.44" y="60.96"/> +<junction x="91.44" y="55.88"/> +<junction x="91.44" y="58.42"/> +<pinref part="R17" gate="R" pin="1"/> +<pinref part="U$533" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R4K4" gate="R" pin="2"/> +<pinref part="R4K14" gate="R" pin="2"/> +<pinref part="R6Y19" gate="R" pin="2"/> +<pinref part="R6W3" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="77.47" y1="41.91" x2="77.47" y2="40.64" width="0.1524" layer="91"/> +<wire x1="77.47" y1="40.64" x2="90.17" y2="40.64" width="0.1524" layer="91"/> +<pinref part="R3R28" gate="R" pin="2"/> +<pinref part="U$51" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="GND" class="0"> +<segment> +<wire x1="123.19" y1="22.86" x2="123.19" y2="19.05" width="0.1524" layer="91"/> +<pinref part="R3R26" gate="R" pin="1"/> +<pinref part="U$382" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="242.57" y1="62.23" x2="242.57" y2="58.42" width="0.1524" layer="91"/> +<wire x1="242.57" y1="58.42" x2="234.95" y2="58.42" width="0.1524" layer="91"/> +<wire x1="234.95" y1="58.42" x2="234.95" y2="72.39" width="0.1524" layer="91"/> +<wire x1="234.95" y1="58.42" x2="227.33" y2="58.42" width="0.1524" layer="91"/> +<wire x1="227.33" y1="58.42" x2="227.33" y2="82.55" width="0.1524" layer="91"/> +<wire x1="227.33" y1="55.88" x2="227.33" y2="58.42" width="0.1524" layer="91"/> +<junction x="234.95" y="58.42"/> +<junction x="227.33" y="58.42"/> +<pinref part="RCONFIG3/B" gate="P1" pin="2"/> +<pinref part="RCONFIG2/A" gate="P1" pin="2"/> +<pinref part="RCONFIG1/B" gate="P1" pin="2"/> +<pinref part="U$376" gate="G$1" pin="GND"/> +</segment> +</net> +<net name="EX-RD-N" class="0"> +<segment> +<wire x1="106.68" y1="73.66" x2="50.8" y2="73.66" width="0.1524" layer="91"/> +<pinref part="R7E26" gate="R" pin="2"/> +<label x="50.8" y="73.66" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EX-WR-N" class="0"> +<segment> +<wire x1="105.41" y1="48.26" x2="50.8" y2="48.26" width="0.1524" layer="91"/> +<pinref part="R33" gate="R" pin="2"/> +<label x="50.8" y="48.26" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$483" class="0"> +<segment> +<wire x1="129.54" y1="44.45" x2="123.19" y2="44.45" width="0.1524" layer="91"/> +<wire x1="123.19" y1="44.45" x2="123.19" y2="33.02" width="0.1524" layer="91"/> +<pinref part="R3R26" gate="R" pin="2"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_RCOMPP"/> +</segment> +</net> +<net name="N$484" class="0"> +<segment> +<wire x1="100.33" y1="40.64" x2="129.54" y2="40.64" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_RCOMPN"/> +<pinref part="R3R28" gate="R" pin="1"/> +</segment> +</net> +<net name="EX-IOWAIT-N" class="0"> +<segment> +<wire x1="64.77" y1="144.78" x2="64.77" y2="140.97" width="0.1524" layer="91"/> +<wire x1="129.54" y1="140.97" x2="116.84" y2="140.97" width="0.1524" layer="91"/> +<wire x1="116.84" y1="140.97" x2="73.66" y2="140.97" width="0.1524" layer="91"/> +<wire x1="73.66" y1="140.97" x2="64.77" y2="140.97" width="0.1524" layer="91"/> +<pinref part="R6W4" gate="R" pin="1"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_IOWAIT_N"/> +</segment> +</net> +<net name="EX-ALE" class="0"> +<segment> +<wire x1="224.79" y1="139.7" x2="236.22" y2="139.7" width="0.1524" layer="91"/> +<pinref part="R8H24" gate="R" pin="2"/> +<label x="236.22" y="139.7" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="N$354" class="0"> +<segment> +<wire x1="207.01" y1="82.55" x2="222.25" y2="82.55" width="0.1524" layer="91"/> +<wire x1="222.25" y1="82.55" x2="222.25" y2="80.01" width="0.1524" layer="91"/> +<wire x1="222.25" y1="80.01" x2="232.41" y2="80.01" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEB" pin="EX_ADDR[21]"/> +<pinref part="RCONFIG2/A" gate="P1" pin="C"/> +</segment> +</net> +<net name="N$356" class="0"> +<segment> +<wire x1="207.01" y1="77.47" x2="213.36" y2="77.47" width="0.1524" layer="91"/> +<wire x1="213.36" y1="77.47" x2="213.36" y2="69.85" width="0.1524" layer="91"/> +<wire x1="213.36" y1="69.85" x2="240.03" y2="69.85" width="0.1524" layer="91"/> +<pinref part="RCONFIG3/B" gate="P1" pin="C"/> +<pinref part="U6E1" gate="LEB" pin="EX_ADDR[23]"/> +</segment> +</net> +<net name="EX-DATA-BUF7" class="0"> +<segment> +<wire x1="106.68" y1="95.25" x2="72.39" y2="95.25" width="0.1524" layer="91"/> +<wire x1="72.39" y1="95.25" x2="69.85" y2="96.52" width="0.1524" layer="91"/> +<label x="73.66" y="95.5675" size="1.778" layer="92"/> +<pinref part="R2V23" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF6" class="0"> +<segment> +<wire x1="106.68" y1="92.71" x2="72.39" y2="92.71" width="0.1524" layer="91"/> +<wire x1="72.39" y1="92.71" x2="69.85" y2="93.98" width="0.1524" layer="91"/> +<label x="73.66" y="93.0275" size="1.778" layer="92"/> +<pinref part="R8H34" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF5" class="0"> +<segment> +<wire x1="106.3625" y1="90.17" x2="72.39" y2="90.17" width="0.1524" layer="91"/> +<wire x1="72.39" y1="90.17" x2="69.85" y2="91.44" width="0.1524" layer="91"/> +<label x="73.66" y="90.4875" size="1.778" layer="92"/> +<pinref part="R2V1" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF4" class="0"> +<segment> +<wire x1="106.68" y1="87.63" x2="72.39" y2="87.63" width="0.1524" layer="91"/> +<wire x1="72.39" y1="87.63" x2="69.85" y2="88.9" width="0.1524" layer="91"/> +<label x="73.66" y="87.9475" size="1.778" layer="92"/> +<pinref part="R8H33" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF3" class="0"> +<segment> +<wire x1="106.68" y1="85.09" x2="72.39" y2="85.09" width="0.1524" layer="91"/> +<wire x1="72.39" y1="85.09" x2="69.85" y2="86.36" width="0.1524" layer="91"/> +<label x="73.66" y="85.4075" size="1.778" layer="92"/> +<pinref part="R2V24" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF2" class="0"> +<segment> +<wire x1="106.68" y1="82.55" x2="72.39" y2="82.55" width="0.1524" layer="91"/> +<wire x1="72.39" y1="82.55" x2="69.85" y2="83.82" width="0.1524" layer="91"/> +<label x="73.66" y="82.8675" size="1.778" layer="92"/> +<pinref part="R8H32" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF1" class="0"> +<segment> +<wire x1="106.68" y1="80.01" x2="72.39" y2="80.01" width="0.1524" layer="91"/> +<wire x1="72.39" y1="80.01" x2="69.85" y2="81.28" width="0.1524" layer="91"/> +<label x="73.66" y="80.3275" size="1.778" layer="92"/> +<pinref part="R2V19" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF0" class="0"> +<segment> +<wire x1="106.68" y1="77.47" x2="72.39" y2="77.47" width="0.1524" layer="91"/> +<wire x1="72.39" y1="77.47" x2="69.85" y2="78.74" width="0.1524" layer="91"/> +<label x="73.66" y="77.7875" size="1.778" layer="92"/> +<pinref part="R8H31" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-CS1" class="0"> +<segment> +<wire x1="88.9" y1="134.62" x2="77.47" y2="134.62" width="0.1524" layer="91"/> +<wire x1="77.47" y1="134.62" x2="44.45" y2="134.62" width="0.1524" layer="91"/> +<wire x1="77.47" y1="144.78" x2="77.47" y2="134.62" width="0.1524" layer="91"/> +<junction x="77.47" y="134.62"/> +<pinref part="R32" gate="R" pin="2"/> +<pinref part="R6Y5" gate="R" pin="2"/> +<label x="44.45" y="134.62" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EX-CS0" class="0"> +<segment> +<wire x1="52.07" y1="137.16" x2="26.67" y2="137.16" width="0.1524" layer="91"/> +<label x="26.67" y="137.16" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="R22" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-CS2" class="0"> +<segment> +<wire x1="88.9" y1="132.08" x2="82.55" y2="132.08" width="0.1524" layer="91"/> +<wire x1="82.55" y1="132.08" x2="25.4" y2="132.08" width="0.1524" layer="91"/> +<wire x1="82.55" y1="144.78" x2="82.55" y2="132.08" width="0.1524" layer="91"/> +<junction x="82.55" y="132.08"/> +<pinref part="R53" gate="R" pin="2"/> +<pinref part="R6Y4" gate="R" pin="2"/> +<label x="25.4" y="132.08" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="EX-DATA-BUF15" class="0"> +<segment> +<wire x1="69.85" y1="116.84" x2="72.39" y2="115.57" width="0.1524" layer="91"/> +<wire x1="72.39" y1="115.57" x2="106.68" y2="115.57" width="0.1524" layer="91"/> +<label x="73.66" y="115.8875" size="1.778" layer="92"/> +<pinref part="R2V9" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF14" class="0"> +<segment> +<wire x1="69.85" y1="114.3" x2="72.39" y2="113.03" width="0.1524" layer="91"/> +<wire x1="72.39" y1="113.03" x2="106.68" y2="113.03" width="0.1524" layer="91"/> +<label x="73.66" y="113.3475" size="1.778" layer="92"/> +<pinref part="R2V8" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF13" class="0"> +<segment> +<wire x1="69.85" y1="111.76" x2="72.39" y2="110.49" width="0.1524" layer="91"/> +<wire x1="72.39" y1="110.49" x2="106.68" y2="110.49" width="0.1524" layer="91"/> +<label x="73.66" y="110.8075" size="1.778" layer="92"/> +<pinref part="R2V7" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF12" class="0"> +<segment> +<wire x1="69.85" y1="109.22" x2="72.39" y2="107.95" width="0.1524" layer="91"/> +<wire x1="72.39" y1="107.95" x2="106.68" y2="107.95" width="0.1524" layer="91"/> +<label x="73.66" y="108.2675" size="1.778" layer="92"/> +<pinref part="R2V6" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF11" class="0"> +<segment> +<wire x1="69.85" y1="106.68" x2="72.39" y2="105.41" width="0.1524" layer="91"/> +<wire x1="72.39" y1="105.41" x2="106.68" y2="105.41" width="0.1524" layer="91"/> +<label x="73.66" y="105.7275" size="1.778" layer="92"/> +<pinref part="R2V5" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF10" class="0"> +<segment> +<wire x1="69.85" y1="104.14" x2="72.39" y2="102.87" width="0.1524" layer="91"/> +<wire x1="72.39" y1="102.87" x2="106.68" y2="102.87" width="0.1524" layer="91"/> +<label x="73.66" y="103.1875" size="1.778" layer="92"/> +<pinref part="R2V4" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF9" class="0"> +<segment> +<wire x1="69.85" y1="101.6" x2="72.39" y2="100.33" width="0.1524" layer="91"/> +<wire x1="72.39" y1="100.33" x2="106.68" y2="100.33" width="0.1524" layer="91"/> +<label x="73.66" y="100.6475" size="1.778" layer="92"/> +<pinref part="R2V3" gate="R" pin="2"/> +</segment> +</net> +<net name="EX-DATA-BUF8" class="0"> +<segment> +<wire x1="69.85" y1="99.06" x2="72.39" y2="97.79" width="0.1524" layer="91"/> +<wire x1="72.39" y1="97.79" x2="106.68" y2="97.79" width="0.1524" layer="91"/> +<label x="73.66" y="98.1075" size="1.778" layer="92"/> +<pinref part="R2V2" gate="R" pin="2"/> +</segment> +</net> +<net name="N$48" class="0"> +<segment> +<wire x1="129.54" y1="129.54" x2="102.87" y2="129.54" width="0.1524" layer="91"/> +<wire x1="102.87" y1="129.54" x2="102.87" y2="144.78" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_CS_N[3]"/> +<pinref part="R6Y3" gate="R" pin="1"/> +</segment> +</net> +<net name="N$49" class="0"> +<segment> +<wire x1="129.54" y1="127" x2="107.95" y2="127" width="0.1524" layer="91"/> +<wire x1="107.95" y1="127" x2="107.95" y2="144.78" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_CS_N[4]"/> +<pinref part="R6Y2" gate="R" pin="1"/> +</segment> +</net> +<net name="N$51" class="0"> +<segment> +<wire x1="129.54" y1="124.46" x2="113.03" y2="124.46" width="0.1524" layer="91"/> +<wire x1="113.03" y1="124.46" x2="113.03" y2="144.78" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_CS_N[5]"/> +<pinref part="R6W5" gate="R" pin="1"/> +</segment> +</net> +<net name="N$52" class="0"> +<segment> +<wire x1="129.54" y1="121.92" x2="118.11" y2="121.92" width="0.1524" layer="91"/> +<wire x1="118.11" y1="121.92" x2="118.11" y2="144.78" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_CS_N[6]"/> +<pinref part="R4K3" gate="R" pin="1"/> +</segment> +</net> +<net name="N$53" class="0"> +<segment> +<wire x1="129.54" y1="119.38" x2="123.19" y2="119.38" width="0.1524" layer="91"/> +<wire x1="123.19" y1="119.38" x2="123.19" y2="144.78" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_CS_N[7]"/> +<pinref part="R6Y1" gate="R" pin="1"/> +</segment> +</net> +<net name="N$61" class="0"> +<segment> +<wire x1="115.57" y1="63.5" x2="129.54" y2="63.5" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_RDY_N[0]"/> +<pinref part="R4K4" gate="R" pin="1"/> +</segment> +</net> +<net name="N$62" class="0"> +<segment> +<wire x1="115.57" y1="60.96" x2="129.54" y2="60.96" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_RDY_N[1]"/> +<pinref part="R4K14" gate="R" pin="1"/> +</segment> +</net> +<net name="N$83" class="0"> +<segment> +<wire x1="115.57" y1="58.42" x2="129.54" y2="58.42" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_RDY_N[2]"/> +<pinref part="R6W3" gate="R" pin="1"/> +</segment> +</net> +<net name="N$84" class="0"> +<segment> +<wire x1="115.57" y1="55.88" x2="129.54" y2="55.88" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_RDY_N[3]"/> +<pinref part="R6Y19" gate="R" pin="1"/> +</segment> +</net> +<net name="N$86" class="0"> +<segment> +<wire x1="115.57" y1="52.07" x2="129.54" y2="52.07" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_BURST"/> +<pinref part="R17" gate="R" pin="2"/> +</segment> +</net> +<net name="LEB-33MHZ-CLK-R" class="0"> +<segment> +<wire x1="215.9" y1="43.18" x2="224.79" y2="43.18" width="0.1524" layer="91"/> +<wire x1="215.9" y1="43.18" x2="215.9" y2="64.77" width="0.1524" layer="91"/> +<wire x1="215.9" y1="64.77" x2="207.01" y2="64.77" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="LEB" pin="EX_CLK"/> +<label x="224.79" y="43.18" size="1.778" layer="92" xref="yes"/> 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name="EX-DATA-BUF0-R" class="0"> +<segment> +<wire x1="116.84" y1="77.47" x2="129.54" y2="77.47" width="0.1524" layer="91"/> +<pinref part="R8H31" gate="R" pin="1"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_DATA[0]"/> +</segment> +</net> +<net name="EX-DATA-BUF1-R" class="0"> +<segment> +<wire x1="116.84" y1="80.01" x2="129.54" y2="80.01" width="0.1524" layer="91"/> +<pinref part="R2V19" gate="R" pin="1"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_DATA[1]"/> +</segment> +</net> +<net name="EX-DATA-BUF2-R" class="0"> +<segment> +<wire x1="116.84" y1="82.55" x2="129.54" y2="82.55" width="0.1524" layer="91"/> +<pinref part="R8H32" gate="R" pin="1"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_DATA[2]"/> +</segment> +</net> +<net name="EX-DATA-BUF3-" class="0"> +<segment> +<wire x1="116.84" y1="85.09" x2="129.54" y2="85.09" width="0.1524" layer="91"/> +<pinref part="R2V24" gate="R" pin="1"/> +<pinref part="U6E1" gate="LEBDATA" pin="EX_DATA[3]"/> +</segment> +</net> +<net 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x2="177.8" y2="45.72" width="0.1524" layer="91"/> +<junction x="180.34" y="54.61"/> +<pinref part="J4F1" gate="G$1" pin="P$1"/> +<pinref part="U$583" gate="G$1" pin="GND"/> +<pinref part="J4F1" gate="G$1" pin="P$2"/> +</segment> +<segment> +<wire x1="170.18" y1="34.29" x2="160.02" y2="34.29" width="0.1524" layer="91"/> +<wire x1="160.02" y1="34.29" x2="160.02" y2="26.67" width="0.1524" layer="91"/> +<wire x1="170.18" y1="26.67" x2="160.02" y2="26.67" width="0.1524" layer="91"/> +<wire x1="160.02" y1="26.67" x2="160.02" y2="19.05" width="0.1524" layer="91"/> +<wire x1="170.18" y1="19.05" x2="160.02" y2="19.05" width="0.1524" layer="91"/> +<wire x1="160.02" y1="19.05" x2="160.02" y2="17.78" width="0.1524" layer="91"/> +<junction x="160.02" y="26.67"/> +<junction x="160.02" y="19.05"/> +<pinref part="JX4E1" gate="G$1" pin="1"/> +<pinref part="JX4E1" gate="G$1" pin="4"/> +<pinref part="JX4E1" gate="G$1" pin="7"/> +<pinref part="U$584" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire 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x1="184.15" y1="74.93" x2="186.69" y2="74.93" width="0.1524" layer="91"/> +<wire x1="186.69" y1="74.93" x2="191.77" y2="74.93" width="0.1524" layer="91"/> +<wire x1="191.77" y1="74.93" x2="198.12" y2="74.93" width="0.1524" layer="91"/> +<wire x1="198.12" y1="74.93" x2="204.47" y2="74.93" width="0.1524" layer="91"/> +<wire x1="204.47" y1="74.93" x2="204.47" y2="82.55" width="0.1524" layer="91"/> +<wire x1="165.1" y1="82.55" x2="165.1" y2="74.93" width="0.1524" layer="91"/> +<wire x1="171.45" y1="82.55" x2="171.45" y2="74.93" width="0.1524" layer="91"/> +<wire x1="177.8" y1="82.55" x2="177.8" y2="74.93" width="0.1524" layer="91"/> +<wire x1="184.15" y1="82.55" x2="184.15" y2="74.93" width="0.1524" layer="91"/> +<wire x1="191.77" y1="82.55" x2="191.77" y2="74.93" width="0.1524" layer="91"/> +<wire x1="198.12" y1="82.55" x2="198.12" y2="74.93" width="0.1524" layer="91"/> +<wire x1="184.15" y1="73.66" x2="184.15" y2="74.93" width="0.1524" layer="91"/> +<junction x="165.1" y="74.93"/> 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x1="184.15" y1="93.98" x2="186.69" y2="93.98" width="0.1524" layer="91"/> +<wire x1="186.69" y1="93.98" x2="186.69" y2="74.93" width="0.1524" layer="91"/> +<junction x="186.69" y="74.93"/> +</segment> +</net> +<net name="SATA-LED-N" class="0"> +<segment> +<wire x1="50.8" y1="13.97" x2="57.15" y2="13.97" width="0.1524" layer="91"/> +<wire x1="50.8" y1="13.97" x2="50.8" y2="8.89" width="0.1524" layer="91"/> +<wire x1="50.8" y1="8.89" x2="88.9" y2="8.89" width="0.1524" layer="91"/> +<wire x1="50.8" y1="13.97" x2="39.37" y2="13.97" width="0.1524" layer="91"/> +<junction x="50.8" y="13.97"/> +<pinref part="U6E1" gate="SATA" pin="SATALED#"/> +<pinref part="R3J3" gate="R" pin="2"/> +<label x="88.9" y="8.89" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="N$431" class="0"> +<segment> +<wire x1="134.62" y1="62.23" x2="157.48" y2="62.23" width="0.1524" layer="91"/> +<wire x1="157.48" y1="62.23" x2="157.48" y2="59.69" width="0.1524" layer="91"/> +<wire x1="157.48" y1="59.69" x2="170.18" y2="59.69" width="0.1524" layer="91"/> +<label x="147.32" y="62.23" size="1.778" layer="95"/> +<pinref part="C6T4" gate="C" pin="1"/> +<pinref part="J4F1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="N$433" class="0"> +<segment> +<wire x1="134.62" y1="57.15" x2="170.18" y2="57.15" width="0.1524" layer="91"/> +<label x="147.32" y="57.15" size="1.778" layer="95"/> +<pinref part="C6T3" gate="C" pin="1"/> +<pinref part="J4F1" gate="G$1" pin="3"/> +</segment> +</net> +<net name="N$439" class="0"> +<segment> +<wire x1="134.62" y1="52.07" x2="170.18" y2="52.07" width="0.1524" layer="91"/> +<label x="147.32" y="52.07" size="1.778" layer="95"/> +<pinref part="C6T2" gate="C" pin="1"/> +<pinref part="J4F1" gate="G$1" pin="5"/> +</segment> +</net> +<net name="N$445" class="0"> +<segment> +<wire x1="134.62" y1="46.99" x2="157.48" y2="46.99" width="0.1524" layer="91"/> +<wire x1="170.18" y1="49.53" x2="157.48" y2="49.53" width="0.1524" layer="91"/> +<wire x1="157.48" y1="46.99" x2="157.48" y2="49.53" width="0.1524" layer="91"/> +<label x="147.32" y="46.99" size="1.778" layer="95"/> +<pinref part="C6T1" gate="C" pin="1"/> +<pinref part="J4F1" gate="G$1" pin="6"/> +</segment> +</net> +<net name="N$459" class="0"> +<segment> +<wire x1="177.8" y1="166.37" x2="139.7" y2="166.37" width="0.1524" layer="91"/> +<wire x1="177.8" y1="142.24" x2="177.8" y2="166.37" width="0.1524" layer="91"/> +<pinref part="FB6A2" gate="A" pin="1"/> +<pinref part="CP6A2" gate="D" pin="2"/> +<pinref part="JCOM1" gate="J" pin="1"/> +<wire x1="177.8" y1="166.37" x2="223.52" y2="166.37" width="0.1524" layer="91"/> +<junction x="177.8" y="166.37"/> +</segment> +</net> +<net name="N$460" class="0"> +<segment> +<wire x1="165.1" y1="161.29" x2="139.7" y2="161.29" width="0.1524" layer="91"/> +<wire x1="165.1" y1="142.24" x2="165.1" y2="161.29" width="0.1524" layer="91"/> +<pinref part="FB6A2" gate="C" pin="1"/> +<pinref part="CP6A2" gate="B" pin="2"/> +<wire x1="165.1" y1="161.29" x2="213.36" y2="161.29" width="0.1524" layer="91"/> +<junction x="165.1" y="161.29"/> +<wire x1="213.36" y1="161.29" x2="213.36" y2="163.83" width="0.1524" layer="91"/> +<pinref part="JCOM1" gate="J" pin="2"/> +<wire x1="213.36" y1="163.83" x2="223.52" y2="163.83" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$461" class="0"> +<segment> +<wire x1="205.74" y1="151.13" x2="139.7" y2="151.13" width="0.1524" layer="91"/> +<wire x1="205.74" y1="142.24" x2="205.74" y2="151.13" width="0.1524" layer="91"/> +<pinref part="FB6B1" gate="A" pin="1"/> +<pinref part="CP6A2" gate="A" pin="2"/> +<wire x1="205.74" y1="151.13" x2="205.74" y2="158.75" width="0.1524" layer="91"/> +<wire x1="205.74" y1="158.75" x2="215.9" y2="158.75" width="0.1524" layer="91"/> +<junction x="205.74" y="151.13"/> +<wire x1="215.9" y1="158.75" x2="215.9" y2="161.29" width="0.1524" layer="91"/> +<pinref part="JCOM1" gate="J" pin="3"/> +<wire x1="215.9" y1="161.29" x2="223.52" y2="161.29" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$462" class="0"> +<segment> +<wire x1="193.04" y1="148.59" x2="139.7" y2="148.59" width="0.1524" layer="91"/> +<wire x1="193.04" y1="142.24" x2="193.04" y2="148.59" width="0.1524" layer="91"/> +<pinref part="FB6B1" gate="C" pin="1"/> +<pinref part="CP6A1" gate="D" pin="2"/> +<wire x1="193.04" y1="148.59" x2="193.04" y2="156.21" width="0.1524" layer="91"/> +<wire x1="193.04" y1="156.21" x2="218.44" y2="156.21" width="0.1524" layer="91"/> +<junction x="193.04" y="148.59"/> +<wire x1="218.44" y1="156.21" x2="218.44" y2="158.75" width="0.1524" layer="91"/> +<pinref part="JCOM1" gate="J" pin="4"/> +<wire x1="218.44" y1="158.75" x2="223.52" y2="158.75" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$465" class="0"> +<segment> +<wire x1="199.39" y1="158.75" x2="139.7" y2="158.75" width="0.1524" layer="91"/> +<wire x1="199.39" y1="142.24" x2="199.39" y2="148.59" width="0.1524" layer="91"/> +<pinref part="FB6B1" gate="B" pin="1"/> +<pinref part="CP6A1" gate="A" pin="2"/> +<wire x1="199.39" y1="148.59" x2="199.39" y2="158.75" width="0.1524" layer="91"/> +<pinref part="JCOM1" gate="J" pin="8"/> +<wire x1="212.09" y1="148.59" x2="223.52" y2="148.59" width="0.1524" layer="91"/> +<wire x1="212.09" y1="148.59" x2="199.39" y2="148.59" width="0.1524" layer="91"/> +<junction x="199.39" y="148.59"/> +</segment> +</net> +<net name="N$466" class="0"> +<segment> +<wire x1="158.75" y1="153.67" x2="139.7" y2="153.67" width="0.1524" layer="91"/> +<wire x1="158.75" y1="142.24" x2="158.75" y2="153.67" width="0.1524" layer="91"/> +<pinref part="FB6A2" gate="D" pin="1"/> +<pinref part="CP6A1" gate="B" pin="2"/> +<wire x1="158.75" y1="153.67" x2="208.28" y2="153.67" width="0.1524" layer="91"/> +<junction x="158.75" y="153.67"/> +<wire x1="208.28" y1="153.67" x2="208.28" y2="151.13" width="0.1524" layer="91"/> +<pinref part="JCOM1" gate="J" pin="7"/> +<wire x1="208.28" y1="151.13" x2="223.52" y2="151.13" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$467" class="0"> +<segment> +<wire x1="171.45" y1="163.83" x2="139.7" y2="163.83" width="0.1524" layer="91"/> +<wire x1="171.45" y1="142.24" x2="171.45" y2="163.83" width="0.1524" layer="91"/> +<pinref part="FB6A2" gate="B" pin="1"/> +<pinref part="CP6A1" gate="C" pin="2"/> +<wire x1="171.45" y1="163.83" x2="210.82" y2="163.83" width="0.1524" layer="91"/> +<junction x="171.45" y="163.83"/> +<pinref part="JCOM1" gate="J" pin="6"/> +<wire x1="210.82" y1="163.83" x2="210.82" y2="153.67" width="0.1524" layer="91"/> +<wire x1="210.82" y1="153.67" x2="223.52" y2="153.67" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<wire x1="116.84" y1="138.43" x2="120.65" y2="138.43" width="0.1524" layer="91"/> +<wire x1="120.65" y1="138.43" x2="125.73" y2="138.43" width="0.1524" layer="91"/> +<wire x1="125.73" y1="138.43" x2="127" y2="138.43" width="0.1524" layer="91"/> +<wire x1="127" y1="138.43" x2="127" y2="133.35" width="0.1524" layer="91"/> +<wire x1="130.81" y1="138.43" x2="127" y2="138.43" width="0.1524" layer="91"/> +<wire x1="120.65" y1="133.35" x2="120.65" y2="138.43" width="0.1524" layer="91"/> +<junction x="127" y="138.43"/> +<junction x="120.65" y="138.43"/> +<pinref part="C4M2" gate="C" pin="1"/> +<pinref part="U6A1" gate="G$1" pin="VCC"/> +<pinref part="P+37" gate="1" pin="VCC"/> +<pinref part="C6B1" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="116.84" y1="86.36" x2="120.65" y2="86.36" width="0.1524" layer="91"/> +<wire x1="120.65" y1="86.36" x2="127" y2="86.36" width="0.1524" layer="91"/> +<wire x1="127" y1="86.36" x2="130.81" y2="86.36" width="0.1524" layer="91"/> +<wire x1="127" y1="85.09" x2="127" y2="86.36" width="0.1524" layer="91"/> +<wire x1="120.65" y1="82.55" x2="120.65" y2="86.36" width="0.1524" layer="91"/> +<junction x="127" y="86.36"/> +<junction x="120.65" y="86.36"/> +<pinref part="U5A1" gate="G$1" pin="VCC"/> +<pinref part="P+38" gate="1" pin="VCC"/> +<pinref part="C5L8" gate="C" pin="1"/> +<pinref part="C5A3" gate="C" pin="2"/> +</segment> +</net> +<net name="+12VPC" class="0"> +<segment> +<wire x1="77.47" y1="86.36" x2="77.47" y2="91.44" width="0.1524" layer="91"/> +<wire x1="77.47" y1="91.44" x2="68.58" y2="91.44" width="0.1524" layer="91"/> +<wire x1="81.28" y1="91.44" x2="77.47" y2="91.44" width="0.1524" layer="91"/> +<junction x="77.47" y="91.44"/> +<pinref part="C5L10" gate="C" pin="1"/> +<pinref part="U$438" gate="+12VPC" pin="+12VPC"/> +<pinref part="U5A1" gate="G$1" pin="VDD+"/> +</segment> +<segment> +<wire x1="77.47" y1="143.51" x2="81.28" y2="143.51" width="0.1524" layer="91"/> +<wire x1="77.47" y1="137.16" x2="77.47" y2="143.51" width="0.1524" layer="91"/> +<wire x1="67.31" y1="143.51" x2="77.47" y2="143.51" width="0.1524" layer="91"/> +<junction x="77.47" y="143.51"/> +<pinref part="U6A1" gate="G$1" pin="VDD+"/> +<pinref part="C4L13" gate="C" pin="1"/> +<pinref part="U$430" gate="+12VPC" pin="+12VPC"/> +</segment> +</net> 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y="91.44"/> +<pinref part="U$439" gate="-12VPC" pin="-12VPC"/> +<pinref part="C5M1" gate="C" pin="1"/> +<pinref part="U5A1" gate="G$1" pin="VDD-"/> +</segment> +</net> +<net name="SIU1-DCD-N" class="0"> +<segment> +<wire x1="81.28" y1="166.37" x2="38.1" y2="166.37" width="0.1524" layer="91"/> +<wire x1="38.1" y1="166.37" x2="38.1" y2="156.21" width="0.1524" layer="91"/> +<label x="63.8175" y="166.6875" size="1.778" layer="92"/> +<pinref part="U6A1" gate="G$1" pin="RY1"/> +<pinref part="U6E1" gate="UART" pin="SIU_DCD1#"/> +</segment> +</net> +<net name="SIU1-DSR-N" class="0"> +<segment> +<wire x1="81.28" y1="163.83" x2="40.64" y2="163.83" width="0.1524" layer="91"/> +<wire x1="40.64" y1="163.83" x2="40.64" y2="153.67" width="0.1524" layer="91"/> +<wire x1="40.64" y1="153.67" x2="38.1" y2="153.67" width="0.1524" layer="91"/> +<label x="63.8175" y="164.1475" size="1.778" layer="92"/> +<pinref part="U6A1" gate="G$1" pin="RY2"/> +<pinref part="U6E1" gate="UART" pin="SIU_DSR1#"/> +</segment> +</net> +<net name="SIU1-RXD" class="0"> +<segment> +<wire x1="81.28" y1="161.29" x2="52.07" y2="161.29" width="0.1524" layer="91"/> +<wire x1="38.1" y1="151.13" x2="43.18" y2="151.13" width="0.1524" layer="91"/> +<wire x1="43.18" y1="151.13" x2="43.18" y2="161.29" width="0.1524" layer="91"/> +<wire x1="43.18" y1="161.29" x2="52.07" y2="161.29" width="0.1524" layer="91"/> +<label x="63.8175" y="161.6075" size="1.778" layer="92"/> +<pinref part="U6A1" gate="G$1" pin="RY3"/> +<pinref part="U6E1" gate="UART" pin="SIU_RXD1"/> +</segment> +</net> +<net name="SIU1-CTS-N" class="0"> +<segment> +<wire x1="38.1" y1="148.59" x2="43.18" y2="148.59" width="0.1524" layer="91"/> +<wire x1="81.28" y1="158.75" x2="45.72" y2="158.75" width="0.1524" layer="91"/> +<wire x1="45.72" y1="158.75" x2="45.72" y2="148.59" width="0.1524" layer="91"/> +<wire x1="45.72" y1="148.59" x2="43.18" y2="148.59" width="0.1524" layer="91"/> +<label x="63.8175" y="159.0675" size="1.778" layer="92"/> +<pinref part="U6A1" gate="G$1" pin="RY4"/> +<pinref part="U6E1" gate="UART" pin="SIU_CTS1#"/> +</segment> +</net> +<net name="SIU1-RI-N" class="0"> +<segment> +<wire x1="38.1" y1="146.05" x2="48.26" y2="146.05" width="0.1524" layer="91"/> +<wire x1="48.26" y1="146.05" x2="48.26" y2="156.21" width="0.1524" layer="91"/> +<wire x1="48.26" y1="156.21" x2="81.28" y2="156.21" width="0.1524" layer="91"/> +<label x="63.8175" y="156.5275" size="1.778" layer="92"/> +<pinref part="U6A1" gate="G$1" pin="RY5"/> +<pinref part="U6E1" gate="UART" pin="SIU_RI1#"/> +</segment> +</net> +<net name="SIU1-RTS-N" class="0"> +<segment> +<wire x1="38.1" y1="143.51" x2="50.8" y2="143.51" width="0.1524" layer="91"/> +<wire x1="50.8" y1="143.51" x2="50.8" y2="153.67" width="0.1524" layer="91"/> +<wire x1="81.28" y1="153.67" x2="50.8" y2="153.67" width="0.1524" layer="91"/> +<label x="63.8175" y="153.9875" size="1.778" layer="92"/> +<pinref part="U6A1" gate="G$1" pin="DA1"/> +<pinref part="U6E1" gate="UART" pin="SIU_RTS1#"/> +</segment> +</net> +<net name="SIU1-DTR-N" class="0"> +<segment> +<wire x1="81.28" y1="148.59" x2="55.88" y2="148.59" width="0.1524" layer="91"/> +<wire x1="55.88" y1="148.59" x2="55.88" y2="138.43" width="0.1524" layer="91"/> +<wire x1="55.88" y1="138.43" x2="38.1" y2="138.43" width="0.1524" layer="91"/> +<label x="63.8175" y="148.9075" size="1.778" layer="92"/> +<pinref part="U6A1" gate="G$1" pin="DA3"/> +<pinref part="U6E1" gate="UART" pin="SIU_DTR1#"/> +</segment> +</net> +<net name="N$510" class="0"> +<segment> +<wire x1="222.25" y1="114.3" x2="171.45" y2="114.3" width="0.1524" layer="91"/> +<wire x1="171.45" y1="114.3" x2="140.97" y2="114.3" width="0.1524" layer="91"/> +<wire x1="171.45" y1="90.17" x2="171.45" y2="114.3" width="0.1524" layer="91"/> +<junction x="171.45" y="114.3"/> +<pinref part="FB6B2" gate="A" pin="1"/> +<pinref part="CP5A2" gate="C" pin="2"/> +<pinref part="JCOM2" gate="J" pin="1"/> +</segment> +</net> +<net name="N$511" class="0"> +<segment> +<wire x1="210.82" y1="109.22" x2="165.1" y2="109.22" width="0.1524" layer="91"/> +<wire x1="165.1" y1="109.22" x2="140.97" y2="109.22" width="0.1524" layer="91"/> +<wire x1="165.1" y1="90.17" x2="165.1" y2="109.22" width="0.1524" layer="91"/> +<junction x="165.1" y="109.22"/> +<pinref part="FB6B2" gate="C" pin="1"/> +<pinref part="CP5A2" gate="B" pin="2"/> +<wire x1="210.82" y1="109.22" x2="210.82" y2="111.76" width="0.1524" layer="91"/> +<pinref part="JCOM2" gate="J" pin="2"/> +<wire x1="210.82" y1="111.76" x2="222.25" y2="111.76" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$512" class="0"> +<segment> +<wire x1="204.47" y1="99.06" x2="140.97" y2="99.06" width="0.1524" layer="91"/> +<wire x1="204.47" y1="90.17" x2="204.47" y2="99.06" width="0.1524" layer="91"/> +<pinref part="FB6A3" gate="A" pin="1"/> +<pinref part="CP5A2" gate="D" pin="2"/> +<wire x1="204.47" y1="99.06" x2="204.47" y2="106.68" width="0.1524" layer="91"/> +<junction x="204.47" y="99.06"/> +<wire x1="204.47" y1="106.68" x2="213.36" y2="106.68" width="0.1524" layer="91"/> +<wire x1="213.36" y1="106.68" x2="213.36" y2="109.22" width="0.1524" layer="91"/> +<pinref part="JCOM2" gate="J" pin="3"/> +<wire x1="213.36" y1="109.22" x2="222.25" y2="109.22" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$513" class="0"> +<segment> +<wire x1="222.25" y1="106.68" x2="215.9" y2="106.68" width="0.1524" layer="91"/> +<wire x1="215.9" y1="106.68" x2="215.9" y2="104.14" width="0.1524" layer="91"/> +<wire x1="215.9" y1="104.14" x2="191.77" y2="104.14" width="0.1524" layer="91"/> +<wire x1="191.77" y1="104.14" x2="191.77" y2="96.52" width="0.1524" layer="91"/> +<wire x1="191.77" y1="96.52" x2="140.97" y2="96.52" width="0.1524" layer="91"/> +<wire x1="191.77" y1="90.17" x2="191.77" y2="96.52" width="0.1524" layer="91"/> +<junction x="191.77" y="96.52"/> +<pinref part="FB6A3" gate="C" pin="1"/> +<pinref part="CP5A1" gate="D" pin="2"/> +<pinref part="JCOM2" gate="J" pin="4"/> +</segment> +</net> +<net name="N$514" class="0"> +<segment> +<wire x1="208.28" y1="111.76" x2="184.15" y2="111.76" width="0.1524" layer="91"/> +<wire x1="184.15" y1="111.76" x2="177.8" y2="111.76" width="0.1524" layer="91"/> +<wire x1="177.8" y1="111.76" x2="140.97" y2="111.76" width="0.1524" layer="91"/> +<wire x1="177.8" y1="90.17" x2="177.8" y2="111.76" width="0.1524" layer="91"/> +<junction x="177.8" y="111.76"/> +<pinref part="FB6B2" gate="B" pin="1"/> +<pinref part="CP5A2" gate="A" pin="2"/> +<wire x1="208.28" y1="111.76" x2="208.28" y2="101.6" width="0.1524" layer="91"/> +<pinref part="JCOM2" gate="J" pin="6"/> +<wire x1="208.28" y1="101.6" x2="222.25" y2="101.6" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$515" class="0"> +<segment> +<wire x1="198.12" y1="106.68" x2="140.97" y2="106.68" width="0.1524" layer="91"/> +<wire x1="198.12" y1="90.17" x2="198.12" y2="96.52" width="0.1524" layer="91"/> +<pinref part="FB6A3" gate="B" pin="1"/> +<pinref part="CP5A1" gate="C" pin="2"/> +<pinref part="JCOM2" gate="J" pin="8"/> +<wire x1="198.12" y1="96.52" x2="198.12" y2="106.68" width="0.1524" layer="91"/> +<wire x1="222.25" y1="96.52" x2="198.12" y2="96.52" width="0.1524" layer="91"/> +<junction x="198.12" y="96.52"/> +</segment> +</net> +<net name="N$516" class="0"> +<segment> +<wire x1="207.01" y1="101.6" x2="158.75" y2="101.6" width="0.1524" layer="91"/> +<wire x1="158.75" y1="101.6" x2="140.97" y2="101.6" width="0.1524" layer="91"/> +<wire x1="158.75" y1="90.17" x2="158.75" y2="101.6" width="0.1524" layer="91"/> +<junction x="158.75" y="101.6"/> +<pinref part="FB6B2" gate="D" pin="1"/> +<pinref part="CP5A1" gate="B" pin="2"/> +<wire x1="207.01" y1="101.6" x2="207.01" y2="99.06" width="0.1524" layer="91"/> +<pinref part="JCOM2" gate="J" pin="7"/> +<wire x1="207.01" y1="99.06" x2="222.25" y2="99.06" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SIU2-DCD-N" class="0"> +<segment> +<wire x1="81.28" y1="114.3" x2="58.42" y2="114.3" width="0.1524" layer="91"/> +<wire x1="58.42" y1="114.3" x2="58.42" y2="130.81" width="0.1524" layer="91"/> +<wire x1="58.42" y1="130.81" x2="38.1" y2="130.81" width="0.1524" layer="91"/> +<label x="63.8175" y="114.6175" size="1.778" layer="92"/> +<pinref part="U5A1" gate="G$1" pin="RY1"/> +<pinref part="U6E1" gate="UART" pin="SIU_DCD2#"/> +<wire x1="58.42" y1="114.3" x2="58.42" y2="82.55" width="0.1524" layer="91"/> +<junction x="58.42" y="114.3"/> +<pinref part="R3R10" gate="R" pin="2"/> +<wire x1="58.42" y1="82.55" x2="53.34" y2="82.55" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SIU2-DSR-N" class="0"> +<segment> +<wire x1="38.1" y1="128.27" x2="53.34" y2="128.27" width="0.1524" layer="91"/> +<wire x1="53.34" y1="128.27" x2="53.34" y2="111.76" width="0.1524" layer="91"/> +<wire x1="81.28" y1="111.76" x2="53.34" y2="111.76" width="0.1524" layer="91"/> +<label x="63.8175" y="112.0775" size="1.778" layer="92"/> +<pinref part="U5A1" gate="G$1" pin="RY2"/> +<pinref part="U6E1" gate="UART" pin="SIU_DSR2#"/> +</segment> +</net> +<net name="SIU2-RXD" class="0"> +<segment> +<wire x1="81.28" y1="109.22" x2="50.8" y2="109.22" width="0.1524" layer="91"/> +<wire x1="50.8" y1="109.22" x2="50.8" y2="125.73" width="0.1524" layer="91"/> +<wire x1="50.8" y1="125.73" x2="38.1" y2="125.73" width="0.1524" layer="91"/> +<label x="63.8175" y="109.5375" size="1.778" layer="92"/> +<pinref part="U5A1" gate="G$1" pin="RY3"/> +<pinref part="U6E1" gate="UART" pin="SIU_RXD2"/> +</segment> +</net> +<net name="SIU2-CTS-N" class="0"> +<segment> +<wire x1="81.28" y1="106.68" x2="48.26" y2="106.68" width="0.1524" layer="91"/> +<wire x1="38.1" y1="123.19" x2="48.26" y2="123.19" width="0.1524" layer="91"/> +<wire x1="48.26" y1="123.19" x2="48.26" y2="106.68" width="0.1524" layer="91"/> +<label x="63.8175" y="106.9975" size="1.778" layer="92"/> +<pinref part="U5A1" gate="G$1" pin="RY4"/> +<pinref part="U6E1" gate="UART" pin="SIU_CTS2#"/> +</segment> +</net> +<net name="SIU2-RTS-N" class="0"> +<segment> +<wire x1="81.28" y1="101.6" x2="43.18" y2="101.6" width="0.1524" layer="91"/> +<wire x1="43.18" y1="101.6" x2="43.18" y2="118.11" width="0.1524" layer="91"/> +<wire x1="43.18" y1="118.11" x2="38.1" y2="118.11" width="0.1524" layer="91"/> +<label x="63.8175" y="101.9175" size="1.778" layer="92"/> +<pinref part="U5A1" gate="G$1" pin="DA1"/> +<pinref part="U6E1" gate="UART" pin="SIU_RTS2#"/> +</segment> +</net> +<net name="SIU2-DTR-N" class="0"> +<segment> +<wire x1="81.28" y1="96.52" x2="55.88" y2="96.52" width="0.1524" layer="91"/> +<label x="63.8175" y="96.8375" size="1.778" layer="92"/> +<pinref part="U5A1" gate="G$1" pin="DA3"/> +<pinref part="R3R11" gate="R" pin="2"/> +<pinref part="R3R13" gate="R" pin="2"/> +<wire x1="55.88" y1="96.52" x2="54.61" y2="96.52" width="0.1524" layer="91"/> +<wire x1="53.34" y1="88.9" x2="55.88" y2="88.9" width="0.1524" layer="91"/> +<wire x1="55.88" y1="88.9" x2="55.88" y2="96.52" width="0.1524" layer="91"/> +<junction x="55.88" y="96.52"/> +</segment> +</net> +<net name="SATAHDR-TXP0" class="0"> +<segment> +<wire x1="127" y1="62.23" x2="95.25" y2="62.23" width="0.1524" layer="91"/> +<wire x1="95.25" y1="62.23" x2="95.25" y2="59.69" width="0.1524" layer="91"/> +<wire x1="95.25" y1="59.69" x2="91.44" y2="59.69" width="0.1524" layer="91"/> +<label x="118.11" y="64.4525" size="1.778" layer="92" rot="R180"/> +<pinref part="C6T4" gate="C" pin="2"/> +<pinref part="U6E1" gate="SATA" pin="SATA_TXP0"/> +</segment> +</net> +<net name="SATAHDR-TXN0" class="0"> +<segment> +<wire x1="127" y1="57.15" x2="91.44" y2="57.15" width="0.1524" layer="91"/> +<label x="118.11" y="59.3725" size="1.778" layer="92" rot="R180"/> +<pinref part="C6T3" gate="C" pin="2"/> +<pinref part="U6E1" gate="SATA" pin="SATA_TXN0"/> +</segment> +</net> +<net name="SATAHDR-RXN0" class="0"> +<segment> +<wire x1="127" y1="52.07" x2="95.25" y2="52.07" width="0.1524" layer="91"/> +<wire x1="95.25" y1="52.07" x2="95.25" y2="54.61" width="0.1524" layer="91"/> +<wire x1="95.25" y1="54.61" x2="91.44" y2="54.61" width="0.1524" layer="91"/> +<label x="118.11" y="54.2925" size="1.778" layer="92" rot="R180"/> +<pinref part="C6T2" gate="C" pin="2"/> +<pinref part="U6E1" gate="SATA" pin="SATA_RXN0"/> +</segment> +</net> +<net name="SATAHDR-RXP0" class="0"> +<segment> +<wire x1="127" y1="46.99" x2="92.71" y2="46.99" width="0.1524" layer="91"/> +<wire x1="92.71" y1="46.99" x2="92.71" y2="52.07" width="0.1524" layer="91"/> +<wire x1="92.71" y1="52.07" x2="91.44" y2="52.07" width="0.1524" layer="91"/> +<label x="118.11" y="49.2125" size="1.778" layer="92" rot="R180"/> +<pinref part="C6T1" gate="C" pin="2"/> +<pinref part="U6E1" gate="SATA" pin="SATA_RXP0"/> +</segment> +</net> +<net name="N$526" class="0"> +<segment> +<wire x1="57.15" y1="21.59" x2="50.8" y2="21.59" width="0.1524" layer="91"/> +<wire x1="50.8" y1="21.59" x2="41.91" y2="21.59" width="0.1524" layer="91"/> +<wire x1="57.15" y1="17.78" x2="50.8" y2="17.78" width="0.1524" layer="91"/> +<wire x1="50.8" y1="17.78" x2="50.8" y2="21.59" width="0.1524" layer="91"/> +<junction x="50.8" y="21.59"/> +<pinref part="U6E1" gate="SATA" pin="SATA_RBIAS#"/> +<pinref part="R5E4" gate="R" pin="2"/> +<pinref part="U6E1" gate="SATA" pin="SATA_RBIAS"/> +</segment> +</net> +<net name="TOL-SATA-100MHZ-N-R" class="0"> +<segment> +<wire x1="57.15" y1="45.72" x2="50.8" y2="45.72" width="0.1524" layer="91"/> +<wire x1="50.8" y1="45.72" x2="50.8" y2="55.88" width="0.1524" layer="91"/> +<wire x1="50.8" y1="55.88" x2="44.45" y2="55.88" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="SATA" pin="SATA_CLKREFN"/> +<label x="44.45" y="55.88" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="TOL-SATA-100MHZ-P-R" class="0"> +<segment> +<wire x1="57.15" y1="43.18" x2="48.26" y2="43.18" width="0.1524" layer="91"/> +<wire x1="48.26" y1="43.18" x2="48.26" y2="49.53" width="0.1524" layer="91"/> +<wire x1="48.26" y1="49.53" x2="44.45" y2="49.53" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="SATA" pin="SATA_CLKREFP"/> +<label x="44.45" y="49.53" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="SIU1-TXD" class="0"> +<segment> +<wire x1="81.28" y1="151.13" x2="53.34" y2="151.13" width="0.1524" layer="91"/> +<wire x1="53.34" y1="151.13" x2="53.34" y2="140.97" width="0.1524" layer="91"/> +<wire x1="53.34" y1="140.97" x2="38.1" y2="140.97" width="0.1524" layer="91"/> +<label x="63.8175" y="151.4475" size="1.778" layer="92"/> +<pinref part="U6A1" gate="G$1" pin="DA2"/> +<pinref part="U6E1" gate="UART" pin="SIU_TXD1"/> +</segment> +</net> +<net name="SIU2-TXD" class="0"> +<segment> +<wire x1="81.28" y1="99.06" x2="40.64" y2="99.06" width="0.1524" layer="91"/> +<wire x1="40.64" y1="99.06" x2="40.64" y2="115.57" width="0.1524" layer="91"/> +<wire x1="40.64" y1="115.57" x2="38.1" y2="115.57" width="0.1524" layer="91"/> +<wire x1="40.64" y1="99.06" x2="33.02" y2="99.06" width="0.1524" layer="91"/> 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width="0.1524" layer="91"/> +<junction x="8.89" y="38.1"/> +<pinref part="U$284" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R45" gate="R" pin="1"/> +<pinref part="R46" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="29.21" y1="13.97" x2="20.32" y2="13.97" width="0.1524" layer="91"/> +<pinref part="U$378" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R3J3" gate="R" pin="1"/> +</segment> +<segment> +<pinref part="R50" gate="R" pin="1"/> +<wire x1="12.7" y1="106.68" x2="19.05" y2="106.68" width="0.1524" layer="91"/> +<pinref part="U$88" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="GPIO26" class="0"> +<segment> +<wire x1="34.29" y1="39.37" x2="36.83" y2="38.1" width="0.1524" layer="91"/> +<wire x1="36.83" y1="38.1" x2="57.15" y2="38.1" width="0.1524" layer="91"/> +<label x="37.7825" y="38.4175" size="1.778" layer="92"/> +<pinref part="U6E1" gate="SATA" pin="GP26_SATA0GP"/> +</segment> +<segment> +<wire x1="34.29" y1="39.37" x2="31.75" y2="38.1" width="0.1524" layer="91"/> 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class="0"> +<segment> +<wire x1="36.83" y1="139.7" x2="36.83" y2="135.89" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GPIO" pin="GPIO[8]"/> +<pinref part="R37" gate="R" pin="1"/> +<wire x1="36.83" y1="139.7" x2="36.83" y2="144.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="191.77" y1="66.04" x2="191.77" y2="63.5" width="0.1524" layer="91"/> +<wire x1="182.88" y1="63.5" x2="191.77" y2="63.5" width="0.1524" layer="91"/> +<wire x1="182.88" y1="63.5" x2="182.88" y2="54.61" width="0.1524" layer="91"/> +<pinref part="U$290" gate="PW-VCC3" pin="VCC3"/> +<pinref part="C64" gate="C" pin="2"/> +<pinref part="U3" gate="PW" pin="VDD"/> +<wire x1="195.58" y1="62.23" x2="195.58" y2="63.5" width="0.1524" layer="91"/> +<wire x1="195.58" y1="63.5" x2="191.77" y2="63.5" width="0.1524" layer="91"/> +<junction x="191.77" y="63.5"/> +</segment> +<segment> +<wire x1="69.85" y1="105.41" x2="69.85" y2="109.22" width="0.1524" layer="91"/> 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gate="R" pin="2"/> +<wire x1="128.27" y1="125.73" x2="148.59" y2="125.73" width="0.1524" layer="91"/> +<pinref part="R16" gate="R" pin="1"/> +<pinref part="U$167" gate="PW-VCC3" pin="VCC3"/> +<wire x1="148.59" y1="125.73" x2="158.75" y2="125.73" width="0.1524" layer="91"/> +<wire x1="158.75" y1="130.81" x2="148.59" y2="130.81" width="0.1524" layer="91"/> +<wire x1="148.59" y1="130.81" x2="148.59" y2="125.73" width="0.1524" layer="91"/> +<junction x="148.59" y="125.73"/> +</segment> +</net> +<net name="GP21" class="0"> +<segment> +<wire x1="45.72" y1="41.91" x2="45.72" y2="64.77" width="0.1524" layer="91"/> +<pinref part="R6T24" gate="R" pin="2"/> +<pinref part="U6E1" gate="GPIOIRQ" pin="GP21_IRQ27"/> +<wire x1="45.72" y1="64.77" x2="45.72" y2="71.12" width="0.1524" layer="91"/> +<wire x1="45.72" y1="64.77" x2="17.78" y2="64.77" width="0.1524" layer="91"/> +<junction x="45.72" y="64.77"/> +<label x="17.78" y="64.77" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> 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size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="GPIO31" class="0"> +<segment> +<wire x1="27.94" y1="41.91" x2="27.94" y2="49.53" width="0.1524" layer="91"/> +<pinref part="R89" gate="R" pin="1"/> +<pinref part="U6E1" gate="GPIOIRQ" pin="GP31_IRQ32"/> +<wire x1="27.94" y1="49.53" x2="27.94" y2="71.12" width="0.1524" layer="91"/> +<wire x1="27.94" y1="49.53" x2="17.78" y2="49.53" width="0.1524" layer="91"/> +<junction x="27.94" y="49.53"/> +<label x="17.78" y="49.53" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="GPIO33" class="0"> +<segment> +<wire x1="25.4" y1="41.91" x2="25.4" y2="71.12" width="0.1524" layer="91"/> +<pinref part="R44" gate="R" pin="1"/> +<pinref part="U6E1" gate="GPIOIRQ" pin="GP33_IRQ33"/> +</segment> +</net> +<net name="GPIO34" class="0"> +<segment> +<wire x1="22.86" y1="41.91" x2="22.86" y2="71.12" width="0.1524" layer="91"/> +<pinref part="R90" gate="R" pin="2"/> +<pinref part="U6E1" gate="GPIOIRQ" pin="GP34_IRQ34"/> +</segment> +</net> +<net name="N$104" class="0"> +<segment> +<wire x1="168.91" y1="125.73" x2="181.61" y2="125.73" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="SBUS" pin="SSP_EXTCLK"/> +<pinref part="R16" gate="R" pin="2"/> +</segment> +</net> +<net name="GPIO15" class="0"> +<segment> +<wire x1="21.59" y1="139.7" x2="21.59" y2="135.89" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GPIO" pin="GPIO[15]"/> +<pinref part="R26" gate="R" pin="1"/> +<wire x1="21.59" y1="139.7" x2="21.59" y2="144.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="GPIO14" class="0"> +<segment> +<wire x1="24.13" y1="139.7" x2="24.13" y2="135.89" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GPIO" pin="GPIO[14]"/> +<pinref part="R42" gate="R" pin="1"/> +<wire x1="24.13" y1="139.7" x2="24.13" y2="144.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="GPIO13" class="0"> +<segment> +<wire x1="26.67" y1="139.7" x2="26.67" y2="135.89" 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y1="139.7" x2="44.45" y2="144.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="GPIO0" class="0"> +<segment> +<wire x1="46.99" y1="139.7" x2="46.99" y2="137.16" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="GPIO" pin="GPIO[0]"/> +<pinref part="R30" gate="R" pin="1"/> +<wire x1="46.99" y1="137.16" x2="46.99" y2="135.89" width="0.1524" layer="91"/> +<wire x1="46.99" y1="139.7" x2="46.99" y2="144.78" width="0.1524" layer="91"/> +<wire x1="46.99" y1="137.16" x2="54.61" y2="137.16" width="0.1524" layer="91"/> +<junction x="46.99" y="137.16"/> +<label x="54.61" y="137.16" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="GPIO11" class="0"> +<segment> +<wire x1="168.91" y1="130.81" x2="181.61" y2="130.81" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="SBUS" pin="GP11_SMBALERT_N"/> +<pinref part="R25" gate="R" pin="1"/> +</segment> +</net> +<net name="V-3P0-BAT-VREG" class="0"> +<segment> +<wire x1="152.4" y1="140.97" x2="158.75" y2="140.97" width="0.1524" layer="91"/> +<pinref part="R8V7" gate="R" pin="1"/> +<label x="152.4" y="140.97" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$114" class="0"> +<segment> +<wire x1="168.91" y1="140.97" x2="181.61" y2="140.97" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="SBUS" pin="INTRUDER_N"/> +<pinref part="R8V7" gate="R" pin="2"/> +</segment> +</net> +<net name="FLASH-WP-LED" class="0"> +<segment> +<wire x1="107.95" y1="97.79" x2="107.95" y2="64.77" width="0.1524" layer="91"/> +<wire x1="107.95" y1="64.77" x2="107.95" y2="46.99" width="0.1524" layer="91"/> +<wire x1="107.95" y1="41.91" x2="107.95" y2="46.99" width="0.1524" layer="91"/> +<wire x1="100.33" y1="64.77" x2="107.95" y2="64.77" width="0.1524" layer="91"/> +<wire x1="100.33" y1="41.91" x2="100.33" y2="64.77" width="0.1524" layer="91"/> +<wire x1="147.32" y1="67.31" x2="147.32" y2="64.77" width="0.1524" layer="91"/> +<wire x1="147.32" y1="64.77" x2="153.67" y2="64.77" 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y="64.77"/> +<label x="106.9975" y="69.215" size="1.778" layer="92" rot="R90"/> +<pinref part="U2" gate="AT26" pin="WP"/> +<pinref part="R15" gate="R" pin="1"/> +<pinref part="R14" gate="R" pin="1"/> +<pinref part="U3" gate="C" pin="@"/> +<pinref part="U3" gate="B" pin="@"/> +<pinref part="U3" gate="D" pin="@"/> +<pinref part="U3" gate="A" pin="@"/> +<pinref part="SV3" gate="1" pin="3"/> +</segment> +</net> +<net name="N$137" class="0"> +<segment> +<wire x1="107.95" y1="31.75" x2="107.95" y2="30.48" width="0.1524" layer="91"/> +<wire x1="107.95" y1="26.67" x2="107.95" y2="30.48" width="0.1524" layer="91"/> +<pinref part="R15" gate="R" pin="2"/> +<pinref part="LED15" gate="LED" pin="A"/> +</segment> +</net> +<net name="SPI-MISO" class="0"> +<segment> +<wire x1="173.99" y1="107.95" x2="179.07" y2="107.95" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="SBUS" pin="SPI_MISO"/> +<pinref part="R2K1" gate="R" pin="1"/> +<pinref part="R20" gate="R" pin="1"/> +<wire x1="179.07" y1="107.95" x2="181.61" y2="107.95" width="0.1524" layer="91"/> +<wire x1="160.02" y1="113.03" x2="179.07" y2="113.03" width="0.1524" layer="91"/> +<wire x1="179.07" y1="113.03" x2="179.07" y2="107.95" width="0.1524" layer="91"/> +<junction x="179.07" y="107.95"/> +</segment> +</net> +<net name="SPI-MOSI" class="0"> +<segment> +<wire x1="173.99" y1="105.41" x2="181.61" y2="105.41" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="SBUS" pin="SPI_MOSI"/> +<pinref part="R6F5" gate="R" pin="1"/> +</segment> +</net> +<net name="SPI-CS-N" class="0"> +<segment> +<wire x1="173.99" y1="102.87" x2="181.61" y2="102.87" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="SBUS" pin="SPI_CS_N"/> +<pinref part="R6F3" gate="R" pin="1"/> +</segment> +</net> +<net name="SPI-SCLK" class="0"> +<segment> +<wire x1="173.99" y1="100.33" x2="181.61" y2="100.33" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="SBUS" pin="SPI_SCLK"/> +<pinref part="R6F4" gate="R" pin="1"/> +</segment> +</net> +<net name="SPI-MISO-R" class="0"> +<segment> +<wire x1="154.94" y1="107.95" x2="161.29" y2="107.95" width="0.1524" layer="91"/> +<wire x1="161.29" y1="107.95" x2="163.83" y2="107.95" width="0.1524" layer="91"/> +<pinref part="U3" gate="B" pin="O"/> +<pinref part="R2K1" gate="R" pin="2"/> +</segment> +</net> +<net name="SPI-MOSI-R" class="0"> +<segment> +<wire x1="152.4" y1="96.52" x2="156.21" y2="96.52" width="0.1524" layer="91"/> +<wire x1="156.21" y1="96.52" x2="156.21" y2="105.41" width="0.1524" layer="91"/> +<wire x1="156.21" y1="105.41" x2="163.83" y2="105.41" width="0.1524" layer="91"/> +<pinref part="U3" gate="D" pin="I"/> +<pinref part="R6F5" gate="R" pin="2"/> +</segment> +</net> +<net name="SPI-CS-N-R" class="0"> +<segment> +<wire x1="158.75" y1="102.87" x2="158.75" y2="85.09" width="0.1524" layer="91"/> +<wire x1="158.75" y1="85.09" x2="152.4" y2="85.09" width="0.1524" layer="91"/> +<wire x1="168.91" y1="85.09" x2="158.75" y2="85.09" width="0.1524" layer="91"/> +<wire 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+<pinref part="SV3" gate="1" pin="10"/> +</segment> +</net> +<net name="MSP-BSL-TEST" class="0"> +<segment> +<wire x1="123.19" y1="33.02" x2="148.59" y2="33.02" width="0.1524" layer="91"/> +<wire x1="123.19" y1="33.02" x2="123.19" y2="45.72" width="0.1524" layer="91"/> +<label x="148.59" y="33.02" size="1.778" layer="92" xref="yes"/> +<pinref part="SV3" gate="1" pin="4"/> +</segment> +</net> +<net name="MSP-BSL-TXD" class="0"> +<segment> +<pinref part="SV3" gate="1" pin="2"/> +<wire x1="120.65" y1="45.72" x2="120.65" y2="29.21" width="0.1524" layer="91"/> +<wire x1="120.65" y1="29.21" x2="148.59" y2="29.21" width="0.1524" layer="91"/> +<label x="148.59" y="29.21" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="MSP-BSL-RXD" class="0"> +<segment> +<pinref part="SV3" gate="1" pin="1"/> +<wire x1="120.65" y1="60.96" x2="116.84" y2="60.96" width="0.1524" layer="91"/> +<wire x1="116.84" y1="60.96" x2="116.84" y2="25.4" width="0.1524" layer="91"/> +<wire x1="116.84" y1="25.4" x2="148.59" y2="25.4" width="0.1524" layer="91"/> +<label x="148.59" y="25.4" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<wire x1="59.69" y1="93.98" x2="231.14" y2="93.98" width="0.1524" layer="94" style="longdash"/> +<text x="138.43" y="83.82" size="3.81" layer="94">SMBUS</text> +<text x="143.51" y="171.45" size="3.81" layer="94">USB</text> +</plain> +<instances> +<instance part="FRAME19" gate="G$1" x="0" y="0"/> +<instance part="FRAME19" gate="G$2" x="180.34" y="0"/> +<instance part="U3G2" gate="U" x="144.78" y="62.23" smashed="yes"> +<attribute name="NAME" x="133.0325" y="71.755" size="1.778" layer="95"/> +<attribute name="VALUE" x="147.32" y="71.755" size="1.778" layer="96"/> +</instance> +<instance part="R6T15" gate="R" x="193.04" y="76.2" rot="R270"> +<attribute name="POWER" x="193.04" y="76.2" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6T16" gate="R" x="199.39" y="76.2" rot="R270"> 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smashed="yes"> +<attribute name="NAME" x="133.0325" y="28.575" size="1.778" layer="95"/> +<attribute name="VALUE" x="147.32" y="28.575" size="1.778" layer="96"/> +</instance> +<instance part="R6T13" gate="R" x="193.04" y="33.02" rot="R270"> +<attribute name="POWER" x="193.04" y="33.02" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6T14" gate="R" x="199.39" y="33.02" rot="R270"> +<attribute name="POWER" x="199.39" y="33.02" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6U2" gate="R" x="87.63" y="26.67" rot="R270"> +<attribute name="POWER" x="87.63" y="26.67" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R6T22" gate="R" x="73.66" y="17.78"> +<attribute name="POWER" x="73.66" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$480" gate="PW-VCC3" x="118.11" y="13.97" rot="MR270"/> +<instance part="U$481" gate="PW-VCC3" x="193.04" y="46.99"/> +<instance part="U$482" gate="PW-VCC3" x="87.63" y="38.1"/> +<instance part="U$483" gate="G$1" x="167.64" y="10.16"/> +<instance part="L8A2" gate="G$1" x="205.74" y="152.4" smashed="yes"> +<attribute name="NAME" x="199.39" y="158.75" size="1.778" layer="95"/> +<attribute name="VALUE" x="208.28" y="158.75" size="1.778" layer="96"/> +</instance> +<instance part="L8A1" gate="G$1" x="207.01" y="120.65" smashed="yes"> +<attribute name="NAME" x="200.66" y="125.73" size="1.778" layer="95"/> +<attribute name="VALUE" x="208.28" y="125.73" size="1.778" layer="96"/> +</instance> +<instance part="U$363" gate="G$1" x="142.24" y="97.79"/> +<instance part="U$364" gate="G$1" x="142.24" y="135.89"/> +<instance part="U9A1" gate="G$1" x="62.23" y="129.54"/> +<instance part="C1L6" gate="C" x="100.33" y="151.13" rot="R180"> +<attribute name="VOLTAGE" x="100.33" y="151.13" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="100.33" y="151.13" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="100.33" y="151.13" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C1L4" gate="C" x="36.83" y="147.32" rot="R180"> +<attribute name="VOLTAGE" x="36.83" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="36.83" y="147.32" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="36.83" y="147.32" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R1L3" gate="R" x="88.9" y="147.32" rot="R90"> +<attribute name="POWER" x="88.9" y="147.32" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R1L1" gate="R" x="78.74" y="148.59" rot="R90"> +<attribute name="POWER" x="78.74" y="148.59" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R1L2" gate="R" x="29.21" y="146.05" smashed="yes" rot="R270"> +<attribute name="NAME" x="32.4506" y="144.9334" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="30.7264" y="144.146" size="1.778" layer="96" rot="R270"/> +<attribute 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y="114.046" size="1.778" layer="96" rot="MR0"/> +<attribute name="VOLTAGE" x="97.79" y="111.76" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="97.79" y="111.76" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="97.79" y="111.76" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C9A4" gate="C" x="78.74" y="111.76" smashed="yes" rot="R270"> +<attribute name="NAME" x="80.391" y="109.474" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="75.184" y="114.046" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="78.74" y="111.76" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="78.74" y="111.76" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="78.74" y="111.76" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$371" gate="G$1" x="104.14" y="104.14" rot="MR0"/> +<instance part="U$372" gate="G$1" x="71.12" y="104.14"/> +<instance part="U$538" gate="G$1" x="87.63" y="104.14"/> +<instance part="J9A1" gate="USB1" x="233.68" y="148.59"/> +<instance part="J9A1" gate="USB2" x="233.68" y="116.84"/> +<instance part="U$259" gate="G$1" x="250.19" y="137.16"/> +<instance part="U$316" gate="G$1" x="250.19" y="104.14"/> +<instance part="U$320" gate="G$1" x="57.15" y="104.14"/> +<instance part="U$357" gate="G$1" x="33.02" y="104.14" rot="MR0"/> +<instance part="FB9A2" gate="F" x="44.45" y="111.76"/> +<instance part="FB8A1" gate="F" x="44.45" y="106.68"/> +<instance part="P+6" gate="1" x="44.45" y="165.1"/> +<instance part="U$58" gate="PW-VCC3" x="88.9" y="166.37"/> +<instance part="R5H1" gate="R" x="142.24" y="119.38" smashed="yes" rot="MR90"> +<attribute name="POWER" x="142.24" y="119.38" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="TOLERANCE" x="142.24" y="119.38" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="NAME" x="140.97" y="120.015" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="140.97" y="120.9675" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="R5H2" gate="R" x="142.24" y="158.75" smashed="yes" rot="MR90"> +<attribute name="POWER" x="142.24" y="158.75" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="TOLERANCE" x="142.24" y="158.75" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="NAME" x="140.97" y="159.0675" size="1.778" layer="95" rot="MR270"/> +<attribute name="VALUE" x="140.97" y="160.3375" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="C9A1" gate="C" x="142.24" y="146.05"> +<attribute name="VOLTAGE" x="142.24" y="146.05" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TOLERANCE" x="142.24" y="146.05" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TYPE" x="142.24" y="146.05" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C1N5" gate="C" x="142.24" y="106.68"> +<attribute name="VOLTAGE" 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layer="96" rot="R90"/> +<attribute name="NAME" x="162.306" y="114.681" size="1.778" layer="95" rot="R270"/> +<attribute name="VALUE" x="164.084" y="117.094" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="C9A2" gate="C" x="172.72" y="116.84" smashed="yes"> +<attribute name="TYPE" x="172.72" y="116.84" size="1.778" layer="96" display="off"/> +<attribute name="DNP" x="175.26" y="116.84" size="1.778" layer="96" rot="R90"/> +<attribute name="NAME" x="169.926" y="114.681" size="1.778" layer="95" rot="R270"/> +<attribute name="VALUE" x="171.704" y="117.094" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="C1L1" gate="C" x="172.72" y="153.67" smashed="yes"> +<attribute name="TYPE" x="172.72" y="153.67" size="1.778" layer="96" display="off"/> +<attribute name="DNP" x="175.26" y="153.67" size="1.778" layer="96" rot="R90"/> +<attribute name="NAME" x="169.926" y="151.511" size="1.778" layer="95" rot="R270"/> +<attribute name="VALUE" x="171.704" y="153.924" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="C1L7" gate="C" x="165.1" y="153.67" smashed="yes"> +<attribute name="TYPE" x="165.1" y="153.67" size="1.778" layer="96" display="off"/> +<attribute name="DNP" x="167.64" y="153.67" size="1.778" layer="96" rot="R90"/> +<attribute name="NAME" x="162.306" y="151.511" size="1.778" layer="95" rot="R270"/> +<attribute name="VALUE" x="164.084" y="153.924" size="1.778" layer="96" rot="R90"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="N$547" class="0"> +<segment> +<wire x1="129.54" y1="60.96" x2="113.03" y2="60.96" width="0.1524" layer="91"/> +<wire x1="113.03" y1="60.96" x2="102.87" y2="60.96" width="0.1524" layer="91"/> +<wire x1="102.87" y1="60.96" x2="87.63" y2="60.96" width="0.1524" layer="91"/> +<wire x1="87.63" y1="58.42" x2="87.63" y2="60.96" width="0.1524" layer="91"/> +<wire x1="87.63" y1="69.85" x2="87.63" y2="60.96" width="0.1524" layer="91"/> +<junction x="87.63" y="60.96"/> +<pinref part="U3G2" gate="U" pin="EN"/> +<pinref part="Q6T2" gate="Q" pin="C"/> +<pinref part="R7U1" gate="R" pin="2"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="129.54" y1="57.15" x2="120.65" y2="57.15" width="0.1524" layer="91"/> +<pinref part="U3G2" gate="U" pin="VCC"/> +<pinref part="U$473" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="193.04" y1="81.28" x2="193.04" y2="88.9" width="0.1524" layer="91"/> +<wire x1="193.04" y1="88.9" x2="199.39" y2="88.9" width="0.1524" layer="91"/> +<wire x1="199.39" y1="88.9" x2="199.39" y2="81.28" width="0.1524" layer="91"/> +<wire x1="193.04" y1="88.9" x2="193.04" y2="93.98" width="0.1524" layer="91"/> +<junction x="193.04" y="88.9"/> +<pinref part="R6T15" gate="R" pin="1"/> +<pinref part="R6T16" gate="R" pin="1"/> +<pinref part="U$474" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="129.54" y1="13.97" x2="120.65" y2="13.97" width="0.1524" layer="91"/> +<pinref part="U4G1" gate="U" pin="VCC"/> +<pinref part="U$480" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="193.04" y1="38.1" x2="193.04" y2="41.91" width="0.1524" layer="91"/> +<wire x1="193.04" y1="41.91" x2="199.39" y2="41.91" width="0.1524" layer="91"/> +<wire x1="199.39" y1="41.91" x2="199.39" y2="38.1" width="0.1524" layer="91"/> +<wire x1="193.04" y1="41.91" x2="193.04" y2="44.45" width="0.1524" layer="91"/> +<junction x="193.04" y="41.91"/> +<pinref part="R6T13" gate="R" pin="1"/> +<pinref part="R6T14" gate="R" pin="1"/> +<pinref part="U$481" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="87.63" y1="31.75" x2="87.63" y2="35.56" width="0.1524" layer="91"/> +<pinref part="R6U2" gate="R" pin="1"/> +<pinref part="U$482" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="87.63" y1="80.01" x2="87.63" y2="86.36" width="0.1524" layer="91"/> +<pinref part="R7U1" gate="R" pin="1"/> +<pinref part="U$475" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="88.9" y1="152.4" x2="88.9" y2="161.29" width="0.1524" layer="91"/> +<wire x1="88.9" y1="161.29" x2="88.9" y2="163.83" width="0.1524" layer="91"/> +<wire x1="100.33" y1="156.21" x2="100.33" y2="161.29" width="0.1524" layer="91"/> +<wire x1="100.33" y1="161.29" x2="88.9" y2="161.29" width="0.1524" layer="91"/> +<wire x1="88.9" y1="161.29" x2="78.74" y2="161.29" width="0.1524" layer="91"/> +<wire x1="78.74" y1="161.29" x2="78.74" y2="153.67" width="0.1524" layer="91"/> +<junction x="88.9" y="161.29"/> +<pinref part="R1L1" gate="R" pin="2"/> +<pinref part="R1L3" gate="R" pin="2"/> +<pinref part="C1L6" gate="C" pin="1"/> +<pinref part="U$58" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="GND" class="0"> +<segment> +<wire x1="161.29" y1="60.96" x2="167.64" y2="60.96" width="0.1524" layer="91"/> +<wire x1="167.64" y1="60.96" x2="167.64" y2="54.61" width="0.1524" layer="91"/> +<pinref part="U3G2" gate="U" pin="GND"/> +<pinref part="U$476" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="87.63" y1="53.34" x2="87.63" y2="49.53" width="0.1524" layer="91"/> +<pinref part="Q6T2" gate="Q" pin="E"/> +<pinref part="U$478" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="161.29" y1="17.78" x2="167.64" y2="17.78" width="0.1524" layer="91"/> +<wire x1="167.64" y1="17.78" x2="167.64" y2="11.43" width="0.1524" layer="91"/> +<pinref part="U4G1" gate="U" pin="GND"/> +<pinref part="U$483" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="152.4" y1="111.76" x2="152.4" y2="100.33" width="0.1524" layer="91"/> +<wire x1="152.4" y1="100.33" x2="165.1" y2="100.33" width="0.1524" layer="91"/> +<wire x1="165.1" y1="100.33" x2="172.72" y2="100.33" width="0.1524" layer="91"/> +<wire x1="172.72" y1="100.33" x2="172.72" y2="111.76" width="0.1524" layer="91"/> +<wire x1="165.1" y1="111.76" x2="165.1" y2="100.33" width="0.1524" layer="91"/> +<wire x1="152.4" y1="100.33" x2="142.24" y2="100.33" width="0.1524" layer="91"/> +<wire x1="142.24" y1="100.33" x2="142.24" y2="99.06" width="0.1524" layer="91"/> +<junction x="165.1" y="100.33"/> +<junction x="152.4" y="100.33"/> +<pinref part="U$363" gate="G$1" pin="GND"/> +<pinref part="C1N5" gate="C" pin="1"/> +<wire x1="142.24" y1="100.33" x2="142.24" y2="101.6" width="0.1524" layer="91"/> +<junction x="142.24" y="100.33"/> +<pinref part="C9A2" gate="C" pin="1"/> +<pinref part="C1L5" gate="C" pin="1"/> +<pinref part="C1L3" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="142.24" y1="140.97" x2="142.24" y2="139.7" width="0.1524" layer="91"/> +<wire x1="142.24" y1="139.7" x2="152.4" y2="139.7" width="0.1524" layer="91"/> +<wire x1="152.4" y1="139.7" x2="165.1" y2="139.7" width="0.1524" layer="91"/> +<wire x1="165.1" y1="139.7" x2="172.72" y2="139.7" width="0.1524" layer="91"/> +<wire x1="172.72" y1="148.59" x2="172.72" y2="139.7" width="0.1524" layer="91"/> +<wire x1="142.24" y1="139.7" x2="142.24" y2="137.16" width="0.1524" layer="91"/> +<junction x="142.24" y="139.7"/> +<pinref part="U$364" gate="G$1" pin="GND"/> +<pinref part="C1L1" gate="C" pin="1"/> +<pinref part="C1L7" gate="C" pin="1"/> +<wire x1="165.1" y1="148.59" x2="165.1" y2="139.7" width="0.1524" layer="91"/> +<junction x="165.1" y="139.7"/> +<pinref part="C9A1" gate="C" pin="1"/> +<pinref part="C1L2" gate="C" pin="1"/> +<wire x1="152.4" y1="139.7" x2="152.4" y2="148.59" width="0.1524" layer="91"/> +<junction x="152.4" y="139.7"/> +</segment> +<segment> +<wire x1="100.33" y1="148.59" x2="100.33" y2="143.51" width="0.1524" layer="91"/> +<pinref part="C1L6" gate="C" pin="2"/> +<pinref part="U$365" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="36.83" y1="144.78" x2="36.83" y2="139.7" width="0.1524" layer="91"/> +<pinref part="C1L4" gate="C" pin="2"/> +<pinref part="U$366" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="44.45" y1="121.92" x2="44.45" y2="125.73" width="0.1524" layer="91"/> +<wire x1="44.45" y1="125.73" x2="46.99" y2="125.73" width="0.1524" layer="91"/> +<pinref part="U$367" gate="G$1" pin="GND"/> +<pinref part="U9A1" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="102.87" y1="111.76" x2="104.14" y2="111.76" width="0.1524" layer="91"/> +<wire x1="104.14" y1="111.76" x2="104.14" y2="105.41" width="0.1524" layer="91"/> +<pinref part="C8A1" gate="C" pin="1"/> +<pinref part="U$371" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="73.66" y1="111.76" x2="71.12" y2="111.76" width="0.1524" layer="91"/> +<wire x1="71.12" y1="111.76" x2="71.12" y2="105.41" width="0.1524" layer="91"/> +<pinref part="C9A4" gate="C" pin="1"/> +<pinref part="U$372" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="33.02" y1="105.41" x2="33.02" y2="106.68" width="0.1524" layer="91"/> +<wire x1="33.02" y1="106.68" x2="33.02" y2="111.76" width="0.1524" layer="91"/> +<wire x1="33.02" y1="111.76" x2="39.37" y2="111.76" width="0.1524" layer="91"/> +<wire x1="39.37" y1="106.68" x2="33.02" y2="106.68" width="0.1524" layer="91"/> +<junction x="33.02" y="106.68"/> +<pinref part="U$357" gate="G$1" pin="GND"/> +<pinref part="FB9A2" gate="F" pin="1"/> +<pinref part="FB8A1" gate="F" pin="1"/> +</segment> +</net> +<net name="I2C-SMBCLK" class="0"> +<segment> +<wire x1="129.54" y1="68.58" x2="123.19" y2="68.58" width="0.1524" layer="91"/> +<pinref part="U3G2" gate="U" pin="SCL0"/> +<label x="123.19" y="68.58" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="129.54" y1="25.4" x2="123.19" y2="25.4" width="0.1524" layer="91"/> +<pinref part="U4G1" gate="U" pin="SCL0"/> +<label x="123.19" y="25.4" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MCH-SMBCLK" class="0"> +<segment> +<wire x1="161.29" y1="68.58" x2="199.39" y2="68.58" width="0.1524" layer="91"/> +<wire x1="199.39" y1="68.58" x2="208.28" y2="68.58" width="0.1524" layer="91"/> +<wire x1="199.39" y1="71.12" x2="199.39" y2="68.58" width="0.1524" layer="91"/> +<junction x="199.39" y="68.58"/> +<pinref part="U3G2" gate="U" pin="SCL1"/> +<pinref part="R6T16" gate="R" pin="2"/> +<label x="208.28" y="68.58" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="MCH-SMBDAT" class="0"> +<segment> +<wire x1="193.04" y1="64.77" x2="208.28" y2="64.77" width="0.1524" layer="91"/> +<wire x1="193.04" y1="71.12" x2="193.04" y2="64.77" width="0.1524" layer="91"/> +<wire x1="161.29" y1="64.77" x2="193.04" y2="64.77" width="0.1524" layer="91"/> +<junction x="193.04" y="64.77"/> +<pinref part="R6T15" gate="R" pin="2"/> +<pinref part="U3G2" gate="U" pin="SDA1"/> +<label x="208.28" y="64.77" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="N$549" class="0"> +<segment> +<wire x1="129.54" y1="17.78" x2="113.03" y2="17.78" width="0.1524" layer="91"/> +<wire x1="113.03" y1="17.78" x2="87.63" y2="17.78" width="0.1524" layer="91"/> +<wire x1="78.74" y1="17.78" x2="87.63" y2="17.78" width="0.1524" layer="91"/> +<wire x1="87.63" y1="17.78" x2="87.63" y2="21.59" width="0.1524" layer="91"/> +<junction x="87.63" y="17.78"/> +<pinref part="U4G1" gate="U" pin="EN"/> +<pinref part="R6U2" gate="R" pin="2"/> +<pinref part="R6T22" gate="R" pin="2"/> +</segment> +</net> +<net name="GP23" class="0"> +<segment> +<wire x1="64.77" y1="55.88" x2="48.26" y2="55.88" width="0.1524" layer="91"/> +<pinref part="R7T10" gate="R" pin="1"/> +<label x="48.26" y="55.88" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="GP21" class="0"> +<segment> +<wire x1="68.58" y1="17.78" x2="48.26" y2="17.78" width="0.1524" layer="91"/> +<pinref part="R6T22" gate="R" pin="1"/> +<label x="48.26" y="17.78" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="DDR-SCL" class="0"> +<segment> +<wire x1="161.29" y1="25.4" x2="199.39" y2="25.4" width="0.1524" layer="91"/> +<wire x1="199.39" y1="25.4" x2="208.28" y2="25.4" width="0.1524" layer="91"/> +<wire x1="199.39" y1="27.94" x2="199.39" y2="25.4" width="0.1524" layer="91"/> +<junction x="199.39" y="25.4"/> +<pinref part="U4G1" gate="U" pin="SCL1"/> +<pinref part="R6T14" gate="R" pin="2"/> +<label x="208.28" y="25.4" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="DDR-SDA" class="0"> +<segment> +<wire x1="193.04" y1="21.59" x2="208.28" y2="21.59" width="0.1524" layer="91"/> +<wire x1="193.04" y1="27.94" x2="193.04" y2="21.59" width="0.1524" layer="91"/> +<wire x1="161.29" y1="21.59" x2="193.04" y2="21.59" width="0.1524" layer="91"/> +<junction x="193.04" y="21.59"/> +<pinref part="R6T13" gate="R" pin="2"/> +<pinref part="U4G1" gate="U" pin="SDA1"/> +<label x="208.28" y="21.59" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="N$413" class="0"> +<segment> +<wire x1="227.33" y1="153.67" x2="213.36" y2="153.67" width="0.1524" layer="91"/> +<wire x1="213.36" y1="153.67" x2="213.36" y2="154.94" width="0.1524" layer="91"/> +<wire x1="213.36" y1="154.94" x2="210.82" y2="154.94" width="0.1524" layer="91"/> +<pinref part="L8A2" gate="G$1" pin="S11"/> +<pinref part="J9A1" gate="USB1" pin="2"/> +</segment> +</net> +<net name="N$414" class="0"> +<segment> +<wire x1="210.82" y1="149.86" x2="213.36" y2="149.86" width="0.1524" layer="91"/> +<wire x1="213.36" y1="149.86" x2="213.36" y2="151.13" width="0.1524" layer="91"/> +<wire x1="213.36" y1="151.13" x2="227.33" y2="151.13" width="0.1524" layer="91"/> +<pinref part="L8A2" gate="G$1" pin="S12"/> +<pinref part="J9A1" gate="USB1" pin="3"/> +</segment> +</net> +<net name="USB0-N" class="0"> +<segment> +<wire x1="200.66" y1="154.94" x2="198.12" y2="154.94" width="0.1524" layer="91"/> +<pinref part="L8A2" gate="G$1" pin="P11"/> +<label x="198.12" y="154.94" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="USB0-P" class="0"> +<segment> +<wire x1="200.66" y1="149.86" x2="198.12" y2="149.86" width="0.1524" layer="91"/> +<pinref part="L8A2" gate="G$1" pin="P12"/> +<label x="198.12" y="149.86" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="USB1-N" class="0"> +<segment> +<wire x1="201.93" y1="123.19" x2="199.39" y2="123.19" width="0.1524" layer="91"/> +<pinref part="L8A1" gate="G$1" pin="P11"/> +<label x="199.39" y="123.19" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="USB1-P" class="0"> +<segment> +<wire x1="201.93" y1="118.11" x2="199.39" y2="118.11" width="0.1524" layer="91"/> +<pinref part="L8A1" gate="G$1" pin="P12"/> +<label x="199.39" y="118.11" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$415" class="0"> +<segment> +<wire x1="212.09" y1="118.11" x2="214.63" y2="118.11" width="0.1524" layer="91"/> +<wire x1="214.63" y1="118.11" x2="214.63" y2="119.38" width="0.1524" layer="91"/> +<wire x1="214.63" y1="119.38" x2="227.33" y2="119.38" width="0.1524" layer="91"/> +<pinref part="L8A1" gate="G$1" pin="S12"/> +<pinref part="J9A1" gate="USB2" pin="3"/> +</segment> +</net> +<net name="N$416" class="0"> +<segment> +<wire x1="227.33" y1="121.92" x2="214.63" y2="121.92" width="0.1524" layer="91"/> +<wire x1="214.63" y1="121.92" x2="214.63" y2="123.19" width="0.1524" layer="91"/> +<wire x1="214.63" y1="123.19" x2="212.09" y2="123.19" width="0.1524" layer="91"/> +<pinref part="L8A1" gate="G$1" pin="S11"/> +<pinref part="J9A1" gate="USB2" pin="2"/> +</segment> +</net> +<net name="N$417" class="0"> +<segment> +<wire x1="152.4" y1="119.38" x2="152.4" y2="128.27" width="0.1524" layer="91"/> +<wire x1="152.4" y1="128.27" x2="165.1" y2="128.27" width="0.1524" layer="91"/> +<wire x1="165.1" y1="128.27" x2="172.72" y2="128.27" width="0.1524" layer="91"/> +<wire x1="172.72" y1="128.27" x2="172.72" y2="119.38" width="0.1524" layer="91"/> +<wire x1="165.1" y1="119.38" x2="165.1" y2="128.27" width="0.1524" layer="91"/> +<wire x1="227.33" y1="124.46" x2="218.44" y2="124.46" width="0.1524" layer="91"/> +<wire x1="218.44" y1="124.46" x2="218.44" y2="128.27" width="0.1524" layer="91"/> +<wire x1="218.44" y1="128.27" x2="172.72" y2="128.27" width="0.1524" layer="91"/> +<wire x1="152.4" y1="128.27" x2="142.24" y2="128.27" width="0.1524" layer="91"/> +<junction x="152.4" y="128.27"/> +<junction x="165.1" y="128.27"/> +<junction x="172.72" y="128.27"/> +<pinref part="U9A1" gate="G$1" pin="OUT2"/> +<pinref part="J9A1" gate="USB2" pin="1"/> +<pinref part="R5H1" gate="R" pin="2"/> +<wire x1="142.24" y1="128.27" x2="77.47" y2="128.27" width="0.1524" layer="91"/> +<wire x1="142.24" y1="124.46" x2="142.24" y2="128.27" width="0.1524" layer="91"/> +<junction x="142.24" y="128.27"/> +<pinref part="C9A2" gate="C" pin="2"/> +<pinref part="C1L5" gate="C" pin="2"/> +<pinref part="C1L3" gate="C" pin="2"/> +</segment> +</net> +<net name="N$419" class="0"> +<segment> +<wire x1="152.4" y1="156.21" x2="152.4" y2="167.64" width="0.1524" layer="91"/> +<wire x1="152.4" y1="167.64" x2="165.1" y2="167.64" width="0.1524" layer="91"/> +<wire x1="165.1" y1="167.64" x2="172.72" y2="167.64" width="0.1524" layer="91"/> +<wire x1="172.72" y1="156.21" x2="172.72" y2="167.64" width="0.1524" layer="91"/> +<wire x1="222.25" y1="167.64" x2="172.72" y2="167.64" width="0.1524" layer="91"/> +<wire x1="227.33" y1="156.21" x2="222.25" y2="156.21" width="0.1524" layer="91"/> +<wire x1="222.25" y1="156.21" x2="222.25" y2="167.64" width="0.1524" layer="91"/> +<wire x1="152.4" y1="167.64" x2="142.24" y2="167.64" width="0.1524" layer="91"/> +<wire x1="142.24" y1="167.64" x2="115.57" y2="167.64" width="0.1524" layer="91"/> +<wire x1="115.57" y1="167.64" x2="115.57" y2="130.81" width="0.1524" layer="91"/> +<wire x1="115.57" y1="130.81" x2="77.47" y2="130.81" width="0.1524" layer="91"/> +<junction x="152.4" y="167.64"/> +<junction x="172.72" y="167.64"/> +<pinref part="U9A1" gate="G$1" pin="OUT1"/> +<pinref part="J9A1" gate="USB1" pin="1"/> +<pinref part="C1L1" gate="C" pin="2"/> +<pinref part="C1L7" gate="C" pin="2"/> +<wire x1="165.1" y1="156.21" x2="165.1" y2="167.64" width="0.1524" layer="91"/> +<junction x="165.1" y="167.64"/> +<pinref part="C1L2" gate="C" pin="2"/> +<pinref part="R5H2" gate="R" pin="2"/> +<wire x1="142.24" y1="163.83" x2="142.24" y2="167.64" width="0.1524" layer="91"/> +<junction x="142.24" y="167.64"/> +</segment> +</net> +<net name="USB0-OC-N" class="0"> +<segment> +<wire x1="77.47" y1="133.35" x2="78.74" y2="133.35" width="0.1524" layer="91"/> +<wire x1="78.74" y1="133.35" x2="92.71" y2="133.35" width="0.1524" layer="91"/> +<wire x1="78.74" y1="143.51" x2="78.74" y2="133.35" width="0.1524" layer="91"/> +<junction x="78.74" y="133.35"/> +<pinref part="U9A1" gate="G$1" pin="OC1*"/> +<pinref part="R1L1" gate="R" pin="1"/> +<label x="92.71" y="133.35" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="USB1-OC-N" class="0"> +<segment> +<wire x1="77.47" y1="125.73" x2="88.9" y2="125.73" width="0.1524" layer="91"/> +<wire x1="88.9" y1="125.73" x2="92.71" y2="125.73" width="0.1524" layer="91"/> +<wire x1="88.9" y1="142.24" x2="88.9" y2="125.73" width="0.1524" layer="91"/> +<junction x="88.9" y="125.73"/> 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x1="81.28" y1="111.76" x2="87.63" y2="111.76" width="0.1524" layer="91"/> +<wire x1="87.63" y1="111.76" x2="87.63" y2="105.41" width="0.1524" layer="91"/> +<wire x1="95.25" y1="111.76" x2="88.9" y2="111.76" width="0.1524" layer="91"/> +<wire x1="88.9" y1="111.76" x2="87.63" y2="111.76" width="0.1524" layer="91"/> +<junction x="87.63" y="111.76"/> +<pinref part="C9A4" gate="C" pin="2"/> +<pinref part="U$538" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="C8A1" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="238.76" y1="123.19" x2="250.19" y2="123.19" width="0.1524" layer="91"/> +<wire x1="250.19" y1="123.19" x2="250.19" y2="118.11" width="0.1524" layer="91"/> +<wire x1="238.76" y1="118.11" x2="250.19" y2="118.11" width="0.1524" layer="91"/> +<wire x1="250.19" y1="118.11" x2="250.19" y2="106.68" width="0.1524" layer="91"/> +<wire x1="250.19" y1="106.68" x2="250.19" y2="105.41" width="0.1524" layer="91"/> +<wire x1="227.33" y1="116.84" x2="222.25" y2="116.84" width="0.1524" layer="91"/> +<wire x1="222.25" y1="106.68" x2="222.25" y2="116.84" width="0.1524" layer="91"/> +<wire x1="250.19" y1="106.68" x2="222.25" y2="106.68" width="0.1524" layer="91"/> +<junction x="250.19" y="118.11"/> +<junction x="250.19" y="106.68"/> +<pinref part="J9A1" gate="USB2" pin="5"/> +<pinref part="J9A1" gate="USB2" pin="6"/> +<pinref part="U$316" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="J9A1" gate="USB2" pin="4"/> +</segment> +<segment> +<wire x1="238.76" y1="154.94" x2="250.19" y2="154.94" width="0.1524" layer="91"/> +<wire x1="250.19" y1="154.94" x2="250.19" y2="149.86" width="0.1524" layer="91"/> +<wire x1="238.76" y1="149.86" x2="250.19" y2="149.86" width="0.1524" layer="91"/> +<wire x1="250.19" y1="138.43" x2="250.19" y2="139.7" width="0.1524" layer="91"/> +<wire x1="250.19" y1="139.7" x2="250.19" y2="149.86" width="0.1524" layer="91"/> +<wire x1="222.25" y1="148.59" x2="227.33" y2="148.59" width="0.1524" layer="91"/> +<wire x1="222.25" y1="148.59" x2="222.25" y2="139.7" width="0.1524" layer="91"/> +<wire x1="222.25" y1="139.7" x2="250.19" y2="139.7" width="0.1524" layer="91"/> +<junction x="250.19" y="149.86"/> +<junction x="250.19" y="139.7"/> +<pinref part="J9A1" gate="USB1" pin="5"/> +<pinref part="J9A1" gate="USB1" pin="6"/> +<pinref part="U$259" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="J9A1" gate="USB1" pin="4"/> +</segment> +<segment> +<wire x1="49.53" y1="111.76" x2="57.15" y2="111.76" width="0.1524" layer="91"/> +<wire x1="57.15" y1="111.76" x2="57.15" y2="106.68" width="0.1524" layer="91"/> +<wire x1="57.15" y1="106.68" x2="57.15" y2="105.41" width="0.1524" layer="91"/> +<wire x1="49.53" y1="106.68" x2="57.15" y2="106.68" width="0.1524" layer="91"/> +<junction x="57.15" y="106.68"/> +<pinref part="FB9A2" gate="F" pin="2"/> +<pinref part="U$320" gate="G$1" pin="GND-CHASSIS"/> +<pinref part="FB8A1" gate="F" pin="2"/> +</segment> +</net> +<net name="N$20" class="0"> +<segment> +<wire x1="74.93" y1="55.88" x2="82.55" y2="55.88" width="0.1524" layer="91"/> +<pinref part="Q6T2" gate="Q" pin="B"/> +<pinref part="R7T10" gate="R" pin="2"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<wire x1="46.99" y1="133.35" x2="44.45" y2="133.35" width="0.1524" layer="91"/> +<wire x1="44.45" y1="133.35" x2="44.45" y2="158.75" width="0.1524" layer="91"/> +<wire x1="44.45" y1="158.75" x2="44.45" y2="162.56" width="0.1524" layer="91"/> +<wire x1="36.83" y1="152.4" x2="36.83" y2="158.75" width="0.1524" layer="91"/> +<wire x1="36.83" y1="158.75" x2="44.45" y2="158.75" width="0.1524" layer="91"/> +<wire x1="21.59" y1="151.13" x2="21.59" y2="158.75" width="0.1524" layer="91"/> +<wire x1="21.59" y1="158.75" x2="29.21" y2="158.75" width="0.1524" layer="91"/> +<wire x1="29.21" y1="158.75" x2="29.21" y2="151.13" width="0.1524" layer="91"/> +<wire x1="29.21" y1="158.75" x2="36.83" y2="158.75" width="0.1524" layer="91"/> +<junction x="44.45" y="158.75"/> +<junction x="29.21" y="158.75"/> +<junction x="36.83" y="158.75"/> +<pinref part="U9A1" gate="G$1" pin="IN"/> +<pinref part="C1L4" gate="C" pin="1"/> +<pinref part="P+6" gate="1" pin="VCC"/> +<pinref part="R1L4" gate="R" pin="1"/> +<pinref part="R1L2" gate="R" pin="1"/> +</segment> +</net> +<net name="I2C-SMBDAT" class="0"> +<segment> +<wire x1="129.54" y1="64.77" x2="123.19" y2="64.77" width="0.1524" layer="91"/> +<pinref part="U3G2" gate="U" pin="SDA0"/> +<label x="123.19" y="64.77" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="129.54" y1="21.59" x2="123.19" y2="21.59" width="0.1524" layer="91"/> +<pinref part="U4G1" gate="U" pin="SDA0"/> +<label x="123.19" y="21.59" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$47" class="0"> +<segment> +<pinref part="R5H2" gate="R" pin="1"/> +<pinref part="C9A1" gate="C" pin="2"/> +<wire x1="142.24" y1="148.59" x2="142.24" y2="153.67" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$63" class="0"> +<segment> +<pinref part="C1N5" gate="C" pin="2"/> +<pinref part="R5H1" gate="R" pin="1"/> +<wire x1="142.24" y1="114.3" x2="142.24" y2="109.22" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="113.03" y="170.18" size="3.81" layer="94">Clock Generation</text> +</plain> +<instances> +<instance part="FRAME26" gate="G$1" x="0" y="0"/> +<instance part="FRAME26" gate="G$2" x="180.34" y="0"/> +<instance part="U3H1" gate="G$1" x="137.16" y="105.41"/> +<instance part="Y2G1" gate="G$1" x="87.63" y="77.47" smashed="yes"> +<attribute name="NAME" x="85.09" y="80.01" size="1.778" layer="95"/> +<attribute name="VALUE" x="80.01" y="72.39" size="1.778" layer="96"/> +</instance> +<instance part="U$495" gate="G$1" x="60.96" y="68.58"/> +<instance part="U$496" gate="G$1" x="113.03" y="55.88"/> +<instance part="U$497" gate="G$1" x="76.2" y="52.07"/> +<instance part="U$498" gate="G$1" x="96.52" y="99.06"/> +<instance part="U$499" gate="G$1" x="24.13" y="119.38" rot="R270"/> +<instance part="U$500" gate="G$1" x="59.69" y="144.78" rot="R270"/> +<instance part="U$503" gate="PW-VCC3" x="60.96" y="114.3"/> +<instance part="U$506" gate="PW-VCC3" x="8.89" y="167.64"/> +<instance part="U$507" gate="G$1" x="67.31" y="91.44" rot="R270"/> +<instance part="U$508" gate="G$1" x="59.69" y="133.35" rot="R270"/> +<instance part="U$509" gate="G$1" x="24.13" y="143.51" rot="R270"/> +<instance part="FB3G4" gate="F" x="20.32" y="163.83" smashed="yes"> +<attribute name="NAME" x="21.4366" y="167.0706" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="22.224" y="165.3464" size="1.778" layer="96"/> +</instance> +<instance part="FB3G3" gate="F" x="90.17" y="133.35" rot="R180"/> +<instance part="U$510" gate="PW-VCC3" x="101.6" y="135.89"/> +<instance part="R3G36" gate="R" x="176.53" y="76.2"> +<attribute name="POWER" x="176.53" y="76.2" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3G34" gate="R" x="176.53" y="69.85"> +<attribute name="POWER" x="176.53" y="69.85" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2G14" gate="R" x="193.04" y="66.04"> +<attribute name="POWER" x="193.04" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="193.04" y="66.04" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2G15" gate="R" x="193.04" y="72.39"> +<attribute name="POWER" x="193.04" y="72.39" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="193.04" y="72.39" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$293" gate="G$1" x="203.2" y="66.04" rot="R90"/> +<instance part="R3H8" gate="R" x="209.55" y="142.24"> +<attribute name="POWER" x="209.55" y="142.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7V4" gate="C" x="227.33" y="138.43" smashed="yes" rot="R270"> +<attribute name="NAME" x="227.457" y="136.398" size="1.778" layer="95"/> +<attribute name="VALUE" x="224.79" y="138.176" size="1.778" layer="96" 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y="153.67" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C3G7" gate="C" x="50.8" y="153.67" smashed="yes" rot="R180"> +<attribute name="NAME" x="51.689" y="156.464" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="51.816" y="154.051" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="50.8" y="153.67" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="50.8" y="153.67" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="50.8" y="153.67" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C3G6" gate="C" x="50.8" y="129.54" smashed="yes" rot="R180"> +<attribute name="NAME" x="51.435" y="132.08" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="51.435" y="129.54" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="50.8" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="50.8" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="50.8" y="129.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C3G8" gate="C" x="43.18" y="129.54" smashed="yes" rot="R180"> +<attribute name="NAME" x="43.815" y="132.08" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="43.815" y="129.54" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="43.18" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="43.18" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="43.18" y="129.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C3H1" gate="C" x="35.56" y="129.54" smashed="yes" rot="R180"> +<attribute name="NAME" x="36.195" y="132.08" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="36.195" y="129.54" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="35.56" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="35.56" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="35.56" y="129.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C3G9" gate="C" x="27.94" y="129.54" smashed="yes" rot="R180"> +<attribute name="NAME" x="28.575" y="132.08" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="28.575" y="129.54" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="27.94" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="27.94" y="129.54" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="27.94" y="129.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C3G4" gate="C" x="27.94" y="153.67" smashed="yes" rot="R180"> +<attribute name="NAME" x="28.829" y="156.464" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="28.956" y="154.051" size="1.778" layer="96" rot="R270"/> +<attribute name="VOLTAGE" x="27.94" y="153.67" size="1.778" layer="96" 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display="off"/> +</instance> +<instance part="R3G28" gate="R" x="78.74" y="91.44"> +<attribute name="POWER" x="78.74" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="78.74" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R7U6" gate="R" x="105.41" y="102.87" rot="R180"> +<attribute name="POWER" x="105.41" y="102.87" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="105.41" y="102.87" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2G3" gate="C" x="76.2" y="66.04" rot="R180"> +<attribute name="VOLTAGE" x="76.2" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="76.2" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="76.2" y="66.04" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2G2" gate="C" x="100.33" y="66.04" rot="R180"> +<attribute name="VOLTAGE" x="100.33" y="66.04" size="1.778" layer="96" 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display="off"/> +</instance> +<instance part="R3H1" gate="R" x="172.72" y="53.34" rot="MR270"> +<attribute name="POWER" x="172.72" y="53.34" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3G35" gate="R" x="179.07" y="53.34" smashed="yes" rot="MR270"> +<attribute name="POWER" x="179.07" y="53.34" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="181.61" y="55.88" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="181.61" y="50.8" size="1.778" layer="96"/> +</instance> +<instance part="C7V1" gate="C" x="172.72" y="30.48" rot="R180"> +<attribute name="DNP" x="172.72" y="30.48" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="172.72" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="172.72" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="172.72" y="30.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7U6" gate="C" x="179.07" y="30.48" rot="R180"> +<attribute name="DNP" x="184.15" y="30.48" size="1.778" layer="96" rot="R90"/> +<attribute name="VOLTAGE" x="179.07" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="179.07" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="179.07" y="30.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$487" gate="G$1" x="172.72" y="16.51"/> +<instance part="R3G13" gate="R" x="176.53" y="99.06"> +<attribute name="POWER" x="176.53" y="99.06" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3G11" gate="R" x="176.53" y="91.44"> +<attribute name="POWER" x="176.53" y="91.44" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3G12" gate="R" x="193.04" y="87.63"> +<attribute name="POWER" x="193.04" y="87.63" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="193.04" y="87.63" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3G14" gate="R" x="193.04" y="95.25"> +<attribute name="POWER" x="193.04" y="95.25" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="193.04" y="95.25" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$577" gate="G$1" x="203.2" y="95.25" rot="R90"/> +<instance part="U$578" gate="G$1" x="203.2" y="87.63" rot="R90"/> +<instance part="R3H4" gate="R" x="209.55" y="123.19"> +<attribute name="POWER" x="209.55" y="123.19" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C7V2" gate="C" x="227.33" y="119.38" smashed="yes" rot="R270"> +<attribute name="NAME" x="227.203" y="117.348" size="1.778" layer="95"/> +<attribute name="VALUE" x="224.79" y="118.872" size="1.778" layer="96" rot="R180"/> +<attribute name="DNP" x="227.33" y="119.38" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="227.33" y="119.38" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="227.33" y="119.38" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="227.33" y="119.38" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$525" gate="G$1" x="248.92" y="119.38" rot="R90"/> +<instance part="TP2" gate="TP" x="205.74" y="129.54" smashed="yes" rot="R270"> +<attribute name="NAME" x="204.216" y="131.318" size="1.778" layer="95"/> +<attribute name="DNP" x="205.74" y="129.54" size="1.778" layer="96"/> +</instance> +<instance part="R3H10" gate="R" x="209.55" y="152.4"> +<attribute name="POWER" x="209.55" y="152.4" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C8V6" gate="C" x="237.49" y="148.59" smashed="yes" rot="R270"> +<attribute name="NAME" x="237.617" y="146.558" size="1.778" layer="95"/> +<attribute name="VALUE" x="233.68" y="148.336" size="1.778" layer="96" rot="R180"/> +<attribute name="DNP" x="237.49" y="148.59" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="237.49" y="148.59" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="237.49" y="148.59" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="237.49" y="148.59" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$338" gate="G$1" x="248.92" y="148.59" rot="R90"/> +<instance part="R3H5" gate="R" x="209.55" y="162.56"> +<attribute name="POWER" x="209.55" y="162.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C8V4" gate="C" x="227.33" y="158.75" smashed="yes" rot="R270"> +<attribute name="NAME" x="227.457" y="156.718" size="1.778" layer="95"/> +<attribute name="VALUE" x="224.79" y="158.496" size="1.778" layer="96" rot="R180"/> +<attribute name="DNP" x="227.33" y="158.75" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="227.33" y="158.75" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="227.33" y="158.75" size="1.778" layer="96" display="off"/> +<attribute name="TYPE" x="227.33" y="158.75" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$30" gate="G$1" x="248.92" y="158.75" rot="R90"/> +<instance part="U$620" gate="G$1" x="203.2" y="72.39" rot="R90"/> +<instance part="R3G26" gate="R" x="176.53" y="114.3"> +<attribute name="POWER" x="176.53" y="114.3" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3G23" gate="R" x="176.53" y="106.68"> +<attribute name="POWER" x="176.53" y="106.68" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3G24" gate="R" x="193.04" y="102.87"> +<attribute name="POWER" x="193.04" y="102.87" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="193.04" y="102.87" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3G27" gate="R" x="193.04" y="110.49"> +<attribute name="POWER" x="193.04" y="110.49" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="193.04" y="110.49" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$317" gate="G$1" x="203.2" y="110.49" rot="R90"/> +<instance part="U$568" gate="G$1" x="203.2" y="102.87" rot="R90"/> +</instances> +<busses> +</busses> +<nets> +<net name="N$552" class="0"> +<segment> +<wire x1="160.02" y1="144.78" x2="165.1" y2="144.78" width="0.1524" layer="91"/> +<wire x1="146.05" y1="163.83" x2="165.1" y2="163.83" width="0.1524" layer="91"/> +<wire x1="165.1" y1="163.83" x2="165.1" y2="144.78" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="PCIF-0/ITP-EN"/> +<pinref part="R7U11" gate="R" pin="2"/> +</segment> +</net> +<net name="N$553" class="0"> +<segment> +<wire x1="87.63" y1="144.78" x2="83.82" y2="144.78" width="0.1524" layer="91"/> +<wire x1="83.82" y1="144.78" x2="83.82" y2="139.7" width="0.1524" layer="91"/> +<wire x1="83.82" y1="139.7" x2="77.47" y2="139.7" width="0.1524" layer="91"/> +<wire x1="77.47" y1="144.78" x2="83.82" y2="144.78" width="0.1524" layer="91"/> +<wire x1="116.84" y1="139.7" x2="83.82" y2="139.7" width="0.1524" layer="91"/> +<wire x1="80.01" y1="139.7" x2="83.82" y2="139.7" width="0.1524" layer="91"/> +<junction x="83.82" y="144.78"/> +<junction x="83.82" y="139.7"/> +<pinref part="U3H1" gate="G$1" pin="VDD-48"/> +<pinref part="C3H3" gate="C" pin="1"/> +<pinref part="C3H4" gate="C" pin="1"/> +<pinref part="R3H11" gate="R" pin="2"/> +</segment> +</net> +<net name="N$554" class="0"> +<segment> +<wire x1="116.84" y1="137.16" x2="111.76" y2="137.16" width="0.1524" layer="91"/> +<wire x1="111.76" y1="137.16" x2="111.76" y2="128.27" width="0.1524" layer="91"/> +<wire x1="77.47" y1="128.27" x2="83.82" y2="128.27" width="0.1524" layer="91"/> +<wire x1="83.82" y1="128.27" x2="83.82" y2="133.35" width="0.1524" layer="91"/> +<wire x1="85.09" y1="133.35" x2="83.82" y2="133.35" width="0.1524" layer="91"/> +<wire x1="83.82" y1="133.35" x2="77.47" y2="133.35" width="0.1524" layer="91"/> +<wire x1="111.76" y1="128.27" x2="83.82" y2="128.27" width="0.1524" layer="91"/> +<junction x="83.82" y="133.35"/> +<junction x="83.82" y="128.27"/> +<pinref part="U3H1" gate="G$1" pin="VDD-A"/> +<pinref part="C3G2" gate="C" pin="1"/> +<pinref part="FB3G3" gate="F" pin="2"/> +<pinref part="C3G3" gate="C" pin="1"/> +</segment> +</net> +<net name="N$555" class="0"> +<segment> +<wire x1="116.84" y1="102.87" x2="110.49" y2="102.87" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="IREF"/> +<pinref part="R7U6" gate="R" pin="1"/> +</segment> +</net> +<net name="N$556" class="0"> +<segment> +<wire x1="91.44" y1="104.14" x2="82.55" y2="104.14" width="0.1524" layer="91"/> +<wire x1="116.84" y1="93.98" x2="91.44" y2="93.98" width="0.1524" layer="91"/> +<wire x1="91.44" y1="93.98" x2="91.44" y2="104.14" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="FS-A"/> +<pinref part="R7U2" gate="R" pin="2"/> +</segment> +</net> +<net name="N$557" class="0"> +<segment> +<wire x1="83.82" y1="91.44" x2="116.84" y2="91.44" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="FS-B/TEST-MODE"/> +<pinref part="R3G28" gate="R" pin="2"/> +</segment> +</net> +<net name="N$558" class="0"> +<segment> +<wire x1="76.2" y1="71.12" x2="76.2" y2="77.47" width="0.1524" layer="91"/> +<wire x1="76.2" y1="77.47" x2="76.2" y2="85.09" width="0.1524" layer="91"/> +<wire x1="76.2" y1="85.09" x2="116.84" y2="85.09" width="0.1524" layer="91"/> +<wire x1="85.09" y1="77.47" x2="76.2" y2="77.47" width="0.1524" layer="91"/> +<junction x="76.2" y="77.47"/> +<pinref part="U3H1" gate="G$1" pin="XTAL-IN"/> +<pinref part="Y2G1" gate="G$1" pin="1"/> +<pinref part="C2G3" gate="C" pin="1"/> +</segment> +</net> +<net name="N$559" class="0"> +<segment> +<wire x1="116.84" y1="82.55" x2="100.33" y2="82.55" width="0.1524" layer="91"/> +<wire x1="100.33" y1="82.55" x2="100.33" y2="77.47" width="0.1524" layer="91"/> +<wire x1="100.33" y1="77.47" x2="100.33" y2="71.12" width="0.1524" layer="91"/> +<wire x1="100.33" y1="77.47" x2="90.17" y2="77.47" width="0.1524" layer="91"/> +<junction x="100.33" y="77.47"/> +<pinref part="U3H1" gate="G$1" pin="XTAL-OUT"/> +<pinref part="Y2G1" gate="G$1" pin="2"/> +<pinref part="C2G2" gate="C" pin="1"/> +</segment> +</net> +<net name="N$560" class="0"> +<segment> +<wire x1="116.84" y1="88.9" x2="60.96" y2="88.9" width="0.1524" layer="91"/> +<wire x1="60.96" y1="88.9" x2="60.96" y2="83.82" width="0.1524" layer="91"/> +<wire x1="60.96" y1="91.44" x2="60.96" y2="88.9" width="0.1524" layer="91"/> +<junction x="60.96" y="88.9"/> +<pinref part="U3H1" gate="G$1" pin="FS-C/TEST-SEL"/> +<pinref part="R3H9" gate="R" pin="1"/> +<pinref part="R7V1" gate="R" pin="1"/> +</segment> +</net> +<net name="GND" class="0"> +<segment> +<wire x1="116.84" y1="78.74" x2="113.03" y2="78.74" width="0.1524" layer="91"/> +<wire x1="113.03" y1="78.74" x2="113.03" y2="76.2" width="0.1524" layer="91"/> +<wire x1="113.03" y1="76.2" x2="113.03" y2="73.66" width="0.1524" layer="91"/> +<wire x1="113.03" y1="73.66" x2="113.03" y2="71.12" width="0.1524" layer="91"/> +<wire x1="113.03" y1="71.12" x2="113.03" y2="67.31" width="0.1524" layer="91"/> +<wire x1="113.03" y1="67.31" x2="113.03" y2="64.77" width="0.1524" layer="91"/> +<wire x1="113.03" y1="64.77" x2="113.03" y2="60.96" width="0.1524" layer="91"/> +<wire x1="113.03" y1="60.96" x2="113.03" y2="57.15" width="0.1524" layer="91"/> +<wire x1="113.03" y1="60.96" x2="116.84" y2="60.96" width="0.1524" layer="91"/> +<wire x1="113.03" y1="64.77" x2="116.84" y2="64.77" width="0.1524" layer="91"/> +<wire x1="116.84" y1="67.31" x2="113.03" y2="67.31" width="0.1524" layer="91"/> +<wire x1="116.84" y1="71.12" x2="113.03" y2="71.12" width="0.1524" layer="91"/> +<wire x1="116.84" y1="73.66" x2="113.03" y2="73.66" width="0.1524" layer="91"/> +<wire x1="116.84" y1="76.2" x2="113.03" y2="76.2" width="0.1524" layer="91"/> +<junction x="113.03" y="76.2"/> +<junction x="113.03" y="73.66"/> +<junction x="113.03" y="71.12"/> +<junction x="113.03" y="67.31"/> +<junction x="113.03" y="64.77"/> +<junction x="113.03" y="60.96"/> +<pinref part="U3H1" gate="G$1" pin="VSS-A"/> +<pinref part="U3H1" gate="G$1" pin="VSS-SRC"/> +<pinref part="U3H1" gate="G$1" pin="VSS-PCI2"/> +<pinref part="U3H1" gate="G$1" pin="VSS-PCI1"/> +<pinref part="U3H1" gate="G$1" pin="VSS-48"/> +<pinref part="U3H1" gate="G$1" pin="VSS-REF"/> +<pinref part="U3H1" gate="G$1" pin="VSS-CPU"/> +<pinref part="U$496" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="76.2" y1="63.5" x2="76.2" y2="54.61" width="0.1524" layer="91"/> +<wire x1="76.2" y1="54.61" x2="76.2" y2="53.34" width="0.1524" layer="91"/> +<wire x1="76.2" y1="54.61" x2="100.33" y2="54.61" width="0.1524" layer="91"/> +<wire x1="100.33" y1="54.61" x2="100.33" y2="63.5" width="0.1524" layer="91"/> +<junction x="76.2" y="54.61"/> +<pinref part="U$497" gate="G$1" pin="GND"/> +<pinref part="C2G3" gate="C" pin="2"/> +<pinref part="C2G2" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="96.52" y1="102.87" x2="96.52" y2="100.33" width="0.1524" layer="91"/> +<wire x1="96.52" y1="102.87" x2="100.33" y2="102.87" width="0.1524" layer="91"/> +<pinref part="U$498" gate="G$1" pin="GND"/> +<pinref part="R7U6" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="27.94" y1="127" x2="27.94" y2="119.38" width="0.1524" layer="91"/> +<wire x1="27.94" y1="119.38" x2="35.56" y2="119.38" width="0.1524" layer="91"/> +<wire x1="35.56" y1="119.38" x2="43.18" y2="119.38" width="0.1524" layer="91"/> +<wire x1="43.18" y1="119.38" x2="50.8" y2="119.38" width="0.1524" layer="91"/> +<wire x1="50.8" y1="119.38" x2="50.8" y2="127" width="0.1524" layer="91"/> +<wire x1="43.18" y1="127" x2="43.18" y2="119.38" width="0.1524" layer="91"/> +<wire x1="35.56" y1="127" x2="35.56" y2="119.38" width="0.1524" layer="91"/> +<wire x1="27.94" y1="119.38" x2="25.4" y2="119.38" width="0.1524" layer="91"/> +<junction x="27.94" y="119.38"/> +<junction x="35.56" y="119.38"/> +<junction x="43.18" y="119.38"/> +<pinref part="U$499" gate="G$1" pin="GND"/> +<pinref part="C3G6" gate="C" pin="2"/> +<pinref part="C3G8" gate="C" pin="2"/> +<pinref part="C3H1" gate="C" pin="2"/> +<pinref part="C3G9" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="69.85" y1="144.78" x2="62.23" y2="144.78" width="0.1524" layer="91"/> +<wire x1="62.23" y1="144.78" x2="62.23" y2="139.7" width="0.1524" layer="91"/> +<wire x1="62.23" y1="139.7" x2="69.85" y2="139.7" width="0.1524" layer="91"/> +<wire x1="62.23" y1="144.78" x2="60.96" y2="144.78" width="0.1524" layer="91"/> +<junction x="62.23" y="144.78"/> +<pinref part="U$500" gate="G$1" pin="GND"/> +<pinref part="C3H3" gate="C" pin="2"/> +<pinref part="C3H4" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="60.96" y1="73.66" x2="60.96" y2="69.85" width="0.1524" layer="91"/> +<pinref part="U$495" gate="G$1" pin="GND"/> +<pinref part="R3H9" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="73.66" y1="91.44" x2="68.58" y2="91.44" width="0.1524" layer="91"/> +<pinref part="U$507" gate="G$1" pin="GND"/> +<pinref part="R3G28" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="69.85" y1="128.27" x2="62.23" y2="128.27" width="0.1524" layer="91"/> +<wire x1="62.23" y1="128.27" x2="62.23" y2="133.35" width="0.1524" layer="91"/> +<wire x1="62.23" y1="133.35" x2="69.85" y2="133.35" width="0.1524" layer="91"/> +<wire x1="62.23" y1="133.35" x2="60.96" y2="133.35" width="0.1524" layer="91"/> +<junction x="62.23" y="133.35"/> +<pinref part="U$508" gate="G$1" pin="GND"/> +<pinref part="C3G3" gate="C" pin="2"/> +<pinref part="C3G2" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="25.4" y1="143.51" x2="27.94" y2="143.51" width="0.1524" layer="91"/> +<wire x1="27.94" y1="143.51" x2="35.56" y2="143.51" width="0.1524" layer="91"/> +<wire x1="35.56" y1="143.51" x2="43.18" y2="143.51" width="0.1524" layer="91"/> +<wire x1="43.18" y1="143.51" x2="50.8" y2="143.51" width="0.1524" layer="91"/> +<wire x1="50.8" y1="143.51" x2="50.8" y2="151.13" width="0.1524" layer="91"/> +<wire x1="35.56" y1="151.13" x2="35.56" y2="143.51" width="0.1524" layer="91"/> +<wire x1="43.18" y1="151.13" x2="43.18" y2="143.51" width="0.1524" layer="91"/> +<wire x1="27.94" y1="151.13" x2="27.94" y2="143.51" width="0.1524" layer="91"/> +<junction x="35.56" y="143.51"/> +<junction x="43.18" y="143.51"/> +<junction x="27.94" y="143.51"/> +<pinref part="U$509" gate="G$1" pin="GND"/> +<pinref part="C3H2" gate="C" pin="2"/> +<pinref part="C3G5" gate="C" pin="2"/> +<pinref part="C3G7" gate="C" pin="2"/> +<pinref part="C3G4" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="229.87" y1="138.43" x2="247.65" y2="138.43" width="0.1524" layer="91"/> +<pinref part="C7V4" gate="C" pin="2"/> +<pinref part="U$565" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="172.72" y1="27.94" x2="172.72" y2="19.05" width="0.1524" layer="91"/> +<wire x1="172.72" y1="19.05" x2="179.07" y2="19.05" width="0.1524" layer="91"/> +<wire x1="179.07" y1="19.05" x2="179.07" y2="27.94" width="0.1524" layer="91"/> +<wire x1="172.72" y1="19.05" x2="172.72" y2="17.78" width="0.1524" layer="91"/> +<wire x1="163.83" y1="27.94" x2="163.83" y2="19.05" width="0.1524" layer="91"/> +<wire x1="172.72" y1="19.05" x2="163.83" y2="19.05" width="0.1524" layer="91"/> +<junction x="172.72" y="19.05"/> +<pinref part="C7V1" gate="C" pin="2"/> +<pinref part="C7U6" gate="C" pin="2"/> +<pinref part="U$487" gate="G$1" pin="GND"/> +<pinref part="C8V2" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="247.65" y1="119.38" x2="229.87" y2="119.38" width="0.1524" layer="91"/> +<pinref part="U$525" gate="G$1" pin="GND"/> +<pinref part="C7V2" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="229.87" y1="158.75" x2="247.65" y2="158.75" width="0.1524" layer="91"/> +<pinref part="C8V4" gate="C" pin="2"/> +<pinref part="U$30" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="201.93" y1="72.39" x2="198.12" y2="72.39" width="0.1524" layer="91"/> +<pinref part="R2G15" gate="R" pin="2"/> +<pinref part="U$620" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="201.93" y1="66.04" x2="198.12" y2="66.04" width="0.1524" layer="91"/> +<pinref part="R2G14" gate="R" pin="2"/> +<pinref part="U$293" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="198.12" y1="87.63" x2="201.93" y2="87.63" width="0.1524" layer="91"/> +<pinref part="R3G12" gate="R" pin="2"/> +<pinref part="U$578" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="201.93" y1="95.25" x2="198.12" y2="95.25" width="0.1524" layer="91"/> +<pinref part="U$577" gate="G$1" pin="GND"/> +<pinref part="R3G14" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="198.12" y1="102.87" x2="201.93" y2="102.87" width="0.1524" layer="91"/> +<pinref part="R3G24" gate="R" pin="2"/> +<pinref part="U$568" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="201.93" y1="110.49" x2="198.12" y2="110.49" width="0.1524" layer="91"/> +<pinref part="U$317" gate="G$1" pin="GND"/> +<pinref part="R3G27" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="240.03" y1="148.59" x2="247.65" y2="148.59" width="0.1524" layer="91"/> +<pinref part="C8V6" gate="C" pin="2"/> +<pinref part="U$338" gate="G$1" pin="GND"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="60.96" y1="101.6" x2="60.96" y2="104.14" width="0.1524" layer="91"/> +<wire x1="60.96" y1="104.14" x2="60.96" y2="111.76" width="0.1524" layer="91"/> +<wire x1="60.96" y1="104.14" x2="72.39" y2="104.14" width="0.1524" layer="91"/> +<junction x="60.96" y="104.14"/> +<pinref part="U$503" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R7V1" gate="R" pin="2"/> +<pinref part="R7U2" gate="R" pin="1"/> +</segment> +<segment> +<wire x1="15.24" y1="163.83" x2="8.89" y2="163.83" width="0.1524" layer="91"/> +<wire x1="8.89" y1="163.83" x2="8.89" y2="165.1" width="0.1524" layer="91"/> +<pinref part="FB3G4" gate="F" pin="1"/> +<pinref part="U$506" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="101.6" y1="133.35" x2="95.25" y2="133.35" width="0.1524" layer="91"/> +<pinref part="U$510" gate="PW-VCC3" pin="VCC3"/> +<pinref part="FB3G3" gate="F" pin="1"/> +</segment> +</net> +<net name="VCC3-CLK" class="0"> +<segment> +<wire x1="27.94" y1="163.83" x2="27.94" y2="158.75" width="0.1524" layer="91"/> +<wire x1="27.94" y1="163.83" x2="25.4" y2="163.83" width="0.1524" layer="91"/> +<wire x1="35.56" y1="163.83" x2="27.94" y2="163.83" width="0.1524" layer="91"/> +<wire x1="35.56" y1="158.75" x2="35.56" y2="163.83" width="0.1524" layer="91"/> +<wire x1="43.18" y1="163.83" x2="35.56" y2="163.83" width="0.1524" layer="91"/> +<wire x1="43.18" y1="158.75" x2="43.18" y2="163.83" width="0.1524" layer="91"/> +<wire x1="50.8" y1="158.75" x2="50.8" y2="163.83" width="0.1524" layer="91"/> +<wire x1="50.8" y1="163.83" x2="43.18" y2="163.83" width="0.1524" layer="91"/> +<wire x1="54.61" y1="163.83" x2="50.8" y2="163.83" width="0.1524" layer="91"/> +<wire x1="135.89" y1="163.83" x2="114.3" y2="163.83" width="0.1524" layer="91"/> +<wire x1="116.84" y1="142.24" x2="114.3" y2="142.24" width="0.1524" layer="91"/> +<wire x1="114.3" y1="142.24" x2="114.3" y2="144.78" width="0.1524" layer="91"/> +<wire x1="116.84" y1="144.78" x2="114.3" y2="144.78" width="0.1524" layer="91"/> +<wire x1="97.79" y1="144.78" x2="114.3" y2="144.78" width="0.1524" layer="91"/> +<wire x1="114.3" y1="144.78" x2="114.3" y2="163.83" width="0.1524" layer="91"/> +<wire x1="114.3" y1="163.83" x2="54.61" y2="163.83" width="0.1524" layer="91"/> +<wire x1="27.94" y1="140.97" x2="27.94" y2="134.62" width="0.1524" layer="91"/> +<wire x1="35.56" y1="140.97" x2="35.56" y2="134.62" width="0.1524" layer="91"/> +<wire x1="35.56" y1="140.97" x2="27.94" y2="140.97" width="0.1524" layer="91"/> +<wire x1="43.18" y1="140.97" x2="43.18" y2="134.62" width="0.1524" layer="91"/> +<wire x1="43.18" y1="140.97" x2="35.56" y2="140.97" width="0.1524" layer="91"/> +<wire x1="50.8" y1="140.97" x2="50.8" y2="134.62" width="0.1524" layer="91"/> +<wire x1="50.8" y1="140.97" x2="43.18" y2="140.97" width="0.1524" layer="91"/> +<wire x1="54.61" y1="140.97" x2="50.8" y2="140.97" width="0.1524" layer="91"/> +<wire x1="54.61" y1="140.97" x2="54.61" y2="163.83" width="0.1524" layer="91"/> +<wire x1="54.61" y1="121.92" x2="54.61" y2="140.97" width="0.1524" layer="91"/> +<wire x1="116.84" y1="121.92" x2="114.3" y2="121.92" width="0.1524" layer="91"/> +<wire x1="114.3" y1="121.92" x2="54.61" y2="121.92" width="0.1524" layer="91"/> +<wire x1="116.84" y1="133.35" x2="114.3" y2="133.35" width="0.1524" layer="91"/> +<wire x1="114.3" y1="133.35" x2="114.3" y2="130.81" width="0.1524" layer="91"/> +<wire x1="116.84" y1="130.81" x2="114.3" y2="130.81" width="0.1524" layer="91"/> +<wire x1="114.3" y1="130.81" x2="114.3" y2="127" width="0.1524" layer="91"/> +<wire x1="116.84" y1="127" x2="114.3" y2="127" width="0.1524" layer="91"/> +<wire x1="114.3" y1="127" x2="114.3" y2="124.46" width="0.1524" layer="91"/> +<wire x1="114.3" y1="124.46" x2="114.3" y2="121.92" width="0.1524" layer="91"/> +<wire x1="116.84" y1="124.46" x2="114.3" y2="124.46" width="0.1524" layer="91"/> +<junction x="27.94" y="163.83"/> +<junction x="35.56" y="163.83"/> +<junction x="43.18" y="163.83"/> +<junction x="50.8" y="163.83"/> +<junction x="114.3" y="144.78"/> +<junction x="114.3" y="163.83"/> +<junction x="54.61" y="163.83"/> +<junction x="35.56" y="140.97"/> +<junction x="43.18" y="140.97"/> +<junction x="50.8" y="140.97"/> +<junction x="54.61" y="140.97"/> +<junction x="114.3" y="121.92"/> +<junction x="114.3" y="130.81"/> +<junction x="114.3" y="127"/> +<junction x="114.3" y="124.46"/> +<label x="58.7375" y="164.1475" size="1.778" layer="92"/> +<pinref part="FB3G4" gate="F" pin="2"/> +<pinref part="C3G4" gate="C" pin="1"/> +<pinref part="C3H2" gate="C" pin="1"/> +<pinref part="C3G5" gate="C" pin="1"/> +<pinref part="C3G7" gate="C" pin="1"/> +<pinref part="R7U11" gate="R" pin="1"/> +<pinref part="U3H1" gate="G$1" pin="VDD-REF"/> +<pinref part="U3H1" gate="G$1" pin="VDD-CPU"/> +<pinref part="R3H11" gate="R" pin="1"/> +<pinref part="C3G9" gate="C" pin="1"/> +<pinref part="C3H1" gate="C" pin="1"/> +<pinref part="C3G8" gate="C" pin="1"/> +<pinref part="C3G6" gate="C" pin="1"/> +<pinref part="U3H1" gate="G$1" pin="VDD-SRC3"/> +<pinref part="U3H1" gate="G$1" pin="VDD-PCI1"/> +<pinref part="U3H1" gate="G$1" pin="VDD-PCI2"/> +<pinref part="U3H1" gate="G$1" pin="VDD-SRC1"/> +<pinref part="U3H1" gate="G$1" pin="VDD-SRC2"/> +</segment> +</net> +<net name="CK410-PWR-GD-N" class="0"> +<segment> +<wire x1="116.84" y1="110.49" x2="109.22" y2="110.49" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="VTT-PWRGD-N/PD"/> +<label x="109.22" y="110.49" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MCH-SMBDAT" class="0"> +<segment> +<wire x1="116.84" y1="114.3" x2="104.14" y2="114.3" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="SCA"/> +<label x="104.14" y="114.3" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MCH-SMBCLK" class="0"> +<segment> +<wire x1="116.84" y1="118.11" x2="104.14" y2="118.11" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="SCL"/> +<label x="104.14" y="118.11" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="TOL-CORE-100MHZ-P" class="0"> +<segment> +<wire x1="160.02" y1="72.39" x2="163.83" y2="72.39" width="0.1524" layer="91"/> +<wire x1="163.83" y1="72.39" x2="163.83" y2="76.2" width="0.1524" layer="91"/> +<wire x1="163.83" y1="76.2" x2="171.45" y2="76.2" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="CPU-0P"/> +<pinref part="R3G36" gate="R" pin="1"/> +</segment> +</net> +<net name="TOL-CORE-100MHZ-N" class="0"> +<segment> +<wire x1="160.02" y1="69.85" x2="171.45" y2="69.85" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="CPU-0N"/> +<pinref part="R3G34" gate="R" pin="1"/> +</segment> +</net> +<net name="TOL-CORE-100MHZ-P-R" class="0"> +<segment> +<wire x1="181.61" y1="76.2" x2="184.15" y2="76.2" width="0.1524" layer="91"/> +<wire x1="184.15" y1="76.2" x2="208.28" y2="76.2" width="0.1524" layer="91"/> +<wire x1="184.15" y1="72.39" x2="184.15" y2="76.2" width="0.1524" layer="91"/> +<wire x1="187.96" y1="72.39" x2="184.15" y2="72.39" width="0.1524" layer="91"/> +<junction x="184.15" y="76.2"/> +<pinref part="R3G36" gate="R" pin="2"/> +<pinref part="R2G15" gate="R" pin="1"/> +<label x="208.28" y="76.2" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="TOL-CORE-100MHZ-N-R" class="0"> +<segment> +<wire x1="181.61" y1="69.85" x2="184.15" y2="69.85" width="0.1524" layer="91"/> +<wire x1="184.15" y1="69.85" x2="208.28" y2="69.85" width="0.1524" layer="91"/> +<wire x1="184.15" y1="66.04" x2="184.15" y2="69.85" width="0.1524" layer="91"/> +<wire x1="187.96" y1="66.04" x2="184.15" y2="66.04" width="0.1524" layer="91"/> +<junction x="184.15" y="69.85"/> +<pinref part="R3G34" gate="R" pin="2"/> +<pinref part="R2G14" gate="R" pin="1"/> +<label x="208.28" y="69.85" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="ICH-33MHZ-CLK-R" class="0"> +<segment> +<wire x1="214.63" y1="142.24" x2="218.44" y2="142.24" width="0.1524" layer="91"/> +<wire x1="218.44" y1="142.24" x2="224.79" y2="142.24" width="0.1524" layer="91"/> +<wire x1="222.25" y1="138.43" x2="218.44" y2="138.43" width="0.1524" layer="91"/> +<wire x1="218.44" y1="138.43" x2="218.44" y2="142.24" width="0.1524" layer="91"/> +<junction x="218.44" y="142.24"/> +<pinref part="R3H8" gate="R" pin="2"/> +<pinref part="C7V4" gate="C" pin="1"/> +<label x="224.79" y="142.24" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="N$279" class="0"> +<segment> +<wire x1="160.02" y1="60.96" x2="163.83" y2="60.96" width="0.1524" layer="91"/> +<wire x1="163.83" y1="60.96" x2="163.83" y2="58.42" width="0.1524" layer="91"/> +<pinref part="U3H1" gate="G$1" pin="REF"/> +<pinref part="R3H3" gate="R" pin="1"/> +</segment> +</net> +<net name="ICH-14MHZ-CLK-R" class="0"> +<segment> +<wire x1="163.83" y1="43.18" x2="128.27" y2="43.18" width="0.1524" layer="91"/> +<wire x1="163.83" y1="35.56" x2="163.83" y2="43.18" width="0.1524" layer="91"/> +<wire x1="163.83" y1="43.18" x2="163.83" y2="48.26" width="0.1524" layer="91"/> +<junction x="163.83" y="43.18"/> +<pinref part="C8V2" gate="C" pin="1"/> +<pinref part="R3H3" gate="R" pin="2"/> +<label x="128.27" y="43.18" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$285" class="0"> +<segment> +<wire x1="160.02" y1="64.77" x2="172.72" y2="64.77" width="0.1524" layer="91"/> +<wire x1="172.72" y1="64.77" x2="179.07" y2="64.77" width="0.1524" layer="91"/> +<wire x1="179.07" y1="64.77" x2="179.07" y2="58.42" width="0.1524" layer="91"/> +<wire x1="172.72" y1="64.77" x2="172.72" y2="58.42" width="0.1524" layer="91"/> +<junction x="172.72" y="64.77"/> +<pinref part="U3H1" gate="G$1" pin="USB-48"/> +<pinref part="R3G35" gate="R" pin="1"/> +<pinref part="R3H1" gate="R" pin="1"/> +</segment> +</net> +<net name="MICH-SIU-48MHZ-CLK" class="0"> +<segment> +<wire x1="172.72" y1="48.26" x2="172.72" y2="41.91" width="0.1524" layer="91"/> +<wire x1="172.72" y1="41.91" x2="172.72" y2="35.56" width="0.1524" layer="91"/> +<wire x1="172.72" y1="41.91" x2="208.28" y2="41.91" width="0.1524" layer="91"/> +<junction x="172.72" y="41.91"/> +<pinref part="R3H1" gate="R" pin="2"/> +<pinref part="C7V1" gate="C" pin="1"/> +<label x="208.28" y="41.91" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="TOL-USB-48MHZ-R" class="0"> +<segment> +<wire x1="179.07" y1="48.26" x2="179.07" y2="46.99" width="0.1524" layer="91"/> +<wire x1="179.07" y1="46.99" x2="179.07" y2="35.56" width="0.1524" layer="91"/> +<wire x1="179.07" y1="46.99" x2="208.28" y2="46.99" width="0.1524" layer="91"/> +<junction x="179.07" y="46.99"/> +<pinref part="R3G35" gate="R" pin="2"/> +<pinref part="C7U6" gate="C" pin="1"/> +<label x="208.28" y="46.99" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="TOL-SATA-100MHZ-N-R" class="0"> +<segment> +<wire x1="181.61" y1="91.44" x2="184.15" y2="91.44" width="0.1524" layer="91"/> +<wire x1="184.15" y1="91.44" x2="208.28" y2="91.44" width="0.1524" layer="91"/> +<wire x1="184.15" y1="91.44" x2="184.15" y2="87.63" width="0.1524" layer="91"/> +<wire x1="187.96" y1="87.63" x2="184.15" y2="87.63" width="0.1524" layer="91"/> +<junction x="184.15" y="91.44"/> +<pinref part="R3G11" gate="R" pin="2"/> +<pinref part="R3G12" gate="R" pin="1"/> +<label x="208.28" y="91.44" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="TOL-SATA-100MHZ-P-R" class="0"> +<segment> +<wire x1="181.61" y1="99.06" x2="184.15" y2="99.06" width="0.1524" layer="91"/> +<wire x1="184.15" y1="99.06" x2="208.28" y2="99.06" width="0.1524" layer="91"/> +<wire x1="184.15" y1="99.06" x2="184.15" y2="95.25" width="0.1524" layer="91"/> +<wire x1="187.96" y1="95.25" x2="184.15" y2="95.25" width="0.1524" layer="91"/> +<junction x="184.15" y="99.06"/> +<pinref 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y2="106.68" width="0.1524" layer="91"/> +<wire x1="163.83" y1="106.68" x2="171.45" y2="106.68" width="0.1524" layer="91"/> +<pinref part="R3G23" gate="R" pin="1"/> +<pinref part="U3H1" gate="G$1" pin="SRC-2N"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="101.6" y="171.45" size="3.81" layer="94">BUS TDM & MISC</text> +<text x="10.16" y="172.72" size="1.778" layer="94">slas504 ext:pdf inurl:ti.com</text> +</plain> +<instances> +<instance part="FRAME27" gate="G$1" x="0" y="0"/> +<instance part="FRAME27" gate="G$2" x="180.34" y="0"/> +<instance part="R7W16" gate="R" x="132.08" y="157.48" smashed="yes"> +<attribute name="NAME" x="129.2225" y="157.7975" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="136.2075" y="157.7975" size="1.778" layer="96"/> +<attribute name="DNP" x="142.24" y="157.48" size="1.778" layer="96"/> +<attribute name="POWER" x="132.08" y="157.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R7W23" gate="R" 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display="off"/> +</instance> +<instance part="R8" gate="R" x="90.17" y="57.15" rot="MR180"> +<attribute name="POWER" x="90.17" y="57.15" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="R9" gate="R" x="74.93" y="15.24" rot="R270"> +<attribute name="POWER" x="74.93" y="15.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R10" gate="R" x="90.17" y="22.86" rot="MR180"> +<attribute name="POWER" x="90.17" y="22.86" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="R7W24" gate="R" x="132.08" y="116.84" smashed="yes"> +<attribute name="NAME" x="129.0691" y="118.8106" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="136.524" y="117.0864" size="1.778" layer="96"/> +<attribute name="DNP" x="142.24" y="116.84" size="1.778" layer="96"/> +<attribute name="POWER" x="132.08" y="116.84" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R7W20" gate="R" x="132.08" y="106.68" smashed="yes"> +<attribute name="NAME" x="129.0691" y="108.6506" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="136.524" y="106.9264" size="1.778" layer="96"/> +<attribute name="DNP" x="142.24" y="106.68" size="1.778" layer="96"/> +<attribute name="POWER" x="132.08" y="106.68" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R80" gate="R" x="177.8" y="121.92" smashed="yes"> +<attribute name="NAME" x="174.625" y="122.2375" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="180.974" y="122.1664" size="1.778" layer="96"/> +<attribute name="POWER" x="177.8" y="121.92" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R75" gate="R" x="177.8" y="111.76" smashed="yes"> +<attribute name="NAME" x="174.625" y="112.0775" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="180.974" y="112.0064" size="1.778" layer="96"/> +<attribute name="POWER" x="177.8" y="111.76" size="1.778" layer="96" display="off"/> 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+<instance part="R79" gate="R" x="177.8" y="97.79" smashed="yes"> +<attribute name="NAME" x="174.625" y="98.1075" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="180.974" y="98.0364" size="1.778" layer="96"/> +<attribute name="POWER" x="177.8" y="97.79" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$38" gate="PW-VCC3" x="162.56" y="134.62"/> +<instance part="U$69" gate="PW-VCC3" x="196.85" y="77.47"/> +</instances> +<busses> +</busses> +<nets> +<net name="HSS-RXCLK0" class="0"> +<segment> +<wire x1="127" y1="157.48" x2="92.71" y2="157.48" width="0.1524" layer="91"/> +<label x="97.79" y="159.385" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7W16" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="RX_CLK0"/> +</segment> +<segment> +<wire x1="104.14" y1="62.23" x2="95.25" y2="62.23" width="0.1524" layer="91"/> +<pinref part="R4" gate="R" pin="2"/> +<label x="104.14" y="62.23" size="1.778" layer="92" xref="yes"/> +</segment> +</net> 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rot="MR180"/> +<pinref part="R6W7" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="TX_CLK0"/> +</segment> +<segment> +<wire x1="80.01" y1="67.31" x2="52.07" y2="67.31" width="0.1524" layer="91"/> +<wire x1="80.01" y1="67.31" x2="80.01" y2="62.23" width="0.1524" layer="91"/> +<wire x1="80.01" y1="62.23" x2="85.09" y2="62.23" width="0.1524" layer="91"/> +<wire x1="80.01" y1="67.31" x2="85.09" y2="67.31" width="0.1524" layer="91"/> +<junction x="80.01" y="67.31"/> +<pinref part="R4" gate="R" pin="1"/> +<pinref part="R5" gate="R" pin="1"/> +<label x="52.07" y="67.31" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="HSS-TXCLK1" class="0"> +<segment> +<wire x1="127" y1="144.78" x2="92.71" y2="144.78" width="0.1524" layer="91"/> +<label x="97.79" y="146.685" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7W15" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="TX_CLK1"/> +</segment> +<segment> +<wire x1="95.25" y1="57.15" x2="107.95" y2="57.15" width="0.1524" layer="91"/> +<pinref part="R8" gate="R" pin="2"/> +<label x="107.95" y="57.15" size="1.778" layer="92" rot="MR180" xref="yes"/> +</segment> +</net> +<net name="HSS-TXCLK2" class="0"> +<segment> +<wire x1="127" y1="142.24" x2="92.71" y2="142.24" width="0.1524" layer="91"/> +<label x="97.79" y="144.145" size="1.778" layer="92" rot="MR180"/> +<pinref part="R5J2" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="TX_CLK2"/> +</segment> +</net> +<net name="HSS-TXFRAME0" class="0"> +<segment> +<wire x1="127" y1="127" x2="92.71" y2="127" width="0.1524" layer="91"/> +<label x="97.79" y="128.905" size="1.778" layer="92" rot="MR180"/> +<pinref part="R6W6" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="TX_FRAME0"/> +</segment> +<segment> +<wire x1="74.93" y1="22.86" x2="52.07" y2="22.86" width="0.1524" layer="91"/> +<wire x1="74.93" y1="22.86" x2="74.93" y2="20.32" width="0.1524" layer="91"/> +<wire x1="74.93" y1="22.86" x2="85.09" y2="22.86" width="0.1524" layer="91"/> +<junction x="74.93" y="22.86"/> +<pinref part="R9" gate="R" pin="1"/> +<pinref part="R10" gate="R" pin="1"/> +<label x="52.07" y="22.86" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="HSS-TXFRAME1" class="0"> +<segment> +<wire x1="64.77" y1="77.47" x2="49.53" y2="77.47" width="0.1524" layer="91"/> +<pinref part="R3" gate="R" pin="1"/> +<label x="49.53" y="77.47" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="127" y1="124.46" x2="92.71" y2="124.46" width="0.1524" layer="91"/> +<label x="97.79" y="126.365" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7W14" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="TX_FRAME1"/> +</segment> +</net> +<net name="HSS-TXFRAME2" class="0"> +<segment> +<wire x1="127" y1="121.92" x2="92.71" y2="121.92" width="0.1524" layer="91"/> +<label x="97.79" y="123.825" size="1.778" layer="92" rot="MR180"/> +<pinref part="R5J1" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="TX_FRAME2"/> +</segment> +</net> +<net name="HSS-RXFRAME0" class="0"> +<segment> +<wire x1="127" y1="137.16" x2="92.71" y2="137.16" width="0.1524" layer="91"/> +<label x="97.79" y="139.065" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7W17" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="RX_FRAME0"/> +</segment> +<segment> +<wire x1="74.93" y1="7.62" x2="52.07" y2="7.62" width="0.1524" layer="91"/> +<wire x1="74.93" y1="7.62" x2="74.93" y2="10.16" width="0.1524" layer="91"/> +<pinref part="R9" gate="R" pin="2"/> +<label x="52.07" y="7.62" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="HSS-RXFRAME1" class="0"> +<segment> +<wire x1="127" y1="134.62" x2="92.71" y2="134.62" width="0.1524" layer="91"/> +<label x="97.79" y="136.525" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7W22" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="RX_FRAME1"/> +</segment> +<segment> +<wire x1="101.6" y1="72.39" x2="95.25" y2="72.39" width="0.1524" layer="91"/> +<pinref part="R1" gate="R" pin="2"/> +<label x="101.6" y="72.39" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="HSS-RXFRAME2" class="0"> +<segment> +<wire x1="127" y1="132.08" x2="92.71" y2="132.08" width="0.1524" layer="91"/> +<label x="97.79" y="133.985" size="1.778" layer="92" rot="MR180"/> +<pinref part="R5K3" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="RX_FRAME2"/> +</segment> +</net> +<net name="HSS-RXDATA0" class="0"> +<segment> +<wire x1="127" y1="116.84" x2="92.71" y2="116.84" width="0.1524" layer="91"/> +<label x="97.79" y="118.745" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="TDM" pin="RX_DATA_IN0"/> +<pinref part="R7W24" gate="R" pin="1"/> +</segment> +</net> +<net name="HSS-RXDATA1" class="0"> +<segment> +<wire x1="127" y1="114.3" x2="92.71" y2="114.3" width="0.1524" layer="91"/> +<label x="97.79" y="116.205" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7W21" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="RX_DATA_IN1"/> +</segment> +</net> +<net name="HSS-RXDATA2" class="0"> +<segment> +<wire x1="127" y1="111.76" x2="92.71" y2="111.76" width="0.1524" layer="91"/> +<label x="97.79" y="113.665" size="1.778" layer="92" rot="MR180"/> +<pinref part="R5J7" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="RX_DATA_IN2"/> +</segment> +</net> +<net name="HSS-TXDATA0" class="0"> +<segment> +<wire x1="127" y1="106.68" x2="92.71" y2="106.68" width="0.1524" layer="91"/> +<label x="97.79" y="108.585" size="1.778" layer="92" rot="MR180"/> +<pinref part="U6E1" gate="TDM" pin="TX_DATA_OUT0"/> +<pinref part="R7W20" gate="R" pin="1"/> +</segment> +</net> +<net name="HSS-TXDATA1" class="0"> +<segment> +<wire x1="127" y1="104.14" x2="92.71" y2="104.14" width="0.1524" layer="91"/> +<label x="97.79" y="106.045" size="1.778" layer="92" rot="MR180"/> +<pinref part="R7W13" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="TX_DATA_OUT1"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="137.16" y1="152.4" x2="152.4" y2="152.4" width="0.1524" layer="91"/> +<wire x1="152.4" y1="152.4" x2="152.4" y2="154.94" width="0.1524" layer="91"/> +<wire x1="152.4" y1="154.94" x2="152.4" y2="157.48" width="0.1524" layer="91"/> +<wire x1="152.4" y1="157.48" x2="152.4" y2="161.29" width="0.1524" layer="91"/> +<wire x1="137.16" y1="154.94" x2="152.4" y2="154.94" width="0.1524" layer="91"/> +<wire x1="137.16" y1="157.48" x2="152.4" y2="157.48" width="0.1524" layer="91"/> +<wire x1="137.16" y1="142.24" x2="152.4" y2="142.24" width="0.1524" layer="91"/> +<wire x1="152.4" y1="142.24" x2="152.4" y2="144.78" width="0.1524" layer="91"/> +<wire x1="152.4" y1="144.78" x2="152.4" y2="147.32" width="0.1524" layer="91"/> +<wire x1="137.16" y1="144.78" x2="152.4" y2="144.78" width="0.1524" layer="91"/> +<wire x1="137.16" y1="147.32" x2="152.4" y2="147.32" width="0.1524" layer="91"/> +<wire x1="152.4" y1="147.32" x2="152.4" y2="152.4" width="0.1524" layer="91"/> +<wire x1="137.16" y1="132.08" x2="152.4" y2="132.08" width="0.1524" layer="91"/> +<wire x1="152.4" y1="132.08" x2="152.4" y2="134.62" width="0.1524" layer="91"/> +<wire x1="152.4" y1="134.62" x2="152.4" y2="137.16" width="0.1524" layer="91"/> +<wire x1="137.16" y1="134.62" x2="152.4" y2="134.62" width="0.1524" layer="91"/> +<wire x1="137.16" y1="137.16" x2="152.4" y2="137.16" width="0.1524" layer="91"/> +<wire x1="152.4" y1="137.16" x2="152.4" y2="142.24" width="0.1524" layer="91"/> +<wire x1="137.16" y1="121.92" x2="152.4" y2="121.92" width="0.1524" layer="91"/> +<wire x1="152.4" y1="121.92" x2="152.4" y2="124.46" width="0.1524" layer="91"/> +<wire x1="152.4" y1="124.46" x2="152.4" y2="127" width="0.1524" layer="91"/> +<wire x1="137.16" y1="124.46" x2="152.4" y2="124.46" width="0.1524" layer="91"/> +<wire x1="137.16" y1="127" x2="152.4" y2="127" width="0.1524" layer="91"/> +<wire x1="152.4" y1="127" x2="152.4" y2="132.08" width="0.1524" layer="91"/> +<wire x1="137.16" y1="111.76" x2="152.4" y2="111.76" width="0.1524" layer="91"/> +<wire x1="152.4" y1="111.76" x2="152.4" y2="114.3" width="0.1524" layer="91"/> +<wire x1="152.4" y1="114.3" x2="152.4" y2="116.84" width="0.1524" layer="91"/> +<wire x1="137.16" y1="114.3" x2="152.4" y2="114.3" width="0.1524" layer="91"/> +<wire x1="137.16" y1="116.84" x2="152.4" y2="116.84" width="0.1524" layer="91"/> +<wire x1="152.4" y1="116.84" x2="152.4" y2="121.92" width="0.1524" layer="91"/> +<wire x1="137.16" y1="101.6" x2="152.4" y2="101.6" width="0.1524" layer="91"/> +<wire x1="152.4" y1="101.6" x2="152.4" y2="104.14" width="0.1524" layer="91"/> +<wire x1="152.4" y1="104.14" x2="152.4" y2="106.68" width="0.1524" layer="91"/> +<wire x1="137.16" y1="104.14" x2="152.4" y2="104.14" width="0.1524" layer="91"/> +<wire x1="137.16" y1="106.68" x2="152.4" y2="106.68" width="0.1524" layer="91"/> +<wire x1="152.4" y1="106.68" x2="152.4" y2="111.76" width="0.1524" layer="91"/> +<junction x="152.4" y="154.94"/> +<junction x="152.4" y="157.48"/> +<junction x="152.4" y="144.78"/> +<junction x="152.4" y="147.32"/> +<junction x="152.4" y="134.62"/> +<junction x="152.4" y="137.16"/> +<junction x="152.4" y="124.46"/> +<junction x="152.4" y="127"/> +<junction x="152.4" y="114.3"/> +<junction x="152.4" y="116.84"/> +<junction x="152.4" y="104.14"/> +<junction x="152.4" y="106.68"/> +<junction x="152.4" y="152.4"/> +<junction x="152.4" y="142.24"/> +<junction x="152.4" y="132.08"/> +<junction x="152.4" y="121.92"/> +<junction x="152.4" y="111.76"/> +<pinref part="R7W16" gate="R" pin="2"/> +<pinref part="R7W23" gate="R" pin="2"/> +<pinref part="R5K2" gate="R" pin="2"/> +<pinref part="R6W7" gate="R" pin="2"/> +<pinref part="R7W15" gate="R" pin="2"/> +<pinref part="R5J2" gate="R" pin="2"/> +<pinref part="R7W17" gate="R" pin="2"/> +<pinref part="R7W22" gate="R" pin="2"/> +<pinref part="R5K3" gate="R" pin="2"/> +<pinref part="R6W6" gate="R" pin="2"/> +<pinref part="R7W14" gate="R" pin="2"/> +<pinref part="R5J1" gate="R" pin="2"/> +<pinref part="R7W21" gate="R" pin="2"/> +<pinref part="R5J7" gate="R" pin="2"/> +<pinref part="R7W13" gate="R" pin="2"/> +<pinref part="R5J3" gate="R" pin="2"/> +<pinref part="U$511" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R7W24" gate="R" pin="2"/> +<pinref part="R7W20" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="162.56" y1="102.87" x2="172.72" y2="102.87" width="0.1524" layer="91"/> +<wire x1="162.56" y1="100.33" x2="162.56" y2="102.87" width="0.1524" layer="91"/> +<wire x1="172.72" y1="100.33" x2="162.56" y2="100.33" width="0.1524" layer="91"/> +<wire x1="172.72" y1="97.79" x2="162.56" y2="97.79" width="0.1524" layer="91"/> +<wire x1="162.56" y1="97.79" x2="162.56" y2="100.33" width="0.1524" layer="91"/> +<wire x1="172.72" y1="111.76" x2="162.56" y2="111.76" width="0.1524" layer="91"/> +<wire x1="162.56" y1="111.76" x2="162.56" y2="109.22" width="0.1524" layer="91"/> +<junction x="162.56" y="100.33"/> +<junction x="162.56" y="102.87"/> +<pinref part="R77" gate="R" pin="1"/> +<pinref part="R78" gate="R" pin="1"/> +<pinref part="R79" gate="R" pin="1"/> +<pinref part="R75" gate="R" pin="1"/> +<wire x1="162.56" y1="109.22" x2="162.56" y2="102.87" width="0.1524" layer="91"/> +<wire x1="162.56" y1="121.92" x2="162.56" y2="132.08" width="0.1524" layer="91"/> +<wire x1="172.72" y1="121.92" x2="162.56" y2="121.92" width="0.1524" layer="91"/> +<wire x1="162.56" y1="114.3" x2="162.56" y2="121.92" width="0.1524" layer="91"/> +<wire x1="172.72" y1="114.3" x2="162.56" y2="114.3" width="0.1524" layer="91"/> +<junction x="162.56" y="121.92"/> +<junction x="162.56" y="114.3"/> +<pinref part="R80" gate="R" pin="1"/> +<pinref part="R81" gate="R" pin="1"/> +<pinref part="R76" gate="R" pin="1"/> +<pinref part="U$38" gate="PW-VCC3" pin="VCC3"/> +<wire x1="162.56" y1="111.76" x2="162.56" y2="114.3" width="0.1524" layer="91"/> +<junction x="162.56" y="111.76"/> +<wire x1="172.72" y1="109.22" x2="162.56" y2="109.22" width="0.1524" layer="91"/> +<junction x="162.56" y="109.22"/> +</segment> +<segment> +<wire x1="196.85" y1="72.39" x2="196.85" y2="74.93" width="0.1524" layer="91"/> +<wire x1="196.85" y1="69.85" x2="196.85" y2="72.39" width="0.1524" layer="91"/> +<pinref part="R5T7" gate="R" pin="1"/> +<pinref part="U$69" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="GND" class="0"> +<segment> +<wire x1="198.12" y1="116.84" x2="196.85" y2="116.84" width="0.1524" layer="91"/> +<pinref part="U$297" gate="G$1" pin="GND"/> +<pinref part="R5T14" gate="R" pin="1"/> +</segment> +</net> +<net name="TOL-CORE-100MHZ-P-R" class="0"> +<segment> +<wire x1="227.33" y1="129.54" x2="213.36" y2="129.54" width="0.1524" layer="91"/> +<wire x1="213.36" y1="129.54" x2="209.55" y2="132.08" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IA32CORE" pin="CLKP100"/> +<label x="209.55" y="132.08" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="TOL-CORE-100MHZ-N-R" class="0"> +<segment> +<wire x1="227.33" y1="127" x2="209.55" y2="127" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IA32CORE" pin="CLKN100"/> +<label x="209.55" y="127" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="IMCH-CPUSLP-N" class="0"> +<segment> +<wire x1="227.33" y1="121.92" x2="194.31" y2="121.92" width="0.1524" layer="91"/> +<wire x1="194.31" y1="121.92" x2="182.88" y2="121.92" width="0.1524" layer="91"/> +<label x="194.437" y="122.301" size="1.778" layer="92"/> +<pinref part="U6E1" gate="IA32CORE" pin="CPUSLP_OUT_N"/> +<pinref part="R80" gate="R" pin="2"/> +</segment> +</net> +<net name="IMCH-LINT1-NMI" class="0"> +<segment> +<wire x1="208.28" y1="116.84" x2="227.33" y2="116.84" width="0.1524" layer="91"/> +<pinref part="R5T14" gate="R" pin="2"/> +<pinref part="U6E1" gate="IA32CORE" pin="NMI"/> +</segment> +</net> +<net name="IMCH-SMI-N" class="0"> +<segment> +<wire x1="182.88" y1="114.3" x2="185.42" y2="114.3" width="0.1524" layer="91"/> +<wire x1="185.42" y1="114.3" x2="227.33" y2="114.3" width="0.1524" layer="91"/> +<pinref part="R81" gate="R" pin="2"/> +<pinref part="U6E1" gate="IA32CORE" pin="SMI_OUT_N"/> +</segment> +</net> +<net name="IMCH-STPCLK-N" class="0"> +<segment> +<wire x1="227.33" y1="111.76" x2="194.31" y2="111.76" width="0.1524" layer="91"/> +<wire x1="194.31" y1="111.76" x2="182.88" y2="111.76" width="0.1524" layer="91"/> +<label x="194.437" y="111.887" size="1.778" layer="92"/> +<pinref part="U6E1" gate="IA32CORE" pin="STPCLK_OUT_N"/> +<pinref part="R75" gate="R" pin="2"/> +</segment> +</net> +<net name="N$115" class="0"> +<segment> +<wire x1="182.88" y1="109.22" x2="189.23" y2="109.22" width="0.1524" layer="91"/> +<wire x1="189.23" y1="109.22" x2="227.33" y2="109.22" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IA32CORE" pin="RCIN_N"/> +<pinref part="R76" gate="R" pin="2"/> +</segment> +</net> +<net name="N$273" class="0"> +<segment> +<wire x1="182.88" y1="102.87" x2="212.09" y2="102.87" width="0.1524" layer="91"/> +<wire x1="212.09" y1="102.87" x2="214.63" y2="102.87" width="0.1524" layer="91"/> +<wire x1="214.63" y1="102.87" x2="218.44" y2="106.68" width="0.1524" layer="91"/> +<wire x1="218.44" y1="106.68" x2="227.33" y2="106.68" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IA32CORE" pin="A20GATE"/> +<pinref part="R77" gate="R" pin="2"/> +</segment> +</net> +<net name="CPURST-N" class="0"> +<segment> +<wire x1="227.33" y1="104.14" x2="220.98" y2="104.14" width="0.1524" layer="91"/> +<wire x1="220.98" y1="104.14" x2="217.17" y2="100.33" width="0.1524" layer="91"/> +<wire x1="217.17" y1="100.33" x2="214.63" y2="100.33" width="0.1524" layer="91"/> +<wire x1="214.63" y1="100.33" x2="193.04" y2="100.33" width="0.1524" layer="91"/> +<wire x1="193.04" y1="100.33" x2="182.88" y2="100.33" width="0.1524" layer="91"/> +<label x="193.04" y="100.6475" size="1.778" layer="92"/> +<pinref part="U6E1" gate="IA32CORE" pin="CPURST_N"/> +<pinref part="R78" gate="R" pin="2"/> +</segment> +</net> +<net name="CPU-PWR-GD" class="0"> +<segment> +<wire x1="182.88" y1="97.79" x2="217.17" y2="97.79" width="0.1524" layer="91"/> +<wire x1="217.17" y1="97.79" x2="219.71" y2="97.79" width="0.1524" layer="91"/> +<wire x1="219.71" y1="97.79" x2="223.52" y2="101.6" width="0.1524" layer="91"/> +<wire x1="223.52" y1="101.6" x2="227.33" y2="101.6" width="0.1524" layer="91"/> +<label x="193.04" y="98.1075" size="1.778" layer="92"/> +<pinref part="U6E1" gate="IA32CORE" pin="CPUPWRGD_OUT"/> +<pinref part="R79" gate="R" pin="2"/> +</segment> +</net> +<net name="GP40.IERR-N" class="0"> +<segment> +<wire x1="227.33" y1="99.06" x2="220.98" y2="92.71" width="0.1524" layer="91"/> +<wire x1="220.98" y1="92.71" x2="190.5" y2="92.71" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IA32CORE" pin="IERR_N"/> +<label x="190.5" y="92.71" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="P-PME-N" class="0"> +<segment> +<wire x1="196.85" y1="59.69" x2="196.85" y2="55.88" width="0.1524" layer="91"/> +<wire x1="196.85" y1="55.88" x2="214.63" y2="55.88" width="0.1524" layer="91"/> +<wire x1="196.85" y1="55.88" x2="177.8" y2="55.88" width="0.1524" layer="91"/> +<junction x="196.85" y="55.88"/> +<pinref part="R5T7" gate="R" pin="2"/> +<pinref part="U6E1" gate="MISCSIG" pin="PME_N"/> +<label x="177.8" y="55.88" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="HSS-TXFRAME1/HSS-RXFRAME1" class="0"> +<segment> +<wire x1="101.6" y1="77.47" x2="76.2" y2="77.47" width="0.1524" layer="91"/> +<wire x1="76.2" y1="77.47" x2="74.93" y2="77.47" width="0.1524" layer="91"/> +<wire x1="85.09" y1="72.39" x2="76.2" y2="72.39" width="0.1524" layer="91"/> +<wire x1="76.2" y1="72.39" x2="76.2" y2="77.47" width="0.1524" layer="91"/> +<junction x="76.2" y="77.47"/> +<pinref part="R3" gate="R" pin="2"/> +<pinref part="R1" gate="R" pin="1"/> +<label x="101.6" y="77.47" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="HSS-RXCLK0/HSS-TXCLK0" class="0"> +<segment> +<wire x1="104.14" y1="67.31" x2="95.25" y2="67.31" width="0.1524" layer="91"/> +<pinref part="R5" gate="R" pin="2"/> +<label x="104.14" y="67.31" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="HSS-RXFRAME0/HSS-TXFRAME0" class="0"> +<segment> +<wire x1="104.14" y1="22.86" x2="95.25" y2="22.86" width="0.1524" layer="91"/> +<pinref part="R10" gate="R" pin="2"/> +<label x="104.14" y="22.86" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="HSS-TXCLK1/HSS-RXCLK1" class="0"> +<segment> +<wire x1="73.66" y1="57.15" x2="80.01" y2="57.15" width="0.1524" layer="91"/> +<wire x1="80.01" y1="57.15" x2="85.09" y2="57.15" width="0.1524" layer="91"/> +<wire x1="85.09" y1="52.07" x2="80.01" y2="52.07" width="0.1524" layer="91"/> +<wire x1="80.01" y1="52.07" x2="80.01" y2="57.15" width="0.1524" layer="91"/> +<junction x="80.01" y="57.15"/> +<pinref part="R6" gate="R" pin="1"/> +<pinref part="R8" gate="R" pin="1"/> +<label x="73.66" y="57.15" size="1.778" layer="92" rot="MR0" xref="yes"/> +</segment> +</net> +<net name="HSS-TXDATA2" class="0"> +<segment> +<wire x1="127" y1="101.6" x2="92.71" y2="101.6" width="0.1524" layer="91"/> +<label x="97.79" y="101.9175" size="1.778" layer="92"/> +<pinref part="R5J3" gate="R" pin="1"/> +<pinref part="U6E1" gate="TDM" pin="TX_DATA_OUT2"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="118.11" y="171.45" size="3.81" layer="94">CPU PW-MANAGE/LPC/IEEE1588/IICHIMCH</text> +<text x="53.34" y="10.16" size="1.778" layer="94">Pour l'interconnection d'un afficheur</text> +<text x="46.99" y="25.4" size="1.778" layer="94">En attente Xavier</text> +</plain> +<instances> +<instance part="FRAME29" gate="G$1" x="0" y="0"/> +<instance part="FRAME29" gate="G$2" x="180.34" y="0"/> +<instance part="R5E11" gate="R" x="85.09" y="105.41" smashed="yes"> +<attribute name="NAME" x="84.9366" y="108.6506" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="85.724" y="106.9264" size="1.778" layer="96"/> +<attribute name="POWER" x="85.09" y="105.41" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R5R9" gate="R" x="85.09" y="95.25" rot="MR180"> +<attribute name="POWER" x="85.09" y="95.25" size="1.778" layer="96" rot="MR180" display="off"/> +<attribute name="DNP" x="85.09" y="95.25" size="1.778" layer="96" rot="MR180" display="off"/> +</instance> +<instance part="R5F2" gate="R" x="144.78" y="137.16" smashed="yes" rot="R270"> +<attribute name="NAME" x="143.1925" y="134.3025" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="148.2725" y="140.335" size="1.778" layer="96" rot="MR270"/> +<attribute name="POWER" x="144.78" y="137.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="Y5F1" gate="Q" x="135.89" y="137.16" rot="MR270"/> +<instance part="C5F9" gate="C" x="125.73" y="146.05" smashed="yes" rot="R270"> +<attribute name="NAME" x="125.73" y="144.78" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="123.19" y="144.78" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="C5E10" gate="C" x="124.46" y="128.27" smashed="yes" rot="MR90"> +<attribute name="NAME" x="124.46" y="129.54" size="1.778" layer="95"/> +<attribute name="VALUE" x="121.92" y="129.54" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="R5T20" gate="R" x="229.87" y="101.6" rot="MR0"> +<attribute name="POWER" x="229.87" y="101.6" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U6E1" gate="IEEE1588" x="88.9" y="153.67" smashed="yes" rot="MR0"> +<attribute name="NAME" x="101.6" y="172.085" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="69.85" y="140.335" size="1.778" layer="96"/> +</instance> +<instance part="U6E1" gate="IICHIMCH" x="173.99" y="135.89" rot="MR0"/> +<instance part="U6E1" gate="LPC11" x="25.4" y="26.67" smashed="yes" rot="MR0"> +<attribute name="NAME" x="22.86" y="49.53" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="38.1" y="8.89" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="U6E1" gate="POWERMANAGE" x="24.13" y="88.9" rot="MR0"/> +<instance part="R5E9" gate="R" x="85.09" y="81.28" rot="R180"> +<attribute name="POWER" x="85.09" y="81.28" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R5T9" gate="R" x="104.14" y="21.59" rot="MR0"> +<attribute name="POWER" x="104.14" y="21.59" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2H12" gate="R" x="229.87" y="121.92"> +<attribute name="POWER" x="229.87" y="121.92" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$567" gate="PW-VCC3" x="251.46" y="139.7"/> +<instance part="R3U16" gate="R" x="229.87" y="125.73" rot="R180"> +<attribute name="POWER" x="229.87" y="125.73" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3R40" gate="R" x="123.19" y="153.67" smashed="yes"> +<attribute name="NAME" x="119.6975" y="155.8925" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="126.365" y="155.8925" size="1.778" layer="96" rot="MR180"/> +<attribute name="POWER" x="123.19" y="153.67" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3R41" gate="R" x="123.19" y="157.48" smashed="yes"> +<attribute name="NAME" x="119.6975" y="159.7025" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="127.635" y="159.7025" size="1.778" layer="96" rot="MR180"/> +<attribute name="POWER" x="123.19" y="157.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$383" gate="G$1" x="137.16" y="153.67" rot="MR270"/> +<instance part="R5T19" gate="R" x="83.82" y="114.3" smashed="yes" rot="MR0"> +<attribute name="NAME" x="79.375" y="114.6175" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="86.6775" y="114.6175" size="1.778" layer="96"/> +<attribute name="POWER" x="83.82" y="114.3" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R5T18" gate="R" x="83.82" y="118.11" smashed="yes" rot="MR0"> +<attribute name="NAME" x="79.375" y="118.4275" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="86.6775" y="118.4275" size="1.778" layer="96"/> +<attribute name="POWER" x="83.82" y="118.11" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R27" gate="R" x="81.28" y="68.58"> +<attribute name="POWER" x="81.28" y="68.58" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3U14" gate="R" x="229.87" y="95.25" rot="R180"> +<attribute name="POWER" x="229.87" y="95.25" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$502" gate="G$1" x="116.84" y="137.16" rot="R90"/> +<instance part="U$505" gate="G$1" x="49.53" y="38.1" rot="R270"/> +<instance part="U$537" gate="G$1" x="71.12" y="38.1" rot="R90"/> +<instance part="U$553" gate="G$1" x="71.12" y="43.18" rot="R90"/> +<instance part="P+7" gate="1" x="41.91" y="58.42"/> +<instance part="R3T4" gate="R" x="229.87" y="128.27" rot="R180"> +<attribute name="POWER" x="229.87" y="128.27" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3T5" gate="R" x="229.87" y="130.81" rot="R180"> +<attribute name="POWER" x="229.87" y="130.81" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R3T6" gate="R" x="229.87" y="133.35" rot="R180"> +<attribute name="POWER" x="229.87" y="133.35" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R12" gate="R" x="222.25" y="81.28"> +<attribute name="POWER" x="222.25" y="81.28" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="222.25" y="81.28" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U5" gate="U" x="170.18" y="73.66"/> +<instance part="U$535" gate="PW-VCC3" x="149.86" y="86.36"/> +<instance part="U$554" gate="G$1" x="158.75" y="67.31" rot="R270"/> +<instance part="U6" gate="U" x="170.18" y="53.34"/> +<instance part="U$561" gate="PW-VCC3" x="149.86" y="66.04"/> +<instance part="U$562" gate="G$1" x="158.75" y="46.99" rot="R270"/> +<instance part="U7" gate="U" x="170.18" y="33.02"/> +<instance part="U$581" gate="G$1" x="157.48" y="26.67" rot="R270"/> +<instance part="C-PORT80" gate="1" x="60.96" y="40.64" rot="R180"/> +<instance part="U$171" gate="PW-VCC3" x="81.28" y="62.23"/> +<instance part="U$62" gate="PW-VCC3" x="104.14" y="72.39"/> +<instance part="U$66" gate="PW-VCC3" x="111.76" y="33.02"/> +<instance part="U$54" gate="PW-VCC3" x="252.73" y="104.14"/> +<instance part="U$53" gate="PW-VCC3" x="95.25" y="123.19"/> +<instance part="U$85" gate="PW-VCC3" x="104.14" y="88.9"/> +<instance part="U$149" gate="G$1" x="149.86" y="44.45"/> +<instance part="TP3" gate="TP" x="102.87" y="100.33" smashed="yes" rot="R270"> +<attribute name="DNP" x="116.84" y="97.79" size="1.778" layer="96"/> +<attribute name="NAME" x="116.84" y="100.33" size="1.778" layer="95"/> +</instance> +</instances> +<busses> +<bus name="GPIO[0..48]"> +<segment> +<wire x1="231.14" y1="135.89" x2="231.14" y2="137.16" width="0.4064" layer="92"/> +<wire x1="231.14" y1="137.16" x2="228.6" y2="137.16" width="0.4064" layer="92"/> +<wire x1="228.6" y1="137.16" x2="228.6" y2="135.89" width="0.4064" layer="92"/> +<wire x1="228.6" y1="135.89" x2="209.55" y2="135.89" width="0.4064" layer="92"/> +<wire x1="209.55" y1="135.89" x2="209.55" y2="125.73" width="0.4064" layer="92"/> +<label x="211.7725" y="136.779" size="1.778" layer="92"/> +</segment> +</bus> +</busses> +<nets> +<net name="CPU-PROC-HOT-N" class="0"> +<segment> +<wire x1="40.64" y1="105.41" x2="68.58" y2="105.41" width="0.1524" layer="91"/> +<wire x1="68.58" y1="105.41" x2="68.58" y2="118.11" width="0.1524" layer="91"/> +<wire x1="68.58" y1="118.11" x2="78.74" y2="118.11" width="0.1524" layer="91"/> +<label x="66.04" y="105.7275" size="1.778" layer="92" rot="MR0"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="PROCHOT_N"/> +<pinref part="R5T18" gate="R" pin="2"/> +</segment> +</net> +<net name="CPU-THERMTRIP-N" class="0"> +<segment> +<wire x1="40.64" y1="101.6" x2="68.58" y2="101.6" width="0.1524" layer="91"/> +<wire x1="68.58" y1="101.6" x2="71.12" y2="101.6" width="0.1524" layer="91"/> +<wire x1="71.12" y1="101.6" x2="71.12" y2="114.3" width="0.1524" layer="91"/> +<wire x1="71.12" y1="114.3" x2="78.74" y2="114.3" width="0.1524" layer="91"/> +<label x="66.04" y="101.9175" size="1.778" layer="92" rot="MR0"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="THRMTRIP_N"/> +<pinref part="R5T19" gate="R" pin="2"/> +</segment> +</net> +<net name="IMCH-SLP-S3-N" class="0"> +<segment> +<wire x1="40.64" y1="97.79" x2="73.66" y2="97.79" width="0.1524" layer="91"/> +<wire x1="73.66" y1="97.79" x2="73.66" y2="105.41" width="0.1524" layer="91"/> +<wire x1="73.66" y1="105.41" x2="80.01" y2="105.41" width="0.1524" layer="91"/> +<label x="66.04" y="98.1075" size="1.778" layer="92" rot="MR0"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="SLP_S3_N"/> +<pinref part="R5E11" gate="R" pin="1"/> +</segment> +</net> +<net name="N$579" class="0"> +<segment> +<wire x1="40.64" y1="95.25" x2="76.2" y2="95.25" width="0.1524" layer="91"/> +<wire x1="80.01" y1="95.25" x2="76.2" y2="95.25" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="SLP_S4_N"/> +<pinref part="R5R9" gate="R" pin="1"/> +</segment> +</net> +<net name="SLP-S4-N" class="0"> +<segment> +<wire x1="90.17" y1="95.25" x2="97.79" y2="95.25" width="0.1524" layer="91"/> +<pinref part="R5R9" gate="R" pin="2"/> +<label x="102.87" y="95.25" size="1.778" layer="92" xref="yes"/> +<pinref part="TP3" gate="TP" pin="1"/> +<wire x1="97.79" y1="95.25" x2="102.87" y2="95.25" width="0.1524" layer="91"/> +<wire x1="100.33" y1="100.33" x2="97.79" y2="100.33" width="0.1524" layer="91"/> +<wire x1="97.79" y1="100.33" x2="97.79" y2="95.25" width="0.1524" layer="91"/> +<junction x="97.79" y="95.25"/> +</segment> +</net> +<net name="SLP-S3-N" class="0"> +<segment> +<wire x1="90.17" y1="105.41" x2="102.87" y2="105.41" width="0.1524" layer="91"/> +<pinref part="R5E11" gate="R" pin="2"/> +<label x="102.87" y="105.41" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="IMCH-PWRBTN-N" class="0"> +<segment> +<wire x1="40.64" y1="85.09" x2="66.04" y2="85.09" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="PWRBTN_N"/> +<label x="66.04" y="85.09" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="MICH-RI-N" class="0"> +<segment> +<wire x1="40.64" y1="81.28" x2="80.01" y2="81.28" width="0.1524" layer="91"/> +<label x="65.8495" y="81.661" size="1.778" layer="92" rot="MR0"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="RI_N"/> +<pinref part="R5E9" gate="R" pin="2"/> +</segment> +</net> +<net name="SYS-RESET-N" class="0"> +<segment> +<wire x1="40.64" y1="77.47" x2="48.26" y2="77.47" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="SYS_RESET_N"/> +<label x="48.26" y="77.47" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="IMCH-SUS-STAT-N" class="0"> +<segment> +<wire x1="40.64" y1="69.85" x2="67.31" y2="69.85" width="0.1524" layer="91"/> +<wire x1="67.31" y1="69.85" x2="67.31" y2="68.58" width="0.1524" layer="91"/> +<wire x1="67.31" y1="68.58" x2="76.2" y2="68.58" width="0.1524" layer="91"/> +<label x="65.9765" y="70.231" size="1.778" layer="92" rot="MR0"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="SUS_STAT_N"/> +<pinref part="R27" gate="R" pin="1"/> +</segment> +</net> +<net name="VRMPWRGD" class="0"> +<segment> +<wire x1="40.64" y1="62.23" x2="49.53" y2="62.23" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="VRMPWRGD"/> +<label x="49.53" y="62.23" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="PLTRST-N" class="0"> +<segment> +<wire x1="40.64" y1="109.22" x2="41.91" y2="109.22" width="0.1524" layer="91"/> +<wire x1="41.91" y1="109.22" x2="41.91" y2="113.03" width="0.1524" layer="91"/> +<wire x1="41.91" y1="113.03" x2="44.45" y2="113.03" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="PLTRST_N"/> +<label x="44.45" y="113.03" size="1.778" layer="92" xref="yes"/> +</segment> +<segment> +<wire x1="227.33" y1="156.21" x2="200.66" y2="156.21" width="0.1524" layer="91"/> +<wire x1="200.66" y1="156.21" x2="200.66" y2="151.13" width="0.1524" layer="91"/> +<wire x1="200.66" y1="151.13" x2="190.5" y2="151.13" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IICHIMCH" pin="RSTIN_N"/> +<label x="227.33" y="156.21" size="1.778" layer="92" xref="yes"/> +</segment> +<segment> +<wire x1="68.58" y1="45.72" x2="85.09" y2="45.72" width="0.1524" layer="91"/> +<pinref part="C-PORT80" gate="1" pin="6"/> +<label x="85.09" y="45.72" size="1.778" layer="92" xref="yes"/> +</segment> +<segment> +<wire x1="152.4" y1="76.2" x2="158.75" y2="76.2" width="0.1524" layer="91"/> +<pinref part="U5" gate="U" pin="I0"/> +<label x="152.4" y="76.2" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="152.4" y1="55.88" x2="158.75" y2="55.88" width="0.1524" layer="91"/> +<pinref part="U6" gate="U" pin="I0"/> +<label x="152.4" y="55.88" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="152.4" y1="30.48" x2="158.75" y2="30.48" width="0.1524" layer="91"/> +<pinref part="U7" gate="U" pin="I1"/> +<label x="152.4" y="30.48" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="RTCX1" class="0"> +<segment> +<wire x1="128.27" y1="146.05" x2="134.62" y2="146.05" width="0.1524" layer="91"/> +<wire x1="134.62" y1="146.05" x2="137.16" y2="146.05" width="0.1524" layer="91"/> +<wire x1="137.16" y1="146.05" x2="144.78" y2="146.05" width="0.1524" layer="91"/> +<wire x1="144.78" y1="146.05" x2="146.05" y2="146.05" width="0.1524" layer="91"/> +<wire x1="137.16" y1="140.97" x2="137.16" y2="146.05" width="0.1524" layer="91"/> +<wire x1="134.62" y1="140.97" x2="134.62" y2="146.05" width="0.1524" layer="91"/> +<wire x1="144.78" y1="142.24" x2="144.78" y2="146.05" width="0.1524" layer="91"/> +<junction x="134.62" y="146.05"/> +<junction x="137.16" y="146.05"/> +<junction x="144.78" y="146.05"/> +<pinref part="C5F9" gate="C" pin="2"/> +<pinref part="R5F2" gate="R" pin="1"/> +<pinref part="Y5F1" gate="Q" pin="3"/> +<pinref part="Y5F1" gate="Q" pin="2"/> +<pinref part="U6E1" gate="IICHIMCH" pin="RTCX1"/> +</segment> +</net> +<net name="N$581" class="0"> +<segment> +<wire x1="146.05" y1="128.27" x2="144.78" y2="128.27" width="0.1524" layer="91"/> +<wire x1="144.78" y1="128.27" x2="137.16" y2="128.27" width="0.1524" layer="91"/> +<wire x1="137.16" y1="128.27" x2="134.62" y2="128.27" width="0.1524" layer="91"/> +<wire x1="134.62" y1="133.35" x2="134.62" y2="128.27" width="0.1524" layer="91"/> +<wire x1="137.16" y1="133.35" x2="137.16" y2="128.27" width="0.1524" layer="91"/> +<wire x1="127" y1="128.27" x2="134.62" y2="128.27" width="0.1524" layer="91" style="longdash"/> +<wire x1="144.78" y1="132.08" x2="144.78" y2="128.27" width="0.1524" layer="91"/> +<junction x="137.16" y="128.27"/> +<junction x="134.62" y="128.27"/> +<junction x="144.78" y="128.27"/> +<pinref part="Y5F1" gate="Q" pin="1"/> +<pinref part="Y5F1" gate="Q" pin="4"/> +<pinref part="R5F2" gate="R" pin="2"/> +<pinref part="U6E1" gate="IICHIMCH" pin="RTCX2"/> +<pinref part="C5E10" gate="C" pin="2"/> +</segment> +</net> +<net name="GND" class="0"> +<segment> +<wire x1="120.65" y1="146.05" x2="113.03" y2="146.05" width="0.1524" layer="91"/> +<wire x1="113.03" y1="146.05" x2="113.03" y2="137.16" width="0.1524" layer="91"/> +<wire x1="113.03" y1="137.16" x2="113.03" y2="128.27" width="0.1524" layer="91"/> +<wire x1="119.38" y1="128.27" x2="113.03" y2="128.27" width="0.1524" layer="91" style="longdash"/> +<wire x1="115.57" y1="137.16" x2="113.03" y2="137.16" width="0.1524" layer="91" style="longdash"/> +<junction x="113.03" y="137.16"/> +<pinref part="C5F9" gate="C" pin="1"/> +<pinref part="C5E10" gate="C" pin="1"/> +<pinref part="U$502" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="135.89" y1="153.67" x2="133.35" y2="153.67" width="0.1524" layer="91"/> +<wire x1="133.35" y1="153.67" x2="128.27" y2="153.67" width="0.1524" layer="91"/> +<wire x1="128.27" y1="157.48" x2="133.35" y2="157.48" width="0.1524" layer="91"/> +<wire x1="133.35" y1="157.48" x2="133.35" y2="153.67" width="0.1524" layer="91"/> +<junction x="133.35" y="153.67"/> +<pinref part="R3R40" gate="R" pin="2"/> +<pinref part="U$383" gate="G$1" pin="GND"/> +<pinref part="R3R41" gate="R" pin="2"/> +</segment> +<segment> +<wire x1="50.8" y1="38.1" x2="53.34" y2="38.1" width="0.1524" layer="91"/> +<pinref part="U$505" gate="G$1" pin="GND"/> +<pinref part="C-PORT80" gate="1" pin="11"/> +</segment> +<segment> +<wire x1="69.85" y1="38.1" x2="68.58" y2="38.1" width="0.1524" layer="91"/> +<pinref part="U$537" gate="G$1" pin="GND"/> +<pinref part="C-PORT80" gate="1" pin="12"/> +</segment> +<segment> +<wire x1="69.85" y1="43.18" x2="68.58" y2="43.18" width="0.1524" layer="91"/> +<pinref part="U$553" gate="G$1" pin="GND"/> +<pinref part="C-PORT80" gate="1" pin="8"/> +</segment> +<segment> +<wire x1="160.02" y1="67.31" x2="161.29" y2="67.31" width="0.1524" layer="91"/> +<pinref part="U5" gate="U" pin="DGND"/> +<pinref part="U$554" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="160.02" y1="46.99" x2="161.29" y2="46.99" width="0.1524" layer="91"/> +<pinref part="U6" gate="U" pin="DGND"/> +<pinref part="U$562" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="158.75" y1="26.67" x2="161.29" y2="26.67" width="0.1524" layer="91"/> +<pinref part="U7" gate="U" pin="DGND"/> +<pinref part="U$581" gate="G$1" pin="GND"/> +</segment> +</net> +<net name="IMCH-RTCRST-N" class="0"> +<segment> +<wire x1="190.5" y1="139.7" x2="199.39" y2="139.7" width="0.1524" layer="91"/> +<wire x1="199.39" y1="139.7" x2="199.39" y2="142.24" width="0.1524" layer="91"/> +<wire x1="199.39" y1="142.24" x2="218.44" y2="142.24" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IICHIMCH" pin="RTEST_N"/> +<label x="218.44" y="142.24" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="WDT-TOUT-N" class="0"> +<segment> +<wire x1="146.05" y1="110.49" x2="140.97" y2="110.49" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IICHIMCH" pin="WDT_TOUT_N"/> +<label x="140.97" y="110.49" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="VSEL" class="0"> +<segment> +<wire x1="190.5" y1="110.49" x2="201.93" y2="110.49" width="0.1524" layer="91"/> +<wire x1="201.93" y1="110.49" x2="201.93" y2="95.25" width="0.1524" layer="91"/> +<wire x1="201.93" y1="95.25" x2="224.79" y2="95.25" width="0.1524" layer="91"/> +<label x="209.55" y="95.5675" size="1.778" layer="92" rot="MR0"/> +<pinref part="U6E1" gate="IICHIMCH" pin="V_SEL"/> +<pinref part="R3U14" gate="R" pin="2"/> +</segment> +</net> +<net name="TOL-HOT-PLUG-N" class="0"> +<segment> +<wire x1="224.79" y1="101.6" x2="204.47" y2="101.6" width="0.1524" layer="91"/> +<wire x1="204.47" y1="101.6" x2="204.47" y2="113.03" width="0.1524" layer="91"/> +<wire x1="204.47" y1="113.03" x2="190.5" y2="113.03" width="0.1524" layer="91"/> +<pinref part="R5T20" gate="R" pin="2"/> +<pinref part="U6E1" gate="IICHIMCH" pin="PE_HPINTR_N"/> +</segment> +</net> +<net name="IMCH-RSMRST-N" class="0"> +<segment> +<wire x1="67.31" y1="73.66" x2="40.64" y2="73.66" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="RSMRST_N"/> +<label x="67.31" y="73.66" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="ICH-33MHZ-CLK-R" class="0"> +<segment> +<wire x1="41.91" y1="15.24" x2="85.09" y2="15.24" width="0.1524" layer="91"/> +<label x="59.055" y="15.748" size="1.778" layer="92"/> +<pinref part="U6E1" gate="LPC11" pin="PCICLK"/> +<label x="85.09" y="15.24" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="GPIO3" class="0"> +<segment> +<wire x1="209.55" y1="132.08" x2="207.01" y2="130.81" width="0.1524" layer="91"/> +<wire x1="190.5" y1="130.81" x2="207.01" y2="130.81" width="0.1524" layer="91"/> +<label x="195.58" y="131.1275" size="1.778" layer="92"/> +<pinref part="U6E1" gate="IICHIMCH" pin="GP3_PIRQF_N"/> +</segment> +<segment> +<wire x1="209.55" y1="132.08" x2="212.09" y2="130.81" width="0.1524" layer="91"/> +<wire x1="212.09" y1="130.81" x2="224.79" y2="130.81" width="0.1524" layer="91"/> +<pinref part="R3T5" gate="R" pin="2"/> +</segment> +</net> +<net name="IMCH-SER-IRQ" class="0"> +<segment> +<wire x1="190.5" y1="121.92" x2="209.55" y2="121.92" width="0.1524" layer="91"/> +<wire x1="209.55" y1="121.92" x2="224.79" y2="121.92" width="0.1524" layer="91"/> +<wire x1="209.55" y1="121.92" x2="209.55" y2="113.03" width="0.1524" layer="91"/> +<wire x1="209.55" y1="113.03" x2="226.06" y2="113.03" width="0.1524" layer="91"/> +<junction x="209.55" y="121.92"/> +<pinref part="R2H12" gate="R" pin="1"/> +<pinref part="U6E1" gate="IICHIMCH" pin="SERIRQ"/> +<label x="226.06" y="113.03" size="1.778" layer="92" xref="yes"/> +</segment> +<segment> +<wire x1="68.58" y1="48.26" x2="102.87" y2="48.26" width="0.1524" layer="91"/> +<pinref part="C-PORT80" gate="1" pin="4"/> +<label x="102.87" y="48.26" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="234.95" y1="121.92" x2="251.46" y2="121.92" width="0.1524" layer="91"/> +<wire x1="251.46" y1="121.92" x2="251.46" y2="125.73" width="0.1524" layer="91"/> +<wire x1="251.46" y1="125.73" x2="251.46" y2="128.27" width="0.1524" layer="91"/> +<wire x1="251.46" y1="128.27" x2="251.46" y2="130.81" width="0.1524" layer="91"/> +<wire x1="251.46" y1="130.81" x2="251.46" y2="133.35" width="0.1524" layer="91"/> +<wire x1="251.46" y1="133.35" x2="251.46" y2="137.16" width="0.1524" layer="91"/> +<wire x1="234.95" y1="125.73" x2="251.46" y2="125.73" width="0.1524" layer="91"/> +<wire x1="234.95" y1="128.27" x2="251.46" y2="128.27" width="0.1524" layer="91"/> +<wire x1="234.95" y1="130.81" x2="251.46" y2="130.81" width="0.1524" layer="91"/> +<wire x1="234.95" y1="133.35" x2="251.46" y2="133.35" width="0.1524" layer="91"/> +<junction x="251.46" y="125.73"/> +<junction x="251.46" y="128.27"/> +<junction x="251.46" y="130.81"/> +<junction x="251.46" y="133.35"/> +<pinref part="R2H12" gate="R" pin="2"/> +<pinref part="U$567" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R3U16" gate="R" pin="1"/> +<pinref part="R3T4" gate="R" pin="1"/> +<pinref part="R3T5" gate="R" pin="1"/> +<pinref part="R3T6" gate="R" pin="1"/> +</segment> +<segment> +<pinref part="R3U14" gate="R" pin="1"/> +<wire x1="245.11" y1="95.25" x2="234.95" y2="95.25" width="0.1524" layer="91"/> +<wire x1="234.95" y1="101.6" x2="245.11" y2="101.6" width="0.1524" layer="91"/> +<pinref part="R5T20" gate="R" pin="1"/> +<pinref part="U$54" gate="PW-VCC3" pin="VCC3"/> +<wire x1="245.11" y1="101.6" x2="252.73" y2="101.6" width="0.1524" layer="91"/> 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x2="161.29" y2="80.01" width="0.1524" layer="91"/> +<pinref part="U5" gate="U" pin="VCC"/> +<pinref part="U$535" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="149.86" y1="63.5" x2="149.86" y2="59.69" width="0.1524" layer="91"/> +<wire x1="149.86" y1="59.69" x2="161.29" y2="59.69" width="0.1524" layer="91"/> +<pinref part="U6" gate="U" pin="VCC"/> +<pinref part="U$561" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="109.22" y1="21.59" x2="111.76" y2="21.59" width="0.1524" layer="91"/> +<wire x1="111.76" y1="21.59" x2="111.76" y2="30.48" width="0.1524" layer="91"/> +<pinref part="R5T9" gate="R" pin="1"/> +<pinref part="U$66" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="104.14" y1="69.85" x2="104.14" y2="68.58" width="0.1524" layer="91"/> +<wire x1="104.14" y1="68.58" x2="86.36" y2="68.58" width="0.1524" layer="91"/> +<pinref part="R27" gate="R" pin="2"/> +<pinref part="U$62" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="88.9" y1="118.11" x2="95.25" y2="118.11" width="0.1524" layer="91"/> +<wire x1="95.25" y1="118.11" x2="95.25" y2="120.65" width="0.1524" layer="91"/> +<wire x1="88.9" y1="114.3" x2="95.25" y2="114.3" width="0.1524" layer="91"/> +<wire x1="95.25" y1="114.3" x2="95.25" y2="118.11" width="0.1524" layer="91"/> +<junction x="95.25" y="118.11"/> +<pinref part="R5T18" gate="R" pin="1"/> +<pinref part="R5T19" gate="R" pin="1"/> +<pinref part="U$53" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="90.17" y1="81.28" x2="104.14" y2="81.28" width="0.1524" layer="91"/> +<wire x1="104.14" y1="81.28" x2="104.14" y2="86.36" width="0.1524" layer="91"/> +<pinref part="R5E9" gate="R" pin="1"/> +<pinref part="U$85" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="ICH-14MHZ-CLK-R" class="0"> +<segment> +<wire x1="190.5" y1="115.57" x2="207.01" y2="115.57" width="0.1524" layer="91"/> +<wire x1="207.01" y1="115.57" x2="207.01" y2="109.22" width="0.1524" layer="91"/> +<wire x1="207.01" y1="109.22" x2="224.79" y2="109.22" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IICHIMCH" pin="CLK14"/> +<label x="224.79" y="109.22" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="SYS-PWR-OK" class="0"> +<segment> +<wire x1="40.64" y1="88.9" x2="44.45" y2="88.9" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="POWERMANAGE" pin="PWROK"/> +<label x="44.45" y="88.9" size="1.778" layer="92" xref="yes"/> +</segment> +<segment> +<wire x1="218.44" y1="148.59" x2="222.25" y2="148.59" width="0.1524" layer="91"/> +<label x="222.25" y="148.59" size="1.778" layer="92" xref="yes"/> +<wire x1="208.28" y1="148.59" x2="190.5" y2="148.59" width="0.1524" layer="91"/> +<label x="193.9925" y="148.9075" size="1.778" layer="92"/> +<pinref part="U6E1" gate="IICHIMCH" pin="PWRGD"/> +<wire x1="218.44" y1="148.59" x2="208.28" y2="148.59" width="0.1524" layer="91"/> +</segment> +</net> +<net name="GPIO2" class="0"> +<segment> +<wire x1="209.55" y1="134.62" x2="207.01" y2="133.35" width="0.1524" layer="91"/> +<wire x1="190.5" y1="133.35" x2="207.01" y2="133.35" width="0.1524" layer="91"/> +<label x="195.58" y="133.6675" size="1.778" layer="92"/> +<pinref part="U6E1" gate="IICHIMCH" pin="GP2_PIRQE_N"/> +</segment> +<segment> +<wire x1="224.79" y1="133.35" x2="212.09" y2="133.35" width="0.1524" layer="91"/> +<wire x1="209.55" y1="134.62" x2="212.09" y2="133.35" width="0.1524" layer="91"/> +<pinref part="R3T6" gate="R" pin="2"/> +</segment> +</net> +<net name="GPIO4" class="0"> +<segment> +<wire x1="209.55" y1="129.54" x2="207.01" y2="128.27" width="0.1524" layer="91"/> +<wire x1="207.01" y1="128.27" x2="190.5" y2="128.27" width="0.1524" layer="91"/> +<label x="195.58" y="128.5875" size="1.778" layer="92"/> +<pinref part="U6E1" gate="IICHIMCH" pin="GP4_PIRQG_N"/> +</segment> +<segment> +<wire x1="209.55" y1="129.54" x2="212.09" y2="128.27" width="0.1524" layer="91"/> +<wire x1="212.09" y1="128.27" x2="213.36" y2="128.27" width="0.1524" layer="91"/> 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x1="118.11" y1="157.48" x2="106.68" y2="157.48" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IEEE1588" pin="ASMSSIG"/> +<pinref part="R3R41" gate="R" pin="1"/> +</segment> +</net> +<net name="N$132" class="0"> +<segment> +<wire x1="118.11" y1="153.67" x2="106.68" y2="153.67" width="0.1524" layer="91"/> +<pinref part="U6E1" gate="IEEE1588" pin="AMMSSIG"/> +<pinref part="R3R40" gate="R" pin="1"/> +</segment> +</net> +<net name="PORT80-33MHZ-CLK-R" class="0"> +<segment> +<wire x1="68.58" y1="40.64" x2="85.09" y2="40.64" width="0.1524" layer="91"/> +<pinref part="C-PORT80" gate="1" pin="10"/> +<label x="85.09" y="40.64" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="EP0-INT-N" class="0"> +<segment> +<wire x1="227.33" y1="81.28" x2="234.95" y2="81.28" width="0.1524" layer="91"/> +<pinref part="R12" gate="R" pin="2"/> +<label x="234.95" y="81.28" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="GP18" class="0"> +<segment> +<wire x1="147.32" y1="35.56" x2="158.75" y2="35.56" width="0.1524" layer="91"/> +<pinref part="U7" gate="U" pin="I0"/> +<label x="147.32" y="35.56" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="GP25" class="0"> +<segment> +<wire x1="147.32" y1="71.12" x2="158.75" y2="71.12" width="0.1524" layer="91"/> +<pinref part="U5" gate="U" pin="I1"/> +<label x="147.32" y="71.12" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="M88E1141-RST-N" class="0"> +<segment> +<wire x1="180.34" y1="33.02" x2="209.55" y2="33.02" width="0.1524" layer="91"/> +<pinref part="U7" gate="U" pin="O"/> +<label x="209.55" y="33.02" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="XHFC-RST-N" class="0"> +<segment> +<wire x1="180.34" y1="53.34" x2="209.55" y2="53.34" width="0.1524" layer="91"/> +<pinref part="U6" gate="U" pin="O"/> +<label x="209.55" y="53.34" size="1.778" layer="92" xref="yes"/> +</segment> +</net> +<net name="FXOFXS-RST-N" class="0"> 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x1="171.45" y1="149.86" x2="133.35" y2="149.86" width="0.1524" layer="91"/> +<label x="81.28" y="149.86" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="UF1" gate="CLKGP" pin="/INT"/> +<wire x1="133.35" y1="149.86" x2="81.28" y2="149.86" width="0.1524" layer="91"/> +<wire x1="129.54" y1="157.48" x2="133.35" y2="157.48" width="0.1524" layer="91"/> +<wire x1="133.35" y1="157.48" x2="133.35" y2="149.86" width="0.1524" layer="91"/> +<junction x="133.35" y="149.86"/> +<pinref part="RF3" gate="R" pin="2"/> +</segment> +</net> +<net name="FXN1" class="0"> +<segment> +<wire x1="81.28" y1="54.61" x2="73.66" y2="54.61" width="0.1524" layer="91"/> +<wire x1="73.66" y1="54.61" x2="71.12" y2="54.61" width="0.1524" layer="91"/> +<wire x1="71.12" y1="54.61" x2="71.12" y2="49.53" width="0.1524" layer="91"/> +<wire x1="71.12" y1="54.61" x2="71.12" y2="57.15" width="0.1524" layer="91"/> +<wire x1="73.66" y1="54.61" x2="73.66" y2="57.15" width="0.1524" layer="91"/> +<junction x="71.12" y="54.61"/> +<junction x="73.66" y="54.61"/> +<pinref part="LFSA1" gate="L" pin="2"/> +<pinref part="QFSA1" gate="G$1" pin="C"/> +<pinref part="QFSA1" gate="G$1" pin="C@2"/> +<pinref part="DFSA1" gate="G$1" pin="C"/> +</segment> +</net> +<net name="FX-VREF" class="0"> +<segment> +<wire x1="217.17" y1="109.22" x2="217.17" y2="101.6" width="0.1524" layer="91"/> +<wire x1="217.17" y1="101.6" x2="212.09" y2="101.6" width="0.1524" layer="91"/> +<wire x1="217.17" y1="87.63" x2="217.17" y2="92.71" width="0.1524" layer="91"/> +<wire x1="217.17" y1="92.71" x2="180.34" y2="92.71" width="0.1524" layer="91"/> +<wire x1="217.17" y1="92.71" x2="217.17" y2="101.6" width="0.1524" layer="91"/> +<junction x="217.17" y="92.71"/> +<junction x="217.17" y="101.6"/> +<pinref part="CFHLT1" gate="C" pin="2"/> +<pinref part="U$360" gate="FX-VREF" pin="FX-VREF"/> +<pinref part="CFREF1" gate="C" pin="1"/> +<pinref part="UF1" gate="SW" pin="VREF"/> +</segment> +</net> +<net name="FX-VBAT" class="0"> +<segment> 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width="0.1524" layer="91"/> +<wire x1="212.09" y1="27.94" x2="214.63" y2="27.94" width="0.1524" layer="91"/> +<wire x1="214.63" y1="27.94" x2="220.98" y2="27.94" width="0.1524" layer="91"/> +<wire x1="220.98" y1="27.94" x2="223.52" y2="27.94" width="0.1524" layer="91"/> +<wire x1="223.52" y1="27.94" x2="245.11" y2="27.94" width="0.1524" layer="91"/> +<wire x1="245.11" y1="27.94" x2="250.19" y2="27.94" width="0.1524" layer="91"/> +<wire x1="180.34" y1="27.94" x2="185.42" y2="27.94" width="0.1524" layer="91"/> +<wire x1="185.42" y1="27.94" x2="190.5" y2="27.94" width="0.1524" layer="91"/> +<wire x1="190.5" y1="40.64" x2="190.5" y2="27.94" width="0.1524" layer="91"/> +<wire x1="185.42" y1="40.64" x2="185.42" y2="27.94" width="0.1524" layer="91"/> +<wire x1="180.34" y1="40.64" x2="180.34" y2="27.94" width="0.1524" layer="91"/> +<wire x1="250.19" y1="40.64" x2="250.19" y2="27.94" width="0.1524" layer="91"/> +<wire x1="245.11" y1="40.64" x2="245.11" y2="27.94" width="0.1524" layer="91"/> +<wire x1="212.09" y1="30.48" x2="212.09" y2="27.94" width="0.1524" layer="91"/> +<wire x1="214.63" y1="30.48" x2="214.63" y2="27.94" width="0.1524" layer="91"/> +<wire x1="220.98" y1="30.48" x2="220.98" y2="27.94" width="0.1524" layer="91"/> +<wire x1="223.52" y1="30.48" x2="223.52" y2="27.94" width="0.1524" layer="91"/> +<wire x1="180.34" y1="27.94" x2="180.34" y2="26.67" width="0.1524" layer="91"/> +<junction x="190.5" y="27.94"/> +<junction x="185.42" y="27.94"/> +<junction x="245.11" y="27.94"/> +<junction x="212.09" y="27.94"/> +<junction x="214.63" y="27.94"/> +<junction x="220.98" y="27.94"/> +<junction x="223.52" y="27.94"/> +<junction x="180.34" y="27.94"/> +<pinref part="U$488" gate="G$1" pin="GND"/> +<pinref part="CFE1" gate="C" pin="1"/> +<pinref part="UF1" gate="PWR" pin="DGND@1"/> +<pinref part="UF1" gate="PWR" pin="DGND@2"/> +<pinref part="UF1" gate="PWR" pin="AGND@1"/> +<pinref part="UF1" gate="PWR" pin="1GND@2"/> +<pinref part="CFB1" gate="C" pin="1"/> +<pinref part="CFC1" gate="C" pin="1"/> +<pinref part="CFD1" gate="C" pin="1"/> +<pinref part="CFF1" gate="C" pin="1"/> +<pinref part="CFG1" gate="C" pin="2"/> +<wire x1="256.54" y1="40.64" x2="256.54" y2="27.94" width="0.1524" layer="91"/> +<wire x1="256.54" y1="27.94" x2="250.19" y2="27.94" width="0.1524" layer="91"/> +<junction x="250.19" y="27.94"/> +</segment> +<segment> +<wire x1="92.71" y1="68.58" x2="92.71" y2="64.77" width="0.1524" layer="91"/> +<wire x1="92.71" y1="64.77" x2="90.17" y2="64.77" width="0.1524" layer="91"/> +<wire x1="90.17" y1="64.77" x2="82.55" y2="64.77" width="0.1524" layer="91"/> +<wire x1="82.55" y1="64.77" x2="82.55" y2="68.58" width="0.1524" layer="91"/> +<wire x1="90.17" y1="64.77" x2="90.17" y2="63.5" width="0.1524" layer="91"/> +<junction x="90.17" y="64.77"/> +<pinref part="CFSB1" gate="C" pin="1"/> +<pinref part="CFSA1" gate="C" pin="-"/> +<pinref part="U$523" gate="G$1" pin="GND"/> +</segment> +<segment> +<wire x1="152.4" y1="36.83" x2="152.4" y2="21.59" width="0.1524" layer="91"/> +<wire x1="160.02" y1="21.59" x2="152.4" y2="21.59" width="0.1524" layer="91"/> +<wire x1="152.4" y1="21.59" x2="129.54" y2="21.59" width="0.1524" layer="91"/> +<wire x1="129.54" y1="21.59" x2="120.65" y2="21.59" width="0.1524" layer="91"/> +<wire x1="120.65" y1="34.29" x2="120.65" y2="21.59" width="0.1524" layer="91"/> +<wire x1="120.65" y1="21.59" x2="114.3" y2="21.59" width="0.1524" layer="91"/> +<wire x1="114.3" y1="21.59" x2="91.44" y2="21.59" width="0.1524" layer="91"/> +<wire x1="91.44" y1="21.59" x2="71.12" y2="21.59" width="0.1524" layer="91"/> +<wire x1="71.12" y1="21.59" x2="71.12" y2="25.4" width="0.1524" layer="91"/> +<wire x1="71.12" y1="20.32" x2="71.12" y2="21.59" width="0.1524" layer="91"/> +<wire x1="71.12" y1="21.59" x2="43.18" y2="21.59" width="0.1524" layer="91"/> +<wire x1="43.18" y1="30.48" x2="43.18" y2="21.59" width="0.1524" layer="91"/> +<wire x1="43.18" y1="21.59" x2="30.48" y2="21.59" width="0.1524" layer="91"/> +<wire x1="30.48" y1="21.59" x2="30.48" y2="31.75" width="0.1524" layer="91"/> +<wire x1="91.44" y1="25.4" x2="91.44" y2="21.59" width="0.1524" layer="91"/> +<wire x1="114.3" y1="34.29" x2="114.3" y2="21.59" width="0.1524" layer="91"/> +<wire x1="161.29" y1="36.83" x2="161.29" y2="21.59" width="0.1524" layer="91"/> +<wire x1="161.29" y1="21.59" x2="160.02" y2="21.59" width="0.1524" layer="91"/> +<junction x="152.4" y="21.59"/> +<junction x="120.65" y="21.59"/> +<junction x="71.12" y="21.59"/> +<junction x="43.18" y="21.59"/> +<junction x="91.44" y="21.59"/> +<junction x="114.3" y="21.59"/> +<pinref part="CFSH1" gate="C" pin="1"/> +<pinref part="CFSG1" gate="C" pin="1"/> +<pinref part="RFSB1" gate="G$1" pin="1"/> +<pinref part="RFSC1" gate="G$1" pin="2"/> +<pinref part="CFSD1" gate="C" pin="2"/> +<pinref part="U$528" gate="G$1" pin="GND"/> +<pinref part="RFLMB1" gate="G$1" pin="1"/> +<pinref part="CFSF1" gate="C" pin="+"/> +<pinref part="CFSJ1" gate="C" pin="+"/> +<pinref part="CFSG2" gate="C" pin="1"/> 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+<pinref part="U$606" gate="G$1" pin="GND"/> +<pinref part="RF2" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="UF1" gate="SW" pin="CSMODE"/> +<pinref part="U$552" gate="G$1" pin="GND"/> +<wire x1="185.42" y1="105.41" x2="180.34" y2="105.41" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FXN3" class="0"> +<segment> +<wire x1="78.74" y1="102.87" x2="86.36" y2="102.87" width="0.1524" layer="91"/> +<pinref part="CFSE1" gate="C" pin="1"/> +<pinref part="RFSE1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FXN4" class="0"> +<segment> +<wire x1="71.12" y1="102.87" x2="62.23" y2="102.87" width="0.1524" layer="91"/> +<wire x1="62.23" y1="102.87" x2="62.23" y2="109.22" width="0.1524" layer="91"/> +<wire x1="101.6" y1="92.71" x2="101.6" y2="99.06" width="0.1524" layer="91"/> +<wire x1="62.23" y1="109.22" x2="78.74" y2="109.22" width="0.1524" layer="91"/> +<pinref part="CFSE1" gate="C" pin="2"/> +<pinref part="CFSL1" gate="C" pin="2"/> +<pinref part="RFVS1" gate="G$1" pin="2"/> +<pinref part="UF1" gate="SW" pin="SWVS"/> +<wire x1="144.78" y1="99.06" x2="101.6" y2="99.06" width="0.1524" layer="91"/> +<junction x="101.6" y="99.06"/> +<wire x1="101.6" y1="99.06" x2="62.23" y2="99.06" width="0.1524" layer="91"/> +<wire x1="62.23" y1="99.06" x2="62.23" y2="102.87" width="0.1524" layer="91"/> +<junction x="62.23" y="102.87"/> +</segment> +</net> +<net name="FXN18" class="0"> +<segment> +<wire x1="144.78" y1="86.36" x2="106.68" y2="86.36" width="0.1524" layer="91"/> +<wire x1="106.68" y1="86.36" x2="106.68" y2="36.83" width="0.1524" layer="91"/> +<wire x1="106.68" y1="36.83" x2="91.44" y2="36.83" width="0.1524" layer="91"/> +<wire x1="91.44" y1="36.83" x2="87.63" y2="36.83" width="0.1524" layer="91"/> +<wire x1="91.44" y1="33.02" x2="91.44" y2="36.83" width="0.1524" layer="91"/> +<junction x="91.44" y="36.83"/> +<pinref part="RFSD1" gate="G$1" pin="1"/> +<pinref part="CFSD1" gate="C" pin="1"/> +<pinref part="UF1" gate="SW" pin="SWIS"/> +</segment> +</net> +<net name="FXN5" class="0"> +<segment> +<wire x1="96.52" y1="102.87" x2="105.41" y2="102.87" width="0.1524" layer="91"/> +<wire x1="105.41" y1="102.87" x2="105.41" y2="109.22" width="0.1524" layer="91"/> +<wire x1="105.41" y1="109.22" x2="86.36" y2="109.22" width="0.1524" layer="91"/> +<pinref part="RFSE1" gate="G$1" pin="1"/> +<pinref part="CFSL1" gate="C" pin="1"/> +<pinref part="UF1" gate="SW" pin="SWCMP"/> +<wire x1="105.41" y1="102.87" x2="144.78" y2="102.87" width="0.1524" layer="91"/> +<junction x="105.41" y="102.87"/> +</segment> +</net> +<net name="FXN6" class="0"> +<segment> +<wire x1="144.78" y1="96.52" x2="30.48" y2="96.52" width="0.1524" layer="91"/> +<wire x1="30.48" y1="96.52" x2="30.48" y2="49.53" width="0.1524" layer="91"/> +<wire x1="30.48" y1="49.53" x2="30.48" y2="41.91" width="0.1524" layer="91"/> +<wire x1="30.48" y1="49.53" x2="38.1" y2="49.53" width="0.1524" layer="91"/> +<junction x="30.48" y="49.53"/> +<pinref part="RFSC1" gate="G$1" pin="1"/> +<pinref part="QFSB1" gate="Q" pin="B"/> +<pinref part="UF1" gate="SW" pin="/SWOUT"/> +</segment> +</net> +<net name="FXN7" class="0"> +<segment> +<wire x1="144.78" y1="93.98" x2="35.56" y2="93.98" width="0.1524" layer="91"/> +<wire x1="35.56" y1="78.74" x2="35.56" y2="93.98" width="0.1524" layer="91"/> +<pinref part="CFSC1" gate="C" pin="2"/> +<pinref part="UF1" gate="SW" pin="SWOUT"/> +</segment> +</net> +<net name="FXN11" class="0"> +<segment> +<wire x1="43.18" y1="67.31" x2="43.18" y2="62.23" width="0.1524" layer="91"/> +<wire x1="43.18" y1="62.23" x2="35.56" y2="62.23" width="0.1524" layer="91"/> +<wire x1="35.56" y1="62.23" x2="35.56" y2="71.12" width="0.1524" layer="91"/> +<wire x1="43.18" y1="62.23" x2="58.42" y2="62.23" width="0.1524" layer="91"/> +<wire x1="58.42" y1="62.23" x2="66.04" y2="62.23" width="0.1524" layer="91"/> +<wire x1="58.42" y1="66.04" x2="58.42" y2="62.23" width="0.1524" layer="91"/> +<wire x1="43.18" y1="52.07" x2="43.18" y2="62.23" width="0.1524" layer="91"/> +<junction x="43.18" y="62.23"/> +<junction x="58.42" y="62.23"/> +<pinref part="RFSA1" gate="G$1" pin="1"/> +<pinref part="CFSC1" gate="C" pin="1"/> +<pinref part="QFSB1" gate="Q" pin="C"/> +<pinref part="QFSA1" gate="G$1" pin="B"/> +<pinref part="DFSB1" gate="D" pin="A"/> +</segment> +</net> +<net name="FXN25" class="0"> +<segment> +<wire x1="43.18" y1="40.64" x2="43.18" y2="46.99" width="0.1524" layer="91"/> +<pinref part="RFSB1" gate="G$1" pin="2"/> +<pinref part="QFSB1" gate="Q" pin="E"/> +</segment> +</net> +<net name="FXN16" class="0"> +<segment> +<wire x1="71.12" y1="35.56" x2="71.12" y2="36.83" width="0.1524" layer="91"/> +<wire x1="71.12" y1="36.83" x2="71.12" y2="39.37" width="0.1524" layer="91"/> +<wire x1="71.12" y1="36.83" x2="77.47" y2="36.83" width="0.1524" layer="91"/> +<junction x="71.12" y="36.83"/> +<pinref part="LFSA1" gate="L" pin="1"/> +<pinref part="RFSD1" gate="G$1" pin="2"/> +<pinref part="RFLMB1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FXN13" class="0"> +<segment> +<wire x1="91.44" y1="54.61" x2="101.6" y2="54.61" width="0.1524" layer="91"/> +<wire x1="101.6" y1="54.61" x2="114.3" y2="54.61" width="0.1524" layer="91"/> +<wire x1="114.3" y1="54.61" x2="120.65" y2="54.61" width="0.1524" layer="91"/> +<wire x1="120.65" y1="54.61" x2="129.54" y2="54.61" width="0.1524" layer="91"/> +<wire x1="129.54" y1="54.61" x2="137.16" y2="54.61" width="0.1524" layer="91"/> +<wire x1="120.65" y1="41.91" x2="120.65" y2="54.61" width="0.1524" layer="91"/> +<wire x1="101.6" y1="82.55" x2="101.6" y2="54.61" width="0.1524" layer="91"/> +<wire x1="114.3" y1="41.91" x2="114.3" y2="54.61" width="0.1524" layer="91"/> +<junction x="120.65" y="54.61"/> +<junction x="101.6" y="54.61"/> +<junction x="114.3" y="54.61"/> +<pinref part="CFSG1" gate="C" pin="2"/> +<pinref part="RFVS1" gate="G$1" pin="1"/> +<pinref part="LFSB1" gate="G$1" pin="1"/> +<pinref part="DFSA1" gate="G$1" pin="A"/> +<pinref part="CFSF1" gate="C" pin="-"/> +<pinref part="CFSG2" gate="C" pin="2"/> +<wire x1="129.54" y1="41.91" x2="129.54" y2="54.61" width="0.1524" layer="91"/> +<junction x="129.54" y="54.61"/> +</segment> +</net> +<net name="FXN19" class="0"> +<segment> +<wire x1="180.34" y1="96.52" x2="189.23" y2="96.52" width="0.1524" layer="91"/> +<pinref part="RFREF1" gate="G$1" pin="1"/> +<pinref part="UF1" gate="SW" pin="IREF"/> +</segment> +</net> +<net name="FXN20" class="0"> +<segment> +<wire x1="180.34" y1="101.6" x2="204.47" y2="101.6" width="0.1524" layer="91"/> +<pinref part="CFHLT1" gate="C" pin="1"/> +<pinref part="UF1" gate="SW" pin="IHL"/> +</segment> +</net> +<net name="FXN22" class="0"> +<segment> +<wire x1="144.78" y1="106.68" x2="134.62" y2="106.68" width="0.1524" layer="91"/> +<pinref part="CFLFC1" gate="C" pin="2"/> +<pinref part="UF1" gate="SW" pin="LFC"/> +</segment> +</net> +<net name="HSS-RXDATA1" class="0"> +<segment> +<wire x1="171.45" y1="129.54" x2="167.64" y2="129.54" width="0.1524" layer="91"/> +<label x="161.29" y="129.54" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="UF1" gate="CLKGP" pin="DXA"/> +<wire x1="167.64" y1="129.54" x2="161.29" y2="129.54" width="0.1524" layer="91"/> +<wire x1="158.75" y1="119.38" x2="167.64" y2="119.38" width="0.1524" layer="91"/> +<wire x1="167.64" y1="119.38" x2="167.64" y2="129.54" width="0.1524" layer="91"/> +<junction x="167.64" y="129.54"/> +<pinref part="RF9" gate="R" pin="2"/> +</segment> +</net> +<net name="HSS-TXDATA1" class="0"> +<segment> +<wire x1="171.45" y1="132.08" x2="128.27" y2="132.08" width="0.1524" layer="91"/> +<label x="128.27" y="132.08" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="UF1" gate="CLKGP" pin="DRA"/> +</segment> +</net> +<net name="SSPS-CLK" class="0"> +<segment> +<label x="86.36" y="139.7" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="RF8" gate="R" pin="2"/> +<wire x1="134.62" y1="139.7" x2="86.36" y2="139.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SSPS-FRM" class="0"> +<segment> +<label x="109.22" y="147.32" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="RF1" gate="R" pin="2"/> +<wire x1="134.62" y1="147.32" x2="109.22" y2="147.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SSPS-TXD" class="0"> +<segment> +<label x="109.22" y="142.24" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="RF7" gate="R" pin="2"/> +<wire x1="134.62" y1="142.24" x2="109.22" y2="142.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="SSPS-RXD" class="0"> +<segment> +<label x="86.36" y="144.78" size="1.778" layer="92" rot="R180" xref="yes"/> +<wire x1="134.62" y1="144.78" x2="130.81" y2="144.78" width="0.1524" layer="91"/> +<wire x1="130.81" y1="144.78" x2="86.36" y2="144.78" width="0.1524" layer="91"/> +<wire x1="130.81" y1="144.78" x2="130.81" y2="119.38" width="0.1524" layer="91"/> +<junction x="130.81" y="144.78"/> +<wire x1="130.81" y1="119.38" x2="102.87" y2="119.38" width="0.1524" layer="91"/> +<pinref part="R19" gate="R" pin="2"/> +<pinref part="RF6" gate="R" pin="2"/> +</segment> +</net> +<net name="FX-FRM" class="0"> +<segment> +<wire x1="171.45" y1="147.32" x2="144.78" y2="147.32" width="0.1524" layer="91"/> +<pinref part="UF1" gate="CLKGP" pin="/CS"/> +<pinref part="RF1" gate="R" pin="1"/> +</segment> +</net> +<net name="FX-RXD" class="0"> +<segment> +<wire x1="171.45" y1="144.78" x2="144.78" y2="144.78" width="0.1524" layer="91"/> +<pinref part="UF1" gate="CLKGP" pin="DOUT"/> +<pinref part="RF6" gate="R" pin="1"/> +</segment> +</net> +<net name="FX-TXD" class="0"> +<segment> +<wire x1="171.45" y1="142.24" x2="144.78" y2="142.24" width="0.1524" layer="91"/> +<pinref part="UF1" gate="CLKGP" pin="DIN"/> +<pinref part="RF7" gate="R" pin="1"/> +</segment> +</net> +<net name="FX-CLK" class="0"> +<segment> +<wire x1="171.45" y1="139.7" x2="144.78" y2="139.7" width="0.1524" layer="91"/> +<pinref part="UF1" gate="CLKGP" pin="DCLK"/> +<pinref part="RF8" gate="R" pin="1"/> +</segment> +</net> +<net name="FX-AVDD" class="0"> +<segment> +<wire x1="250.19" y1="48.26" x2="250.19" y2="60.96" width="0.1524" layer="91"/> +<wire x1="245.11" y1="60.96" x2="250.19" y2="60.96" width="0.1524" layer="91"/> +<wire x1="245.11" y1="48.26" x2="245.11" y2="60.96" width="0.1524" layer="91"/> +<wire x1="220.98" y1="57.15" x2="220.98" y2="60.96" width="0.1524" layer="91"/> +<wire x1="220.98" y1="60.96" x2="223.52" y2="60.96" width="0.1524" layer="91"/> +<wire x1="223.52" y1="60.96" x2="227.33" y2="60.96" width="0.1524" layer="91"/> +<wire x1="227.33" y1="60.96" x2="245.11" y2="60.96" width="0.1524" layer="91"/> +<wire x1="223.52" y1="57.15" x2="223.52" y2="60.96" width="0.1524" layer="91"/> +<wire x1="224.79" y1="66.04" x2="227.33" y2="66.04" width="0.1524" layer="91"/> +<wire x1="227.33" y1="66.04" x2="227.33" y2="60.96" width="0.1524" layer="91"/> +<wire x1="227.33" y1="60.96" x2="223.52" y2="60.96" width="0.1524" layer="91"/> +<junction x="245.11" y="60.96"/> +<junction x="223.52" y="60.96"/> +<junction x="227.33" y="60.96"/> +<junction x="250.19" y="60.96"/> +<pinref part="RFAV1" gate="G$1" pin="2"/> +<pinref part="CFE1" gate="C" pin="2"/> +<pinref part="UF1" gate="PWR" pin="AVDD@1"/> +<pinref part="UF1" gate="PWR" pin="AVDD@2"/> +<pinref part="CFF1" gate="C" pin="2"/> +<pinref part="CFG1" gate="C" pin="1"/> +<wire x1="250.19" y1="60.96" x2="256.54" y2="60.96" width="0.1524" layer="91"/> +<wire x1="256.54" y1="60.96" x2="256.54" y2="48.26" width="0.1524" layer="91"/> +<label x="229.87" y="62.23" size="1.778" layer="92"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="148.59" y1="119.38" x2="138.43" y2="119.38" width="0.1524" layer="91"/> +<pinref part="U$64" gate="PW-VCC3" pin="VCC3"/> +<pinref part="RF9" gate="R" pin="1"/> +</segment> +<segment> +<pinref part="U$43" gate="PW-VCC3" pin="VCC3"/> +<pinref part="R19" gate="R" pin="1"/> +<wire x1="92.71" y1="119.38" x2="72.39" y2="119.38" width="0.1524" layer="91"/> +</segment> +<segment> +<wire x1="190.5" y1="48.26" x2="190.5" y2="60.96" width="0.1524" layer="91"/> +<wire x1="185.42" y1="60.96" x2="190.5" y2="60.96" width="0.1524" layer="91"/> +<wire x1="185.42" y1="48.26" x2="185.42" y2="60.96" width="0.1524" layer="91"/> +<wire x1="180.34" y1="60.96" x2="185.42" y2="60.96" width="0.1524" layer="91"/> +<wire x1="180.34" y1="48.26" x2="180.34" y2="60.96" width="0.1524" layer="91"/> +<wire x1="190.5" y1="60.96" x2="212.09" y2="60.96" width="0.1524" layer="91"/> +<wire x1="212.09" y1="60.96" x2="214.63" y2="60.96" width="0.1524" layer="91"/> +<wire x1="214.63" y1="60.96" x2="214.63" y2="57.15" width="0.1524" layer="91"/> +<wire x1="212.09" y1="57.15" x2="212.09" y2="60.96" width="0.1524" layer="91"/> +<wire x1="214.63" y1="66.04" x2="212.09" y2="66.04" width="0.1524" layer="91"/> +<wire x1="212.09" y1="66.04" x2="212.09" y2="60.96" width="0.1524" layer="91"/> +<wire x1="180.34" y1="60.96" x2="180.34" y2="62.23" width="0.1524" layer="91"/> +<junction x="190.5" y="60.96"/> +<junction x="185.42" y="60.96"/> +<junction x="212.09" y="60.96"/> +<junction x="180.34" y="60.96"/> +<pinref part="RFAV1" gate="G$1" pin="1"/> +<pinref part="UF1" gate="PWR" pin="DVDD@1"/> +<pinref part="UF1" gate="PWR" pin="VDD@2"/> +<pinref part="CFB1" gate="C" pin="2"/> +<pinref part="CFC1" gate="C" pin="2"/> +<pinref part="CFD1" gate="C" pin="2"/> +<pinref part="U$97" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="+12VPC" class="0"> +<segment> +<wire x1="92.71" y1="76.2" x2="92.71" y2="83.82" width="0.1524" layer="91"/> +<wire x1="92.71" y1="83.82" x2="82.55" y2="83.82" width="0.1524" layer="91"/> +<wire x1="82.55" y1="76.2" x2="82.55" y2="83.82" width="0.1524" layer="91"/> +<wire x1="82.55" y1="83.82" x2="71.12" y2="83.82" width="0.1524" layer="91"/> +<wire x1="71.12" y1="83.82" x2="58.42" y2="83.82" width="0.1524" layer="91"/> +<wire x1="58.42" y1="76.2" x2="58.42" y2="83.82" width="0.1524" layer="91"/> +<wire x1="58.42" y1="83.82" x2="43.18" y2="83.82" width="0.1524" layer="91"/> +<wire x1="43.18" y1="83.82" x2="43.18" y2="77.47" width="0.1524" layer="91"/> +<wire x1="71.12" y1="85.09" x2="71.12" y2="83.82" width="0.1524" layer="91"/> +<wire x1="71.12" y1="67.31" x2="71.12" y2="83.82" width="0.1524" layer="91"/> +<junction x="58.42" y="83.82"/> +<junction x="82.55" y="83.82"/> +<junction x="71.12" y="83.82"/> +<pinref part="CFSB1" gate="C" pin="2"/> +<pinref part="CFSA1" gate="C" pin="+"/> +<pinref part="RFSA1" gate="G$1" pin="2"/> +<pinref part="QFSA1" gate="G$1" pin="E"/> +<pinref part="U$63" gate="+12VPC" pin="+12VPC"/> +<pinref part="DFSB1" gate="D" pin="C"/> +</segment> +</net> +<net name="GP30" class="0"> +<segment> +<label x="105.41" y="157.48" size="1.778" layer="92" rot="R180" xref="yes"/> +<wire x1="105.41" y1="157.48" x2="119.38" y2="157.48" width="0.1524" layer="91"/> +<pinref part="RF3" gate="R" pin="1"/> +</segment> +</net> +<net name="FXOFXS-RST-N" class="0"> +<segment> +<pinref part="RF2" gate="G$1" pin="1"/> +<wire x1="171.45" y1="152.4" x2="166.37" y2="152.4" width="0.1524" layer="91"/> +<label x="109.22" y="152.4" size="1.778" layer="92" rot="R180" xref="yes"/> +<pinref part="UF1" gate="CLKGP" pin="/RST"/> +<wire x1="166.37" y1="152.4" x2="109.22" y2="152.4" width="0.1524" layer="91"/> +<wire x1="160.02" y1="157.48" x2="166.37" y2="157.48" width="0.1524" layer="91"/> +<wire x1="166.37" y1="157.48" x2="166.37" y2="152.4" width="0.1524" layer="91"/> +<junction x="166.37" y="152.4"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="228.6" y="11.43" size="1.778" layer="94">FXOFXS POWER & CORE</text> +<text x="92.71" y="173.99" size="3.81" layer="94">FXO FXS</text> +</plain> +<instances> +<instance part="FRAME35" gate="G$1" x="0" y="0"/> +<instance part="FRAME35" gate="G$2" x="180.34" y="0"/> +<instance part="UF4" gate="G$1" x="104.14" y="109.22" smashed="yes"> +<attribute name="NAME" x="91.44" y="130.175" size="1.778" layer="95"/> +<attribute name="VALUE" x="90.17" y="102.235" size="1.778" layer="96"/> +</instance> +<instance part="CFICT1" gate="C" x="62.23" y="134.62" smashed="yes"> +<attribute name="NAME" x="53.34" y="137.16" size="1.778" layer="95"/> +<attribute name="VALUE" x="53.34" y="132.08" size="1.778" layer="96"/> +<attribute name="TYPE" x="63.5" y="137.16" size="1.778" layer="96"/> +<attribute name="DNP" x="62.23" y="132.08" size="1.778" layer="96"/> +</instance> +<instance part="CFICR1" gate="C" x="62.23" y="120.65" smashed="yes"> +<attribute name="NAME" x="52.07" y="123.19" size="1.778" layer="95"/> +<attribute name="VALUE" x="53.34" y="116.84" size="1.778" layer="96"/> +<attribute name="TYPE" x="62.23" y="123.19" size="1.778" layer="96"/> +<attribute name="DNP" x="62.23" y="116.84" size="1.778" layer="96"/> +</instance> +<instance part="CFICG1" gate="C" x="62.23" y="107.95" smashed="yes"> +<attribute name="NAME" x="52.07" y="110.49" size="1.778" layer="95"/> +<attribute name="VALUE" x="53.34" y="104.14" size="1.778" layer="96"/> +<attribute name="TYPE" x="62.23" y="110.49" size="1.778" layer="96"/> +<attribute name="DNP" x="62.23" y="104.14" size="1.778" layer="96"/> +</instance> +<instance part="CFHC1" gate="C" x="85.09" y="101.6" smashed="yes" rot="R90"> +<attribute name="NAME" x="86.614" y="96.901" size="1.778" layer="95"/> +<attribute name="VALUE" x="86.614" y="94.361" size="1.778" layer="96"/> +</instance> +<instance part="RFBST1" gate="G$1" x="129.54" y="127" smashed="yes"> +<attribute name="NAME" x="124.46" y="130.81" size="1.778" layer="95"/> +<attribute name="VALUE" x="132.08" y="130.175" size="1.778" layer="96" rot="R180"/> +<attribute name="POWER" x="129.54" y="127" size="1.778" layer="96" display="off"/> +</instance> +<instance part="RFRNG1" gate="G$1" x="127" y="87.63" smashed="yes" rot="MR0"> +<attribute name="NAME" x="120.8034" y="90.8706" size="1.778" layer="95" rot="MR180"/> +<attribute name="VALUE" x="132.716" y="84.0664" size="1.778" layer="96" rot="MR0"/> +</instance> +<instance part="QFBST1" gate="Q" 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gate="COM" pin="TDC"/> +</segment> +</net> +<net name="RAC" class="0"> +<segment> +<wire x1="25.4" y1="33.02" x2="44.45" y2="33.02" width="0.1524" layer="91"/> +<wire x1="44.45" y1="33.02" x2="44.45" y2="27.94" width="0.1524" layer="91"/> +<wire x1="44.45" y1="27.94" x2="64.77" y2="27.94" width="0.1524" layer="91"/> +<label x="27.94" y="33.3375" size="1.778" layer="92"/> +<pinref part="UF1" gate="COM" pin="RAC"/> +<pinref part="CFRAC1" gate="C" pin="1"/> +</segment> +</net> +<net name="TAC" class="0"> +<segment> +<wire x1="25.4" y1="55.88" x2="34.29" y2="55.88" width="0.1524" layer="91"/> +<label x="27.94" y="56.1975" size="1.778" layer="92"/> +<pinref part="UF1" gate="COM" pin="TAC"/> +</segment> +<segment> +<wire x1="110.49" y1="74.93" x2="120.65" y2="74.93" width="0.1524" layer="91"/> +<label x="111.76" y="75.2475" size="1.778" layer="92"/> +<pinref part="CFTAC1" gate="C" pin="1"/> +</segment> +</net> +<net name="TIP2" class="0"> +<segment> +<wire x1="233.68" y1="71.12" x2="247.65" y2="71.12" width="0.1524" layer="91"/> +<wire x1="247.65" y1="71.12" x2="247.65" y2="55.88" width="0.1524" layer="91"/> +<label x="244.1575" y="58.42" size="1.778" layer="92" rot="MR90"/> +<pinref part="FFBA2" gate="G$1" pin="2"/> +<pinref part="JF2" gate="G$1" pin="4"/> +</segment> +</net> +<net name="RING2" class="0"> +<segment> +<wire x1="233.68" y1="27.94" x2="246.38" y2="27.94" width="0.1524" layer="91"/> +<wire x1="246.38" y1="43.18" x2="246.38" y2="27.94" width="0.1524" layer="91"/> +<label x="244.1575" y="31.75" size="1.778" layer="92" rot="MR90"/> +<pinref part="FFBB2" gate="G$1" pin="2"/> +<pinref part="JF2" gate="G$1" pin="3"/> +</segment> +</net> +<net name="FX-VBAT" class="0"> +<segment> +<wire x1="152.4" y1="66.04" x2="152.4" y2="63.5" width="0.1524" layer="91"/> +<pinref part="RFPA1" gate="G$1" pin="2"/> +<pinref part="U$614" gate="FX-VBAT" pin="FX-VBAT"/> +</segment> +<segment> +<wire x1="196.85" y1="48.26" x2="196.85" y2="66.04" width="0.1524" layer="91"/> +<pinref part="U$617" gate="FX-VBAT" pin="FX-VBAT"/> +<pinref part="RFLP1" gate="G$1" pin="2"/> +</segment> +<segment> +<wire x1="54.61" y1="76.2" x2="46.99" y2="76.2" width="0.1524" layer="91"/> +<wire x1="46.99" y1="76.2" x2="46.99" y2="82.55" width="0.1524" layer="91"/> +<wire x1="46.99" y1="82.55" x2="46.99" y2="87.63" width="0.1524" layer="91"/> +<wire x1="54.61" y1="82.55" x2="46.99" y2="82.55" width="0.1524" layer="91"/> +<junction x="46.99" y="82.55"/> +<pinref part="DFBT1" gate="G$1" pin="C"/> +<pinref part="RFBT1" gate="G$1" pin="2"/> +<pinref part="U$98" gate="FX-VBAT" pin="FX-VBAT"/> +</segment> +</net> +<net name="GND" class="0"> +<segment> +<wire x1="83.82" y1="82.55" x2="87.63" y2="82.55" width="0.1524" layer="91"/> +<pinref part="U$633" gate="G$1" pin="GND"/> +<pinref part="CFBT1" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="119.38" y1="58.42" x2="119.38" y2="49.53" width="0.1524" layer="91"/> +<wire x1="119.38" y1="49.53" x2="119.38" y2="40.64" width="0.1524" layer="91"/> +<wire x1="109.22" y1="49.53" x2="114.3" y2="49.53" width="0.1524" layer="91"/> +<wire x1="114.3" y1="49.53" x2="119.38" y2="49.53" width="0.1524" layer="91"/> +<wire x1="109.22" y1="52.07" x2="114.3" y2="52.07" width="0.1524" layer="91"/> +<wire x1="114.3" y1="52.07" x2="114.3" y2="49.53" width="0.1524" layer="91"/> +<wire x1="114.3" y1="48.26" x2="114.3" y2="49.53" width="0.1524" layer="91"/> +<junction x="119.38" y="49.53"/> +<junction x="114.3" y="49.53"/> +<pinref part="UF2" gate="U" pin="AGND"/> +<pinref part="UF2" gate="U" pin="BGND"/> +<pinref part="U$630" gate="G$1" pin="GND"/> +<pinref part="CFTD1" gate="C" pin="1"/> +<pinref part="CFRD1" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="147.32" y1="38.1" x2="147.32" y2="34.29" width="0.1524" layer="91"/> +<wire x1="147.32" y1="33.02" x2="147.32" y2="34.29" width="0.1524" layer="91"/> +<wire x1="147.32" y1="34.29" x2="152.4" y2="34.29" width="0.1524" layer="91"/> +<wire x1="152.4" y1="34.29" x2="152.4" y2="38.1" width="0.1524" layer="91"/> +<junction x="147.32" y="34.29"/> +<pinref part="DF1" gate="DIODE" pin="C"/> +<pinref part="U$631" gate="G$1" pin="GND"/> +<pinref part="CFPA1" gate="C" pin="1"/> +</segment> +<segment> +<wire x1="46.99" y1="63.5" x2="53.34" y2="63.5" width="0.1524" layer="91"/> +<pinref part="U$632" gate="G$1" pin="GND"/> +<pinref part="CFA1" gate="C" pin="2"/> +</segment> +<segment> +<wire x1="187.96" y1="49.53" x2="189.23" y2="49.53" width="0.1524" layer="91"/> +<wire x1="189.23" y1="49.53" x2="190.5" y2="49.53" width="0.1524" layer="91"/> +<wire x1="187.96" y1="46.99" x2="189.23" y2="46.99" width="0.1524" layer="91"/> +<wire x1="189.23" y1="46.99" x2="189.23" y2="49.53" width="0.1524" layer="91"/> +<junction x="189.23" y="49.53"/> +<pinref part="UF3" gate="G$1" pin="A$1"/> +<pinref part="U$634" gate="G$1" pin="GND"/> +<pinref part="UF3" gate="G$1" pin="A$0"/> +</segment> +</net> +<net name="FX-VREF" class="0"> +<segment> +<wire x1="78.74" y1="58.42" x2="77.47" y2="58.42" width="0.1524" layer="91"/> +<wire x1="77.47" y1="58.42" x2="77.47" y2="69.85" width="0.1524" layer="91"/> +<pinref part="UF2" gate="U" pin="VREF"/> +<pinref part="U$650" gate="FX-VREF" pin="FX-VREF"/> +</segment> +</net> +<net name="FXN10" class="0"> +<segment> +<wire x1="64.77" y1="107.95" x2="81.28" y2="107.95" width="0.1524" layer="91"/> +<wire x1="81.28" y1="107.95" x2="81.28" y2="118.11" width="0.1524" layer="91"/> +<wire x1="81.28" y1="118.11" x2="85.09" y2="118.11" width="0.1524" layer="91"/> +<wire x1="81.28" y1="107.95" x2="81.28" y2="87.63" width="0.1524" layer="91"/> +<wire x1="81.28" y1="87.63" x2="121.92" y2="87.63" width="0.1524" layer="91"/> +<junction x="81.28" y="107.95"/> +<pinref part="CFICG1" gate="C" pin="2"/> +<pinref part="UF4" gate="G$1" pin="ICG"/> +<pinref part="RFRNG1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FXN2" class="0"> +<segment> +<wire x1="171.45" y1="101.6" x2="171.45" y2="92.71" width="0.1524" layer="91"/> +<wire x1="193.04" y1="119.38" x2="193.04" y2="92.71" width="0.1524" layer="91"/> +<wire x1="193.04" y1="92.71" x2="180.34" y2="92.71" width="0.1524" layer="91"/> +<wire x1="180.34" y1="92.71" x2="180.34" y2="106.68" width="0.1524" layer="91"/> +<wire x1="171.45" y1="92.71" x2="180.34" y2="92.71" width="0.1524" layer="91"/> +<wire x1="114.3" y1="92.71" x2="114.3" y2="93.98" width="0.1524" layer="91"/> +<wire x1="85.09" y1="96.52" x2="85.09" y2="92.71" width="0.1524" layer="91"/> +<wire x1="85.09" y1="92.71" x2="114.3" y2="92.71" width="0.1524" layer="91"/> +<wire x1="171.45" y1="92.71" x2="114.3" y2="92.71" width="0.1524" layer="91"/> +<junction x="171.45" y="92.71"/> +<junction x="114.3" y="92.71"/> +<junction x="180.34" y="92.71"/> +<pinref part="LFIMM1" gate="L" pin="1"/> +<pinref part="BFR1" gate="B" pin="P$2"/> +<pinref part="CFHC1" gate="C" pin="1"/> +<pinref part="CFBR1" gate="C" pin="1"/> +<pinref part="RFDCC1" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FXN44" class="0"> +<segment> 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y2="123.19" width="0.1524" layer="91"/> +<wire x1="64.77" y1="134.62" x2="81.28" y2="134.62" width="0.1524" layer="91"/> +<wire x1="81.28" y1="134.62" x2="81.28" y2="167.64" width="0.1524" layer="91"/> +<wire x1="81.28" y1="167.64" x2="124.46" y2="167.64" width="0.1524" layer="91"/> +<junction x="81.28" y="134.62"/> +<pinref part="CFICT1" gate="C" pin="2"/> +<pinref part="UF4" gate="G$1" pin="ICT"/> +<pinref part="RFTIP1" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FXN26" class="0"> +<segment> +<wire x1="85.09" y1="120.65" x2="64.77" y2="120.65" width="0.1524" layer="91"/> +<pinref part="UF4" gate="G$1" pin="ICR"/> +<pinref part="CFICR1" gate="C" pin="2"/> +</segment> +</net> +<net name="FXN40" class="0"> +<segment> +<wire x1="111.76" y1="127" x2="114.3" y2="127" width="0.1524" layer="91"/> +<wire x1="114.3" y1="127" x2="124.46" y2="127" width="0.1524" layer="91"/> +<wire x1="114.3" y1="148.59" x2="114.3" y2="139.7" width="0.1524" layer="91"/> +<wire x1="114.3" y1="139.7" x2="114.3" y2="127" width="0.1524" layer="91"/> +<wire x1="114.3" y1="139.7" x2="97.79" y2="139.7" width="0.1524" layer="91"/> +<wire x1="97.79" y1="139.7" x2="97.79" y2="142.24" width="0.1524" layer="91"/> +<junction x="114.3" y="127"/> +<junction x="114.3" y="139.7"/> +<pinref part="UF4" gate="G$1" pin="VREG"/> +<pinref part="RFBST1" gate="G$1" pin="1"/> +<pinref part="QFHKA1" gate="Q" pin="E"/> +<pinref part="RFSN1" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FXN43" class="0"> +<segment> +<wire x1="170.18" y1="162.56" x2="167.64" y2="162.56" width="0.1524" layer="91"/> +<wire x1="167.64" y1="162.56" x2="114.3" y2="162.56" width="0.1524" layer="91"/> +<wire x1="114.3" y1="162.56" x2="97.79" y2="162.56" width="0.1524" layer="91"/> +<wire x1="97.79" y1="162.56" x2="97.79" y2="161.29" width="0.1524" layer="91"/> +<wire x1="114.3" y1="153.67" x2="114.3" y2="162.56" width="0.1524" layer="91"/> +<wire x1="176.53" y1="156.21" x2="167.64" y2="156.21" width="0.1524" layer="91"/> +<wire x1="167.64" y1="156.21" x2="167.64" y2="162.56" width="0.1524" layer="91"/> +<junction x="114.3" y="162.56"/> +<junction x="167.64" y="162.56"/> +<pinref part="QFHKA1" gate="Q" pin="C"/> +<pinref part="RFLD1" gate="G$1" pin="1"/> +<pinref part="CFSN1" gate="C" pin="2"/> +<pinref part="QFLD1" gate="G$1" pin="B"/> +</segment> +</net> +<net name="FXN42" class="0"> +<segment> +<wire x1="97.79" y1="152.4" x2="97.79" y2="153.67" width="0.1524" layer="91"/> +<pinref part="CFSN1" gate="C" pin="1"/> +<pinref part="RFSN1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FXN50" class="0"> +<segment> +<wire x1="160.02" y1="106.68" x2="167.64" y2="106.68" width="0.1524" layer="91"/> +<wire x1="167.64" y1="106.68" x2="167.64" y2="111.76" width="0.1524" layer="91"/> +<wire x1="160.02" y1="111.76" x2="167.64" y2="111.76" width="0.1524" layer="91"/> +<wire x1="167.64" y1="111.76" x2="167.64" y2="116.84" width="0.1524" layer="91"/> +<wire x1="160.02" y1="116.84" x2="167.64" y2="116.84" width="0.1524" layer="91"/> +<wire x1="167.64" y1="116.84" x2="167.64" y2="134.62" width="0.1524" layer="91"/> +<wire x1="167.64" y1="134.62" x2="167.64" y2="151.13" width="0.1524" layer="91"/> +<wire x1="161.29" y1="134.62" x2="167.64" y2="134.62" width="0.1524" layer="91"/> +<wire x1="160.02" y1="151.13" x2="167.64" y2="151.13" width="0.1524" layer="91"/> +<wire x1="167.64" y1="151.13" x2="181.61" y2="151.13" width="0.1524" layer="91"/> +<wire x1="181.61" y1="151.13" x2="181.61" y2="153.67" width="0.1524" layer="91"/> +<junction x="167.64" y="111.76"/> +<junction x="167.64" y="116.84"/> +<junction x="167.64" y="134.62"/> +<junction x="167.64" y="151.13"/> +<pinref part="CFDB1" gate="C" pin="2"/> +<pinref part="RFDCB1" gate="G$1" pin="2"/> +<pinref part="RFZA1" gate="G$1" pin="2"/> +<pinref part="RFZB1" gate="G$1" pin="2"/> +<pinref part="RFZC1" gate="G$1" pin="2"/> +<pinref part="QFLD1" gate="G$1" pin="C"/> +</segment> +</net> +<net name="FXN46" class="0"> +<segment> +<wire x1="139.7" y1="151.13" x2="146.05" y2="151.13" width="0.1524" layer="91"/> +<wire x1="146.05" y1="151.13" x2="146.05" y2="144.78" width="0.1524" layer="91"/> +<wire x1="146.05" y1="151.13" x2="149.86" y2="151.13" width="0.1524" layer="91"/> +<junction x="146.05" y="151.13"/> +<pinref part="CFBST1" gate="C" pin="2"/> +<pinref part="RFDCB1" gate="G$1" pin="1"/> +<pinref part="RFDCA1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FXN39" class="0"> +<segment> +<wire x1="111.76" y1="121.92" x2="114.3" y2="121.92" width="0.1524" layer="91"/> +<wire x1="114.3" y1="121.92" x2="114.3" y2="104.14" width="0.1524" layer="91"/> +<wire x1="114.3" y1="121.92" x2="146.05" y2="121.92" width="0.1524" layer="91"/> +<wire x1="146.05" y1="121.92" x2="146.05" y2="124.46" width="0.1524" layer="91"/> +<junction x="114.3" y="121.92"/> +<pinref part="UF4" gate="G$1" pin="IGND"/> +<pinref part="QFBST1" gate="Q" pin="E"/> +<pinref part="RFDCC1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FXN37" class="0"> +<segment> +<wire x1="111.76" y1="111.76" x2="123.19" y2="111.76" width="0.1524" layer="91"/> +<pinref part="UF4" gate="G$1" pin="ZB"/> +<pinref part="CFZB1" gate="C" pin="1"/> +</segment> +</net> +<net name="FXN36" class="0"> +<segment> +<wire x1="111.76" y1="106.68" x2="123.19" y2="106.68" width="0.1524" layer="91"/> +<pinref part="UF4" gate="G$1" pin="ZC"/> +<pinref part="CFZC1" gate="C" pin="1"/> +</segment> +</net> +<net name="FXN55" class="0"> +<segment> +<wire x1="185.42" y1="127" x2="185.42" y2="118.11" width="0.1524" layer="91"/> +<wire x1="185.42" y1="118.11" x2="203.2" y2="118.11" width="0.1524" layer="91"/> +<wire x1="203.2" y1="87.63" x2="203.2" y2="118.11" width="0.1524" layer="91"/> +<wire x1="203.2" y1="118.11" x2="209.55" y2="118.11" width="0.1524" layer="91"/> +<wire x1="209.55" y1="121.92" x2="209.55" y2="118.11" width="0.1524" layer="91"/> +<wire x1="209.55" y1="118.11" x2="212.725" y2="118.11" width="0.1524" layer="91"/> +<wire x1="132.08" y1="87.63" x2="203.2" y2="87.63" width="0.1524" layer="91"/> +<junction x="209.55" y="118.11"/> +<junction x="203.2" y="118.11"/> +<pinref part="BFR1" gate="B" pin="A"/> +<pinref part="FFBB1" gate="G$1" pin="1"/> +<pinref part="RFRNG1" gate="G$1" pin="1"/> +<pinref part="CFEMB1" gate="C" pin="1"/> +</segment> +</net> +<net name="FXN53" class="0"> +<segment> +<wire x1="181.61" y1="158.75" x2="181.61" y2="162.56" width="0.1524" layer="91"/> +<wire x1="181.61" y1="162.56" x2="180.34" y2="162.56" width="0.1524" layer="91"/> +<wire x1="181.61" y1="162.56" x2="193.04" y2="162.56" width="0.1524" layer="91"/> +<wire x1="171.45" y1="135.89" x2="180.34" y2="135.89" width="0.1524" layer="91"/> +<wire x1="180.34" y1="135.89" x2="180.34" y2="114.3" width="0.1524" layer="91"/> +<wire x1="193.04" y1="134.62" x2="193.04" y2="135.89" width="0.1524" layer="91"/> +<wire x1="193.04" y1="135.89" x2="180.34" y2="135.89" width="0.1524" layer="91"/> +<wire x1="193.04" y1="162.56" x2="193.04" y2="135.89" width="0.1524" layer="91"/> +<wire x1="171.45" y1="135.89" x2="171.45" y2="125.73" width="0.1524" layer="91"/> +<junction x="181.61" y="162.56"/> +<junction x="180.34" y="135.89"/> +<junction x="193.04" y="135.89"/> +<pinref part="RFLD1" gate="G$1" pin="2"/> +<pinref part="BFR1" gate="B" pin="P$1"/> +<pinref part="CFIMM1" gate="C" pin="2"/> +<pinref part="CFBR1" gate="C" pin="2"/> +<pinref part="QFLD1" gate="G$1" pin="E"/> +</segment> +</net> +<net name="FXN56" class="0"> +<segment> +<wire x1="200.66" y1="127" x2="200.66" y2="144.78" width="0.1524" layer="91"/> +<wire x1="200.66" y1="144.78" x2="200.66" y2="167.64" width="0.1524" layer="91"/> +<wire x1="200.66" y1="167.64" x2="134.62" y2="167.64" width="0.1524" layer="91"/> +<wire x1="211.455" y1="144.78" x2="209.55" y2="144.78" width="0.1524" layer="91"/> +<wire x1="209.55" y1="144.78" x2="200.66" y2="144.78" width="0.1524" layer="91"/> +<wire x1="209.55" y1="142.24" x2="209.55" y2="144.78" width="0.1524" layer="91"/> +<junction x="200.66" y="144.78"/> +<junction x="209.55" y="144.78"/> +<pinref part="BFR1" gate="B" pin="C"/> +<pinref part="FFBA1" gate="G$1" pin="1"/> +<pinref part="RFTIP1" gate="G$1" pin="2"/> +<pinref part="CFEMA1" gate="C" pin="2"/> +</segment> +</net> +<net name="FXN30" class="0"> +<segment> +<wire x1="220.98" y1="144.78" x2="226.06" y2="144.78" width="0.1524" layer="91"/> +<wire x1="226.06" y1="144.78" x2="229.235" y2="144.78" width="0.1524" layer="91"/> +<wire x1="226.06" y1="133.35" x2="226.06" y2="144.78" width="0.1524" layer="91"/> +<junction x="226.06" y="144.78"/> +<pinref part="FFSA1" gate="G$1" pin="1"/> +<pinref part="FFBA1" gate="G$1" pin="2"/> +<pinref part="TFVS1" gate="G$1" pin="P$2"/> +</segment> +</net> +<net name="FXN60" class="0"> +<segment> +<wire x1="207.01" y1="76.2" x2="222.25" y2="76.2" width="0.1524" layer="91"/> +<wire x1="222.25" y1="76.2" x2="222.25" y2="71.12" width="0.1524" layer="91"/> +<wire x1="224.155" y1="71.12" x2="222.25" y2="71.12" width="0.1524" layer="91"/> +<wire x1="220.98" y1="50.8" x2="222.25" y2="50.8" width="0.1524" layer="91"/> +<wire x1="222.25" y1="50.8" x2="222.25" y2="71.12" width="0.1524" layer="91"/> +<junction x="222.25" y="71.12"/> +<pinref part="FFBA2" gate="G$1" pin="1"/> +<pinref part="RFTDC1" gate="G$1" pin="2"/> +<pinref part="PFTCA1" gate="G$1" pin="4"/> +</segment> +</net> +<net name="FXN63" class="0"> +<segment> +<wire x1="222.25" y1="27.94" x2="222.25" y2="20.32" width="0.1524" layer="91"/> +<wire x1="222.25" y1="20.32" x2="210.82" y2="20.32" width="0.1524" layer="91"/> +<wire x1="222.25" y1="27.94" x2="224.155" y2="27.94" width="0.1524" layer="91"/> +<wire x1="220.98" y1="48.26" x2="222.25" y2="48.26" width="0.1524" layer="91"/> +<wire x1="222.25" y1="48.26" x2="222.25" y2="27.94" width="0.1524" layer="91"/> +<junction x="222.25" y="27.94"/> +<pinref part="FFBB2" gate="G$1" pin="1"/> +<pinref part="RFRDC1" gate="G$1" pin="2"/> +<pinref part="PFTCA1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FXN32" class="0"> +<segment> +<wire x1="109.22" y1="36.83" x2="110.49" y2="36.83" width="0.1524" layer="91"/> +<wire x1="110.49" y1="36.83" x2="110.49" y2="27.94" width="0.1524" layer="91"/> +<wire x1="110.49" y1="27.94" x2="119.38" y2="27.94" width="0.1524" layer="91"/> +<wire x1="119.38" y1="27.94" x2="161.29" y2="27.94" width="0.1524" layer="91"/> +<wire x1="119.38" y1="33.02" x2="119.38" y2="27.94" width="0.1524" layer="91"/> +<wire x1="161.29" y1="44.45" x2="161.29" y2="27.94" width="0.1524" layer="91"/> +<wire x1="161.29" y1="27.94" x2="189.23" y2="27.94" width="0.1524" layer="91"/> +<wire x1="189.23" y1="27.94" x2="196.85" y2="27.94" width="0.1524" layer="91"/> +<wire x1="196.85" y1="27.94" x2="205.74" y2="27.94" width="0.1524" layer="91"/> +<wire x1="207.01" y1="48.26" x2="205.74" y2="48.26" width="0.1524" layer="91"/> +<wire x1="205.74" y1="48.26" x2="205.74" y2="27.94" width="0.1524" layer="91"/> +<wire x1="187.96" y1="44.45" x2="189.23" y2="44.45" width="0.1524" layer="91"/> +<wire x1="189.23" y1="44.45" x2="189.23" y2="27.94" width="0.1524" layer="91"/> +<wire x1="110.49" y1="27.94" x2="101.6" y2="27.94" width="0.1524" layer="91"/> +<wire x1="196.85" y1="38.1" x2="196.85" y2="27.94" width="0.1524" layer="91"/> +<wire x1="161.29" y1="44.45" x2="162.56" y2="44.45" width="0.1524" layer="91"/> +<junction x="119.38" y="27.94"/> +<junction x="161.29" y="27.94"/> +<junction x="189.23" y="27.94"/> +<junction x="110.49" y="27.94"/> +<junction x="196.85" y="27.94"/> +<pinref part="UF2" gate="U" pin="RING"/> +<pinref part="UF3" gate="G$1" pin="K1B"/> +<pinref part="RFRAC1" gate="G$1" pin="2"/> +<pinref part="CFRD1" gate="C" pin="1"/> +<pinref part="RFLP1" gate="G$1" pin="1"/> +<pinref part="PFTCA1" gate="G$1" pin="1"/> +<pinref part="UF3" gate="G$1" pin="K1A"/> +</segment> +</net> +<net name="FXN29" class="0"> +<segment> +<wire x1="109.22" y1="58.42" x2="110.49" y2="58.42" width="0.1524" layer="91"/> +<wire x1="110.49" y1="58.42" x2="110.49" y2="71.12" width="0.1524" layer="91"/> +<wire x1="110.49" y1="71.12" x2="119.38" y2="71.12" width="0.1524" layer="91"/> +<wire x1="119.38" y1="71.12" x2="161.29" y2="71.12" width="0.1524" layer="91"/> +<wire x1="119.38" y1="66.04" x2="119.38" y2="71.12" width="0.1524" layer="91"/> +<wire x1="161.29" y1="52.07" x2="161.29" y2="71.12" width="0.1524" layer="91"/> +<wire x1="161.29" y1="71.12" x2="189.23" y2="71.12" width="0.1524" layer="91"/> +<wire x1="189.23" y1="71.12" x2="205.74" y2="71.12" width="0.1524" layer="91"/> +<wire x1="207.01" y1="50.8" x2="205.74" y2="50.8" width="0.1524" layer="91"/> +<wire x1="205.74" y1="50.8" x2="205.74" y2="71.12" width="0.1524" layer="91"/> +<wire x1="187.96" y1="52.07" x2="189.23" y2="52.07" width="0.1524" layer="91"/> +<wire x1="189.23" y1="52.07" x2="189.23" y2="71.12" width="0.1524" layer="91"/> +<wire x1="146.05" y1="74.93" x2="161.29" y2="74.93" width="0.1524" layer="91"/> +<wire x1="161.29" y1="74.93" x2="161.29" y2="71.12" width="0.1524" layer="91"/> +<wire x1="161.29" y1="52.07" x2="162.56" y2="52.07" width="0.1524" layer="91"/> +<junction x="119.38" y="71.12"/> +<junction x="161.29" y="71.12"/> +<junction x="189.23" y="71.12"/> +<pinref part="UF2" gate="U" pin="TIP"/> +<pinref part="UF3" gate="G$1" pin="K2B"/> +<pinref part="RFTAC1" gate="G$1" pin="2"/> +<pinref part="CFTD1" gate="C" pin="2"/> +<pinref part="PFTCA1" gate="G$1" pin="3"/> +<pinref part="UF3" gate="G$1" pin="K2A"/> +</segment> +</net> +<net name="FXN54" class="0"> +<segment> +<wire x1="91.44" y1="27.94" x2="72.39" y2="27.94" width="0.1524" layer="91"/> +<pinref part="CFRAC1" gate="C" pin="2"/> +<pinref part="RFRAC1" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FXN8" class="0"> +<segment> +<wire x1="25.4" y1="52.07" x2="49.53" y2="52.07" width="0.1524" layer="91"/> +<pinref part="UF1" gate="COM" pin="RTV"/> +<pinref part="RFTV1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FXN28" class="0"> +<segment> +<wire x1="64.77" y1="82.55" x2="72.39" y2="82.55" width="0.1524" layer="91"/> +<wire x1="64.77" y1="76.2" x2="72.39" y2="76.2" width="0.1524" layer="91"/> +<wire x1="72.39" y1="82.55" x2="76.2" y2="82.55" width="0.1524" layer="91"/> +<wire x1="72.39" y1="82.55" x2="72.39" y2="76.2" width="0.1524" layer="91"/> +<wire x1="78.74" y1="55.88" x2="72.39" y2="55.88" width="0.1524" layer="91"/> +<wire x1="72.39" y1="55.88" x2="72.39" y2="76.2" width="0.1524" layer="91"/> +<junction x="72.39" y="82.55"/> +<junction x="72.39" y="76.2"/> +<pinref part="UF2" gate="U" pin="VBAT"/> +<pinref part="RFBT1" gate="G$1" pin="1"/> +<pinref part="DFBT1" gate="G$1" pin="A"/> +<pinref part="CFBT1" gate="C" pin="1"/> +</segment> +</net> +<net name="FXN9" class="0"> +<segment> +<wire x1="171.45" y1="111.76" x2="171.45" y2="118.11" width="0.1524" layer="91"/> +<pinref part="LFIMM1" gate="L" pin="2"/> +<pinref part="CFIMM1" gate="C" pin="1"/> +</segment> +</net> +<net name="FXN34" class="0"> +<segment> +<wire x1="85.09" y1="106.68" x2="85.09" y2="104.14" width="0.1524" layer="91"/> +<pinref part="UF4" gate="G$1" pin="HC"/> +<pinref part="CFHC1" gate="C" pin="2"/> +</segment> +</net> +<net name="FXN41" class="0"> +<segment> +<wire x1="134.62" y1="127" x2="140.97" y2="127" width="0.1524" layer="91"/> +<pinref part="RFBST1" gate="G$1" pin="2"/> +<pinref part="QFBST1" gate="Q" pin="B"/> +</segment> +</net> +<net name="FXN45" class="0"> +<segment> +<wire x1="146.05" y1="137.16" x2="146.05" y2="129.54" width="0.1524" layer="91"/> +<pinref part="CFBST1" gate="C" pin="1"/> +<pinref part="QFBST1" gate="Q" pin="C"/> +</segment> +</net> +<net name="FXN48" class="0"> +<segment> +<wire x1="130.81" y1="111.76" x2="149.86" y2="111.76" width="0.1524" layer="91"/> +<pinref part="RFZB1" gate="G$1" pin="1"/> +<pinref part="CFZB1" gate="C" pin="2"/> +</segment> +</net> +<net name="FXN49" class="0"> +<segment> +<wire x1="130.81" y1="106.68" x2="149.86" y2="106.68" width="0.1524" layer="91"/> +<pinref part="RFZC1" gate="G$1" pin="1"/> +<pinref part="CFZC1" gate="C" pin="2"/> +</segment> +</net> +<net name="FXN51" class="0"> +<segment> +<wire x1="135.89" y1="74.93" x2="128.27" y2="74.93" width="0.1524" layer="91"/> +<pinref part="CFTAC1" gate="C" pin="2"/> +<pinref part="RFTAC1" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$45" class="0"> +<segment> +<wire x1="123.19" y1="116.84" x2="111.76" y2="116.84" width="0.1524" layer="91"/> +<pinref part="UF4" gate="G$1" pin="ZA"/> +<pinref part="CFZA1" gate="C" pin="1"/> +</segment> +</net> +<net name="N$46" class="0"> +<segment> +<wire x1="130.81" y1="116.84" x2="149.86" y2="116.84" width="0.1524" layer="91"/> +<pinref part="RFZA1" gate="G$1" pin="1"/> +<pinref part="CFZA1" gate="C" pin="2"/> +</segment> +</net> +<net name="FXVTS" class="0"> +<segment> +<wire x1="147.32" y1="49.53" x2="147.32" y2="45.72" width="0.1524" layer="91"/> +<wire x1="147.32" y1="49.53" x2="152.4" y2="49.53" width="0.1524" layer="91"/> +<wire x1="152.4" y1="49.53" x2="152.4" y2="53.34" width="0.1524" layer="91"/> +<wire x1="152.4" y1="45.72" x2="152.4" y2="49.53" width="0.1524" layer="91"/> +<wire x1="162.56" y1="46.99" x2="160.02" y2="46.99" width="0.1524" layer="91"/> +<wire x1="160.02" y1="46.99" x2="160.02" y2="49.53" width="0.1524" layer="91"/> +<wire x1="160.02" y1="49.53" x2="152.4" y2="49.53" width="0.1524" layer="91"/> +<junction x="152.4" y="49.53"/> +<pinref part="DF1" gate="DIODE" pin="A"/> +<pinref part="RFPA1" gate="G$1" pin="1"/> +<pinref part="UF3" gate="G$1" pin="NC/G"/> +<pinref part="CFPA1" gate="C" pin="2"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="78.74" y1="53.34" x2="64.77" y2="53.34" width="0.1524" layer="91"/> +<wire x1="64.77" y1="53.34" x2="64.77" y2="63.5" width="0.1524" layer="91"/> +<wire x1="64.77" y1="63.5" x2="64.77" y2="69.85" width="0.1524" layer="91"/> +<wire x1="64.77" y1="63.5" x2="60.96" y2="63.5" width="0.1524" layer="91"/> +<junction x="64.77" y="63.5"/> +<pinref part="UF2" gate="U" pin="VCC"/> +<pinref part="CFA1" gate="C" pin="1"/> +<pinref part="U$100" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +<net name="GND-CHASSIS" class="0"> +<segment> +<wire x1="209.55" y1="129.54" x2="209.55" y2="132.08" width="0.1524" layer="91"/> +<wire x1="209.55" y1="132.08" x2="209.55" y2="134.62" width="0.1524" layer="91"/> +<wire x1="209.55" y1="132.08" x2="215.9" y2="132.08" width="0.1524" layer="91"/> +<junction x="209.55" y="132.08"/> +<pinref part="CFEMA1" gate="C" pin="1"/> +<pinref part="CFEMB1" gate="C" pin="2"/> +<pinref part="U$108" gate="G$1" pin="GND-CHASSIS"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<plain> +<text x="107.95" y="171.45" size="3.81" layer="94">ISDN CORE</text> +</plain> +<instances> +<instance part="FRAME40" gate="G$1" x="0" y="0"/> +<instance part="FRAME40" gate="G$2" x="180.34" y="0"/> +<instance part="UI33" gate="C" x="161.29" y="142.24" rot="MR0"/> +<instance part="UI33" gate="A" x="212.09" y="63.5"/> +<instance part="UI33" gate="PWR" x="40.64" y="109.22" smashed="yes"> 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x="120.65" y="52.07" size="1.778" layer="96" rot="R270"/> +</instance> +<instance part="RI21" gate="R" x="96.52" y="49.53" smashed="yes" rot="R270"> +<attribute name="NAME" x="99.06" y="46.99" size="1.778" layer="95"/> +<attribute name="VALUE" x="99.06" y="49.53" size="1.778" layer="96"/> +</instance> +<instance part="U$103" gate="G$1" x="119.38" y="44.45"/> +<instance part="TRI1" gate="A" x="199.39" y="152.4" smashed="yes" rot="MR0"> +<attribute name="NAME" x="195.58" y="143.51" size="1.778" layer="95"/> +<attribute name="VALUE" x="196.85" y="140.97" size="1.778" layer="96"/> +</instance> +<instance part="TRI1" gate="B" x="199.39" y="106.68" smashed="yes" rot="MR0"> +<attribute name="NAME" x="195.58" y="118.11" size="1.778" layer="95"/> +<attribute name="VALUE" x="196.85" y="115.57" size="1.778" layer="96"/> +</instance> +<instance part="QI2" gate="A" x="111.76" y="57.15" smashed="yes"> +<attribute name="NAME" x="99.06" y="54.61" size="1.778" layer="95"/> +<attribute name="VALUE" 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y="139.7" smashed="yes"> +<attribute name="NAME" x="213.106" y="141.351" size="1.778" layer="95" rot="R270"/> +<attribute name="VALUE" x="219.71" y="137.795" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="217.805" y="140.335" size="1.778" layer="96"/> +<attribute name="DNP" x="217.805" y="135.255" size="1.778" layer="96"/> +</instance> +<instance part="CI12" gate="C" x="217.17" y="125.73" smashed="yes"> +<attribute name="NAME" x="213.106" y="127.381" size="1.778" layer="95" rot="R270"/> +<attribute name="VALUE" x="219.71" y="123.825" size="1.778" layer="96"/> +<attribute name="VOLTAGE" x="217.805" y="126.365" size="1.778" layer="96"/> +<attribute name="DNP" x="217.805" y="120.65" size="1.778" layer="96"/> +</instance> +<instance part="CI13" gate="C" x="224.79" y="152.4" smashed="yes"> +<attribute name="NAME" x="218.059" y="152.781" size="1.778" layer="95"/> +<attribute name="VALUE" x="218.694" y="148.336" size="1.778" layer="96"/> +<attribute name="DNP" x="225.425" y="153.035" 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x1="194.31" y1="107.95" x2="196.85" y2="107.95" width="0.1524" layer="91"/> +<wire x1="194.31" y1="105.41" x2="196.85" y2="105.41" width="0.1524" layer="91"/> +<wire x1="194.31" y1="105.41" x2="194.31" y2="101.6" width="0.1524" layer="91"/> +<wire x1="194.31" y1="101.6" x2="132.08" y2="101.6" width="0.1524" layer="91"/> +<wire x1="132.08" y1="101.6" x2="132.08" y2="115.57" width="0.1524" layer="91"/> +<wire x1="102.87" y1="144.78" x2="121.92" y2="144.78" width="0.1524" layer="91"/> +<wire x1="121.92" y1="144.78" x2="121.92" y2="115.57" width="0.1524" layer="91"/> +<wire x1="121.92" y1="115.57" x2="102.87" y2="115.57" width="0.1524" layer="91"/> +<wire x1="132.08" y1="115.57" x2="121.92" y2="115.57" width="0.1524" layer="91"/> +<junction x="194.31" y="105.41"/> +<junction x="121.92" y="115.57"/> +<label x="160.9725" y="101.9175" size="1.778" layer="92"/> +<pinref part="UI26" gate="S" pin="Y1"/> +<pinref part="UI29" gate="S" pin="Y0"/> +<pinref part="TRI4" gate="B" pin="S12"/> +<pinref part="TRI4" gate="B" pin="S21"/> +</segment> +</net> +<net name="F3R-B&T-B" class="0"> +<segment> +<wire x1="129.54" y1="104.14" x2="121.92" y2="104.14" width="0.1524" layer="91"/> +<wire x1="181.61" y1="97.79" x2="181.61" y2="107.95" width="0.1524" layer="91"/> +<wire x1="181.61" y1="97.79" x2="129.54" y2="97.79" width="0.1524" layer="91"/> +<wire x1="129.54" y1="97.79" x2="129.54" y2="104.14" width="0.1524" layer="91"/> +<wire x1="144.78" y1="104.14" x2="129.54" y2="104.14" width="0.1524" layer="91"/> +<wire x1="129.54" y1="156.21" x2="129.54" y2="104.14" width="0.1524" layer="91"/> +<wire x1="102.87" y1="156.21" x2="129.54" y2="156.21" width="0.1524" layer="91"/> +<wire x1="181.61" y1="97.79" x2="196.85" y2="97.79" width="0.1524" layer="91"/> +<wire x1="196.85" y1="97.79" x2="196.85" y2="100.33" width="0.1524" layer="91"/> +<junction x="129.54" y="104.14"/> +<junction x="181.61" y="97.79"/> +<label x="160.9725" y="98.1075" size="1.778" layer="92"/> +<pinref part="RI79" gate="R" pin="2"/> +<pinref part="DI11" gate="F" pin="AC1"/> +<pinref part="RI73" gate="R" pin="1"/> +<pinref part="UI25" gate="S" pin="Y1"/> +<pinref part="TRI4" gate="B" pin="S22"/> +</segment> +</net> +<net name="F3R-A&T-A" class="0"> +<segment> +<wire x1="114.3" y1="127" x2="116.84" y2="127" width="0.1524" layer="91"/> +<wire x1="116.84" y1="127" x2="116.84" y2="133.35" width="0.1524" layer="91"/> +<wire x1="116.84" y1="133.35" x2="102.87" y2="133.35" width="0.1524" layer="91"/> +<wire x1="181.61" y1="121.92" x2="181.61" y2="127" width="0.1524" layer="91"/> +<wire x1="181.61" y1="127" x2="194.31" y2="127" width="0.1524" layer="91"/> +<wire x1="194.31" y1="127" x2="194.31" y2="113.03" width="0.1524" layer="91"/> +<wire x1="194.31" y1="113.03" x2="196.85" y2="113.03" width="0.1524" layer="91"/> +<wire x1="181.61" y1="127" x2="162.56" y2="127" width="0.1524" layer="91"/> +<wire x1="162.56" y1="121.92" x2="162.56" y2="127" width="0.1524" layer="91"/> +<wire x1="116.84" y1="127" x2="162.56" y2="127" width="0.1524" layer="91"/> +<junction x="181.61" y="127"/> +<junction x="162.56" y="127"/> +<junction x="116.84" y="127"/> +<pinref part="RI74" gate="R" pin="2"/> +<pinref part="UI27" gate="S" pin="Y1"/> +<pinref part="DI11" gate="F" pin="AC2"/> +<pinref part="UI31" gate="S" pin="Z"/> +<pinref part="TRI4" gate="B" pin="S11"/> +</segment> +</net> +<net name="F3AS-GND" class="0"> +<segment> +<wire x1="172.72" y1="49.53" x2="180.34" y2="49.53" width="0.1524" layer="91"/> +<wire x1="180.34" y1="49.53" x2="180.34" y2="54.61" width="0.1524" layer="91"/> +<wire x1="180.34" y1="54.61" x2="172.72" y2="54.61" width="0.1524" layer="91"/> +<wire x1="180.34" y1="49.53" x2="185.42" y2="49.53" width="0.1524" layer="91"/> +<wire x1="185.42" y1="49.53" x2="195.58" y2="49.53" width="0.1524" layer="91"/> +<wire x1="195.58" y1="49.53" x2="201.93" y2="49.53" width="0.1524" layer="91"/> +<wire x1="201.93" y1="49.53" x2="208.28" y2="49.53" width="0.1524" layer="91"/> +<wire x1="208.28" y1="49.53" x2="214.63" y2="49.53" width="0.1524" layer="91"/> +<wire x1="214.63" y1="49.53" x2="220.98" y2="49.53" width="0.1524" layer="91"/> +<wire x1="220.98" y1="49.53" x2="227.33" y2="49.53" width="0.1524" layer="91"/> +<wire x1="227.33" y1="49.53" x2="233.68" y2="49.53" width="0.1524" layer="91"/> +<wire x1="233.68" y1="49.53" x2="240.03" y2="49.53" width="0.1524" layer="91"/> +<wire x1="240.03" y1="49.53" x2="240.03" y2="55.88" width="0.1524" layer="91"/> +<wire x1="233.68" y1="49.53" x2="233.68" y2="55.88" width="0.1524" layer="91"/> +<wire x1="227.33" y1="49.53" x2="227.33" y2="55.88" width="0.1524" layer="91"/> +<wire x1="220.98" y1="49.53" x2="220.98" y2="55.88" width="0.1524" layer="91"/> +<wire x1="214.63" y1="49.53" x2="214.63" y2="55.88" width="0.1524" layer="91"/> +<wire x1="208.28" y1="49.53" x2="208.28" y2="55.88" width="0.1524" layer="91"/> +<wire x1="201.93" y1="49.53" x2="201.93" y2="55.88" width="0.1524" layer="91"/> +<wire x1="195.58" y1="49.53" x2="195.58" y2="55.88" width="0.1524" layer="91"/> +<wire x1="185.42" y1="55.88" x2="185.42" y2="49.53" width="0.1524" layer="91"/> +<junction x="180.34" y="49.53"/> +<junction x="233.68" y="49.53"/> +<junction x="227.33" y="49.53"/> +<junction x="220.98" y="49.53"/> +<junction x="214.63" y="49.53"/> +<junction x="208.28" y="49.53"/> +<junction x="201.93" y="49.53"/> +<junction x="195.58" y="49.53"/> +<junction x="185.42" y="49.53"/> +<label x="189.23" y="46.6725" size="1.778" layer="92"/> +<pinref part="RI70" gate="R" pin="1"/> +<pinref part="CI35" gate="C" pin="2"/> +<pinref part="UI32" gate="PWR" pin="G"/> +<pinref part="UI31" gate="PWR" pin="G"/> +<pinref part="UI30" gate="PWR" pin="G"/> +<pinref part="UI29" gate="PWR" pin="G"/> +<pinref part="UI28" gate="PWR" pin="G"/> +<pinref part="UI27" gate="PWR" pin="G"/> +<pinref part="UI26" gate="PWR" pin="G"/> +<pinref part="UI25" gate="PWR" pin="G"/> +<pinref part="DI12" gate="DIODE" pin="A"/> +</segment> +</net> +<net name="N3I$3" class="0"> +<segment> +<wire x1="217.17" y1="152.4" x2="217.17" y2="143.51" width="0.1524" layer="91"/> +<wire x1="207.01" y1="153.67" x2="209.55" y2="153.67" width="0.1524" layer="91"/> +<wire x1="209.55" y1="153.67" x2="209.55" y2="152.4" width="0.1524" layer="91"/> +<wire x1="209.55" y1="152.4" x2="217.17" y2="152.4" width="0.1524" layer="91"/> +<wire x1="209.55" y1="152.4" x2="209.55" y2="151.13" width="0.1524" layer="91"/> +<wire x1="209.55" y1="151.13" x2="207.01" y2="151.13" width="0.1524" layer="91"/> +<junction x="209.55" y="152.4"/> +<pinref part="CI31" gate="C" pin="2"/> +<pinref part="TRI4" gate="A" pin="P12"/> +<pinref part="TRI4" gate="A" pin="P21"/> +</segment> +</net> +<net name="F3-TERM" class="0"> +<segment> +<wire x1="158.75" y1="156.21" x2="158.75" y2="158.75" width="0.1524" layer="91"/> +<wire x1="158.75" y1="158.75" x2="152.4" y2="158.75" width="0.1524" layer="91"/> +<pinref part="UI32" gate="S" pin="S"/> +<label x="152.4" y="158.75" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="158.75" y1="121.92" x2="158.75" y2="123.19" width="0.1524" layer="91"/> +<wire x1="158.75" y1="123.19" x2="157.48" y2="123.19" width="0.1524" layer="91"/> +<pinref part="UI31" gate="S" pin="S"/> +<label x="157.48" y="123.19" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="F3-NTTE" class="0"> +<segment> +<wire x1="87.63" y1="109.22" x2="80.01" y2="109.22" width="0.1524" layer="91"/> +<wire x1="87.63" y1="97.79" x2="80.01" y2="97.79" width="0.1524" layer="91"/> +<wire x1="80.01" y1="97.79" x2="80.01" y2="109.22" width="0.1524" layer="91"/> +<wire x1="87.63" y1="120.65" x2="80.01" y2="120.65" width="0.1524" layer="91"/> +<wire x1="80.01" y1="109.22" x2="80.01" y2="120.65" width="0.1524" layer="91"/> +<wire x1="87.63" y1="132.08" x2="80.01" y2="132.08" width="0.1524" layer="91"/> +<wire x1="80.01" y1="120.65" x2="80.01" y2="132.08" width="0.1524" layer="91"/> +<wire x1="87.63" y1="143.51" x2="80.01" y2="143.51" width="0.1524" layer="91"/> +<wire x1="80.01" y1="132.08" x2="80.01" y2="143.51" width="0.1524" layer="91"/> +<wire x1="87.63" y1="154.94" x2="80.01" y2="154.94" width="0.1524" layer="91"/> +<wire x1="80.01" y1="154.94" x2="27.94" y2="154.94" width="0.1524" layer="91"/> +<wire x1="80.01" y1="143.51" x2="80.01" y2="154.94" width="0.1524" layer="91"/> +<junction x="80.01" y="109.22"/> +<junction x="80.01" y="120.65"/> +<junction x="80.01" y="132.08"/> +<junction x="80.01" y="143.51"/> +<junction x="80.01" y="154.94"/> +<pinref part="UI30" gate="S" pin="S"/> +<pinref part="UI29" gate="S" pin="S"/> +<pinref part="UI28" gate="S" pin="S"/> +<pinref part="UI27" gate="S" pin="S"/> +<pinref part="UI26" gate="S" pin="S"/> +<pinref part="UI25" gate="S" pin="S"/> +<label x="27.94" y="154.94" size="1.778" layer="92" rot="R180" xref="yes"/> +</segment> +</net> +<net name="VCC3" class="0"> +<segment> +<wire x1="15.24" y1="132.08" x2="15.24" y2="130.81" width="0.1524" layer="91"/> +<wire x1="15.24" y1="130.81" x2="22.86" y2="130.81" width="0.1524" layer="91"/> +<pinref part="RI81" gate="R" pin="2"/> +<pinref part="U$624" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="16.51" y1="102.87" x2="16.51" y2="101.6" width="0.1524" layer="91"/> +<wire x1="16.51" y1="101.6" x2="22.86" y2="101.6" width="0.1524" layer="91"/> +<pinref part="RI89" gate="R" pin="1"/> +<pinref part="U$627" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="166.37" y1="78.74" x2="161.29" y2="78.74" width="0.1524" layer="91"/> +<wire x1="161.29" y1="78.74" x2="161.29" y2="73.66" width="0.1524" layer="91"/> +<wire x1="161.29" y1="73.66" x2="167.64" y2="73.66" width="0.1524" layer="91"/> +<wire x1="161.29" y1="78.74" x2="153.67" y2="78.74" width="0.1524" layer="91"/> +<wire x1="153.67" y1="78.74" x2="153.67" y2="80.01" width="0.1524" layer="91"/> +<junction x="161.29" y="78.74"/> +<pinref part="RI71" gate="R" pin="1"/> +<pinref part="CI36" gate="C" pin="2"/> +<pinref part="U$635" gate="PW-VCC3" pin="VCC3"/> +</segment> +<segment> +<wire x1="116.84" y1="77.47" x2="116.84" y2="81.28" width="0.1524" layer="91"/> +<wire x1="116.84" y1="77.47" x2="116.84" y2="74.93" width="0.1524" layer="91"/> +<wire x1="93.98" y1="77.47" x2="116.84" y2="77.47" width="0.1524" layer="91"/> +<wire x1="93.98" y1="64.77" x2="93.98" y2="77.47" width="0.1524" layer="91"/> +<junction x="116.84" y="77.47"/> +<pinref part="RI90" gate="R" pin="1"/> +<pinref part="QI7" gate="B" pin="C"/> +<pinref part="U$636" gate="PW-VCC3" pin="VCC3"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +</eagle> |