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-rw-r--r--main.c133
1 files changed, 68 insertions, 65 deletions
diff --git a/main.c b/main.c
index a080774..dd46683 100644
--- a/main.c
+++ b/main.c
@@ -1,5 +1,5 @@
/*
- * XIOHV5.12 power sequence
+ * XIOH power sequence
* Copyright (C) 2012, 2013 Avencall
*
* main.c
@@ -190,13 +190,13 @@ static inline void init_s3n_st(void)
static void update_s3n_st(void)
{
if (S3N_ASSERTED) {
- if (!(P4IN & SLP_S3_N))
+ if (!SLP_S3_N(in))
init_s3n_st();
else if (((Timer_A_count - s3n_st) & S3N_COUNT_MASK)
>= S3N_DEASSERT_MS)
s3n_st = S3N_DEB_MASK;
} else /* S3N_DEASSERTED */ {
- if (P4IN & SLP_S3_N) {
+ if (SLP_S3_N(in)) {
s3n_st = S3N_DEB_MASK;
} else {
s3n_st++;
@@ -295,18 +295,18 @@ int main(void)
break;
case RST_PRESSED:
- ClrBit(P2REN, SYS_RESET_N);
- SetBit(P2DIR, SYS_RESET_N);
- ClrBit(P2OUT, SYS_RESET_N);
+ Set(SYS_RESET_N(dir));
+ Clr(SYS_RESET_N(ren));
+ Clr(SYS_RESET_N(out));
Timer2 = MS(150);
resetState = RST_WAIT;
break;
case RST_WAIT:
if (Timer2 == 0) {
- SetBit(P2OUT, SYS_RESET_N);
- ClrBit(P2DIR, SYS_RESET_N);
- SetBit(P2REN, SYS_RESET_N);
+ Set(SYS_RESET_N(out));
+ Set(SYS_RESET_N(ren));
+ Clr(SYS_RESET_N(dir));
if (SW2State == 0)
resetState = RST_NO;
}
@@ -344,7 +344,7 @@ int main(void)
switch (in_range(state, STATE_UPPER_LIMIT)) {
Xcase(MACHINE_OFF)
- ClrBit(P4OUT, CMDPWR);
+ Clr(CMDPWR(out));
#ifdef LOOP_REBOOT
change_state(WAIT_START_CMDPWR);
#endif
@@ -362,7 +362,7 @@ int main(void)
Xcase(WAIT_START_CMDPWR)
if (SW1State == 0) {
- SetBit(P4OUT, CMDPWR);
+ Set(CMDPWR(out));
// Start Atx Power Supply
Timer1 = MS(2000);
change_state(WAIT_ATX_START_V1P2);
@@ -373,9 +373,8 @@ int main(void)
/* WARNING: no timeout when not monitoring tensions */
if (SW1State || TENSION_EXPIRED)
change_state(STOP_INHIBIT);
- if ((P4IN & ATX_PWROK)
- && TENSION_WAIT(bV2P5 && bVCC3)) {
- ClrBit(P1OUT, V1P2_CORE_EN_N);
+ if (ATX_PWROK(in) && TENSION_WAIT(bV2P5 && bVCC3)) {
+ Clr(V1P2_CORE_EN_N(out));
Timer1 = MS(30);
change_state(WAIT_V1P2_START_V1P8);
}
@@ -386,7 +385,7 @@ int main(void)
change_state(STOP_INHIBIT);
if (TENSION_WAIT(bV1P2)) {
Timer1 = MS(30);
- SetBit(P4OUT, V1P8_CMD);
+ Set(V1P8_CMD(out));
change_state(DEASSERT_RSMRST_N);
}
break;
@@ -395,7 +394,7 @@ int main(void)
if (SW1State)
change_state(STOP_INHIBIT);
if (Timer1 < MS(19)) {
- SetBit(P2OUT, IMCH_RSMRST_N);
+ Set(IMCH_RSMRST_N(out));
change_state(WAIT_V1P8_START_V1P0);
}
break;
@@ -404,7 +403,7 @@ int main(void)
if (SW1State || TENSION_EXPIRED)
change_state(STOP_INHIBIT);
if (TENSION_WAIT(bV1P8)) {
- ClrBit(P2OUT, CPU_VCCP_EN_N);
+ Clr(CPU_VCCP_EN_N(out));
Timer1 = MS(30);
change_state(WAIT_V1P0_ASSERT_VRMPWRGD);
}
@@ -414,36 +413,36 @@ int main(void)
if (SW1State || TENSION_EXPIRED)
change_state(STOP_INHIBIT);
if (TENSION_WAIT(bV1P0)) {
- SetBit(P3OUT, VRMPWRGD);
- ClrBit(P2OUT, GREEN_LED_N);
+ Set(VRMPWRGD(out));
+ Clr(GREEN_LED_N(out));
Timer1 = MS(3);
change_state(ASSERT_CK410_PWR_GD_N);
}
break;
Xcase(ASSERT_CK410_PWR_GD_N)
- if (!(P4IN & ATX_PWROK))
+ if (!ATX_PWROK(in))
change_state(STOP_INHIBIT);
if (Timer1 == 0) {
- SetBit(P2DIR, CK410_PWR_GD_N);
- ClrBit(P2OUT, CK410_PWR_GD_N);
+ Set(CK410_PWR_GD_N(dir)); // BUGBUG REN
+ Clr(CK410_PWR_GD_N(out));
Timer1 = MS(105);
change_state(ASSERT_SYS_PWR_OK);
}
break;
Xcase(ASSERT_SYS_PWR_OK)
- if (!(P4IN & ATX_PWROK))
+ if (!ATX_PWROK(in))
change_state(STOP_INHIBIT);
if (Timer1 == 0) {
- SetBit(P3OUT, SYS_PWR_OK);
+ Set(SYS_PWR_OK(out));
Timer1 = MS(10);
change_state(PRESS_PWRBTN);
}
break;
Xcase(PRESS_PWRBTN)
- if (!(P4IN & ATX_PWROK))
+ if (!ATX_PWROK(in))
change_state(STOP_INHIBIT);
if (Timer1 == 0) {
// Start the EP80579 by driving IMCH_PWRBTN_N.
@@ -452,7 +451,7 @@ int main(void)
// in some cases it is only released after
// IMCH_PWRBTN_N has been driven, proving
// that this is necessary.
- SetBit(P2DIR, IMCH_PWRBTN_N);
+ Set(IMCH_PWRBTN_N(dir));
Timer1 = MS(50);
init_s3n_st();
change_state(RELEASE_PWRBTN);
@@ -460,11 +459,11 @@ int main(void)
break;
Xcase(RELEASE_PWRBTN)
- if (!(P4IN & ATX_PWROK))
+ if (!ATX_PWROK(in))
change_state(STOP_INHIBIT);
update_s3n_st();
if ((Timer1 == 0) || S3N_DEASSERTED) {
- ClrBit(P2DIR, IMCH_PWRBTN_N);
+ Clr(IMCH_PWRBTN_N(dir));
#ifdef LOOP_REBOOT
Timer1 = LOOP_REBOOT;
#endif
@@ -480,10 +479,10 @@ int main(void)
powerfail_recover = PF_MAX;
update_s3n_st();
if ((SW1State >= MS(3800)) // approx 4 seconds
- || S3N_ASSERTED) {
+ || S3N_ASSERTED) {
powerfail_recover = 0;
change_state(STOP_INHIBIT);
- } else if (!(P4IN & ATX_PWROK)) {
+ } else if (!ATX_PWROK(in)) {
change_state(STOP_INHIBIT);
}
break;
@@ -492,7 +491,7 @@ int main(void)
InitPorts();
// Disable any other Power up for 3 s:
Timer1 = MS(3000);
- ClrBit(P2OUT, RED_LED_N);
+ Clr(RED_LED_N(out));
change_state(STOP_FINAL);
break;
@@ -501,7 +500,7 @@ int main(void)
powerfail_recover = 0;
if ((Timer1 == 0) && (SW1State == 0)) {
// Restart is possible now: all leds off
- SetBit(P2OUT, RED_LED_N);
+ Set(RED_LED_N(out));
change_state(MACHINE_OFF);
}
break;
@@ -542,12 +541,12 @@ __interrupt void Timer_A(void)
Timer_A_count++;
- if (!(P1IN & START_SW1_N))
+ if (!START_SW_N(in))
SW1State++;
else
SW1State = 0;
- if (!(P1IN & RST_SW2_N))
+ if (!RST_SW_N(in))
SW2State++;
else
SW2State = 0;
@@ -564,38 +563,42 @@ __interrupt void Timer_A(void)
static void InitPorts(void)
{
- /* DIR: direction: 0 input 1 output
- * SEL: function: 0 gpio
- * REN: resistor enabled
- * OUT: output when REN=0 and DIR=1
- * 0 pull-down 1 pull-up if REN=1
- * IES: Interrupt Edge Select
- * IE: Interrupt Enable
- */
+#define DECLARE_PORT_INIT(port) \
+ u8 port##SEL_init = 0; \
+ u8 port##OUT_init = 0; \
+ u8 port##REN_init = 0; \
+ u8 port##DIR_init = 0;
+
+ DECLARE_PORT_INIT(P1)
+ DECLARE_PORT_INIT(P2)
+ DECLARE_PORT_INIT(P3)
+ DECLARE_PORT_INIT(P4)
+
+#define GD__gen_init(port, bit, dir, ren, sel, out) \
+ { \
+ port##REN_init |= ((ren) ? (bit) : 0); \
+ port##SEL_init |= ((sel) ? (bit) : 0); \
+ port##DIR_init |= ((dir) ? (bit) : 0); \
+ port##OUT_init |= ((out) ? (bit) : 0); \
+ }
+
+ ALL_SIGNALS(gen_init)
+
+#define INIT_PORT(port) \
+ port##SEL = port##SEL_init; \
+ port##OUT = port##OUT_init; \
+ port##REN = port##REN_init; \
+ port##DIR = port##DIR_init;
+
+ P1IE = 0;
+ P1IES = 0;
+ P2IE = 0;
+ P2IES = 0;
- P1DIR = P1DIR_INIT;
- P1SEL = P1SEL_INIT;
- P1REN = P1REN_INIT;
- P1OUT = P1OUT_INIT;
- P1IES = P1IES_INIT;
- P1IE = P1IE_INIT;
-
- P2OUT = P2OUT_INIT;
- P2SEL = P2SEL_INIT;
- P2REN = P2REN_INIT;
- P2DIR = P2DIR_INIT;
- P2IES = P2IES_INIT;
- P2IE = P2IE_INIT;
-
- P3OUT = P3OUT_INIT;
- P3SEL = P3SEL_INIT;
- P3DIR = P3DIR_INIT;
- P3REN = P3REN_INIT;
-
- P4OUT = P4OUT_INIT;
- P4SEL = P4SEL_INIT;
- P4DIR = P4DIR_INIT;
- P4REN = P4REN_INIT;
+ INIT_PORT(P1)
+ INIT_PORT(P2)
+ INIT_PORT(P3)
+ INIT_PORT(P4)
}
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-05 08:30:40 +0000