diff options
Diffstat (limited to 'hardware.h')
| -rw-r--r-- | hardware.h | 333 |
1 files changed, 239 insertions, 94 deletions
@@ -1,11 +1,9 @@ /* - * XIOHV5.12 power sequence - * Copyright (C) 2012 Avencall + * XIOH power sequence + * Copyright (C) 2013 Avencall * * hardware.h - platform definitions - * Authors: - * Jean-Marc Ouvrard - * Noe Rubinstein + * Author: * Guillaume Knispel * * This program is free software: you can redistribute it and/or modify @@ -25,96 +23,243 @@ #ifndef HARDWARE_H #define HARDWARE_H -// In signal names, - are replaced by _ - -// used in PORT1 -#define START_SW1_N BIT0 -#define V1P2_CORE_EN_N BIT1 -#define RST_SW2_N BIT2 -#define WDT_TOUT_N BIT3 - -// used in PORT2 -#define CK410_PWR_GD_N BIT0 -#define GP24 BIT1 -#define CPU_VCCP_EN_N BIT2 -#define GREEN_LED_N BIT3 -#define RED_LED_N BIT4 -#define SYS_RESET_N BIT5 -#define IMCH_PWRBTN_N BIT6 -#define IMCH_RSMRST_N BIT7 - -// used in PORT3 -#define VCC3 BIT0 -#define I2C_SMBDAT BIT1 -#define I2C_SMBCLK BIT2 -#define SYS_PWR_OK BIT3 -#define MSP_BSL_TXD BIT4 -#define MSP_BSL_RXD BIT5 -#define P1V8_PGOOD BIT6 -#define VRMPWRGD BIT7 - -// used in PORT4 -#define SLP_S3_N BIT0 -#define ATX_PWROK BIT1 -#define CMDPWR BIT2 -#define V1P0 BIT3 -#define V1P2 BIT4 -#define V1P8_DDR BIT5 -#define V2P5 BIT6 -#define V1P8_CMD BIT7 - -/* Information Config see datasheet -PxOUT_INIT //Init Output data of portx -PxDIR_INIT //Init of Portx Data-Direction Reg (Out=1 / Inp=0) -PxSEL_INIT //Px-Modules: -PxREN_INIT //Pull up resistor -PxIE_INIT //Interrupt Enable (0=dis 1=enabled) -PxIES_INIT //Interrupt Edge Select (0=pos 1=neg) +enum port_gpio { + P1, P2, P3, P4, // not really used; might detect spurious defines +}; + +enum gpio_dir { // fixed values + DIR_IN = 0, + DIR_OUT = 1, +}; + +enum gpio_ren { // fixed values + REN_NO = 0, + REN_PULL = 1, +}; + +enum gpio_sel { // fixed values + SEL_GPIO = 0, + SEL_PERIPH = 1, +}; + + +/* macros for dir_ren_sel */ +#define GPIO_IN_FLOAT DIR_IN, REN_NO, SEL_GPIO +#define GPIO_IN_PULL DIR_IN, REN_PULL, SEL_GPIO +#define GPIO_OUT DIR_OUT, REN_NO, SEL_GPIO +#define PERIPH DIR_IN, REN_NO, SEL_PERIPH + +/* +for i in xrange(1, 5): + for b in xrange(0, 8): + print "#define P" + str(i) + "_" + str(b) + \ + "\t\tP" + str(i) + ", BIT" + str(b) + print */ -// NOTES: -// -// * V1P2_CORE_EN_N is initialized as an output high for a reason! -// -// ATX specifies that there can be as much as 20 ms between 5V reaching -// its 95% level and 3.3V doing likewise. U5H1 (ISL6545) is powered by -// 5V, and Q5U1 (that disables it) has a pull-up to 3.3V on its gate. -// ISL6545 can ramp up its output between ~ 10 and 17 ms after -// Power On Reset (defined by an high enough voltage on the 5V plane), -// and might do it even before. -// So when only using the pull-up to 3.3V rail and with an ATX -// power supply that has a particular timing, V1P2 would start to -// ramp up too early. - - -// PORT1 -#define P1OUT_INIT (START_SW1_N | RST_SW2_N | V1P2_CORE_EN_N) -#define P1DIR_INIT (V1P2_CORE_EN_N) -#define P1SEL_INIT 0 -#define P1REN_INIT (START_SW1_N | RST_SW2_N) -#define P1IE_INIT 0 -#define P1IES_INIT 0 - -// PORT2 -#define P2OUT_INIT (CK410_PWR_GD_N | CPU_VCCP_EN_N | GREEN_LED_N \ - | RED_LED_N | SYS_RESET_N) -#define P2DIR_INIT (CPU_VCCP_EN_N | GREEN_LED_N | RED_LED_N \ - | IMCH_RSMRST_N) -#define P2REN_INIT (CK410_PWR_GD_N | SYS_RESET_N) -#define P2SEL_INIT 0 -#define P2IE_INIT 0 -#define P2IES_INIT 0 - -// PORT3 -#define P3OUT_INIT 0 -#define P3DIR_INIT (SYS_PWR_OK | VRMPWRGD) -#define P3REN_INIT 0 -#define P3SEL_INIT (MSP_BSL_TXD | MSP_BSL_RXD) - -// PORT4 -#define P4OUT_INIT 0 -#define P4DIR_INIT (CMDPWR | V1P8_CMD) -#define P4REN_INIT (SLP_S3_N) -#define P4SEL_INIT 0 +#define P1_0 P1, BIT0 +#define P1_1 P1, BIT1 +#define P1_2 P1, BIT2 +#define P1_3 P1, BIT3 +#define P1_4 P1, BIT4 +#define P1_5 P1, BIT5 +#define P1_6 P1, BIT6 +#define P1_7 P1, BIT7 + +#define P2_0 P2, BIT0 +#define P2_1 P2, BIT1 +#define P2_2 P2, BIT2 +#define P2_3 P2, BIT3 +#define P2_4 P2, BIT4 +#define P2_5 P2, BIT5 +#define P2_6 P2, BIT6 +#define P2_7 P2, BIT7 + +#define P3_0 P3, BIT0 +#define P3_1 P3, BIT1 +#define P3_2 P3, BIT2 +#define P3_3 P3, BIT3 +#define P3_4 P3, BIT4 +#define P3_5 P3, BIT5 +#define P3_6 P3, BIT6 +#define P3_7 P3, BIT7 + +#define P4_0 P4, BIT0 +#define P4_1 P4, BIT1 +#define P4_2 P4, BIT2 +#define P4_3 P4, BIT3 +#define P4_4 P4, BIT4 +#define P4_5 P4, BIT5 +#define P4_6 P4, BIT6 +#define P4_7 P4, BIT7 + +/** + * GD(w, port, bit, dir, ren, sel, out) - Gpio Descriptor + * + * GD describes both on which pin the signal is and the initial + * configuration to be given to it. + * + * w: Propagated from the parameter of the signal symbol + * At use time, this selects in which way the macro expands + * + * port: one of P1 to P4 - port in which the pin is + * bit: one of BIT0 to BIT7 - pin in the port + * + * =WARNING= see MSP430 datasheets and errata for restrictions + * on the following parameters + * + * dir: DIR_IN or DIR_OUT + * Initial value in register PxDIR + * Drive the output if DIR_OUT (only if ren=REN_NO) + * + * ren: REN_NO or REN_PULL + * Initial value in register PxREN + * Activate pull down / up if REN_PULL + * + * sel: SEL_GPIO or SEL_PERIPH + * Initial value in register PxSEL + * + * out: 0 or 1 + * Initial value in register PxOUT + * If sel=SEL_GPIO: + * If ren=REN_PULL: Pull down or up + * Else If dir=DIR_OUT: Drive low or high + */ +#define GD(w, port, bit, dir, ren, sel, out) \ + GD__##w(port, bit, dir, ren, sel, out) + +/** + * GD_(w, port_bit, dir_ren_sel, out) - Like GD(), except shorter + * + * GD_ lets you use shortcuts to describe signals and pins more concisely. + * + * w: Propagated from the parameter of the signal symbol + * At use time, this selects in which way the macro expands + * + * port_bit: for ex. P1_5 means bit 5 on port 1 + * + * dir_ren_sel: for ex. GPIO_IN_FLOAT or PERIPH + * + * out: 0 or 1, see description in GD() + */ +#define GD_(w, port_bit, dir_ren_sel, out) \ + GD(w, port_bit, dir_ren_sel, out) + +#define GD__out(port, bit, dir, ren, sel, out) (port##OUT), (bit) +#define GD__ren(port, bit, dir, ren, sel, out) (port##REN), (bit) +#define GD__sel(port, bit, dir, ren, sel, out) (port##SEL), (bit) +#define GD__dir(port, bit, dir, ren, sel, out) (port##DIR), (bit) + +#define GD__in(port, bit, dir, ren, sel, out) (!!((port##IN) & (bit))) + +#define GD__inreg(port, bit, dir, ren, sel, out) (port##IN) +#define GD__bit(port, bit, dir, ren, sel, out) (bit) + +#define SetBit(reg, bit) ((reg) |= (bit)) +#define ClrBit(reg, bit) ((reg) &= (~(bit))) + +#define Set(reg_bit) SetBit(reg_bit) +#define Clr(reg_bit) ClrBit(reg_bit) + +/* NOTES: + * + * * V1P2_CORE_EN_N is initialized as an output high for a reason! + * + * ATX specifies that there can be as much as 20 ms between 5V reaching + * its 95% level and 3.3V doing likewise. U5H1 (ISL6545) is powered by + * 5V, and Q5U1 (that disables it) has a pull-up to 3.3V on its gate. + * ISL6545 can ramp up its output between ~ 10 and 17 ms after + * Power On Reset (defined by an high enough voltage on the 5V plane), + * and might do it even before. + * So when only using the pull-up to 3.3V rail and with an ATX + * power supply that has a particular timing, V1P2 would start to + * ramp up too early. + */ + +/* PYTHON: +defines=""" + * WARNING: DON'T FORGET TO MAINTAIN ALL_SIGNALS(w) + */ +#define START_SW_N(w) GD_(w, P1_0, GPIO_IN_PULL, 1) +#define V1P2_CORE_EN_N(w) GD_(w, P1_1, GPIO_OUT, 1) +#define RST_SW_N(w) GD_(w, P1_2, GPIO_IN_PULL, 1) +#define WDT_TOUT_N(w) GD_(w, P1_3, GPIO_IN_FLOAT, 0) +#define CK410_PWR_GD_N(w) GD_(w, P2_0, GPIO_IN_PULL, 1) +#define GP24(w) GD_(w, P2_1, GPIO_IN_FLOAT, 0) +#define CPU_VCCP_EN_N(w) GD_(w, P2_2, GPIO_OUT, 1) +#define GREEN_LED_N(w) GD_(w, P2_3, GPIO_OUT, 1) +#define RED_LED_N(w) GD_(w, P2_4, GPIO_OUT, 1) +#define SYS_RESET_N(w) GD_(w, P2_5, GPIO_IN_PULL, 1) +#define IMCH_PWRBTN_N(w) GD_(w, P2_6, GPIO_IN_FLOAT, 0) +#define IMCH_RSMRST_N(w) GD_(w, P2_7, GPIO_OUT, 0) +#define VCC3(w) GD_(w, P3_0, GPIO_IN_FLOAT, 0) +#define I2C_SMBDAT(w) GD_(w, P3_1, GPIO_IN_FLOAT, 0) +#define I2C_SMBCLK(w) GD_(w, P3_2, GPIO_IN_FLOAT, 0) +#define SYS_PWR_OK(w) GD_(w, P3_3, GPIO_OUT, 0) +#ifdef TRACE_SERIAL +# define MSP_BSL_TXD(w) GD_(w, P3_4, PERIPH, 0) +# define MSP_BSL_RXD(w) GD_(w, P3_5, PERIPH, 0) +#else /* ndef TRACE_SERIAL */ +# define MSP_BSL_TXD(w) GD_(w, P3_4, GPIO_IN_FLOAT, 0) +# define MSP_BSL_RXD(w) GD_(w, P3_5, GPIO_IN_FLOAT, 0) +#endif /* TRACE_SERIAL */ +#define P1V8_PGOOD(w) GD_(w, P3_6, GPIO_IN_FLOAT, 0) +#define VRMPWRGD(w) GD_(w, P3_7, GPIO_OUT, 0) +#define SLP_S3_N(w) GD_(w, P4_0, GPIO_IN_PULL, 0) +#define ATX_PWROK(w) GD_(w, P4_1, GPIO_IN_FLOAT, 0) +#define CMDPWR(w) GD_(w, P4_2, GPIO_OUT, 0) +#define V1P0(w) GD_(w, P4_3, GPIO_IN_FLOAT, 0) +#define V1P2(w) GD_(w, P4_4, GPIO_IN_FLOAT, 0) +#define V1P8_DDR(w) GD_(w, P4_5, GPIO_IN_FLOAT, 0) +#define V2P5(w) GD_(w, P4_6, GPIO_IN_FLOAT, 0) +#define V1P8_CMD(w) GD_(w, P4_7, GPIO_OUT, 0) +/* + * WARNING: DON'T FORGET TO MAINTAIN ALL_SIGNALS(w) +""" +deflines = [line.strip() + for line in defines.splitlines() + if "define " in line] +import re +all_signals = list(set([re.search(r'define\s+([^\s]+)', line).group(1) + for line in deflines])) +def add_backslash(s): + return s + (" " * (20 - len(s))) + "\\" + +def print_stuff(): + print "#define ALL_SIGNALS(w)\t\t" + add_backslash(all_signals[0]) + for sig in all_signals[1:-1]: + print "\t\t\t\t" + add_backslash(sig) + print "\t\t\t\t" + all_signals[-1] + +print_stuff() + */ +#define ALL_SIGNALS(w) RED_LED_N(w) \ + CPU_VCCP_EN_N(w) \ + IMCH_RSMRST_N(w) \ + SYS_PWR_OK(w) \ + MSP_BSL_TXD(w) \ + V2P5(w) \ + START_SW_N(w) \ + RST_SW_N(w) \ + IMCH_PWRBTN_N(w) \ + ATX_PWROK(w) \ + V1P0(w) \ + WDT_TOUT_N(w) \ + VCC3(w) \ + I2C_SMBDAT(w) \ + V1P2(w) \ + P1V8_PGOOD(w) \ + MSP_BSL_RXD(w) \ + SLP_S3_N(w) \ + GREEN_LED_N(w) \ + GP24(w) \ + CK410_PWR_GD_N(w) \ + V1P8_CMD(w) \ + VRMPWRGD(w) \ + CMDPWR(w) \ + SYS_RESET_N(w) \ + V1P2_CORE_EN_N(w) \ + I2C_SMBCLK(w) \ + V1P8_DDR(w) #endif //HARDWARE_H |