add comments

1 files changed, 15 insertions, 1 deletions

diff --git a/main.c b/main.c
index 5df5758..a6a06be 100644
--- a/main.c
+++ b/main.c
@@ -97,6 +97,7 @@
 
 // UNEXPECTED_ISR_LIST *must* be manually maintained for IAR and TI
 // (UNEXPECTED_ISR_LIST will not be used during an mspgcc build)
+// Note that this does not include the vectors that are undefined on this chip.
 #define UNEXPECTED_ISR_LIST						\
     PORT1_VECTOR,PORT2_VECTOR,ADC10_VECTOR,USCIAB0TX_VECTOR,		\
     USCIAB0RX_VECTOR,TIMERA0_VECTOR,WDT_VECTOR,TIMERB1_VECTOR,		\
@@ -139,6 +140,9 @@ volatile u8 bVCC3 = true;
 #endif /* CAN_WAIT_TENSION */
 
 
+    ////////////////////////////////////////////////////////////////////
+
+
 enum machine_state {
 	MACHINE_OFF			= SV(0),
 	WAIT_START_CMDPWR		= SV(1),
@@ -165,6 +169,9 @@ enum reset_state {
 #define RESET_UPPER_LIMIT	RST_WAIT
 
 
+    ////////////////////////////////////////////////////////////////////
+
+
 u8 s3n_st = 0;
 #define S3N_COUNT_MASK		0x7fu
 #define S3N_DEB_MASK		0x80u
@@ -200,6 +207,9 @@ static void update_s3n_st(void)
 }
 
 
+    ////////////////////////////////////////////////////////////////////
+
+
 // It seems that TI compiler does not honor inlines from ISR
 #define reboot()	do { WDTCTL = 0; } while (1)
 
@@ -208,7 +218,11 @@ static void update_s3n_st(void)
 // autoboot after power failure max _PF_MAX+1 times (if power seq unsuccessful)
 #define _PF_MAX		0x03
 
-// powerfail_recover MUST BE EXPLICITELY INITIALIZED TO 0.
+// powerfail_recover MUST BE EXPLICITLY INITIALIZED TO 0.
+// (The "= 0" must be present in the source code.)
+// Initializing to 0 ensures that the board won't be unconditionally started
+// on an MSP power up -- this shall never be done unconditionally and at the
+// moment we have no code to check the conditions for which this would be safe.
 u8 powerfail_recover = 0;	// THIS IS SAFETY-RELATED.
 
 static inline u8 PF_COUNT(u8 v)