diff options
Diffstat (limited to 'Acceleration/library/icp_telephony')
77 files changed, 37648 insertions, 0 deletions
diff --git a/Acceleration/library/icp_telephony/Makefile b/Acceleration/library/icp_telephony/Makefile new file mode 100644 index 0000000..1964a7e --- /dev/null +++ b/Acceleration/library/icp_telephony/Makefile @@ -0,0 +1,148 @@ +############################################################################### +# +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# +############################################################################### + +# Ensure The ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +#Add your project environment Makefile +include $(ICP_ENV_DIR)/environment.mk + +##directories +BUILD_OUTPUT_DIR=build/$(ICP_OS)/$(ICP_OS_LEVEL)/#the folder where the output will be created. +FINAL_OUTPUT_DIR=$(BUILD_OUTPUT_DIR) + + +OUTPUT_NAME?=tdm_infra +LIB_STATIC=$(OUTPUT_NAME).a + + +MODULE_SOURCES= ssp_access/icp_sspacc_symbols.c tdm_io_access/icp_hssacc_symbols.c tdm_infrastructure_queue_manager/IxQMgrSymbols.c tdm_infrastructure_downloader/source/IxPiuDlSymbols.c tdm_infrastructure_message_handler/IxPiuMhSymbols.c + + + +INCLUDES+= -I$(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I$(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I$(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I$(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I$(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I$(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem\ + -I$(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt\ + -I$(ICP_OSAL_DIR)/common/include/modules/ioMem\ + -I$(ICP_OSAL_DIR)/common/include/modules/bufferMgt\ + -I$(src)/include \ + -I$(PWD)/include \ + -I$(ICP_API_DIR) \ + -I$(ICP_API_DIR)/hss \ + -I$(ICP_API_DIR)/accel_infra \ + -I$(ICP_OSAL_DIR)/common/include \ + -I$(ICP_TDM_IO_DIR)/include + +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DIX_HW_COHERENT_MEMORY=1 -DENABLE_IOMEM -DENABLE_BUFFERMGT +EXTRA_LDFLAGS+=-whole-archive + +# add the path and list of source libraries, +ADDITIONAL_KERNEL_LIBS=ssp_access/$(BUILD_OUTPUT_DIR)/sspAcc.a\ + tdm_infrastructure_downloader/$(BUILD_OUTPUT_DIR)/tdm_Dl.a\ + tdm_io_access/$(BUILD_OUTPUT_DIR)/tdmIOAcc.a\ + tdm_infrastructure_message_handler/$(BUILD_OUTPUT_DIR)/tdm_Mh.a \ + tdm_infrastructure_queue_manager/$(BUILD_OUTPUT_DIR)/tdm_qMgr.a \ + $(OSAL_RELATIVE_PATH)/lib/EP805XX/linux/linuxle/libosal.a + +SUBDIRS=ssp_access/ tdm_infrastructure_downloader/ tdm_io_access/ tdm_infrastructure_message_handler/ tdm_infrastructure_queue_manager/ + +kernel_module: lib_kernel + @echo 'Creating kernel module $(OUTPUT_NAME).ko'; \ + make -C $(KERNEL_SOURCE_ROOT)/ M=$(PWD) + echo "Copying outputs to $(BUILD_OUTPUT_DIR)";\ + test -d $(BUILD_OUTPUT_DIR) || mkdir -p $(BUILD_OUTPUT_DIR);\ + test -f lib.a && mv lib.a $(BUILD_OUTPUT_DIR)/$(LIB_STATIC);\ + test -f $(OUTPUT_NAME).ko && mv -f $(OUTPUT_NAME).ko $(BUILD_OUTPUT_DIR);\ + test -f $(OUTPUT_NAME).o && mv -f *.o $(BUILD_OUTPUT_DIR);\ + $(RM) -rf *.mod.* .*.cmd; + +obj-m := $(OUTPUT_NAME).o +$(OUTPUT_NAME)-objs := $(ADDITIONAL_KERNEL_LIBS)\ + $(patsubst %.c,%.o, $(MODULE_SOURCES)) + +lib_kernel::clean + @for dir in $(SUBDIRS); do \ + (echo ; echo $$dir :; cd $$dir; \ + ($(MAKE) clean && $(MAKE) lib_static) || return 1) \ + done + + +include $(ICP_BUILDSYSTEM_PATH)/build_files/Core/$(ICP_CORE).mk +include $(ICP_BUILDSYSTEM_PATH)/build_files/OS/$(ICP_OS).mk +##################################################################################### + + +.DEFAULT: kernel_module + + +clean: + @echo 'Removing derived objects...'; \ + $(RM) -rf *.o *.a *.mod.* *.ko .*.cmd; \ + $(RM) -rf .tmp_versions; \ + $(RM) -rf $(BUILD_OUTPUT_DIR); diff --git a/Acceleration/library/icp_telephony/environment.mk b/Acceleration/library/icp_telephony/environment.mk new file mode 100644 index 0000000..c3366e7 --- /dev/null +++ b/Acceleration/library/icp_telephony/environment.mk @@ -0,0 +1,108 @@ +##################################################################### +# +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +# +##################################################################### + +ICP_OSAL_DIR=$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL +OSAL_DIR=$(ICP_ROOT)/Acceleration/library/icp_utils/OSAL +ICP_API_DIR=$(ICP_ROOT)/Acceleration/include +API_DIR=$(ICP_ROOT)/Acceleration/include +ICP_BUILDSYSTEM_PATH=$(ICP_ROOT)/build_system +#access variables +ICP_ACC_DIR=$(ICP_ROOT)/Acceleration/library/icp_telephony +ICP_TDM_IO_DIR=$(ICP_ACC_DIR)/tdm_io_access +ICP_TDM_IO_NAME=tdmIOAcc +ICP_SSPACC_DIR=$(ICP_ACC_DIR)/ssp_access +ICP_TDM_QMGR_DIR=$(ICP_ACC_DIR)/tdm_infrastructure_queue_manager +ICP_TDM_QMGR_NAME=tdm_qMgr +ICP_TDM_MSG_HDLR_DIR=$(ICP_ACC_DIR)/tdm_infrastructure_message_handler +ICP_TDM_MSG_HDLR_NAME=tdm_Mh +ICP_TDM_DL_DIR=$(ICP_ACC_DIR)/tdm_infrastructure_downloader +ICP_TDM_DL_NAME=tdm_Dl + +OSAL_RELATIVE_PATH=../icp_utils/OSAL/ + +#driver variables +ICP_DRIVERS_DIR=$(ICP_ROOT)/Acceleration/drivers/icp_tdm +ICP_VOICE_DRV_DIR=$(ICP_DRIVERS_DIR)/hss_voice_driver +ICP_TDM_SETUP_DRV_DIR=$(ICP_DRIVERS_DIR)/tdm_setup_driver +ICP_COMMON_PLATFORM= +ICP_OS_TYPE= +ICP_SLASH= +ICP_DEVICE= + +#KERNEL_SOURCE_ROOT=/lib/modules/`uname -r`/build +#KERNEL_SOURCE_ROOT?=/localdisk/tolapai/linux-2.6.15.3 + +ICP_OS_LEVEL?=kernel_space +OS_LEVEL?=kernel_space + + +#OSAL VARIABLES +IX_TARGET?=linuxle +IX_OSAL_PLATFORM?=ixpTolapai +IX_HW_COHERENT_MEMORY?=1 + +ICP_INTEL_DEV?=YES + +ICP_CORE=ia +ICP_OS=linux_2.6 +CORE=ia +OS=linux_2.6 diff --git a/Acceleration/library/icp_telephony/ssp_access/Makefile b/Acceleration/library/icp_telephony/ssp_access/Makefile new file mode 100644 index 0000000..a2daba7 --- /dev/null +++ b/Acceleration/library/icp_telephony/ssp_access/Makefile @@ -0,0 +1,135 @@ +######################################################################### +# This Template Makefile will create the libraries, executables and module and place them in the output folder +# Remove the comments around the sections you wish to build for. +# +#Procedure +#1) Copy this template to the location of your source files +#2) "Common variables and defintions" must be filled out +#3) Edit as desired the "Libraries and executable section" and/or the "Linux kernel 2.6 Module section" depending on what you wish to build +#4) Remove the comments around the section and delete the other unnecessary section +#5) Save changes, return to command line and type "make". +# +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears all derived objects +# +# included makefiles +# common.mk - common defintions +# depend.mk - depend and cleandepend rules +# rules.mk - build rules. +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +# Ensure The ICP_BUILDSYSTEM_PATH envorionmental var is defined. +ifndef ICP_BUILDSYSTEM_PATH +$(error ICP_BUILDSYSTEM_PATH is undefined. Please set the path to the top of the build structure \ + "-> setenv ICP_BUILDSYSTEM_PATH <path>") +endif + +#Add your project environment Makefile, extra comment +include $(ICP_ENV_DIR)/environment.mk + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=sspAcc + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES = icp_sspacc.c + + +# Setup include directory +INCLUDES += -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/hss \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_OSAL_DIR)/common/include \ + -I $(ICP_OSAL_DIR)/common/ossl_shim/linux_kernel/include + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES += -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_SSPACC_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + +# Install the module to the output dir +install: module + + +###################Include rules and dependency makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules and dependency inclusion######################### + diff --git a/Acceleration/library/icp_telephony/ssp_access/icp_sspacc.c b/Acceleration/library/icp_telephony/ssp_access/icp_sspacc.c new file mode 100644 index 0000000..5e3dbb6 --- /dev/null +++ b/Acceleration/library/icp_telephony/ssp_access/icp_sspacc.c @@ -0,0 +1,1361 @@ +/** + * @file icp_sspacc.c + * + * @description Contents of this file provide the implementation of the Synchronous + * Serial Port (SSP) Access Library + * + * @ingroup icp_SspAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#include "IxOsal.h" +#include "icp_sspacc.h" + +#define PRIVATE static + + +/** + * Local #defines + */ +#define IX_SSP_CR0_OFFSET 0x0 /* SSP Control Register 0 (SSCR0) + offset from SSP Physical Address */ +#define IX_SSP_CR1_OFFSET 0x4 /* SSP Control Register 1 (SSCR1) + offset from SSP Physical Address */ +#define IX_SSP_SR_OFFSET 0x8 /* SSP Status Register (SSSR) + offset from SSP Physical Address */ +#define IX_SSP_DR_OFFSET 0x10 /* SSP Data Register (SSDR) + offset from SSP Physical Address */ + +#define IX_SSP_FIFO_EMPTY 0x00 /* SSP FIFO empty value is + zero */ +#define IX_SSP_FIFO_FULL 0x10 /* SSP FIFO full value is 16 */ + +#define IX_SSP_FIFO_FULL_OR_EMPTY 0x00/* FIFO level indicates it can + either be empty of full */ +#define IX_SSP_TX_FIFO_EXCEED_THLD 0x0 /* zero indicates a Tx FIFO + exceed threshold for the + Tx FIFO svc request bit of + the SSSR */ +#define IX_SSP_RX_FIFO_BELOW_THLD 0x0 /* zero indicates a Rx FIFO + below threshold for the Rx + FIFO svc request bit of the + SSSR */ +#define IX_SSP_IS_BUSY 0x1 /* One indicates a SSP busy for + the SSP busy bit of the SSSR */ +#define IX_SSP_TX_FIFO_FULL 0x0 /* zero indicates a TX FIFO Full + in the Tx FIFO not full bit + of the SSSR */ +#define IX_SSP_RX_FIFO_EMPTY 0x0 /* zero indicates a RX FIFO Empty + in the Rx FIFO not empty bit + of the SSSR */ +#define IX_SSP_OVERRUN_HAS_OCCURRED 0x1 /* one indicates an overrun has + occurred in the overrun bit + of the SSSR */ +#define IX_SSP_INTERRUPT_ENABLE 0x1 /* one enables the interrupt in + the SSCR1 */ +#define IX_SSP_INTERRUPT_DISABLE 0x0 /* one disables the interrupt in + the SSCR1 */ +#define IX_SSP_INTERRUPTED 0x1 /* one indicates an interrupt has + occured in the SSSR */ + +#define IX_SSP_SET_TO_BE_CLEARED 0x1 /* Use for write 1 to clear in + the registers */ + +/* #defines for mask and location of SSP Control and Status Registers + * contents */ +#define IX_SSP_SERIAL_CLK_RATE_LOC 0x8 +#define IX_SSP_SERIAL_CLK_RATE_MASK (0xFF << IX_SSP_SERIAL_CLK_RATE_LOC) +#define IX_SSP_PORT_STATUS_LOC 0x7 +#define IX_SSP_PORT_STATUS_MASK (0x1 << IX_SSP_PORT_STATUS_LOC) +#define IX_SSP_CLK_SRC_LOC 0x6 +#define IX_SSP_CLK_SRC_MASK (0x1 << IX_SSP_CLK_SRC_LOC) +#define IX_SSP_FRAME_FORMAT_LOC 0x4 +#define IX_SSP_FRAME_FORMAT_MASK (0x3 << IX_SSP_FRAME_FORMAT_LOC) +#define IX_SSP_DATA_SIZE_LOC 0x0 +#define IX_SSP_DATA_SIZE_MASK (0xF << IX_SSP_DATA_SIZE_LOC) +#define IX_SSP_RX_FIFO_THLD_LOC 0xA +#define IX_SSP_RX_FIFO_THLD_MASK (0xF << IX_SSP_RX_FIFO_THLD_LOC) +#define IX_SSP_TX_FIFO_THLD_LOC 0x6 +#define IX_SSP_TX_FIFO_THLD_MASK (0xF << IX_SSP_TX_FIFO_THLD_LOC) +#define IX_SSP_MICROWIRE_CTL_WORD_LOC 0x5 +#define IX_SSP_MICROWIRE_CTL_WORD_MASK (0x1 << IX_SSP_MICROWIRE_CTL_WORD_LOC) +#define IX_SSP_SPI_SCLK_PHASE_LOC 0x4 +#define IX_SSP_SPI_SCLK_PHASE_MASK (0x1 << IX_SSP_SPI_SCLK_PHASE_LOC) +#define IX_SSP_SPI_SCLK_POLARITY_LOC 0x3 +#define IX_SSP_SPI_SCLK_POLARITY_MASK (0x1 << IX_SSP_SPI_SCLK_POLARITY_LOC) +#define IX_SSP_LOOPBACK_ENABLE_LOC 0x2 +#define IX_SSP_LOOPBACK_ENABLE_MASK (0x1 << IX_SSP_LOOPBACK_ENABLE_LOC) +#define IX_SSP_TX_FIFO_INT_ENABLE_LOC 0x1 +#define IX_SSP_TX_FIFO_INT_ENABLE_MASK (0x1 << IX_SSP_TX_FIFO_INT_ENABLE_LOC) +#define IX_SSP_RX_FIFO_INT_ENABLE_LOC 0x0 +#define IX_SSP_RX_FIFO_INT_ENABLE_MASK (0x1 << IX_SSP_RX_FIFO_INT_ENABLE_LOC) +#define IX_SSP_RX_FIFO_LVL_LOC 0xC +#define IX_SSP_RX_FIFO_LVL_MASK (0xF << IX_SSP_RX_FIFO_LVL_LOC) +#define IX_SSP_TX_FIFO_LVL_LOC 0x8 +#define IX_SSP_TX_FIFO_LVL_MASK (0xF << IX_SSP_TX_FIFO_LVL_LOC) +#define IX_SSP_RX_FIFO_OVERRUN_LOC 0x7 +#define IX_SSP_RX_FIFO_OVERRUN_MASK (0x1 << IX_SSP_RX_FIFO_OVERRUN_LOC) +#define IX_SSP_RX_FIFO_SVC_REQ_LOC 0x6 +#define IX_SSP_RX_FIFO_SVC_REQ_MASK (0x1 << IX_SSP_RX_FIFO_SVC_REQ_LOC) +#define IX_SSP_TX_FIFO_SVC_REQ_LOC 0x5 +#define IX_SSP_TX_FIFO_SVC_REQ_MASK (0x1 << IX_SSP_TX_FIFO_SVC_REQ_LOC) +#define IX_SSP_BUSY_LOC 0x4 +#define IX_SSP_BUSY_MASK (0x1 << IX_SSP_BUSY_LOC) +#define IX_SSP_RX_FIFO_NOT_EMPTY_LOC 0x3 +#define IX_SSP_RX_FIFO_NOT_EMPTY_MASK (0x1 << IX_SSP_RX_FIFO_NOT_EMPTY_LOC) +#define IX_SSP_TX_FIFO_NOT_FULL_LOC 0x2 +#define IX_SSP_TX_FIFO_NOT_FULL_MASK (0x1 << IX_SSP_TX_FIFO_NOT_FULL_LOC) + +#define ICP_SSP_MAP_SIZE 0x14 +/** + * macros + */ +#define IX_SSP_INIT_SUCCESS_CHECK(funcName, returnType) \ + if(ICP_FALSE == ixSspAccInitComplete){ \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \ + funcName": SSP Access not initialized\n", \ + 0,0,0,0,0,0); \ + return returnType; \ + } /* end of ICP_FALSE == ixSspAccInitComplete */ + + +#ifdef SW_SWAPPING +#define IX_SSP_READ_REGISTER(wAddr) \ + IX_OSAL_READ_BE_SHARED_LONG((uint32_t *) wAddr) +#define IX_SSP_WRITE_REGISTER(wAddr, wData) \ + IX_OSAL_WRITE_BE_SHARED_LONG((uint32_t *)wAddr, wData) +#else +#define IX_SSP_READ_REGISTER(wAddr) \ + IX_OSAL_READ_LONG_RAW((uint32_t *) wAddr) +#define IX_SSP_WRITE_REGISTER(wAddr, wData) \ + IX_OSAL_WRITE_LONG_RAW((uint32_t *)wAddr, wData) +#endif /*SSP_SWAP*/ + + +#define ICP_SSPACC_MAJOR_VERSION 1 +#define ICP_SSPACC_MINOR_VERSION 0 +#define ICP_SSPACC_PATCH_VERSION 1 +#define ICP_SSPACC_DEBUG_MODULE_NAME "SSP" + + +/** + * typedef + */ + +/* typedef to contain both SSP Control Register 0 and 1 */ +typedef struct +{ + uint32_t sscr0; + uint32_t sscr1; +} IxSspAccConfig; + +/** + * Static variables defined here + */ + +/* Interrupt handler function pointers */ +PRIVATE icp_sspacc_rx_fifo_overrun_handler_t ixRxFIFOOverrunHdlr = NULL; +PRIVATE icp_sspacc_rx_fifo_threshold_handler_t ixRxFIFOThsldHdlr = NULL; +PRIVATE icp_sspacc_tx_fifo_threshold_handler_t ixTxFIFOThsldHdlr = NULL; + +/* The addresses to be used to access the SSP Control Register 0 (CR0), + SSP Control Register 1 (CR1), SSP Status Register (SR), and SSP + Data Register (DR). The address is assigned on init. */ +PRIVATE uint32_t ixSspCR0Addr = 0; +PRIVATE uint32_t ixSspCR1Addr = 0; +PRIVATE uint32_t ixSspSRAddr = 0; +PRIVATE uint32_t ixSspDRAddr = 0; + +/* Storage for the SSP configuration which is used over many functions to +increase efficiency */ +PRIVATE IxSspAccConfig ixSspAccCfgStored; + +/* Storage for the SSP status which is used by many functions to avoid + declaration of the same struct multiple times */ +PRIVATE uint32_t ixSspAccStsStored; + +/* Storage for the SSP statistics counters */ +PRIVATE icp_sspacc_stats_counters_t ixSspAccStatsCounters; + +/* Flag to indicate if the mode is interrupt or poll. */ +PRIVATE icp_boolean_t ixSspAccInterruptMode = ICP_FALSE; + +/* Flag to indicate if the init has been done and thus not performing some + instructions that should not be done more than once (please refer to the + init API. Example: memory mapping). if init is called more than once + (which is allowed) */ +PRIVATE icp_boolean_t ixSspAccInitComplete = ICP_FALSE; + +/* Flag to indicate if the physical address of the SSP unit has been set */ +PRIVATE icp_boolean_t ixSspAccPhysicalAddressSet = ICP_FALSE; + +/* Storage for the SSP phiysical address base register */ +PRIVATE uint32_t ixSspPhysicalRegisterBase = 0x00; +/* Flag to indicate if the interrupt number of the SSP unit has been set */ +PRIVATE icp_boolean_t ixSspAccInterruptNumberSet = ICP_FALSE; + +/* Storage for the SSP interrupt number */ +PRIVATE unsigned int ixSspAccInterruptNumber = 0; + +/** + * static function declaration + */ +PRIVATE void ixSspAccInterruptDetected (void); + +/** + * Function definitions + */ + +icp_status_t +icp_SspAccInterruptSet ( + unsigned int interruptNumber) +{ + + icp_status_t status = ICP_STATUS_FAIL; + + if(ICP_FALSE == ixSspAccInitComplete) + { + ixSspAccInterruptNumber = interruptNumber; + ixSspAccInterruptNumberSet = ICP_TRUE; + status = ICP_STATUS_SUCCESS; + } + return status; +} + +icp_status_t +icp_SspAccPhysicalAddressSet ( + uint32_t address) +{ + + icp_status_t status = ICP_STATUS_FAIL; + + if(ICP_FALSE == ixSspAccInitComplete) + { + ixSspPhysicalRegisterBase = address; + ixSspAccPhysicalAddressSet = ICP_TRUE; + status = ICP_STATUS_SUCCESS; + } + return status; +} + +icp_status_t +icp_SspAccInit ( + icp_sspacc_init_vars_t *initVarsSelected) +{ + icp_status_t temp_return = ICP_STATUS_SUCCESS; + + /* Check if the initVarsSelected is NULL */ + if(NULL == initVarsSelected) + { + return ICP_STATUS_NULL_PARAM; + } + + /* Check if SSP Init has been called before to avoid multiple instances of + memory mapping */ + if(ICP_FALSE == ixSspAccInitComplete) + { + /* Memory map the control, status, and data registers of the SSP */ + if(ICP_TRUE == ixSspAccPhysicalAddressSet) + { + ixSspCR0Addr = (uint32_t)ixOsalIoRemap + (ixSspPhysicalRegisterBase, ICP_SSP_MAP_SIZE); + + + + ixSspCR1Addr = ixSspCR0Addr + IX_SSP_CR1_OFFSET; + ixSspSRAddr = ixSspCR0Addr + IX_SSP_SR_OFFSET; + ixSspDRAddr = ixSspCR0Addr + IX_SSP_DR_OFFSET; + /* Reset the hardware*/ + IX_SSP_WRITE_REGISTER(ixSspCR0Addr, 0x00); + icp_SspAccStatsReset(); /* Clear the SSP statistics counters */ + } + else + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccInit: Base Address not set.\n", + 0,0,0,0,0,0); + return ICP_STATUS_RESOURCE; + } + + ixSspAccInitComplete = ICP_TRUE; /* Set the Init Complete flag so + that a call to init will not + mem map, clear the stats and + register with the debug + component again*/ + } /* end of ICP_FALSE == ixSspAccInitComplete */ + + /* Set the SSP frame format (SPI, SSP, or Microwire) if format is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccFrameFormatSelect( + initVarsSelected->frameFormatSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Set the data size if range is valid and FIFOs empty */ + temp_return = icp_SspAccDataSizeSelect(initVarsSelected->dataSizeSelected); + if(ICP_STATUS_SUCCESS != temp_return) + { + return temp_return; + } + + /* Set the clock source if source is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccClockSourceSelect( + initVarsSelected->clkSourceSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Set the Tx FIFO Threshold if level is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccTxFifoThresholdSet( + initVarsSelected->txFIFOThresholdSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Set the Rx FIFO Threshold if level is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccRxFifoThresholdSet( + initVarsSelected->rxFIFOThresholdSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Unbind the SSP ISR if interrupt mode was enabled previously */ + if(ICP_TRUE == ixSspAccInterruptMode) + { + if(IX_SUCCESS != ixOsalIrqUnbind(ixSspAccInterruptNumber)) + { + return ICP_STATUS_RESOURCE; + } /* end of ixOsalIrqUnbind Fail */ + icp_SspAccRxFifoIntDisable(); + icp_SspAccTxFifoIntDisable(); + ixSspAccInterruptMode = ICP_FALSE; + } /* end of ixSspAccInterruptMode == ICP_TRUE */ + + /* Check if either the Rx FIFO or the Tx FIFO interrupt is selected to be + enabled, then enable interrupt mode */ + if((ICP_TRUE == initVarsSelected->txFIFOIntrEnable) || + (ICP_TRUE == initVarsSelected->rxFIFOIntrEnable)) + { + /* Check if the Rx FIFO Overrun handler is NULL */ + if(NULL == initVarsSelected->rxFIFOOverrunHdlr) + { + return ICP_STATUS_NULL_PARAM; + } + + /* Set the Rx FIFO Overrun handler */ + ixRxFIFOOverrunHdlr = initVarsSelected->rxFIFOOverrunHdlr; + if(ICP_TRUE == ixSspAccInterruptNumberSet) + { + /* Bind the SSP to the SSP ISR */ + if(IX_SUCCESS != ixOsalIrqBind(ixSspAccInterruptNumber, + (IxOsalVoidFnVoidPtr)ixSspAccInterruptDetected, + NULL)) + { + return ICP_STATUS_RESOURCE; + } + ixSspAccInterruptMode = ICP_TRUE; /* Set the Interrupt Mode flag to + ICP_TRUE */ + } + else + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccInit: Interrupt number not set.\n", + 0,0,0,0,0,0); + return ICP_STATUS_RESOURCE; + } + + } /* end of interrupt mode selected */ + else /* start of polling mode selected */ + { + /* Set the Rx FIFO Overrun handler to NULL */ + ixRxFIFOOverrunHdlr = NULL; + + ixSspAccInterruptMode = ICP_FALSE; /* Set the Interrupt Mode flag to + ICP_FALSE */ + } /* end of polling mode selected */ + + /* Check if the Rx FIFO interrupt is selected to be enabled */ + if(ICP_TRUE == initVarsSelected->rxFIFOIntrEnable) + { + /* Enable the Rx FIFO and set the Rx FIFO handler if handler pointer is + not NULL */ + if(ICP_STATUS_SUCCESS != icp_SspAccRxFifoIntEnable( + initVarsSelected->rxFIFOThsldHdlr)) + { + return ICP_STATUS_NULL_PARAM; + } + } /* end of Rx FIFOIntrEnable Selected */ + + /* Check if the Tx FIFO interrupt is selected to be enabled */ + if(ICP_TRUE == initVarsSelected->txFIFOIntrEnable) + { + /* Enable the Tx FIFO and set the Tx FIFO handler if handler pointer is + not NULL */ + if(ICP_STATUS_SUCCESS != icp_SspAccTxFifoIntEnable( + initVarsSelected->txFIFOThsldHdlr)) + { + return ICP_STATUS_NULL_PARAM; + } + } /* end of Tx FIFOIntrEnable Selected */ + + /* Enable/disable the loopback */ + icp_SspAccLoopbackEnable(initVarsSelected->loopbackEnable); + + if(ICP_SSPACC_FRAME_FORMAT_SPI == initVarsSelected->frameFormatSelected) + { + /* Set the SPI SCLK phase if phase selected is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccSpiSclkPhaseSet( + initVarsSelected->spiSclkPhaseSelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Set the SPI SCLK polarity if polarity selected is valid */ + if(ICP_STATUS_SUCCESS != icp_SspAccSpiSclkPolaritySet( + initVarsSelected->spiSclkPolaritySelected)) + { + return ICP_STATUS_INVALID_PARAM; + } + } /* end of ICP_SSPACC_FRAME_FORMAT_SPI */ + + if(ICP_SSPACC_FRAME_FORMAT_MICROWIRE == + initVarsSelected->frameFormatSelected) + { + /* Set the Microwire control word size if size is valid and Tx FIFO + * empty */ + temp_return = icp_SspAccMicrowireControlWordSet( + initVarsSelected->microwireCtlWordSelected); + if(ICP_STATUS_SUCCESS != temp_return) + { + if(ICP_STATUS_RESOURCE == temp_return) + { + return ICP_STATUS_RESOURCE; + } + else + { + return ICP_STATUS_INVALID_PARAM; + } + } /* end of temp_return != ICP_STATUS_SUCCESS */ + } /* end of ICP_SSPACC_FRAME_FORMAT_MICROWIRE */ + + /* Set the Serial clock rate to the selected */ + icp_SspAccSerialClockRateConfigure(initVarsSelected->serialClkRateSelected); + + /* Enable the SSP Port to start receiving and transmitting data */ + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_ENABLE); + + return ICP_STATUS_SUCCESS; +} /* endo of icp_SspAccInit */ + + +icp_status_t +icp_SspAccUninit ( + void) +{ + if(ICP_TRUE == ixSspAccInitComplete) + { + /* Disable the SSP hardware */ + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_DISABLE); + + /* Unbind the SSP ISR if interrupt mode is enabled */ + if(ICP_TRUE == ixSspAccInterruptMode) + { + if(IX_SUCCESS != ixOsalIrqUnbind(ixSspAccInterruptNumber)) + { + return ICP_STATUS_FAIL; + } /* end of ixOsalIrqUnbind Fail */ + icp_SspAccRxFifoIntDisable(); + icp_SspAccTxFifoIntDisable(); + /* Set all Handler pointers to NULL */ + ixRxFIFOOverrunHdlr = NULL; + ixSspAccInterruptMode = ICP_FALSE; + } /* end of ICP_TRUE == ixSspAccInterruptMode */ + + /* Return the memory that was mapped during init which is the SSP + control and status registers and the SSP data register. */ + ixOsalIoUnmap(ixSspCR0Addr, ICP_SSP_MAP_SIZE); + + ixSspAccInitComplete = ICP_FALSE; + } /* end of ICP_TRUE == ixSspAccInitComplete */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccUninit */ + +icp_status_t +icp_SspAccFifoDataSubmit ( + uint16_t* data, + uint32_t amtOfData) +{ + uint32_t dataLoc = 0; + + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccFifoDataSubmit", ICP_STATUS_RESOURCE); + + /* Check if the data pointer provided is NULL */ + if(NULL == data) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccFifoDataSubmit: data pointer is NULL.\n", + 0,0,0,0,0,0); + return ICP_STATUS_NULL_PARAM; + } /* end of NULL == data */ + + /* Check if the Tx FIFO has sufficient space to store the number of data + specified by amtOfData */ + if((icp_SspAccTxFifoLevelGet() + amtOfData) > IX_SSP_FIFO_FULL) + { + return ICP_STATUS_FAIL; + } + + /* Copy the data from the data buffer pointer into the SSP Data Register */ + while(amtOfData > dataLoc) + { + IX_SSP_WRITE_REGISTER(ixSspDRAddr, (uint32_t)data[dataLoc]); + dataLoc++; + } + + /* Increment the SSP stats counter for data transmitted */ + ixSspAccStatsCounters.xmitCounter+=amtOfData; + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccFifoDataSubmit */ + +icp_status_t +icp_SspAccFifoDataReceive ( + uint16_t* data, + uint32_t amtOfData) +{ + uint32_t dataLoc = 0; + + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccFifoDataReceive", ICP_STATUS_RESOURCE); + + /* Check if the data pointer provided is NULL */ + if(NULL == data) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccFifoDataReceive: data pointer is NULL.\n", + 0,0,0,0,0,0); + return ICP_STATUS_NULL_PARAM; + } /* end of NULL == data */ + + /* Check if the Rx FIFO has the number of data specified by amtOfData to be + retrieved */ + if(icp_SspAccRxFifoLevelGet() < amtOfData) + { + return ICP_STATUS_FAIL; + } + + /* Overrun Check is called to increment the overrun counter if it occured + and not used to determine whether an overrun occured therefore no + checking of the return value is necessary */ + icp_SspAccRxFifoOverrunCheck(); + + /* Copy the data from the SSP Data Register into the data buffer pointer */ + while(amtOfData > dataLoc) + { + data[dataLoc] = (uint16_t) IX_SSP_READ_REGISTER(ixSspDRAddr); + dataLoc++; + } + + + /* Increment the SSP stats counter for data received */ + ixSspAccStatsCounters.rcvCounter+=amtOfData; + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccFifoDataReceive */ + +icp_status_t +icp_SspAccTxFifoHitLowThresholdCheck ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoHitLowThresholdCheck", + ICP_STATUS_RESOURCE); + + /* Read the SSP status register, SSSR */ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + + /* Check the Tx FIFO Service Request bit has been set to determine if the + threshold has been hit or is below */ + if(IX_SSP_TX_FIFO_EXCEED_THLD == + ((ixSspAccStsStored & IX_SSP_TX_FIFO_SVC_REQ_MASK) >> + IX_SSP_TX_FIFO_SVC_REQ_LOC)) + { + return ICP_STATUS_FAIL; + } + else + { + return ICP_STATUS_SUCCESS; + } +} /* end of icp_SspAccTxFifoHitLowThresholdCheck */ + +icp_status_t +icp_SspAccRxFifoHitHighThresholdCheck ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoHitHighThresholdCheck", + ICP_STATUS_RESOURCE); + + /* Read the SSP status register, SSSR */ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + + /* Check the Rx FIFO Service Request bit has been set to determine if the + threshold has been hit or is above */ + if(IX_SSP_RX_FIFO_BELOW_THLD == + ((ixSspAccStsStored & IX_SSP_RX_FIFO_SVC_REQ_MASK) >> + IX_SSP_RX_FIFO_SVC_REQ_LOC)) + { + return ICP_STATUS_FAIL; + } + else + { + return ICP_STATUS_SUCCESS; + } +} /* end of icp_SspAccRxFifoHitHighThresholdCheck */ + +/** + * Configuration functions + */ + +icp_status_t +icp_SspAccSspPortStatusSet ( + icp_sspacc_port_status_t portStatusSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSspPortStatusSet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(portStatusSelected >= ICP_SSPACC_PORT_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the SSP Port Enable of SSCR0 register if + selected differ from current status */ + if(((ixSspAccCfgStored.sscr0 & IX_SSP_PORT_STATUS_MASK) >> + IX_SSP_PORT_STATUS_LOC) != portStatusSelected) + { + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_PORT_STATUS_MASK)) | + (portStatusSelected << IX_SSP_PORT_STATUS_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + } /* end of parameter write when current differs from selected */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccSspPortStatusSet */ + +icp_status_t +icp_SspAccFrameFormatSelect ( + icp_sspacc_frame_format_t frameFormatSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccFrameFormatSelect", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(frameFormatSelected >= ICP_SSPACC_FRAME_FORMAT_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Determine if the SSP port is enabled. */ + if (ICP_SSPACC_PORT_ENABLE == + ((ixSspAccCfgStored.sscr0 & IX_SSP_PORT_STATUS_MASK) >> + IX_SSP_PORT_STATUS_LOC)) + { + /* SSP Port enabled. + Disable the SSP Port (clears FIFOs), then write the parameter + into the Frame Format bit of SSCR0 register and re-enable the SSP + Port. */ + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_DISABLE); + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_FRAME_FORMAT_MASK)) | + (frameFormatSelected << IX_SSP_FRAME_FORMAT_LOC); + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_ENABLE); /* Both the format + and the status will + be written into the + SSCR0 register + together.*/ + } /* end of ICP_SSPACC_PORT_ENABLE */ + else /* start of ICP_SSPACC_PORT_DISABLE */ + { + /* SSP Port not enabled. + Write the parameter into the Frame Format bit of SSCR0 register */ + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_FRAME_FORMAT_MASK)) | + (frameFormatSelected << IX_SSP_FRAME_FORMAT_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + } /* end of ICP_SSPACC_PORT_DISABLE */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccFrameFormatSelect */ + +icp_status_t +icp_SspAccDataSizeSelect ( + icp_sspacc_data_size_t dataSizeSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccDataSizeSelect", ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if( (dataSizeSelected <= ICP_SSPACC_DATA_SIZE_TOO_SMALL) || + (dataSizeSelected >= ICP_SSPACC_DATA_SIZE_TYPE_DELIMITER) ) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Only allow change if Tx FIFO is empty */ + if(IX_SSP_FIFO_EMPTY != icp_SspAccTxFifoLevelGet()) + { + return ICP_STATUS_RESOURCE; + } + + /* Only allow change if Rx FIFO is empty */ + if(IX_SSP_FIFO_EMPTY != icp_SspAccRxFifoLevelGet()) + { + return ICP_STATUS_RESOURCE; + } + + /* Determine if the SSP port is enabled. */ + if (ICP_SSPACC_PORT_ENABLE == + ((ixSspAccCfgStored.sscr0 & IX_SSP_PORT_STATUS_MASK) >> + IX_SSP_PORT_STATUS_LOC)) + { + /* SSP Port enabled. + Disable the SSP Port (clears FIFOs), then write the parameter + into the data size select bit of SSCR0 register and re-enable the + SSP Port. */ + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_DISABLE); + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_DATA_SIZE_MASK)) | + (dataSizeSelected << IX_SSP_DATA_SIZE_LOC); + icp_SspAccSspPortStatusSet(ICP_SSPACC_PORT_ENABLE); /* Both the data + size and the status + will be written + into the SSCR0 + register together. + */ + } /* end of ICP_SSPACC_PORT_ENABLE */ + else /* start of ICP_SSPACC_PORT_DISABLE */ + { + /* SSP Port not enabled. + Write the parameter into the data size select bit of SSCR0 + register */ + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_DATA_SIZE_MASK)) | + (dataSizeSelected << IX_SSP_DATA_SIZE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + } /* end of ICP_SSPACC_PORT_DISABLE */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccDataSizeSelect */ + +icp_status_t +icp_SspAccClockSourceSelect ( + icp_sspacc_clk_source_t clkSourceSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccClockSourceSelect", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(clkSourceSelected >= ICP_SSPACC_CLK_SOURCE_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the Clock Source bit of SSCR0 register */ + ixSspAccCfgStored.sscr0 = (ixSspAccCfgStored.sscr0 & + (~IX_SSP_CLK_SRC_MASK)) + | (clkSourceSelected << IX_SSP_CLK_SRC_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccClockSourceSelect */ + +icp_status_t +icp_SspAccSerialClockRateConfigure ( + uint8_t serialClockRateSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSerialClockRateConfigure", + ICP_STATUS_RESOURCE); + + /* Write the parameter into the Clock Rate bits of SSCR0 register */ + ixSspAccCfgStored.sscr0 = + (ixSspAccCfgStored.sscr0 & (~IX_SSP_SERIAL_CLK_RATE_MASK)) | + (serialClockRateSelected << IX_SSP_SERIAL_CLK_RATE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR0Addr, ixSspAccCfgStored.sscr0); + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccSerialClockRateConfigure */ + +icp_status_t +icp_SspAccRxFifoIntEnable ( + icp_sspacc_rx_fifo_threshold_handler_t rxFIFOIntrHandler) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoIntEnable", ICP_STATUS_RESOURCE); + + /* Only allow to enable the interrupt if interrupt mode is set at init */ + if(ICP_FALSE == ixSspAccInterruptMode) + { + return ICP_STATUS_FAIL; + } + + /* Check if a handler is provided */ + if(NULL == rxFIFOIntrHandler) + { + return ICP_STATUS_NULL_PARAM; + } + + /* Set the Rx FIFO threshold interrupt handler function pointer to point to + the function pointer parameter and enable the Rx FIFO interrupt by writing + a one to the Rx FIFO Interrupt enable bit ofthe SSCR1 register */ + ixRxFIFOThsldHdlr = rxFIFOIntrHandler; + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_RX_FIFO_INT_ENABLE_MASK)) | + (IX_SSP_INTERRUPT_ENABLE << IX_SSP_RX_FIFO_INT_ENABLE_LOC); + + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccRxFifoIntEnable */ + +icp_status_t +icp_SspAccRxFifoIntDisable( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoIntDisable", + ICP_STATUS_RESOURCE); + + if(ICP_TRUE == ixSspAccInterruptMode) + { + /* Disable the Rx FIFO interrupt by writing zero to the Rx FIFO + Interrupt enable bit ofthe SSCR1 register and setting the Tx + FIFO threshold interrupt handler function pointer to NULL.*/ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_RX_FIFO_INT_ENABLE_MASK)) | + (IX_SSP_INTERRUPT_DISABLE << IX_SSP_RX_FIFO_INT_ENABLE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + ixRxFIFOThsldHdlr = NULL; + } /* end of ICP_TRUE == ixSspAccInterruptMode */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccRxFifoIntDisable */ + +icp_status_t +icp_SspAccTxFifoIntEnable ( + icp_sspacc_tx_fifo_threshold_handler_t txFIFOIntrHandler) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoIntEnable", ICP_STATUS_RESOURCE); + + /* Only allow to enable the interrupt if interrupt mode is set at init */ + if(ICP_FALSE == ixSspAccInterruptMode) + { + return ICP_STATUS_FAIL; + } + + /* Check if a handler is provided */ + if(NULL == txFIFOIntrHandler) + { + return ICP_STATUS_NULL_PARAM; + } + + /* Set the Tx FIFO threshold interrupt handler function pointer to point to + the function pointer parameter and enable the Tx FIFO interrupt by + writing a one to the Rx FIFO Interrupt enable bit ofthe SSCR1 + register */ + ixTxFIFOThsldHdlr = txFIFOIntrHandler; + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_TX_FIFO_INT_ENABLE_MASK)) | + (IX_SSP_INTERRUPT_ENABLE << IX_SSP_TX_FIFO_INT_ENABLE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccTxFifoIntEnable */ + +icp_status_t +icp_SspAccTxFifoIntDisable ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoIntDisable", + ICP_STATUS_RESOURCE); + + if(ICP_TRUE == ixSspAccInterruptMode) + { + /* Disable the Tx FIFO interrupt by writing zero to the Rx FIFO + Interrupt enable bit ofthe SSCR1 register and setting the Tx + FIFO threshold interrupt handler function pointer to NULL. */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_TX_FIFO_INT_ENABLE_MASK)) | + (IX_SSP_INTERRUPT_DISABLE << IX_SSP_TX_FIFO_INT_ENABLE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + ixTxFIFOThsldHdlr = NULL; + } /* end of ICP_TRUE == ixSspAccInterruptMode */ + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccTxFifoIntDisable */ + +icp_status_t +icp_SspAccLoopbackEnable ( + icp_boolean_t loopbackEnable) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccLoopbackEnable", ICP_STATUS_RESOURCE); + + /* Write the parameter into the loopback enable bit of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_LOOPBACK_ENABLE_MASK)) | + (loopbackEnable << IX_SSP_LOOPBACK_ENABLE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccLoopbackEnable */ + +icp_status_t +icp_SspAccSpiSclkPolaritySet ( + icp_sspacc_spi_sclk_polarity_t spiSclkPolaritySelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSpiSclkPolaritySet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(spiSclkPolaritySelected >= ICP_SSPACC_SPI_SCLK_POLARITY_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the SPI SCLK Polarity bit of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_SPI_SCLK_POLARITY_MASK)) | + (spiSclkPolaritySelected << IX_SSP_SPI_SCLK_POLARITY_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccSpiSclkPolaritySet */ + +icp_status_t +icp_SspAccSpiSclkPhaseSet ( + icp_sspacc_spi_sclk_phase_t spiSclkPhaseSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSpiSclkPhaseSet", ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(spiSclkPhaseSelected >= ICP_SSPACC_SPI_SCLK_PHASE_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the SPI SCLK Phase bit of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_SPI_SCLK_PHASE_MASK)) | + (spiSclkPhaseSelected << IX_SSP_SPI_SCLK_PHASE_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccSpiSclkPhaseSet */ + +icp_status_t +icp_SspAccMicrowireControlWordSet ( + icp_sspacc_microwire_ctl_word_t microwireCtlWordSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccMicrowireControlWordSet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(microwireCtlWordSelected >= + ICP_SSPACC_MICROWIRE_CTL_WORD_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Only allow change if Tx FIFO is empty */ + if(IX_SSP_FIFO_EMPTY != icp_SspAccTxFifoLevelGet()) + { + return ICP_STATUS_RESOURCE; + } + + /* Write the parameter into the Microwire Data Size bit of SSCR1 register*/ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_MICROWIRE_CTL_WORD_MASK)) | + (microwireCtlWordSelected << IX_SSP_MICROWIRE_CTL_WORD_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccMicrowireControlWordSet */ + +icp_status_t +icp_SspAccTxFifoThresholdSet ( + icp_sspacc_fifo_threshold_t txFIFOThresholdSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoThresholdSet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(txFIFOThresholdSelected >= ICP_SSPACC_FIFO_TSHLD_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the Tx FIFO threshold bits of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_TX_FIFO_THLD_MASK)) | + (txFIFOThresholdSelected << IX_SSP_TX_FIFO_THLD_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccTxFifoThresholdSet */ + +icp_status_t +icp_SspAccRxFifoThresholdSet ( + icp_sspacc_fifo_threshold_t rxFIFOThresholdSelected) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoThresholdSet", + ICP_STATUS_RESOURCE); + + /* Check for validity of parameter */ + if(rxFIFOThresholdSelected >= ICP_SSPACC_FIFO_TSHLD_TYPE_DELIMITER) + { + return ICP_STATUS_INVALID_PARAM; + } + + /* Write the parameter into the Rx FIFO threshold bits of SSCR1 register */ + ixSspAccCfgStored.sscr1 = + (ixSspAccCfgStored.sscr1 & (~IX_SSP_RX_FIFO_THLD_MASK)) | + (rxFIFOThresholdSelected << IX_SSP_RX_FIFO_THLD_LOC); + IX_SSP_WRITE_REGISTER (ixSspCR1Addr, ixSspAccCfgStored.sscr1); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccRxFifoThresholdSet */ + +/** + * Debug functions + */ + +icp_status_t +icp_SspAccStatsGet ( + icp_sspacc_stats_counters_t *sspStats) +{ + if(NULL == sspStats) + { + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, + "icp_SspAccStatsGet: stats pointer is NULL.\n", + 0,0,0,0,0,0); + return ICP_STATUS_NULL_PARAM; + } /* end of NULL == sspStats */ + /* Copy the SSP stats counters to the struct pointer passed in */ + sspStats->rcvCounter = ixSspAccStatsCounters.rcvCounter; + sspStats->xmitCounter = ixSspAccStatsCounters.xmitCounter; + sspStats->overflowCounter = ixSspAccStatsCounters.overflowCounter; + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccStatsGet */ + +void +icp_SspAccStatsReset ( + void) +{ + /* Clear the SSP stats counters to zero */ + ixSspAccStatsCounters.rcvCounter = 0; + ixSspAccStatsCounters.xmitCounter = 0; + ixSspAccStatsCounters.overflowCounter = 0; + + return; +} /* end of icp_SspAccStatsReset */ + +icp_status_t +icp_SspAccShow ( + void) +{ + icp_sspacc_stats_counters_t sspStats; + uint8_t TxFIFOLevel; + uint8_t RxFIFOLevel; + + /* Disallow this function from running further if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccShow", ICP_STATUS_RESOURCE); + + /* Read and display the SSP status */ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + + RxFIFOLevel = icp_SspAccRxFifoLevelGet(); + TxFIFOLevel = icp_SspAccTxFifoLevelGet(); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Rx FIFO Level : %d\n", RxFIFOLevel,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Tx FIFO Level : %d\n", TxFIFOLevel,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "1 = YES, 0 = NO\n",0,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Rx FIFO Overrun: %d\n", ((ixSspAccStsStored & + IX_SSP_RX_FIFO_OVERRUN_MASK) >> IX_SSP_RX_FIFO_OVERRUN_LOC),0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "SSP Busy: %d\n", ((ixSspAccStsStored & IX_SSP_BUSY_MASK) >> + IX_SSP_BUSY_LOC),0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Rx FIFO Threshold Hit or Above: %d\n", + ((ixSspAccStsStored & IX_SSP_RX_FIFO_SVC_REQ_MASK) >> + IX_SSP_RX_FIFO_SVC_REQ_LOC),0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Tx FIFO Threshold Hit or Below: %d\n", + ((ixSspAccStsStored & IX_SSP_TX_FIFO_SVC_REQ_MASK) >> + IX_SSP_TX_FIFO_SVC_REQ_LOC),0,0,0,0,0); + + /* Read and display the SSP stats counters */ + icp_SspAccStatsGet(&sspStats); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "SSP frames received : %d\n", sspStats.rcvCounter,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "SSP frames transmitted: %d\n", sspStats.xmitCounter,0,0,0,0,0); + ixOsalLog(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "SSP overflow occurence: %d\n", sspStats.overflowCounter,0,0,0,0,0); + + return ICP_STATUS_SUCCESS; +} /* end of icp_SspAccShow */ + +icp_status_t +icp_SspAccSspIdleCheck ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccSspIdleCheck", ICP_STATUS_RESOURCE); + + /* Read the SSSR to determine the state of the SSP */ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + /* Return the status of the SSP Port (busy or idle) */ + if(IX_SSP_IS_BUSY == + ((ixSspAccStsStored & IX_SSP_BUSY_MASK) >> IX_SSP_BUSY_LOC)) + { + return ICP_STATUS_FAIL; + } + else + { + return ICP_STATUS_SUCCESS; + } +} /* end of icp_SspAccSspIdleCheck */ + +uint8_t +icp_SspAccTxFifoLevelGet ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccTxFifoLevelGet", ICP_STATUS_RESOURCE); + + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + /* If the Tx FIFO level is non-zero, the value is the actual level */ + if(IX_SSP_FIFO_FULL_OR_EMPTY != + ((ixSspAccStsStored & IX_SSP_TX_FIFO_LVL_MASK) >> + IX_SSP_TX_FIFO_LVL_LOC)) + { + return ((ixSspAccStsStored & IX_SSP_TX_FIFO_LVL_MASK) >> + IX_SSP_TX_FIFO_LVL_LOC); + } + + /* If the Tx FIFO level is zero, the value can be 0 (empty) or 16 (full) + depending on the Tx FIFO Not Full bit */ + if(IX_SSP_TX_FIFO_FULL == + ((ixSspAccStsStored & IX_SSP_TX_FIFO_NOT_FULL_MASK) >> + IX_SSP_TX_FIFO_NOT_FULL_LOC)) + { + return IX_SSP_FIFO_FULL; + } + else + { + return IX_SSP_FIFO_EMPTY; + } +} /* end of icp_SspAccTxFifoLevelGet */ + +uint8_t +icp_SspAccRxFifoLevelGet ( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoLevelGet", ICP_STATUS_RESOURCE); + + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + /* If the Rx FIFO level is non-zero, the value is the actual level */ + if(IX_SSP_FIFO_FULL_OR_EMPTY != + ((((ixSspAccStsStored & IX_SSP_RX_FIFO_LVL_MASK) >> + IX_SSP_RX_FIFO_LVL_LOC) + 1) & 0xF)) + { + return (((ixSspAccStsStored & IX_SSP_RX_FIFO_LVL_MASK) >> + IX_SSP_RX_FIFO_LVL_LOC) + 1); + } + + /* If the Rx FIFO level is zero, the value can be 0 (empty) or 16 (full) + depending on the Rx FIFO Not Empty bit */ + if(IX_SSP_RX_FIFO_EMPTY == + ((ixSspAccStsStored & IX_SSP_RX_FIFO_NOT_EMPTY_MASK) >> + IX_SSP_RX_FIFO_NOT_EMPTY_LOC)) + { + return IX_SSP_FIFO_EMPTY; + } + else + { + return IX_SSP_FIFO_FULL; + } +} /* end of icp_SspAccRxFifoLevelGet */ + +icp_status_t +icp_SspAccRxFifoOverrunCheck( + void) +{ + /* Disallow this function from running if SSP not initialized */ + IX_SSP_INIT_SUCCESS_CHECK("icp_SspAccRxFifoOverrunCheck", + ICP_STATUS_RESOURCE); + + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + /* Check if an overrun has occurred*/ + if(IX_SSP_OVERRUN_HAS_OCCURRED != + ((ixSspAccStsStored & IX_SSP_RX_FIFO_OVERRUN_MASK) >> + IX_SSP_RX_FIFO_OVERRUN_LOC)) + { + return ICP_STATUS_SUCCESS; + } + + /* Update the overrun stats counter */ + ixSspAccStatsCounters.overflowCounter++; + + /* Write 1 to clear the overrun bit */ + ixSspAccStsStored = IX_SSP_SET_TO_BE_CLEARED << IX_SSP_RX_FIFO_OVERRUN_LOC; + IX_SSP_WRITE_REGISTER (ixSspSRAddr, ixSspAccStsStored); + + return ICP_STATUS_FAIL; +} /* end of icp_SspAccRxFifoOverrunCheck */ + +/** + * @ingroup IxSspAcc + * + * @fn ixSspAccInterruptDetected ( + void); + * + * @brief The top level Interrupt Service Routine that is called when an SSP + * interrupt occurs + * + * @param - None + * + * This function is the interrupt service routine that is called when a SSP + * interrupt occurs. It will determine the source of the interrupt by checking + * the SSSR and call the appropriate handler - ixRxFIFOOverrunHdlr, + * ixRxFIFOThsldHdlr, or ixTxFIFOThsldHdlr + * + * @return + * - void + * + * @li Reentrant : no + * @li ISR Callable : yes + * + */ +PRIVATE void ixSspAccInterruptDetected ( + void) +{ + ixSspAccStsStored = IX_SSP_READ_REGISTER (ixSspSRAddr); + if(IX_SSP_INTERRUPTED == ((ixSspAccStsStored & + IX_SSP_RX_FIFO_OVERRUN_MASK) >> IX_SSP_RX_FIFO_OVERRUN_LOC)) + { + /* Increment the overrun counter */ + ixSspAccStatsCounters.overflowCounter++; + + /* Call the Rx FIFO Overrun handler registered in the IxSspInitVars */ + (*ixRxFIFOOverrunHdlr)(); + + /* Clear the overrun interrupt */ + ixSspAccStsStored = IX_SSP_SET_TO_BE_CLEARED << + IX_SSP_RX_FIFO_OVERRUN_LOC; + IX_SSP_WRITE_REGISTER (ixSspSRAddr, ixSspAccStsStored); + return; + } /* end of rxFIFOOverrun interrupt detected */ + + if((IX_SSP_INTERRUPTED == + ((ixSspAccStsStored & IX_SSP_RX_FIFO_SVC_REQ_MASK) >> + IX_SSP_RX_FIFO_SVC_REQ_LOC)) && (NULL != ixRxFIFOThsldHdlr)) + { + /* Call the Rx FIFO threshold handler registered through the function + ixSspAccInit or ixSspAccRxFIFOIntEnable */ + (*ixRxFIFOThsldHdlr)(); + return; + } /* end of rxFIFO interrupt detected */ + + if((IX_SSP_INTERRUPTED == + ((ixSspAccStsStored & IX_SSP_TX_FIFO_SVC_REQ_MASK) >> + IX_SSP_TX_FIFO_SVC_REQ_LOC)) && (NULL != ixTxFIFOThsldHdlr)) + { + /* Call the Tx FIFO threshold handler registered through the function + ixSspAccInit or ixSspAccTxFIFOIntEnable */ + (*ixTxFIFOThsldHdlr)(); + return; + } /* end of TxFIFO interrupt detected */ + + return; +} /* end of ixSspAccInterruptDetected */ + diff --git a/Acceleration/library/icp_telephony/ssp_access/icp_sspacc_symbols.c b/Acceleration/library/icp_telephony/ssp_access/icp_sspacc_symbols.c new file mode 100644 index 0000000..e3dd726 --- /dev/null +++ b/Acceleration/library/icp_telephony/ssp_access/icp_sspacc_symbols.c @@ -0,0 +1,103 @@ +/** + * @file icp_sspacc_symbols.c + * + * @description Contents of this file provide the Linux kernel symbols for + * Synchronous Serial Port (SSP) Access Library + * + * @ingroup icp_SspAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ +#include <linux/module.h> +#include "icp_sspacc.h" + +EXPORT_SYMBOL(icp_SspAccInterruptSet); +EXPORT_SYMBOL(icp_SspAccPhysicalAddressSet); +EXPORT_SYMBOL(icp_SspAccInit); +EXPORT_SYMBOL(icp_SspAccUninit); +EXPORT_SYMBOL(icp_SspAccFifoDataSubmit); +EXPORT_SYMBOL(icp_SspAccFifoDataReceive); +EXPORT_SYMBOL(icp_SspAccTxFifoHitLowThresholdCheck); +EXPORT_SYMBOL(icp_SspAccRxFifoHitHighThresholdCheck); +EXPORT_SYMBOL(icp_SspAccSspPortStatusSet); +EXPORT_SYMBOL(icp_SspAccFrameFormatSelect); +EXPORT_SYMBOL(icp_SspAccDataSizeSelect); +EXPORT_SYMBOL(icp_SspAccClockSourceSelect); +EXPORT_SYMBOL(icp_SspAccSerialClockRateConfigure); +EXPORT_SYMBOL(icp_SspAccRxFifoIntEnable); +EXPORT_SYMBOL(icp_SspAccRxFifoIntDisable); +EXPORT_SYMBOL(icp_SspAccTxFifoIntEnable); +EXPORT_SYMBOL(icp_SspAccTxFifoIntDisable); +EXPORT_SYMBOL(icp_SspAccLoopbackEnable); +EXPORT_SYMBOL(icp_SspAccSpiSclkPolaritySet); +EXPORT_SYMBOL(icp_SspAccSpiSclkPhaseSet); +EXPORT_SYMBOL(icp_SspAccMicrowireControlWordSet); +EXPORT_SYMBOL(icp_SspAccTxFifoThresholdSet); +EXPORT_SYMBOL(icp_SspAccRxFifoThresholdSet); +EXPORT_SYMBOL(icp_SspAccStatsGet); +EXPORT_SYMBOL(icp_SspAccStatsReset); +EXPORT_SYMBOL(icp_SspAccShow); +EXPORT_SYMBOL(icp_SspAccSspIdleCheck); +EXPORT_SYMBOL(icp_SspAccTxFifoLevelGet); +EXPORT_SYMBOL(icp_SspAccRxFifoLevelGet); +EXPORT_SYMBOL(icp_SspAccRxFifoOverrunCheck); + diff --git a/Acceleration/library/icp_telephony/ssp_access/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/ssp_access/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..91ac681 --- /dev/null +++ b/Acceleration/library/icp_telephony/ssp_access/linux_2.6_kernel_space.mk @@ -0,0 +1,74 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DIX_HW_COHERENT_MEMORY=1 +EXTRA_LDFLAGS+=-whole-archive + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/Makefile b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/Makefile new file mode 100644 index 0000000..c0321a7 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/Makefile @@ -0,0 +1,148 @@ +######################################################################### +# This Template Makefile will create the libraries, executables and module and place them in the output folder +# Remove the comments around the sections you wish to build for. +# +#Procedure +#1) Copy this template to the location of your source files +#2) "Common variables and defintions" must be filled out +#3) Edit as desired the "Libraries and executable section" and/or the "Linux kernel 2.6 Module section" depending on what you wish to build +#4) Remove the comments around the section and delete the other unnecessary section +#5) Save changes, return to command line and type "make". +# +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears all derived objects +# +# included makefiles +# common.mk - common defintions +# depend.mk - depend and cleandepend rules +# rules.mk - build rules. +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +# Ensure The ICP_BUILDSYSTEM_PATH envorionmental var is defined. +ifndef ICP_BUILDSYSTEM_PATH +$(error ICP_BUILDSYSTEM_PATH is undefined. Please set the path to the top of the build structure \ + "-> setenv ICP_BUILDSYSTEM_PATH <path>") +endif + +#Add your project environment Makefile, extra comment +include $(ICP_ENV_DIR)/environment.mk + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=$(ICP_TDM_DL_NAME) + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES = source/IxPiuDl.c \ + source/IxPiuDlImageMgr.c \ + source/IxPiuDlPiuMgr.c \ + source/IxPiuDlPiuMgrUtils.c \ + + +# Setup include directory +INCLUDES += -I $(src)/include \ + -I $(PWD)/include \ + -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_NPEDL_DIR)/../include \ + -I $(ICP_NPEFW_DIR)/src \ + -I $(ICP_OSAL_DIR)/common/include \ + -I $(ICP_OSAL_DIR)/common/ossl_shim/linux_kernel/include \ + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES += -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM -DENABLE_BUFFERMGT + +ifndef IX_INCLUDE_MICROCODE +SOURCES += source/IxPiuDlFwLoader.c +EXTRA_CFLAGS += -DIX_PIUDL_READ_MICROCODE_FROM_FILE +endif + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_TDM_DL_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + +# Install the module to the output dir +install: module + + +###################Include rules and dependency makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules and dependency inclusion######################### + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlFwLoader_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlFwLoader_p.h new file mode 100644 index 0000000..5ca9e9e --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlFwLoader_p.h @@ -0,0 +1,131 @@ +/** + * @file IxPiuDlFwLoader_p.h + * + * @date 25 June 2007 + + * @brief This file contains the API for reading PIU firmware from file using + * the 'request_firmware' loading mechanism available in Linux kernel v2.6 + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/** + * @defgroup IxPiuDlFwLoader_p IxPiuDlFwLoader_p + * + * @brief header file for loading firmware from file + * + * @{ + */ + +#ifndef IXPIUDLFWLOADER_P_H +#define IXPIUDLFWLOADER_P_H + +/* + * Put the user defined include files required + */ +#include "IxPiuDl.h" + +/* + * Prototypes for interface functions + */ + +/** + * @fn ix_error ixPiuDlFwLoaderGetFw (ix_uint32** firmwareArray) + * + * @brief This function loads an PIU firmware image from a file + * + * @param ix_uint32[out] firmwareArray - pointer to pointer to hold loaded + * firmware image + + * This function uses the firmware loading mechanism available in Linux kernel + * v2.6 to read a firmware file into kernel space memory + * + * @return + * - IX_SUCCESS if the file was loaded successfully + * - IX_FAIL if the firmware load failed + */ +ix_error +ixPiuDlFwLoaderGetFw(ix_uint32** firmwareArray); + +/** + * @fn ix_error ixPiuDlFwLoaderCleanup (void) + * + * @brief This function performs cleanup following loading an PIU firmware + * image from a file + * + * This function performs cleanup after loading PIU firmware which has used the + * loading mechanism available in Linux kernel v2.6 to read a firmware file + * into kernel space memory + * + * @return + * - nothing + */ +void +ixPiuDlFwLoaderCleanup(void); + +#endif /* IXPIUDLFWLOADER_P_H */ + +/** + * @} defgroup IxPiuDlFwLoader_p + */ + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlImageMgr_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlImageMgr_p.h new file mode 100644 index 0000000..361b893 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlImageMgr_p.h @@ -0,0 +1,339 @@ +/** + * @file IxPiuDlImageMgr_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + + * @brief This file contains the private API for the ImageMgr module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuDlImageMgr_p IxPiuDlImageMgr_p + * + * @brief The private API for the IxPiuDl ImageMgr module + * + * @{ + */ + +#ifndef IXPIUDLIMAGEMGR_P_H +#define IXPIUDLIMAGEMGR_P_H + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" + + +/* + * #defines and macros + */ + +/** + * @def IX_PIUDL_IMAGEMGR_SIGNATURE + * + * @brief Signature found as 1st word in a microcode image library + */ +#define IX_PIUDL_IMAGEMGR_SIGNATURE 0xFEEDF00D + +/** + * @def IX_PIUDL_IMAGEMGR_END_OF_HEADER + * + * @brief Marks end of header in a microcode image library + */ +#define IX_PIUDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF + +/** + * @def IX_PIUDL_IMAGEID_PIUID_OFFSET + * + * @brief Offset from LSB of PIU ID field in Image ID + */ +#define IX_PIUDL_IMAGEID_PIUID_OFFSET 25 + +/** + * @def IX_PIUDL_IMAGEID_PIUCODE_OFFSET + * + * @brief Offset from LSB of PIU CODE (PIU ID+ Chip architecture) field in Image ID + */ +#define IX_PIUDL_IMAGEID_PIUCODE_OFFSET 24 + +/** + * @def IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET + * + * @brief Offset from LSB of Functionality ID field in Image ID + */ +#define IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET 16 + +/** + * @def IX_PIUDL_IMAGEID_MAJOR_OFFSET + * + * @brief Offset from LSB of Major revision field in Image ID + */ +#define IX_PIUDL_IMAGEID_MAJOR_OFFSET 8 + +/** + * @def IX_PIUDL_IMAGEID_MINOR_OFFSET + * + * @brief Offset from LSB of Minor revision field in Image ID + */ +#define IX_PIUDL_IMAGEID_MINOR_OFFSET 0 + + +/** + * @def IX_PIUDL_PIUIMAGE_FIELD_MASK + * + * @brief Mask for PIU Image ID's Field + * + */ +#define IX_PIUDL_PIUIMAGE_FIELD_MASK 0xff + +/** + * @def IX_PIUDL_PIUIMAGE_PIUID_MASK + * + * @brief Mask for PIU Image ID's PIU ID Field + * + */ +#define IX_PIUDL_PIUIMAGE_PIUID_MASK 0x07 + +/** + * @def IX_PIUDL_PIUID_FROM_IMAGEID_GET + * + * @brief Macro to extract PIU ID field from Image ID + */ +#define IX_PIUDL_PIUID_FROM_IMAGEID_GET(imageId) \ + (((imageId) >> IX_PIUDL_IMAGEID_PIUID_OFFSET) & \ + IX_PIUDL_PIUIMAGE_PIUID_MASK) + +/** + * @def IX_PIUDL_FUNCTIONID_FROM_IMAGEID_GET + * + * @brief Macro to extract Functionality ID field from Image ID + */ +#define IX_PIUDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \ + (((imageId) >> IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET) & \ + IX_PIUDL_PIUIMAGE_FIELD_MASK) + +/** + * @def IX_PIUDL_MAJOR_FROM_IMAGEID_GET + * + * @brief Macro to extract Major revision field from Image ID + */ +#define IX_PIUDL_MAJOR_FROM_IMAGEID_GET(imageId) \ + (((imageId) >> IX_PIUDL_IMAGEID_MAJOR_OFFSET) & \ + IX_PIUDL_PIUIMAGE_FIELD_MASK) + +/** + * @def IX_PIUDL_MINOR_FROM_IMAGEID_GET + * + * @brief Macro to extract Minor revision field from Image ID + */ +#define IX_PIUDL_MINOR_FROM_IMAGEID_GET(imageId) \ + (((imageId) >> IX_PIUDL_IMAGEID_MINOR_OFFSET) & \ + IX_PIUDL_PIUIMAGE_FIELD_MASK) + +/** + * @def IX_PIUDL_IMAGEID_FROM_STRUCT_GET + * + * @brief Macro to combine Image Id fields into a uint32 + */ +#define IX_PIUDL_IMAGEID_FROM_STRUCT_GET(imageId) \ + (((imageId).piuId << IX_PIUDL_IMAGEID_PIUID_OFFSET) | \ + ((imageId).functionalityId << IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET) | \ + ((imageId).major << IX_PIUDL_IMAGEID_MAJOR_OFFSET) | \ + ((imageId).minor << IX_PIUDL_IMAGEID_MINOR_OFFSET)) + + +/* + * Prototypes for interface functions + */ + + + + +/** + * @fn void ixPiuDlImageMgrStatsShow (void) + * + * @brief This function will display the statistics of the IxPiuDl ImageMgr + * module + * + * @return none + */ +void +ixPiuDlImageMgrStatsShow (void); + + +/** + * @fn void ixPiuDlImageMgrStatsReset (void) + * + * @brief This function will reset the statistics of the IxPiuDl ImageMgr + * module + * + * @return none + */ +void +ixPiuDlImageMgrStatsReset (void); + + +/** + * @fn ix_error ixPiuDlImageMgrImageFind (ix_uint32 *imageLibrary, + ix_uint32 imageId, + ix_uint32 **imagePtr, + ix_uint32 *imageSize) + * + * @brief Finds a image block in the PIU microcode image library. + * + * @param ix_uint32* [in] imageLibrary - the image library to use + * @param ix_uint32 [in] imageId - the id of the image to locate + * @param ix_uint32** [out] imagePtr - pointer to the image in memory + * @param ix_uint32* [out] imageSize - size (in 32-bit words) of image + * + * This function examines the header of the specified microcode image library + * for the location and size of the specified image. It returns a pointer to + * the image in the <i>imagePtr</i> parameter. + * If no image library is specified (imageLibrary == NULL), then the default + * built-in image library will be used. + * + * @pre + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlImageMgrImageFind (ix_uint32 *imageLibrary, + ix_uint32 imageId, + ix_uint32 **imagePtr, + ix_uint32 *imageSize); + + + +/** + * @fn ix_error ixPiuDlImageMgrImageListExtract (IxPiuDlImageId *imageListPtr, + ix_uint32 *numImages) + * + * @brief Extracts a list of images available in the PIU microcode image library. + * + * @param IxPiuDlImageId* [out] imageListPtr - pointer to array to contain + * a list of images. If NULL, + * only the number of images + * is returned (in + * <i>numImages</i>) + * @param ix_uint32* [inout] numImages - As input, it points to a variable + * containing the number of images which + * can be stored in the + * <i>imageListPtr</i> array. Its value + * is ignored as input if + * <i>imageListPtr</i> is NULL. As an + * output, it will contain number of + * images in the image library. + * + * This function reads the header of the microcode image library and extracts a list of the + * images available in the image library. It can also be used to find the number of + * images in the image library. + * + * + * @pre + * - if <i>imageListPtr</i> != NULL, <i>numImages</i> should reflect the + * number of image Id elements the <i>imageListPtr</i> can contain. + * + * @post + * - <i>numImages</i> will reflect the number of image Id's found in the + * microcode image library. + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlImageMgrImageListExtract (IxPiuDlImageId *imageListPtr, + ix_uint32 *numImages); + + + +/** + * @fn void ixPiuDlImageMgrImageIdFormat (ix_uint32 rawImageId, + IxPiuDlImageId *imageId) + * + * @brief Converts a raw image Id (uint32) to the PIU Dl structure. + * + * @param ix_uint32 [in] rawImageId - the raw image Id to be converted + * @param IxPiuDlImageId [out] *imageId - placeholder for the converted Id. + * + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ + +void +ixPiuDlImageMgrImageIdFormat ( + ix_uint32 rawImageId, + IxPiuDlImageId *imageId); +#endif /* IXPIUDLIMAGEMGR_P_H */ + +/** + * @} defgroup IxPiuDlImageMgr_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlMacros_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlMacros_p.h new file mode 100644 index 0000000..252ba7c --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlMacros_p.h @@ -0,0 +1,287 @@ +/** + * @file IxPiuDlMacros_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @brief This file contains the macros for the IxPiuDl component. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuDlMacros_p IxPiuDlMacros_p + * + * @brief Macros for the IxPiuDl component. + * + * @{ + */ + +#ifndef IXPIUDLMACROS_P_H +#define IXPIUDLMACROS_P_H + + +/* + * Put the user defined include files required. + */ + + +#include "IxOsal.h" +#ifdef __KERNEL__ +#define printf printk +#endif + + + +/* + * Typedefs + */ + +/** + * @typedef IxPiuDlTraceTypes + * @brief Enumeration defining IxPiuDl trace levels + */ +typedef enum +{ + IX_PIUDL_TRACE_OFF, /**< no trace */ + IX_PIUDL_DEBUG, /**< debug */ + IX_PIUDL_FN_ENTRY_EXIT /**< function entry/exit */ +} IxPiuDlTraceTypes; + + +/* + * #defines and macros. + */ + +/* Implementation of the following macros for use with IxPiuDl unit test code */ + +/* Implementation of the following macros when integrated with IxOsal */ + +/** + * @def IX_PIUDL_TRACE_LEVEL + * + * @brief IxPiuDl debug trace level + */ +#define IX_PIUDL_TRACE_LEVEL IX_PIUDL_TRACE_OFF + +/** + * @def IX_PIUDL_ERROR_REPORT + * + * @brief Mechanism for reporting IxPiuDl software errors + * + * @param char* [in] STR - Error string to report + * + * This macro is used to report IxPiuDl software errors. + * + * @return none + */ +#define IX_PIUDL_ERROR_REPORT(STR) \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, STR, \ + 0, 0, 0, 0, 0, 0); + +/** + * @def IX_PIUDL_WARNING_REPORT + * + * @brief Mechanism for reporting IxPiuDl software warnings + * + * @param char* [in] STR - Warning string to report + * + * This macro is used to report IxPiuDl software warnings. + * + * @return none + */ +#define IX_PIUDL_WARNING_REPORT(STR) \ + ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, STR, \ + 0, 0, 0, 0, 0, 0); + + +/** + * @def IX_PIUDL_TRACE0 + * + * @brief Mechanism for tracing debug for the IxPiuDl component, for no arguments + * + * @param unsigned [in] LEVEL - one of IxPiuDlTraceTypes enumerated values + * @param char* [in] STR - Trace string + * + * This macro simply prints the trace string passed, if the level is supported. + * + * @return none + */ +#define IX_PIUDL_TRACE0(LEVEL, STR) \ +do { \ + if (LEVEL <= IX_PIUDL_TRACE_LEVEL) \ + { \ + if (LEVEL == IX_PIUDL_FN_ENTRY_EXIT) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, \ + 0, 0, 0, 0, 0, 0); \ + } \ + else if (LEVEL == IX_PIUDL_DEBUG) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, \ + 0, 0, 0, 0, 0, 0); \ + } \ + } \ +} while(0) + +/** + * @def IX_PIUDL_TRACE1 + * + * @brief Mechanism for tracing debug for the IxPiuDl component, with 1 argument + * + * @param unsigned [in] LEVEL - one of IxPiuDlTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * + * This macro simply prints the trace string passed, if the level is supported. + * + * @return none + */ +#define IX_PIUDL_TRACE1(LEVEL, STR, ARG1) \ +do { \ + if (LEVEL <= IX_PIUDL_TRACE_LEVEL) \ + { \ + if (LEVEL == IX_PIUDL_FN_ENTRY_EXIT) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, \ + ARG1, 0, 0, 0, 0, 0); \ + } \ + else if (LEVEL == IX_PIUDL_DEBUG) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, \ + ARG1, 0, 0, 0, 0, 0); \ + } \ + } \ +} while(0) + +/** + * @def IX_PIUDL_TRACE2 + * + * @brief Mechanism for tracing debug for the IxPiuDl component, with 2 arguments + * + * @param unsigned [in] LEVEL - one of IxPiuDlTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * @param argType [in] ARG2 - Argument to trace + * + * This macro simply prints the trace string passed, if the level is supported. + * + * @return none + */ +#define IX_PIUDL_TRACE2(LEVEL, STR, ARG1, ARG2) \ +do { \ + if (LEVEL <= IX_PIUDL_TRACE_LEVEL) \ + { \ + if (LEVEL == IX_PIUDL_FN_ENTRY_EXIT) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, IX_OSAL_LOG_DEV_STDOUT, STR, \ + ARG1, ARG2, 0, 0, 0, 0); \ + } \ + else if (LEVEL == IX_PIUDL_DEBUG) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, \ + ARG1, ARG2, 0, 0, 0, 0); \ + } \ + } \ +} while(0) + +/** + * @def IX_PIUDL_REG_WRITE + * + * @brief Mechanism for writing to a memory-mapped register + * + * @param ix_uint32 [in] base - Base memory address for this PIU's registers + * @param ix_uint32 [in] offset - Offset from base memory address + * @param ix_uint32 [in] value - Value to write to register + * + * This macro forms the address of the register from base address + offset, and + * dereferences that address to write the contents of the register. + * + * @return none + */ +#define IX_PIUDL_REG_WRITE(base, offset, value) \ + (*((volatile ix_uint32*)((base) + (offset))) = value) + + +/** + * @def IX_PIUDL_REG_READ + * + * @brief Mechanism for reading from a memory-mapped register + * + * @param ix_uint32 [in] base - Base memory address for this PIU's registers + * @param ix_uint32 [in] offset - Offset from base memory address + * @param ix_uint32 *[out] value - Value read from register + * + * This macro forms the address of the register from base address + offset, and + * dereferences that address to read the register contents. + * + * @return none + */ +#define IX_PIUDL_REG_READ(base, offset, valuePtr) \ + (*(valuePtr) = *((volatile ix_uint32*)((base) + (offset)))) + + +#endif /* IXPIUDLMACROS_P_H */ + +/** + * @} defgroup IxPiuDlMacros_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrEcRegisters_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrEcRegisters_p.h new file mode 100644 index 0000000..3a8351b --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrEcRegisters_p.h @@ -0,0 +1,982 @@ +/** + * @file IxPiuDlPiuMgrEcRegisters_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +#ifndef IXPIUDLPIUMGRECREGISTERS_P_H +#define IXPIUDLPIUMGRECREGISTERS_P_H + +/* + * Put the system defined include files required. + */ + +#if defined(__linux) +#if !defined(__ep805xx) +#include <asm/hardware.h> +#endif +#endif + +/* + * Put the user defined include files required. + */ + + +/* + * Instruction Memory Size (in words) for each PIU + */ + +#define IX_PIUDL_PIUBASEADDRESS_PIU0_MAP(phys)\ +IX_OSAL_MEM_MAP((phys),0) + +#define IX_PIUDL_PIUBASEADDRESS_PIU1_MAP(phys)\ +IX_OSAL_MEM_MAP((phys),0) + +#define IX_PIUDL_PIUBASEADDRESS_UNMAP(virt)\ +IX_OSAL_MEM_UNMAP((virt)) + + + + + +/** + * @def IX_PIUDL_INS_MEMSIZE_WORDS_PIU0 + * @brief Size (in words) of PIU-0 Instruction Memory + */ +#if defined(__ep805xx) +#define IX_PIUDL_INS_MEMSIZE_WORDS_PIU0 (8192) +#else +#define IX_PIUDL_INS_MEMSIZE_WORDS_PIU0 (4096) +#endif + +/** + * @def IX_PIUDL_INS_MEMSIZE_WORDS_PIU1 + * @brief Size (in words) of PIU-1 Instruction Memory + */ +#define IX_PIUDL_INS_MEMSIZE_WORDS_PIU1 (4096) + + +/* + * Data Memory Size (in words) for each PIU + */ + +/** + * @def IX_PIUDL_DATA_MEMSIZE_WORDS_PIU0 + * @brief Size (in words) of PIU-0 Data Memory + */ +#define IX_PIUDL_DATA_MEMSIZE_WORDS_PIU0 (8192) + +/** + * @def IX_PIUDL_DATA_MEMSIZE_WORDS_PIU1 + * @brief Size (in words) of PIU-1 Data Memory + */ +#define IX_PIUDL_DATA_MEMSIZE_WORDS_PIU1 (4096) + + +/* + * Configuration Bus Register offsets (in bytes) from PIU Base Address + */ + +/** + * @def IX_PIUDL_REG_OFFSET_EXAD + * @brief Offset (in bytes) of EXAD (Execution Address) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXAD (0x00000000) + +/** + * @def IX_PIUDL_REG_OFFSET_EXDATA + * @brief Offset (in bytes) of EXDATA (Execution Data) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXDATA (0x00000004) + +/** + * @def IX_PIUDL_REG_OFFSET_EXCTL + * @brief Offset (in bytes) of EXCTL (Execution Control) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXCTL (0x00000008) + +/** + * @def IX_PIUDL_REG_OFFSET_EXCT + * @brief Offset (in bytes) of EXCT (Execution Count) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXCT (0x0000000C) + +/** + * @def IX_PIUDL_REG_OFFSET_AP0 + * @brief Offset (in bytes) of AP0 (Action Point 0) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP0 (0x00000010) + +/** + * @def IX_PIUDL_REG_OFFSET_AP1 + * @brief Offset (in bytes) of AP1 (Action Point 1) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP1 (0x00000014) + +/** + * @def IX_PIUDL_REG_OFFSET_AP2 + * @brief Offset (in bytes) of AP2 (Action Point 2) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP2 (0x00000018) + +/** + * @def IX_PIUDL_REG_OFFSET_AP3 + * @brief Offset (in bytes) of AP3 (Action Point 3) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP3 (0x0000001C) + +/** + * @def IX_PIUDL_REG_OFFSET_WFIFO + * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_WFIFO (0x00000020) + +/** + * @def IX_PIUDL_REG_OFFSET_WC + * @brief Offset (in bytes) of WC (Watch Count) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_WC (0x00000024) + +/** + * @def IX_PIUDL_REG_OFFSET_PROFCT + * @brief Offset (in bytes) of PROFCT (Profile Count) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_PROFCT (0x00000028) + +/** + * @def IX_PIUDL_REG_OFFSET_STAT + * @brief Offset (in bytes) of STAT (Messaging Status) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_STAT (0x0000002C) + +/** + * @def IX_PIUDL_REG_OFFSET_CTL + * @brief Offset (in bytes) of CTL (Messaging Control) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_CTL (0x00000030) + +/** + * @def IX_PIUDL_REG_OFFSET_MBST + * @brief Offset (in bytes) of MBST (Mailbox Status) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_MBST (0x00000034) + +/** + * @def IX_PIUDL_REG_OFFSET_FIFO + * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from PIU + * Base Address + */ +#define IX_PIUDL_REG_OFFSET_FIFO (0x00000038) + + +/* + * Non-zero reset values for the Configuration Bus registers + */ + +/** + * @def IX_PIUDL_REG_RESET_FIFO + * @brief Reset value for Mailbox (MBST) register + * NOTE that if used, it should be complemented with an PIU intruction + * to clear the Mailbox at the PIU side as well + */ +#define IX_PIUDL_REG_RESET_MBST (0x0000F0F0) + + +/* + * Bit-masks used to read/write particular bits in Configuration Bus registers + */ + +/** + * @def IX_PIUDL_MASK_WFIFO_VALID + * @brief Masks the VALID bit in the WFIFO register + */ +#define IX_PIUDL_MASK_WFIFO_VALID (0x80000000) + +/** + * @def IX_PIUDL_MASK_STAT_OFNE + * @brief Masks the OFNE bit in the STAT register + */ +#define IX_PIUDL_MASK_STAT_OFNE (0x00010000) + +/** + * @def IX_PIUDL_MASK_STAT_IFNE + * @brief Masks the IFNE bit in the STAT register + */ +#define IX_PIUDL_MASK_STAT_IFNE (0x00080000) + + +/* + * EXCTL (Execution Control) Register commands +*/ + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_STEP + * @brief EXCTL Command to Step execution of an PIU Instruction + */ + +#define IX_PIUDL_EXCTL_CMD_PIU_STEP (0x01) + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_START + * @brief EXCTL Command to Start PIU execution + */ +#define IX_PIUDL_EXCTL_CMD_PIU_START (0x02) + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_STOP + * @brief EXCTL Command to Stop PIU execution + */ +#define IX_PIUDL_EXCTL_CMD_PIU_STOP (0x03) + +/** + * @def IX_PIUDL_EXCTL_CMD_CLR_TRIGGER + * @brief EXCTL Command to clear TRIGGER interrupt event source + */ +#define IX_PIUDL_EXCTL_CMD_CLR_TRIGGER (0x0d) + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE + * @brief EXCTL Command to Clear PIU instruction pipeline + */ +#define IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE (0x04) + +/** + * @def IX_PIUDL_EXCTL_CMD_RD_INS_MEM + * @brief EXCTL Command to read PIU instruction memory at address in EXAD + * register and return value in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_RD_INS_MEM (0x10) + +/** + * @def IX_PIUDL_EXCTL_CMD_WR_INS_MEM + * @brief EXCTL Command to write PIU instruction memory at address in EXAD + * register with data in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_WR_INS_MEM (0x11) + +/** + * @def IX_PIUDL_EXCTL_CMD_RD_DATA_MEM + * @brief EXCTL Command to read PIU data memory at address in EXAD + * register and return value in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_RD_DATA_MEM (0x12) + +/** + * @def IX_PIUDL_EXCTL_CMD_WR_DATA_MEM + * @brief EXCTL Command to write PIU data memory at address in EXAD + * register with data in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_WR_DATA_MEM (0x13) + +/** + * @def IX_PIUDL_EXCTL_CMD_RD_ECS_REG + * @brief EXCTL Command to read Execution Access register at address in EXAD + * register and return value in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_RD_ECS_REG (0x14) + +/** + * @def IX_PIUDL_EXCTL_CMD_WR_ECS_REG + * @brief EXCTL Command to write Execution Access register at address in EXAD + * register with data in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_WR_ECS_REG (0x15) + +/** + * @def IX_PIUDL_EXCTL_CMD_CLR_PROFILE_CNT + * @brief EXCTL Command to clear Profile Count register + */ +#define IX_PIUDL_EXCTL_CMD_CLR_PROFILE_CNT (0x0C) + + +/* + * EXCTL (Execution Control) Register status bit masks + */ + +/** + * @def IX_PIUDL_EXCTL_STATUS_RUN + * @brief Masks the RUN status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_RUN (0x80000000) + +/** + * @def IX_PIUDL_EXCTL_STATUS_STOP + * @brief Masks the STOP status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_STOP (0x40000000) + +/** + * @def IX_PIUDL_EXCTL_STATUS_CLEAR + * @brief Masks the CLEAR status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_CLEAR (0x20000000) + +/** + * @def IX_PIUDL_EXCTL_STATUS_ECS_K + * @brief Masks the K (pipeline Klean) status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_ECS_K (0x00800000) + + +/* + * Executing Context Stack (ECS) level registers + */ + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Backgound + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_0 (0x00) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Backgound + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_1 (0x01) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Backgound + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_2 (0x02) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Priority 1 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_0 (0x04) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Priority 1 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_1 (0x05) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Priority 1 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_2 (0x06) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Priority 2 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_0 (0x08) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Priority 2 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_1 (0x09) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Priority 2 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_2 (0x0A) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Debug + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_0 (0x0C) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Debug + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_1 (0x0D) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Debug + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_2 (0x0E) + +/** + * @def IX_PIUDL_ECS_INSTRUCT_REG + * @brief Execution Access register address for PIU Instruction Register + */ +#define IX_PIUDL_ECS_INSTRUCT_REG (0x11) + + +/* + * Execution Access register reset values + */ + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Background ECS level register 0 + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_0_RESET (0xA0000000) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Background ECS level register 1 + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_1_RESET (0x01000000) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Background ECS level register 2 + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_2_RESET (0x00008000) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Priority 1 ECS level register 0 + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_0_RESET (0x20000080) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Priority 1 ECS level register 1 + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_1_RESET (0x01000000) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Priority 1 ECS level register 2 + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_2_RESET (0x00008000) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Priority 2 ECS level register 0 + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_0_RESET (0x20000080) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Priority 2 ECS level register 1 + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_1_RESET (0x01000000) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Priority 2 ECS level register 2 + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_2_RESET (0x00008000) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Debug ECS level register 0 + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_0_RESET (0x20000000) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Debug ECS level register 1 + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_1_RESET (0x00000000) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Debug ECS level register 2 + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_2_RESET (0x001E0000) + +/** + * @def IX_PIUDL_ECS_INSTRUCT_REG_RESET + * @brief Reset value for Execution Access PIU Instruction Register + */ +#define IX_PIUDL_ECS_INSTRUCT_REG_RESET (0x1003C00F) + + +/* + * masks used to read/write particular bits in Execution Access registers + */ + +/** + * @def IX_PIUDL_MASK_ECS_REG_0_ACTIVE + * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS + * levels + */ +#define IX_PIUDL_MASK_ECS_REG_0_ACTIVE (0x80000000) + +/** + * @def IX_PIUDL_MASK_ECS_REG_0_NEXTPC + * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS + * levels (except Debug ECS level) + */ +#define IX_PIUDL_MASK_ECS_REG_0_NEXTPC (0x1FFF0000) + +/** + * @def IX_PIUDL_MASK_ECS_REG_0_LDUR + * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels + */ +#define IX_PIUDL_MASK_ECS_REG_0_LDUR (0x00000700) + +/** + * @def IX_PIUDL_MASK_ECS_REG_1_CCTXT + * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels + */ +#define IX_PIUDL_MASK_ECS_REG_1_CCTXT (0x000F0000) + +/** + * @def IX_PIUDL_MASK_ECS_REG_1_SELCTXT + * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels + */ +#define IX_PIUDL_MASK_ECS_REG_1_SELCTXT (0x0000000F) + +/** + * @def IX_PIUDL_MASK_ECS_DBG_REG_2_IF + * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level + */ +#define IX_PIUDL_MASK_ECS_DBG_REG_2_IF (0x00100000) + +/** + * @def IX_PIUDL_MASK_ECS_DBG_REG_2_IE + * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level + */ +#define IX_PIUDL_MASK_ECS_DBG_REG_2_IE (0x00080000) + + +/* + * Bit-Offsets from LSB of particular bit-fields in Execution Access registers + */ + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_0_NEXTPC + * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS + * levels (except Debug ECS level) + */ +#define IX_PIUDL_OFFSET_ECS_REG_0_NEXTPC (16) + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_0_LDUR + * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS + * levels + */ +#define IX_PIUDL_OFFSET_ECS_REG_0_LDUR (8) + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_1_CCTXT + * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS + * levels + */ +#define IX_PIUDL_OFFSET_ECS_REG_1_CCTXT (16) + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_1_SELCTXT + * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS + * levels + */ +#define IX_PIUDL_OFFSET_ECS_REG_1_SELCTXT (0) + + +/* + * PIU core & co-processor instruction templates to load into PIU Instruction + * Register, for read/write of PIU register file registers + */ + +/** + * @def IX_PIUDL_INSTR_RD_REG_BYTE + * @brief PIU Instruction, used to read an 8-bit PIU internal logical register + * and return the value in the EXDATA register (aligned to MSB). + * PIU Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" + */ +#define IX_PIUDL_INSTR_RD_REG_BYTE (0x0FC00000) + +/** + * @def IX_PIUDL_INSTR_RD_REG_SHORT + * @brief PIU Instruction, used to read a 16-bit PIU internal logical register + * and return the value in the EXDATA register (aligned to MSB). + * PIU Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec" + */ +#define IX_PIUDL_INSTR_RD_REG_SHORT (0x0FC08010) + +/** + * @def IX_PIUDL_INSTR_RD_REG_WORD + * @brief PIU Instruction, used to read a 16-bit PIU internal logical register + * and return the value in the EXDATA register. + * PIU Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec" + */ +#define IX_PIUDL_INSTR_RD_REG_WORD (0x0FC08210) + +/** + * @def IX_PIUDL_INSTR_WR_REG_BYTE + * @brief PIU Immediate-Mode Instruction, used to write an 8-bit PIU internal + * logical register. + * PIU Assembler instruction: "mov8 d0, #0" + */ +#define IX_PIUDL_INSTR_WR_REG_BYTE (0x00004000) + +/** + * @def IX_PIUDL_INSTR_WR_REG_SHORT + * @brief PIU Immediate-Mode Instruction, used to write a 16-bit PIU internal + * logical register. + * PIU Assembler instruction: "mov16 d0, #0" + */ +#define IX_PIUDL_INSTR_WR_REG_SHORT (0x0000C000) + +/** + * @def IX_PIUDL_INSTR_RD_FIFO + * @brief PIU Immediate-Mode Instruction, used to write a 16-bit PIU internal + * logical register. + * PIU Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" + */ +#define IX_PIUDL_INSTR_RD_FIFO (0x0F888220) + +/** + * @def IX_PIUDL_INSTR_RESET_MBOX + * @brief PIU Instruction, used to reset Mailbox (MBST) register + * PIU Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" + */ +#define IX_PIUDL_INSTR_RESET_MBOX (0x0FAC8210) + + +/** + * @def IX_PIUDL_INSTR_RESET_COPROCS + * @brief PIU Instruction, used to reset co-processors. Register d0 must + * contain the value (0xFFFF to reset all co-processors. + * PIU Assembler instruction: "mov16 d0, d0 &&&DBG_WrRst" + */ +#define IX_PIUDL_INSTR_RESET_COPROCS (0xAFB88010) + + +/* + * Bit-offsets from LSB, of particular bit-fields in an PIU instruction + */ + +/** + * @def IX_PIUDL_OFFSET_INSTR_SRC + * @brief LSB-offset to SRC (source operand) field of an PIU Instruction + */ +#define IX_PIUDL_OFFSET_INSTR_SRC (4) + +/** + * @def IX_PIUDL_OFFSET_INSTR_DEST + * @brief LSB-offset to DEST (destination operand) field of an PIU Instruction + */ +#define IX_PIUDL_OFFSET_INSTR_DEST (9) + +/** + * @def IX_PIUDL_OFFSET_INSTR_COPROC + * @brief LSB-offset to COPROC (coprocessor instruction) field of an PIU + * Instruction + */ +#define IX_PIUDL_OFFSET_INSTR_COPROC (18) + + +/* + * masks used to read/write particular bits of an PIU Instruction + */ + +/** + * @def IX_PIUDL_MASK_IMMED_INSTR_SRC_DATA + * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in + * SRC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_MASK_IMMED_INSTR_SRC_DATA (0x1F) + +/** + * @def IX_PIUDL_MASK_IMMED_INSTR_COPROC_DATA + * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in + * COPROC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_MASK_IMMED_INSTR_COPROC_DATA (0xFFE0) + +/** + * @def IX_PIUDL_OFFSET_IMMED_INSTR_COPROC_DATA + * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits) + * to be used in COPROC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_OFFSET_IMMED_INSTR_COPROC_DATA (5) + +/** + * @def IX_PIUDL_DISPLACE_IMMED_INSTR_COPROC_DATA + * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit + * data value into COPROC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_DISPLACE_IMMED_INSTR_COPROC_DATA \ + (IX_PIUDL_OFFSET_INSTR_COPROC - IX_PIUDL_OFFSET_IMMED_INSTR_COPROC_DATA) + +/** + * @def IX_PIUDL_WR_INSTR_LDUR + * @brief LDUR value used with immediate-mode PIU Instructions by the PiuDl + * for writing to PIU internal logical registers + */ +#define IX_PIUDL_WR_INSTR_LDUR (1) + +/** + * @def IX_PIUDL_RD_INSTR_LDUR + * @brief LDUR value used with NON-immediate-mode PIU Instructions by the PiuDl + * for reading from PIU internal logical registers + */ +#define IX_PIUDL_RD_INSTR_LDUR (0) + + +/** + * @enum IxPiuDlCtxtRegNum + * @brief Numeric values to identify the PIU internal Context Store registers + */ +typedef enum +{ + IX_PIUDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */ + IX_PIUDL_CTXT_REG_STARTPC, /**< identifies STARTPC */ + IX_PIUDL_CTXT_REG_REGMAP, /**< identifies REGMAP */ + IX_PIUDL_CTXT_REG_CINDEX, /**< identifies CINDEX */ + IX_PIUDL_CTXT_REG_MAX /**< Total number of Context Store registers */ +} IxPiuDlCtxtRegNum; + + +/* + * PIU Context Store register logical addresses + */ + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_STEVT + * @brief Logical address of STEVT PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_STEVT (0x0000001B) + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_STARTPC + * @brief Logical address of STARTPC PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_STARTPC (0x0000001C) + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_REGMAP + * @brief Logical address of REGMAP PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_REGMAP (0x0000001E) + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_CINDEX + * @brief Logical address of CINDEX PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_CINDEX (0x0000001F) + + +/* + * PIU Context Store register reset values + */ + +/** + * @def IX_PIUDL_CTXT_REG_RESET_STEVT + * @brief Reset value of STEVT PIU internal Context Store register + * (STEVT = off, 0x80) + */ +#define IX_PIUDL_CTXT_REG_RESET_STEVT (0x80) + +/** + * @def IX_PIUDL_CTXT_REG_RESET_STARTPC + * @brief Reset value of STARTPC PIU internal Context Store register + * (STARTPC = 0x0000) + */ +#define IX_PIUDL_CTXT_REG_RESET_STARTPC (0x0000) + +/** + * @def IX_PIUDL_CTXT_REG_RESET_REGMAP + * @brief Reset value of REGMAP PIU internal Context Store register + * (REGMAP = d0->p0, d8->p2, d16->p4) + */ +#define IX_PIUDL_CTXT_REG_RESET_REGMAP (0x0820) + +/** + * @def IX_PIUDL_CTXT_REG_RESET_CINDEX + * @brief Reset value of CINDEX PIU internal Context Store register + * (CINDEX = 0) + */ +#define IX_PIUDL_CTXT_REG_RESET_CINDEX (0x00) + + +/* + * numeric range of context levels available on an PIU + */ + +/** + * @def IX_PIUDL_CTXT_NUM_MIN + * @brief Lowest PIU Context number in range + */ +#define IX_PIUDL_CTXT_NUM_MIN (0) + +/** + * @def IX_PIUDL_CTXT_NUM_MAX + * @brief Highest PIU Context number in range + */ +#define IX_PIUDL_CTXT_NUM_MAX (15) + + +/* + * Physical PIU internal registers + */ + +/** + * @def IX_PIUDL_TOTAL_NUM_PHYS_REG + * @brief Number of Physical registers currently supported + * Initial PIU implementations will have a 32-word register file. + * Later implementations may have a 64-word register file. + */ +#define IX_PIUDL_TOTAL_NUM_PHYS_REG (32) + +/** + * @def IX_PIUDL_OFFSET_PHYS_REG_ADDR_REGMAP + * @brief LSB-offset of Regmap number in Physical PIU register address, used + * for Physical To Logical register address mapping in the PIU + */ +#define IX_PIUDL_OFFSET_PHYS_REG_ADDR_REGMAP (1) + +/** + * @def IX_PIUDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR + * @brief Mask to extract a logical PIU register address from a physical + * register address, used for Physical To Logical address mapping + */ +#define IX_PIUDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR (0x1) + +#if defined(__ep805xx) +/* + * application specific dual related defines + */ + +/** + * @def IX_PIUDL_APPDUAL_ID_MAX + * @brief The maximum number for an application specific dual coprocessor + * instruction Id + */ +#define IX_PIUDL_APPDUAL_ID_MAX (0xF) + +/** + * @def IX_PIUDL_APPDUAL_COPR_ID_MAX + * @brief The maximum number for an application specific dual coprocessor + * instruction coprocessor Id + */ +#define IX_PIUDL_APPDUAL_COPR_ID_MAX (0xF) + +/** + * @def IX_PIUDL_APPDUAL_INST_ID_MAX + * @brief The maximum number for an application specific dual coprocessor + * instruction instruction Id + */ +#define IX_PIUDL_APPDUAL_INST_ID_MAX (0x3F) + +/** + * @def IX_PIUDL_APPDUAL_REG_OFFSET + * @brief The register offset from the base address for application specific + * dual coprocessor instruction configuration registers + */ +#define IX_PIUDL_APPDUAL_REG_OFFSET (0x20) + +/** + * @def IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 0 decode field + */ +#define IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET (16) + +/** + * @def IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 0 instruction decode field + */ +#define IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET (0) + +/** + * @def IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 1 decode field + */ +#define IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET (24) + +/** + * @def IX_PIUDL_APPDUAL_REG_INST1_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 1 instruction decode field + */ +#define IX_PIUDL_APPDUAL_REG_INST1_BIT_OFFSET (8) + +#endif // #if defined(__ep805xx) + +#endif /* IXPIUDLPIUMGRECREGISTERS_P_H */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrUtils_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrUtils_p.h new file mode 100644 index 0000000..93b00e8 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrUtils_p.h @@ -0,0 +1,499 @@ +/** + * @file IxPiuDlPiuMgrUtils_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + * @brief This file contains the private API for the PiuMgr module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/** + * @defgroup IxPiuDlPiuMgrUtils_p IxPiuDlPiuMgrUtils_p + * + * @brief The private API for the IxPiuDl PiuMgr Utils module + * + * @{ + */ + +#ifndef IXpiuDLpiuMGRUTILS_P_H +#define IXpiuDLpiuMGRUTILS_P_H + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" +#include "IxPiuDlPiuMgrEcRegisters_p.h" + + +/* + * Function Prototypes + */ + +/** + * @fn ix_error ixPiuDlPiuMgrInsMemWrite (ix_uint32 piuBaseAddress, + ix_uint32 insMemAddress, + ix_uint32 insMemData, + BOOL verify) + * + * @brief Writes a word to piu Instruction memory + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] insMemAddress - piu instruction memory address to write + * @param ix_uint32 [in] insMemData - data to write to instruction memory + * @param BOOL [in] verify - if TRUE, verify the memory location is + * written successfully. + * + * This function is used to write a single word of data to a location in piu + * instruction memory. If the <i>verify</i> option is ON, PiuDl will read back + * from the memory location to verify that it was written successfully + * + * @pre + * + * @post + * + * @return + * - IX_FAIL if verify is TRUE and the memory location was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrInsMemWrite (ix_uint32 piuBaseAddress, ix_uint32 insMemAddress, + ix_uint32 insMemData, BOOL verify); + + +/** + * @fn ix_error ixPiuDlPiuMgrDataMemWrite (ix_uint32 piuBaseAddress, + ix_uint32 dataMemAddress, + ix_uint32 dataMemData, + BOOL verify) + * + * @brief Writes a word to piu Data memory + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] dataMemAddress - piu data memory address to write + * @param ix_uint32 [in] dataMemData - data to write to piu data memory + * @param BOOL [in] verify - if TRUE, verify the memory location is + * written successfully. + * + * This function is used to write a single word of data to a location in piu + * data memory. If the <i>verify</i> option is ON, PiuDl will read back from + * the memory location to verify that it was written successfully + * + * @pre + * + * @post + * + * @return + * - IX_FAIL if verify is TRUE and the memory location was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrDataMemWrite (ix_uint32 piuBaseAddress, ix_uint32 dataMemAddress, + ix_uint32 dataMemData, BOOL verify); + + +/** + * @fn void ixPiuDlPiuMgrExecAccRegWrite (ix_uint32 piuBaseAddress, + ix_uint32 regAddress, + ix_uint32 regData) + * + * @brief Writes a word to an piu Execution Access register + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] regAddress - piu Execution Access register address + * @param ix_uint32 [in] regData - data to write to register + * + * This function is used to write a single word of data to an piu Execution + * Access register. + * + * @pre + * + * @post + * + * @return none + */ +void +ixPiuDlPiuMgrExecAccRegWrite (ix_uint32 piuBaseAddress, ix_uint32 regAddress, + ix_uint32 regData); + +#if defined(__ep805xx) +/** + * @fn ix_error ixPiuDlPiuMgrAppDualRegWrite (ix_uint32 piuBaseAddress, + * ix_uint32 appDualRegAddress, + * ix_uint32 appDualRegData, + * BOOL verify) + * + * @brief Configures an application specific dual coprocessor register + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] appDualRegAddress - address of appDual reg to write + * @param ix_uint32 [in] appDualRegData - data to write to appDual reg + * @param BOOL [in] verify - if TRUE, verify the register is + * written successfully. + * + * This function is used to configure an application specific dual coprocessor + * register. If the <i>verify</i> option is ON, the register will be read back + * to verify that it was written successfully + * + * @pre + * - it is assumed that a valid value is passed in for the register i.e. all + * reserved bits have been set to zero + * @post + * + * @return + * - IX_FAIL if verify is TRUE and the register was not written + * successfully + * + * - IX_SUCCESS otherwise + */ +ix_uint32 +ixPiuDlPiuMgrAppDualRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 appDualRegAddress, + ix_uint32 appDualRegData, + BOOL verify); +#endif // #if defined(__ep805xx) + +/** + * @fn ix_uint32 ixPiuDlPiuMgrExecAccRegRead (ix_uint32 piuBaseAddress, + ix_uint32 regAddress) + * + * @brief Reads the contents of an piu Execution Access register + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] regAddress - piu Execution Access register address + * + * This function is used to read the contents of an piu Execution + * Access register. + * + * @pre + * + * @post + * + * @return The value read from the Execution Access register + */ +ix_uint32 +ixPiuDlPiuMgrExecAccRegRead (ix_uint32 piuBaseAddress, ix_uint32 regAddress); + + +/** + * @fn void ixPiuDlPiuMgrCommandIssue (ix_uint32 piuBaseAddress, + ix_uint32 command) + * + * @brief Issues an piu Execution Control command + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] command - Command to issue + * + * This function is used to issue a stand-alone piu Execution Control command + * (e.g. command to Stop piu execution) + * + * @pre + * + * @post + * + * @return none + */ +void +ixPiuDlPiuMgrCommandIssue (ix_uint32 piuBaseAddress, ix_uint32 command); + + +/** + * @fn void ixPiuDlPiuMgrDebugInstructionPreExec (ix_uint32 piuBaseAddress) + * + * @brief Prepare to executes one or more piu instructions in the Debug + * Execution Stack level. + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * + * This function should be called once before a sequence of calls to + * ixPiuDlPiuMgrDebugInstructionExec(). + * + * @pre + * + * @post + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called to restore + * registers values altered by this function + * + * @return none + */ +void +ixPiuDlPiuMgrDebugInstructionPreExec (ix_uint32 piuBaseAddress); + + +/** + * @fn void ixPiuDlPiuMgrDebugInstructionExec (ix_uint32 piuBaseAddress, + ix_uint32 piuInstruction, + ix_uint32 ctxtNum, + ix_uint32 ldur) + * + * @brief Executes a single instruction on the piu at the Debug Execution Stack + * level + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] piuInstruction - Value to write to INSTR (Instruction) + * register + * @param ix_uint32 [in] ctxtNum - context the instruction will be executed + * in and which context store it may access + * @param ix_uint32 [in] ldur - Long Immediate Duration, set to non-zero + * to use long-immediate mode instruction + * + * This function is used to execute a single instruction in the piu pipeline at + * the debug Execution Context Stack level. It won't disturb the state of other + * executing contexts. Its useful for performing piu operations, such as + * writing to piu Context Store registers and physical registers, that cannot + * be carried out directly using the Configuration Bus registers. + * + * @pre + * - The piu should be stopped and in a clean state + * - ixPiuDlPiuMgrDebugInstructionPreExec() should be called once before + * a sequential of 1 or more calls to this function + * + * @post + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called after + * a sequence of calls to this function + * + * @return none + */ +void +ixPiuDlPiuMgrDebugInstructionExec (ix_uint32 piuBaseAddress, + ix_uint32 piuInstruction, + ix_uint32 ctxtNum, ix_uint32 ldur); + + +/** + * @fn void ixPiuDlPiuMgrDebugInstructionPostExec (ix_uint32 piuBaseAddress) + * + * @brief Clean up after executing one or more piu instructions in the + * Debug Stack Level + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * + * This function should be called once following a sequence of calls to + * ixPiuDlPiuMgrDebugInstructionExec(). + * + * @pre + * - ixPiuDlPiuMgrDebugInstructionPreExec() was called earlier + * + * @post + * - The Instruction Pipeline will cleared + * + * @return none + */ +void +ixPiuDlPiuMgrDebugInstructionPostExec (ix_uint32 piuBaseAddress); + + +/** + * @fn ix_error ixPiuDlPiuMgrLogicalRegWrite (ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regValue, + ix_uint32 regSize, + ix_uint32 ctxtNum, + BOOL verify) + * + * @brief Write a logical registers in the piu data + * register file + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] regAddr - number of the physical register (0-31)* + * @param ix_uint32 [in] regValue - value to write to the register + * @param ix_uint32 [in] regSize - the size in bits of the value to be written + * @param ix_uint32 [in] ctxtNum - the context number + * @param BOOL [in] verify - if TRUE, verify the register is written + * successfully. + * + * This function writes a logical register in the piu data register file. + * If the <i>verify</i> option is ON, PiuDl will read back the register to + * verify that it was written successfully + * + * @pre + * - The piu should be stopped and in a clean state + * - ixPiuDlPiuMgrDebugInstructionPreExec() should be called once before + * a sequential of 1 or more calls to this function + * + * @post + * - Contents of REGMAP Context Store register for Context 0 will be altered + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called after + * a sequence of calls to this function + * + * @return + * - IX_FAIL if verify is TRUE and the Context Register was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrLogicalRegWrite (ix_uint32 piuBaseAddress, ix_uint32 regAddr, + ix_uint32 regVal, ix_uint32 regSize, + ix_uint32 ctxtNum, BOOL verify); + +/** + * @fn ix_error ixPiuDlPiuMgrPhysicalRegWrite (ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regValue, + BOOL verify) + * + * @brief Write one of the 32* 32-bit physical registers in the piu data + * register file + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] regAddr - number of the physical register (0-31)* + * @param ix_uint32 [in] regValue - value to write to the physical register + * @param BOOL [in] verify - if TRUE, verify the register is written + * successfully. + * + * This function writes a physical register in the piu data register file. + * If the <i>verify</i> option is ON, PiuDl will read back the register to + * verify that it was written successfully + * *Note that release 1.0 of this software supports 32 physical + * registers, but 64 may be supported in future versions. + * + * @pre + * - The piu should be stopped and in a clean state + * - ixPiuDlPiuMgrDebugInstructionPreExec() should be called once before + * a sequential of 1 or more calls to this function + * + * @post + * - Contents of REGMAP Context Store register for Context 0 will be altered + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called after + * a sequence of calls to this function + * + * @return + * - IX_FAIL if verify is TRUE and the Context Register was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrPhysicalRegWrite (ix_uint32 piuBaseAddress, ix_uint32 regAddr, + ix_uint32 regValue, BOOL verify); + + +/** + * @fn ix_error ixPiuDlPiuMgrCtxtRegWrite (ix_uint32 piuBaseAddress, + ix_uint32 ctxtNum, + IxPiuDlCtxtRegNum ctxtReg, + ix_uint32 ctxtRegVal, + BOOL verify) + * + * @brief Writes a value to a Context Store register on an piu + * + * @param ix_uint32 [in] piuBaseAddress - Base Address of piu + * @param ix_uint32 [in] ctxtNum - context store to access + * @param IxPiuDlCtxtRegNum [in] ctxtReg - which Context Store reg to write + * @param ix_uint32 [in] ctxtRegVal - value to write to the Context Store + * register + * @param BOOL [in] verify - if TRUE, verify the register is + * written successfully. + * + * This function writes the contents of a Context Store register in the piu + * register file. If the <i>verify</i> option is ON, PiuDl will read back the + * register to verify that it was written successfully + * + * @pre + * - The piu should be stopped and in a clean state + * - ixPiuDlPiuMgrDebugInstructionPreExec() should be called once before + * a sequential of 1 or more calls to this function + * + * @post + * - ixPiuDlPiuMgrDebugInstructionPostExec() should be called after + * a sequence of calls to this function + * + * @return + * - IX_FAIL if verify is TRUE and the Context Register was not written + * successfully + * - IX_SUCCESS otherwise + */ +ix_error +ixPiuDlPiuMgrCtxtRegWrite (ix_uint32 piuBaseAddress, ix_uint32 ctxtNum, + IxPiuDlCtxtRegNum ctxtReg, ix_uint32 ctxtRegVal, + BOOL verify); + + +/** + * @fn void ixPiuDlPiuMgrUtilsStatsShow (void) + * + * @brief This function will display the statistics of the IxPiuDl PiuMgrUtils + * module + * + * @return none + */ +void +ixPiuDlPiuMgrUtilsStatsShow (void); + + +/** + * @fn void ixPiuDlPiuMgrUtilsStatsReset (void) + * + * @brief This function will reset the statistics of the IxPiuDl PiuMgrUtils + * module + * + * @return none + */ +void +ixPiuDlPiuMgrUtilsStatsReset (void); + + +#endif /* IXpiuDLpiuMGRUTILS_P_H */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgr_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgr_p.h new file mode 100644 index 0000000..3a6286b --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgr_p.h @@ -0,0 +1,370 @@ +/** + * @file IxPiuDlPiuMgr_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + * @brief This file contains the private API for the PiuMgr module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/** + * @defgroup IxPiuDlPiuMgr_p IxPiuDlPiuMgr_p + * + * @brief The private API for the IxPiuDl PiuMgr module + * + * @{ + */ + +#ifndef IXPIUDLPIUMGR_P_H +#define IXPIUDLPIUMGR_P_H + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" + + +/* + * Function Prototypes + */ +#if defined(__ep805xx) +/** + * @fn ix_error ixPiuDlPiuMgrPhysicalAddressSet ( + * IxPiuDlPiuId piuId, + * ix_uint32 address) + * + * @brief This function sets the physical base address for the given PIU. + * + * @param piuId @ref IxPiuDlPiuId [in] - The ID of the PIU whose physical base + * address will be set - note that it assumed that this has been validated + * by the caller + * @param address ix_uint32 [in] - The address to set the physical address to + * + * This function sets the physical base address for the given PIU. It must be + * called when the piuDl component is not initialized i.e. prior to calling the + * @ref ixPiuDlPiuMgrInit function (maps the physical address to a virtual + * address) or after calling the @ref ixPiuDlPiuMgrUninit function. + * + * @return + * - IX_SUCCESS if the address was set successfully + * - IX_FAIL if the function is called after memory has been initialised + */ +ix_error +ixPiuDlPiuMgrPhysicalAddressSet ( + IxPiuDlPiuId piuId, + ix_uint32 address); + +/** + * @fn ix_error ixPiuDlPiuMgrAppDualSet ( + * IxPiuDlPiuId piuId, + * ix_uint32 appDualId, + * IxPiuDlAppDualInstruction *appDualInstruction + * ) + * + * @brief This function configures an PIU application specific dual coprocessor + * instruction register + * + * @param piuId IxPiuDlPiuId [in] - Id of the target PIU. + * @param appDualId ix_uint32 [in] - The application specific dual coprocessor + * instruction Id + * @param IxPiuDlAppDualInstruction appDualInstruction [in] - pointer to an + * application specific dual coprocessor instruction structure + * + * This function configures an PIU application specific dual coprocessor + * instruction register which allows 2 arbitrary coprocessor instructions to + * execute at the same time. + * + * @return + * - IX_SUCCESS if the dual instruction was set successfully + * - IX_PIUDL_PARAM_ERR if a parameter error occurred + * - IX_FAIL if the verification of the register write fails + */ + +ix_error +ixPiuDlPiuMgrAppDualSet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction +); + +/** + * @fn ix_error ixPiuDlPiuMgrAppDualGet ( + * IxPiuDlPiuId piuId, + * ix_uint32 appDualId, + * IxPiuDlAppDualInstruction *appDualInstruction + * ) + * + * @brief This function retrieves the fields of an PIU application specific + * dual coprocessor instruction register + * + * @param piuId IxPiuDlPiuId [in] - Id of the target PIU. + * @param appDualId ix_uint32 [in] - The application specific dual coprocessor + * instruction Id + * @param IxPiuDlAppDualInstruction appDualInstruction [out] - pointer to an + * application specific dual coprocessor instruction structure which will be + * filled by this function + * + * This function retrieves the fields of an PIU application specific dual + * coprocessor instruction. + * + * @return + * - IX_SUCCESS if the dual instruction was set successfully + * - IX_PIUDL_PARAM_ERR if a parameter error occurred + */ + +ix_error +ixPiuDlPiuMgrAppDualGet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction +); + +#endif // #if defined(__ep805xx) + +/** + * @fn void ixPiuDlPiuMgrInit (void) + * + * @brief Initialises the PiuMgr module + * + * @param none + * + * This function initialises the PiuMgr module. + * It should be called before any other function in this module is called. + * It only needs to be called once, but can be called multiple times safely. + * The code will ASSERT on failure. + * + * @pre + * - It must be called before any other function in this module + * + * @post + * - PIU Configuration Register memory space will be mapped using + * IxOsal. This memory will not be unmapped by this module. + * + * @return none + */ +void +ixPiuDlPiuMgrInit (void); + + +/** + * @fn ix_error ixPiuDlPiuMgrUninit (void) + * + * @brief This function will uninitialise the IxPiuDlPiuMgr sub-component. + * + * This function will uninitialise the IxPiuDlPiuMgr sub-component. + * It should only be called once, and only if the IxPiuDlPiuMgr sub-component + * has already been initialised by calling @ref ixPiuDlPiuMgrInit(). + * No other IxPiuDlPiuMgr sub-component API functions should be called + * until @ref ixPiuDlPiuMgrInit() is called again. + * If possible, this function should be called before a soft reboot or unloading + * a kernel module to perform any clean up operations required for IxPiuDl. + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ + +ix_error ixPiuDlPiuMgrUninit (void); + + +/** + * @fn ix_error ixPiuDlPiuMgrImageLoad (IxPiuDlPiuId piuId, + ix_uint32 *imageCodePtr, + BOOL verify) + * + * @brief Loads a image of microcode onto an PIU + * + * @param IxPiuDlPiuId [in] piuId - Id of target PIU + * @param ix_uint32* [in] imageCodePtr - pointer to image code in image to be + * downloaded + * @param BOOL [in] verify - if TRUE, verify each word written to + * PIU memory. + * + * This function loads a image containing blocks of microcode onto a + * particular PIU. If the <i>verify</i> option is ON, PiuDl will read back each + * word written and verify that it was written successfully + * + * @pre + * - The PIU should be stopped beforehand + * + * @post + * - The PIU Instruction Pipeline may be flushed clean + * + * @return + * - IX_SUCCESS if the download was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuMgrImageLoad (IxPiuDlPiuId piuId, ix_uint32 *imageCodePtr, + BOOL verify); + + +/** + * @fn ix_error ixPiuDlPiuMgrPiuReset (IxPiuDlPiuId piuId) + * + * @brief sets a PIU to RESET state + * + * @param IxPiuDlPiuId [in] piuId - id of target PIU + * + * This function performs a soft PIU reset by writing reset values to the + * Configuration Bus Execution Control registers, the Execution Context Stack + * registers, the Physical Register file, and the Context Store registers for + * each context number. It also clears inFIFO, outFIFO and Watchpoint FIFO. + * It does not reset PIU Co-processors. + * + * @pre + * - The PIU should be stopped beforehand + * + * @post + * - PIU NextProgram Counter (NextPC) will be set to a fixed initial value, + * such as 0. This should be explicitly set by downloading State + * Information before starting PIU Execution. + * - The PIU Instruction Pipeline will be in a clean state. + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuMgrPiuReset (IxPiuDlPiuId piuId); + + +/** + * @fn ix_error ixPiuDlPiuMgrPiuStart (IxPiuDlPiuId piuId) + * + * @brief Starts PIU Execution + * + * @param IxPiuDlPiuId [in] piuId - Id of target PIU + * + * Ensures only background Execution Stack Level is Active, clears instruction + * pipeline, and starts Execution on a PIU by sending a Start PIU command to + * the PIU. Checks the execution status of the PIU to verify that it is + * running. + * + * @pre + * - The PIU should be stopped beforehand. + * - Note that this function does not set the PIU Next Program Counter + * (NextPC), so it should be set beforehand if required by downloading + * appropriate State Information. + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuMgrPiuStart (IxPiuDlPiuId piuId); + + +/** + * @fn ix_error ixPiuDlPiuMgrPiuStop (IxPiuDlPiuId piuId) + * + * @brief Halts PIU Execution + * + * @param IxPiuDlPiuId [in] piuId - id of target PIU + * + * Stops execution on an PIU by sending a Stop PIU command to the PIU. + * Checks the execution status of the PIU to verify that it has stopped. + * + * @pre + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuMgrPiuStop (IxPiuDlPiuId piuId); + + +/** + * @fn void ixPiuDlPiuMgrStatsShow (void) + * + * @brief This function will display statistics of the IxPiuDl PiuMgr module + * + * @return none + */ +void +ixPiuDlPiuMgrStatsShow (void); + + +/** + * @fn void ixPiuDlPiuMgrStatsReset (void) + * + * @brief This function will reset the statistics of the IxPiuDl PiuMgr module + * + * @return none + */ +void +ixPiuDlPiuMgrStatsReset (void); + + +#endif /* IXPIUDLIMAGEMGR_P_H */ + +/** + * @} defgroup IxPiuDlPiuMgr_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlTestReg.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlTestReg.h new file mode 100644 index 0000000..c333ceb --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlTestReg.h @@ -0,0 +1,110 @@ +/** + * @file IxPiuDlTestReg.h + * + * @author Intel Corporation + * @date 13 August 2003 + * @brief This file contains some test function prototypes. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuDlTestReg IxPiuDlTestReg + * + * @brief Test PIU register read/write function prototypes. + * + * @{ + */ + +#ifndef IXPIUDLTESTREG_P_H +#define IXPIUDLTESTREG_P_H + + +/* + * Put the user defined include files required. + */ + +#include "IxPiuTypes.h" + +extern ix_uint32 ixp23xx_reset1_reg; +#define IXP23XX_RESET1_REG ixp23xx_reset1_reg + +/* + * Prototypes for interface functions. + */ + +void ixPiuDlTestRegRead ( + ix_uint32 baseAddr, + ix_uint32 offset, + ix_uint32 *value); + +void ixPiuDlTestRegWrite ( + ix_uint32 baseAddr, + ix_uint32 offset, + ix_uint32 value); + + +#endif /* IXPIUDLTESTREG_P_H */ + +/** + * @} defgroup IxPiuDlTest_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDl_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDl_p.h new file mode 100644 index 0000000..713c542 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDl_p.h @@ -0,0 +1,167 @@ +/** + * @file IxPiuDl_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + + * @brief This file contains the private API for the ImageMgr module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/** + * @defgroup IxPiuDl_p IxPiuDl_p + * + * @brief The private API for the IxPiuDl module + * + * @{ + */ + +#ifndef IXPIUDL_P_H +#define IXPIUDL_P_H + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" + + +/* + * #defines and macros + */ + + +/* + * Prototypes for interface functions +*/ + +/** + * @ingroup IxPiuDl_p + * + * @fn ix_error ixPiuDlPiuExecutionStart (IxPiuDlPiuId piuId) + * + * @brief Starts code execution on a PIU + * + * @param IxPiuDlPiuId [in] piuId - Id of the target PIU + * + * Starts execution of code on a particular PIU. A client would typically use + * this after a download to PIU is performed, to start/restart code execution + * on the PIU. + * + * @note It is no longer necessary to call this function after downloading + * a new image to the PIU. It is left on the API only to allow greater control + * of PIU execution if required. Where appropriate, use @ref ixPiuDlPiuInitAndStart + * or @ref ixPiuDlCustomImagePiuInitAndStart instead. + * + * @pre + * - The Client is responsible for ensuring mutual access to the PIU. + * - Note that this function does not set the PIU Next Program Counter + * (NextPC), so it should be set beforehand if required by downloading + * appropriate State Information (using ixPiuDlVersionDownload()). + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuExecutionStart (IxPiuDlPiuId piuId); + +/** + * @ingroup IxPiuDl_p + * + * @fn ix_error ixPiuDlPiuExecutionStop (IxPiuDlPiuId piuId) + * + * @brief Stops code execution on a PIU + * + * @param IxPiuDlPiuId [in] piuId - Id of the target PIU + * + * Stops execution of code on a particular PIU. This would typically be used + * by a client before a download to PIU is performed, to stop code execution on + * an PIU, unless ixPiuDlPiuStopAndReset() is used instead. Unlike + * ixPiuDlPiuStopAndReset(), this function only halts the PIU and leaves + * all registers and settings intact. This is useful, for example, between + * stages of a multi-stage download, to stop the PIU prior to downloading the + * next image while leaving the current state of the PIU intact.. + * + * @pre + * - The Client is responsible for ensuring mutual access to the PIU. + * + * @post + * + * @return + * - IX_SUCCESS if the operation was successful + * - IX_PIUDL_PARAM_ERR if a parameter error occured + * - IX_FAIL otherwise + */ +ix_error +ixPiuDlPiuExecutionStop (IxPiuDlPiuId piuId); + +#endif /* IXPIUDL_P_H */ + +/** + * @} defgroup IxPiuDl_p + */ + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuMicrocode.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuMicrocode.h new file mode 100644 index 0000000..cf34b49 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuMicrocode.h @@ -0,0 +1,123 @@ +/** + * @date February 25, 2009 + * + * @brief IXP400 PIU Microcode Image file + * + * This file was generated by the IxPiuDlImageGen tool. + * It contains a PIU microcode image suitable for use + * with the PIU Downloader (IxPiuDl) component in the + * IXP400 Access Driver software library. + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMicrocode Intel (R) IXP400 PIU Microcode Image Library + * + * @brief Library containing a set of PIU firmware images, for use + * with PIU Downloader s/w component + * + * @{ + */ + +/** + * @def IX_PIU_IMAGE_INCLUDE + * + * @brief Wrap the following Image identifiers with "#if IX_PIU_IMAGE_INCLUDE ... #endif" to include the image in the library + */ +#define IX_PIU_IMAGE_INCLUDE 1 + +/** + * @def IX_PIU_IMAGE_OMIT + * + * @brief Wrap the following Image identifiers with "#if IX_PIU_IMAGE_OMIT ... #endif" to OMIT the image from the library + */ +#define IX_PIU_IMAGE_OMIT 0 + + +#if IX_PIU_IMAGE_INCLUDE +/** + * @def IX_PIUDL_PIUIMAGE_PIU_HSS_TOLAPAI + * + * @brief Common HSS Build for Tolapai platform + */ +#define IX_PIUDL_PIUIMAGE_PIU_HSS_TOLAPAI 0x30010000 +#endif + +/* Number of PIU firmware images in this library */ +#define IX_PIU_MICROCODE_AVAILABLE_VERSIONS_COUNT 1 + +/* Location of Microcode Images */ +#ifdef IX_PIU_MICROCODE_FIRMWARE_INCLUDED +#ifdef IX_PIUDL_READ_MICROCODE_FROM_FILE + +extern UINT32* ixPiuMicrocode_binaryArray; + +#else + +extern unsigned IxPiuMicrocode_array[]; + +#endif +#endif + +/** + * @} defgroup IxPiuMicrocode + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..6feb7cc --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/linux_2.6_kernel_space.mk @@ -0,0 +1,76 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DEP805XX -D__ep805xx -DIX_HW_COHERENT_MEMORY=1 +EXTRA_LDFLAGS+=-whole-archive + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDl.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDl.c new file mode 100644 index 0000000..6f36c1e --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDl.c @@ -0,0 +1,599 @@ +/** + * @file IxPiuDl.c + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @description Contents are the implementation of the public API for the + * PIU Downloader component + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/* + * Put the system defined include files required + */ + +/* + * Put the user defined include files required + */ +#include "IxPiuDl.h" +#include "IxPiuDlImageMgr_p.h" +#include "IxPiuDlPiuMgr_p.h" +#include "IxPiuDlMacros_p.h" +#include "IxPiuDl_p.h" + +/* + * #defines used in this file + */ +#define IMAGEID_MAJOR_NUMBER_DEFAULT 0 +#define IMAGEID_MINOR_NUMBER_DEFAULT 0 + +/* + * Typedefs whose scope is limited to this file. + */ +typedef struct +{ + BOOL validImage; + IxPiuDlImageId imageId; +} IxPiuDlPiuState; + +/* module statistics counters */ +typedef struct +{ + ix_uint32 attemptedDownloads; + ix_uint32 successfulDownloads; + ix_uint32 criticalFailDownloads; /*This means the PIU is in a bad state*/ +} IxPiuDlStats; + +/* + * Variable declarations global to this file only. Externs are followed + * by static variables. + */ +static IxPiuDlPiuState ixPiuDlPiuState[IX_PIUDL_PIUID_MAX] = +{ + { + FALSE, /*TRUE if valid image downloaded*/ + {0,0,0,0} /* ID of the image*/ + } + +#if !defined(__ep805xx) + , + { + FALSE, /*TRUE if valid image downloaded*/ + {0,0,0,0} /* ID of the image*/ + } +#endif +}; + +static IxPiuDlStats ixPiuDlStats; + +/* + * Software guard to prevent PIU from being started multiple times. + */ +#if defined(__ep805xx) +static BOOL ixPiuDlPiuStarted[IX_PIUDL_PIUID_MAX] ={FALSE } ; +#else +static BOOL ixPiuDlPiuStarted[IX_PIUDL_PIUID_MAX] ={FALSE, FALSE } ; +#endif + +/* + * static function prototypes. + */ +PIU_PRIVATE ix_error +ixPiuDlPiuInitAndStartInternal (ix_uint32 *imageLibrary, ix_uint32 imageId); + + +/* + * Function definition: ixPiuDlPiuStopAndReset + */ +ix_error +ixPiuDlPiuStopAndReset (IxPiuDlPiuId piuId) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuStopAndReset\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuStopAndReset - invalid parameter\n"); + status = IX_PIUDL_PARAM_ERR; + } + + if (status == IX_SUCCESS) + { + /* Ensure initialisation has been completed */ + ixPiuDlPiuMgrInit(); + + /* call PiuMgr function to stop the PIU */ + status = ixPiuDlPiuMgrPiuStop (piuId); + } + + if (status == IX_SUCCESS) + { + /* call PiuMgr function to reset the PIU */ + status = ixPiuDlPiuMgrPiuReset (piuId); + } + + if (IX_SUCCESS == status) + { + /* Indicate PIU has been stopped */ + ixPiuDlPiuStarted[piuId] = FALSE ; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuStopAndReset : status = %u\n", status); + + return status; +} + +/* + * Function definition: ixPiuDlPiuExecutionStart + */ +ix_error +ixPiuDlPiuExecutionStart (IxPiuDlPiuId piuId) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuExecutionStart\n"); + + if (TRUE == ixPiuDlPiuStarted[piuId]) + { + /* PIU has been started. */ + return IX_SUCCESS ; + } + + /* Ensure initialisation has been completed */ + ixPiuDlPiuMgrInit(); + + /* call PiuMgr function to start the PIU */ + status = ixPiuDlPiuMgrPiuStart (piuId); + + if (IX_SUCCESS == status) + { + /* Indicate PIU has started */ + ixPiuDlPiuStarted[piuId] = TRUE ; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuExecutionStart : status = %u\n", + status); + + return status; +} + +/* + * Function definition: ixPiuDlPiuExecutionStop + */ +ix_error +ixPiuDlPiuExecutionStop (IxPiuDlPiuId piuId) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuExecutionStop\n"); + + /* Ensure initialisation has been completed */ + ixPiuDlPiuMgrInit(); + + /* call PiuMgr function to stop the PIU */ + status = ixPiuDlPiuMgrPiuStop (piuId); + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuExecutionStop : status = %u\n", + status); + + if (IX_SUCCESS == status) + { + /* Indicate PIU has been stopped */ + ixPiuDlPiuStarted[piuId] = FALSE ; + } + + return status; +} + +/* + * Function definition: ixPiuDlUnload + */ +ix_error +ixPiuDlUnload (void) +{ + ix_error status; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlUnload\n"); + + status = ixPiuDlPiuMgrUninit(); + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlUnload : status = %u\n", + status); + return status; +} + +/* + * Function definition: ixPiuDlStatsShow + */ +void +ixPiuDlStatsShow (void) +{ + printf("\nixPiuDlStatsShow:\n"); + + printf("\tDownloads Attempted by user: %u\n", + ixPiuDlStats.attemptedDownloads); + printf("\tSuccessful Downloads: %u\n", + ixPiuDlStats.successfulDownloads); + printf("\tFailed Downloads (due to Critical Error, PIU in bad state): %u\n", + ixPiuDlStats.criticalFailDownloads); + + printf("\n"); + + ixPiuDlImageMgrStatsShow (); + ixPiuDlPiuMgrStatsShow (); +} + +/* + * Function definition: ixPiuDlStatsReset + */ +void +ixPiuDlStatsReset (void) +{ + ixPiuDlStats.attemptedDownloads = 0; + ixPiuDlStats.successfulDownloads = 0; + ixPiuDlStats.criticalFailDownloads = 0; + + ixPiuDlImageMgrStatsReset (); + ixPiuDlPiuMgrStatsReset (); +} + +/* + * Function definition: ixPiuDlPiuInitAndStartInternal + */ +PIU_PRIVATE ix_error +ixPiuDlPiuInitAndStartInternal (ix_uint32 *imageLibrary, + ix_uint32 imageId) +{ + ix_uint32 imageSize; + ix_uint32 *imageCodePtr = NULL; + ix_error status; + IxPiuDlPiuId piuId = IX_PIUDL_PIUID_FROM_IMAGEID_GET(imageId); + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuInitAndStartInternal\n"); + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "Download and Start Image 0x%08X\n", + imageId); + + ixPiuDlStats.attemptedDownloads++; + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuInitAndStartInternal - " + "invalid parameter\n"); + } + else + { + /* Ensure initialisation has been completed */ + ixPiuDlPiuMgrInit(); + + /* stop and reset the PIU */ + if (IX_SUCCESS != ixPiuDlPiuStopAndReset (piuId)) + { + IX_PIUDL_ERROR_REPORT ("Failed to stop and reset PIU\n"); + return IX_FAIL; + } + + /* Locate image */ + status = ixPiuDlImageMgrImageFind (imageLibrary, imageId, + &imageCodePtr, &imageSize); + + if (IX_SUCCESS == status) + { + /* + * If download was successful, store image Id in list of + * currently loaded images. If a critical error occured + * during download, record that the PIU has an invalid image + */ + status = ixPiuDlPiuMgrImageLoad (piuId, imageCodePtr, TRUE); + + if (IX_SUCCESS == status) + { + ixPiuDlPiuState[piuId].validImage = TRUE; + ixPiuDlStats.successfulDownloads++; + + status = ixPiuDlPiuExecutionStart (piuId); + } + else if ((status == IX_PIUDL_CRITICAL_PIU_ERR) || + (status == IX_PIUDL_CRITICAL_MICROCODE_ERR)) + { + ixPiuDlPiuState[piuId].validImage = FALSE; + ixPiuDlStats.criticalFailDownloads++; + } + + ixPiuDlImageMgrImageIdFormat(imageId, + &(ixPiuDlPiuState[piuId].imageId)); + + } /* end of if(IX_SUCCESS) */ + /* condition: image located successfully in microcode image */ + } /* end of if-else(piuId) *//* condition: parameter checks ok */ + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuInitAndStartInternal : " + "status = %u\n", status); + return status; +} + +/* + * Function definition: ixPiuDlCustomImagePiuInitAndStart + */ +ix_error +ixPiuDlCustomImagePiuInitAndStart (ix_uint32 *imageLibrary, + ix_uint32 imageId) +{ + ix_error status; + if (imageLibrary == NULL) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlCustomImagePiuInitAndStart " + "- invalid parameter\n"); + } + else + { + status = ixPiuDlPiuInitAndStartInternal (imageLibrary,imageId ); + } /* end of if-else(imageLibrary) */ + + return status; +} + +/* + * Function definition: ixPiuDlPiuInitAndStart + */ +ix_error +ixPiuDlPiuInitAndStart (ix_uint32 imageId) +{ + return ixPiuDlPiuInitAndStartInternal (NULL, imageId); +} + +/* + * Function definition: ixPiuDlLoadedImageGet + */ +ix_error +ixPiuDlLoadedImageGet (IxPiuDlPiuId piuId, + IxPiuDlImageId *imageIdPtr) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlLoadedImageGet\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0) || (imageIdPtr == NULL)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlLoadedImageGet - invalid parameter\n"); + } + else + { + + if (ixPiuDlPiuState[piuId].validImage) + { + /* use piuId to get imageId from list of currently loaded + images */ + *imageIdPtr = ixPiuDlPiuState[piuId].imageId; + } + else + { + status = IX_FAIL; + IX_PIUDL_ERROR_REPORT ("ixPiuDlLoadedImageGet - " + "PIU does not have a valid image\n"); + } /* end of if-else(ixPiuDlPiuState) */ + } /* end of if-else(piuId) */ + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlLoadedImageGet : status = %d\n", + status); + return status; +} + + +/* + * Function definition: ixPiuDlAvailableImagesListGet + */ +ix_error +ixPiuDlAvailableImagesListGet (IxPiuDlImageId *imageIdListPtr, + ix_uint32 *listSizePtr) +{ + ix_error status; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlAvailableImagesListGet\n"); + + /* Check input parameters */ + if ((imageIdListPtr == NULL) || (listSizePtr == NULL)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlAvailableImagesListGet - " + "invalid parameter\n"); + } + else + { + /* Call ImageMgr to get list of images listed in Image Library Header */ + status = ixPiuDlImageMgrImageListExtract (imageIdListPtr, + listSizePtr); + } /* end of if-else(imageIdListPtr) */ + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlAvailableImagesListGet : status = %d\n", + status); + return status; +} +#if defined(__ep805xx) + +/* + * Function definition: ixPiuDlPhysicalAddressSet + */ +ix_error +ixPiuDlPhysicalAddressSet ( + IxPiuDlPiuId piuId, + ix_uint32 address) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPhysicalAddressSet\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT("ixPiuDlPhysicalAddressSet - invalid " + "parameter\n"); + } + else + { + /* store the address */ + status = ixPiuDlPiuMgrPhysicalAddressSet(piuId, address); + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPhysicalAddressSet : status = %d\n", + status); + return status; +} + +/* + * Function definition: ixPiuDlAppDualSet + */ +ix_error +ixPiuDlAppDualSet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction ) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlAppDualSet\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlAppDualSet - invalid parameter\n"); + return IX_PIUDL_PARAM_ERR; + } + if (appDualInstruction == NULL) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlAppDualSet - invalid parameter\n"); + return IX_PIUDL_PARAM_ERR; + } + + /* set the appDual register */ + status = ixPiuDlPiuMgrAppDualSet(piuId, appDualId, appDualInstruction); + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlAppDualSet : status = %d\n", + status); + return status; +} + +/* + * Function definition: ixPiuDlAppDualGet + */ +ix_error +ixPiuDlAppDualGet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction ) +{ + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlAppDualGet\n"); + + /* Check input parameters */ + if ((piuId >= IX_PIUDL_PIUID_MAX) || (piuId < 0)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlAppDualGet - invalid parameter\n"); + return IX_PIUDL_PARAM_ERR; + } + if (appDualInstruction == NULL) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlAppDualSet - invalid parameter\n"); + return IX_PIUDL_PARAM_ERR; + } + + /* get the appDual register */ + status = ixPiuDlPiuMgrAppDualGet(piuId, appDualId,appDualInstruction); + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlAppDualGet : status = %d\n", + status); + return status; +} + +#endif /* #if defined(__ep805xx) */ + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlFwLoader.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlFwLoader.c new file mode 100644 index 0000000..79ccf51 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlFwLoader.c @@ -0,0 +1,210 @@ +/** + * @file IxPiuDlFwLoader.c + * + * @author Intel Corporation + * @date 25 June 2007 + * + * @brief Contents are the implementation of a method for reading PIU firmware + * from file using the 'request_firmware' loading mechanism available in Linux + * kernel v2.6 + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/* + * Put the system defined include files required + */ + +#include "linux/device.h" +#include "linux/firmware.h" + +/* + * Put the user defined include files required + */ +#include "IxPiuDlFwLoader_p.h" +#include "IxPiuDlMacros_p.h" + +/* + * Variable declarations global to this file only. Externs are followed + * by static variables. + */ + +/* + * release function for piu firmware temporary device below + */ +static void piuDeviceRelease(struct device *dev) +{ + printk("piuDevice released after loading firmware\n"); +} + +/* + * The following is a temporary device which is used for loading the firmware + * image - the 'request_firmware()' function needs a device to be passed to it - + * it doesn't matter what the device is - once the device is within the system, + * the udev looks for the requested file from the /lib/firmware location - the + * approach here is to create a temporary device so as not to have any + * dependencies on any particular devices + */ + +static struct device piuFirmwareDevice = { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) + .init_name = "piuDevice", +#else + .bus_id = "piuDevice", +#endif + .release = piuDeviceRelease +}; + +/* + * the following is used to record when firmware has been loaded such that + * loading a new image without freeing a previous one and freeing an image + * before loading can be prevented + */ +static BOOL piuFwLoaded = FALSE; + +/* + * the following is used to store the firmware (populated by the + * request_firmware function) + */ +const struct firmware *piuFwEntry; + +/* + * the name of the file to load + */ +#define PIU_FIRMWARE_FILENAME "IxPiuMicrocode.dat" + +/* + * Function definition: ixPiuDlFwLoaderGetFw + */ +ix_error +ixPiuDlFwLoaderGetFw(ix_uint32** firmwareArray) +{ + int r; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlFwLoaderGetFw\n"); + + /* + * first check if the fw is already loaded - if it is then release the + * piuFwEntry structure + */ + if (piuFwLoaded) + { + release_firmware(piuFwEntry); + piuFwLoaded = FALSE; + } + + /* register the temporary device used for requesting firmware */ + if (device_register(&piuFirmwareDevice) != 0) + { + /* BUGBUG? should we also put_device? */ + IX_PIUDL_ERROR_REPORT ("ixPiuDlFwLoaderGetFw: could not register device\n"); + return IX_FAIL; + } + + /* load the firmware */ + if ((r = request_firmware(&piuFwEntry, PIU_FIRMWARE_FILENAME, + &piuFirmwareDevice)) != 0) + { + ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, + "Error loading " PIU_FIRMWARE_FILENAME " from file: %d\n", + r, 0, 0, 0, 0, 0); + + /* unregister the temporary device from the system */ + device_unregister(&piuFirmwareDevice); + + return IX_FAIL; + } + + /* record successful load */ + piuFwLoaded = TRUE; + + /* cast the firmware pointer to the required type */ + *firmwareArray = (ix_uint32*) piuFwEntry->data; + + /* unregister the temporary device from the system */ + device_unregister(&piuFirmwareDevice); + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlFwLoaderGetFw\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuDlFwLoaderCleanup + */ +void +ixPiuDlFwLoaderCleanup(void) +{ + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlFwLoaderCleanup\n"); + + if (piuFwLoaded) + { + /* release the structure used to hold the firmware */ + release_firmware(piuFwEntry); + piuFwLoaded = FALSE; + } + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlFwLoaderCleanup\n"); +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlImageMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlImageMgr.c new file mode 100644 index 0000000..76685b6 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlImageMgr.c @@ -0,0 +1,416 @@ +/** + * @file IxPiuDlImageMgr.c + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @description Contents are the implementation of the private API for the + * PIU Downloader ImageMgr module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDlImageMgr_p.h" +#include "IxPiuDlMacros_p.h" + +#if defined(IX_PIUDL_READ_MICROCODE_FROM_FILE) && defined (__ep805xx) +#include "IxPiuDlFwLoader_p.h" +#else +/* + * define the flag which toggles the firmare inclusion + */ +#define IX_PIU_MICROCODE_FIRMWARE_INCLUDED +#include "IxPiuMicrocode.h" +#endif + + +/* + * Typedefs whose scope is limited to this file. + */ + +typedef struct +{ + ix_uint32 size; + ix_uint32 offset; + ix_uint32 id; +} IxPiuDlImageMgrImageEntry; + +typedef union +{ + IxPiuDlImageMgrImageEntry image; + ix_uint32 eohMarker; +} IxPiuDlImageMgrHeaderEntry; + +typedef struct +{ + ix_uint32 signature; + /* 1st entry in the header (there may be more than one) */ + IxPiuDlImageMgrHeaderEntry entry[1]; +} IxPiuDlImageMgrImageLibraryHeader; + + +/* + * PIU Image Header definition, used in new PIU Image Library format + */ +typedef struct +{ + ix_uint32 marker; + ix_uint32 id; + ix_uint32 size; +} IxPiuDlImageMgrImageHeader; + + +/* module statistics counters */ +typedef struct +{ + ix_uint32 invalidSignature; + ix_uint32 imageIdListOverflow; + ix_uint32 imageIdNotFound; +} IxPiuDlImageMgrStats; + + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ +static IxPiuDlImageMgrStats ixPiuDlImageMgrStats; + +/* default image */ +#ifdef IX_PIUDL_READ_MICROCODE_FROM_FILE + +#if !defined(__ep805xx) +extern ix_uint32 *ixPiuMicrocode_binaryArray; +#endif + +static ix_uint32 *IxPiuMicroCodeImageLibrary = NULL; + +#else +static ix_uint32 *IxPiuMicroCodeImageLibrary = (ix_uint32*)IxPiuMicrocode_array; +#endif + +/* + * static function prototypes. + */ +PIU_PRIVATE BOOL +ixPiuDlImageMgrSignatureCheck (ix_uint32 *microCodeImageLibrary); + + +/* + * Function definition: ixPiuDlImageMgrSignatureCheck + */ +PIU_PRIVATE BOOL +ixPiuDlImageMgrSignatureCheck (ix_uint32 *microCodeImageLibrary) +{ + IxPiuDlImageMgrImageLibraryHeader *header = + (IxPiuDlImageMgrImageLibraryHeader *) microCodeImageLibrary; + BOOL result = TRUE; + + if (header->signature != IX_PIUDL_IMAGEMGR_SIGNATURE) + { + result = FALSE; + ixPiuDlImageMgrStats.invalidSignature++; + } + + return result; +} + + + +/* + * Function definition: ixPiuDlImageMgrStatsShow + */ +void +ixPiuDlImageMgrStatsShow (void) +{ + printf ("\nixPiuDlImageMgrStatsShow:\n"); + + printf ("\tInvalid Image Signatures: %u\n", + ixPiuDlImageMgrStats.invalidSignature); + printf ("\tImage Id List capacity too small: %u\n", + ixPiuDlImageMgrStats.imageIdListOverflow); + printf ("\tImage Id not found: %u\n", + ixPiuDlImageMgrStats.imageIdNotFound); + + printf ("\n"); +} + + +/* + * Function definition: ixPiuDlImageMgrStatsReset + */ +void +ixPiuDlImageMgrStatsReset (void) +{ + ixPiuDlImageMgrStats.invalidSignature = 0; + ixPiuDlImageMgrStats.imageIdListOverflow = 0; + ixPiuDlImageMgrStats.imageIdNotFound = 0; +} + +/* + * Function definition: ixPiuDlImageMgrImageFind + */ +ix_error +ixPiuDlImageMgrImageFind ( + ix_uint32 *imageLibrary, + ix_uint32 imageId, + ix_uint32 **imagePtr, + ix_uint32 *imageSize) +{ + ix_uint32 offset = 0; + IxPiuDlImageMgrImageHeader *image; + ix_error status = IX_FAIL; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlImageMgrImageFind\n"); + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "Looking for Image 0x%08X\n",imageId); + + + /* If user didn't specify a library to use, use the default + * one from IxPiuMicrocode.h + */ + if (imageLibrary == NULL) + { +#ifdef IX_PIUDL_READ_MICROCODE_FROM_FILE + +#if defined(__ep805xx) + /* + * For EP805xx use the linux 2.6 firmware download mechanism available + * in the kernel to read the firmware + */ + + if (ixPiuDlFwLoaderGetFw(&imageLibrary) != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: Failed " + "to load Microcode Image from file\n"); + return IX_FAIL; + } +#else + /* + * For ixp23xx use the pre linux 2.6 download mechanism which uses an + * PIU character device driver to read the firmware + */ + if (ixPiuMicrocode_binaryArray == NULL) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: " + "No Microcode Loaded in memory\n"); + return IX_FAIL; + } + else + { + imageLibrary = ixPiuMicrocode_binaryArray; + } +#endif /* #if defined(__ep805xx) */ + +#else + /* + * image is already in memory + */ + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "Looking in library at 0x%08X\n", + (ix_uint32)IxPiuMicroCodeImageLibrary); + imageLibrary = IxPiuMicroCodeImageLibrary; +#endif + } + + if (ixPiuDlImageMgrSignatureCheck (imageLibrary)) + { + while (*(imageLibrary+offset) == IX_PIUDL_IMAGEMGR_SIGNATURE) + { + image = (IxPiuDlImageMgrImageHeader *)(imageLibrary+offset); + offset += sizeof(IxPiuDlImageMgrImageHeader)/sizeof(ix_uint32); + + if (image->id == imageId) + { + *imagePtr = imageLibrary + offset; + *imageSize = image->size; + return IX_SUCCESS; + } + /* 2 consecutive IX_PIUDL_IMAGEMGR_SIGNATURE's indicates end of + * library */ + else if (image->id == IX_PIUDL_IMAGEMGR_SIGNATURE) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: " + "imageId not found in image library header\n"); + ixPiuDlImageMgrStats.imageIdNotFound++; + /* reached end of library, image not found */ + return IX_FAIL; + } + offset += image->size; + } + /* If we get here, our image library may be corrupted */ + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: " + "image library format may be invalid or corrupted\n"); + } + else + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageFind: " + "invalid signature in image library\n"); + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlImageMgrImageFind: status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlImageMgrImageIdFormat + */ +void +ixPiuDlImageMgrImageIdFormat ( + ix_uint32 rawImageId, + IxPiuDlImageId *imageId) +{ + imageId->piuId = (rawImageId >> + IX_PIUDL_IMAGEID_PIUCODE_OFFSET) & + IX_PIUDL_PIUIMAGE_FIELD_MASK; + imageId->functionalityId = (rawImageId >> + IX_PIUDL_IMAGEID_FUNCTIONID_OFFSET) & + IX_PIUDL_PIUIMAGE_FIELD_MASK; + imageId->major = (rawImageId >> + IX_PIUDL_IMAGEID_MAJOR_OFFSET) & + IX_PIUDL_PIUIMAGE_FIELD_MASK; + imageId->minor = (rawImageId >> + IX_PIUDL_IMAGEID_MINOR_OFFSET) & + IX_PIUDL_PIUIMAGE_FIELD_MASK; + +} + +/* + * Function definition: ixPiuDlImageMgrImageListExtract + */ +ix_error +ixPiuDlImageMgrImageListExtract ( + IxPiuDlImageId *imageListPtr, + ix_uint32 *numImages) +{ + IxPiuDlImageId formattedImageId; + ix_error status = IX_SUCCESS; + ix_uint32 imageCount = 0; + IxPiuDlImageMgrImageLibraryHeader *header; + ix_uint32 *microcode; + ix_uint32 index = 0; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlImageMgrImageListExtract\n"); + + microcode = (ix_uint32*) IxPiuMicroCodeImageLibrary; + header = (IxPiuDlImageMgrImageLibraryHeader *) IxPiuMicroCodeImageLibrary; + + if (ixPiuDlImageMgrSignatureCheck ((ix_uint32*)header)) + { + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlImageMgrImageListExtract: About to search\n"); + while (!((microcode[index] == IX_PIUDL_IMAGEMGR_SIGNATURE) && + (microcode[index+1] == IX_PIUDL_IMAGEMGR_SIGNATURE))) + { + if (microcode[index] == IX_PIUDL_IMAGEMGR_SIGNATURE) + { + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlImageMgrImageListExtract: found an image\n"); + ixPiuDlImageMgrImageIdFormat (microcode[index+1], + &formattedImageId); + imageListPtr[imageCount] = formattedImageId; + imageCount++; + } + index++; + } + + /* + * if image list container from calling function was too small to + * contain all image ids in the header, set return status to FAIL + */ + if ((imageListPtr != NULL) && (imageCount > *numImages)) + { + status = IX_FAIL; + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageListExtract: " + "number of Ids found exceeds list capacity\n"); + ixPiuDlImageMgrStats.imageIdListOverflow++; + } + /* return number of image ids found in image library header */ + *numImages = imageCount; + } + else + { + status = IX_FAIL; + IX_PIUDL_ERROR_REPORT ("ixPiuDlImageMgrImageListExtract: " + "invalid signature in image\n"); + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlImageMgrImageListExtract: status = %d\n", + status); + return status; +} + + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgr.c new file mode 100644 index 0000000..4fe9a41 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgr.c @@ -0,0 +1,1547 @@ +/** + * @file IxPiuDlPiuMgr.c + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @description Contents are the implementation of the private API for the + * PIU Downloader PiuMgr module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/* + * Put the user defined include files required. + */ + + +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" +#include "IxPiuDlPiuMgr_p.h" +#include "IxPiuDlPiuMgrUtils_p.h" +#include "IxPiuDlPiuMgrEcRegisters_p.h" +#include "IxPiuDlMacros_p.h" + +#if defined(IX_PIUDL_READ_MICROCODE_FROM_FILE) && defined (__ep805xx) +#include "IxPiuDlFwLoader_p.h" +#endif + +/* + * #defines and macros used in this file. + */ +#define IX_PIUDL_BYTES_PER_WORD 4 + +/* used to read download map from version in microcode image */ +#define IX_PIUDL_BLOCK_TYPE_INSTRUCTION 0x00000000 +#define IX_PIUDL_BLOCK_TYPE_DATA 0x00000001 +#define IX_PIUDL_BLOCK_TYPE_STATE 0x00000002 +#define IX_PIUDL_END_OF_DOWNLOAD_MAP 0x0000000F + + + +#define IX_PIUDL_PIU0_RESET_BIT_OFFSET 4 +#define IX_PIUDL_PIU1_RESET_BIT_OFFSET 5 + + +/* + * masks used to extract address info from State information context + * register addresses as read from microcode image + */ +#define IX_PIUDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F +#define IX_PIUDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0 + +/* LSB offset of Context Number field in State-Info Context Address */ +#define IX_PIUDL_OFFSET_STATE_ADDR_CTXT_NUM 4 + +/* size (in words) of single State Information entry (ctxt reg address|data) */ +#define IX_PIUDL_STATE_INFO_ENTRY_SIZE 2 + +/* size of Co-Processor reset instruction */ +#define IX_PIUDL_CP_RESET_SIZE 16 + +/* value for Co-Processor. There is one bit for each of 16 possible + co-processors. If a co-processor does not exist, setting it's bit + to one has no effect. */ +#define IX_PIUDL_CP_RESET_VALUE 0xFFFF + + + +/* + * Typedefs whose scope is limited to this file. + */ + +typedef struct +{ + ix_uint32 type; + ix_uint32 offset; +} IxPiuDlPiuMgrDownloadMapBlockEntry; + +typedef union +{ + IxPiuDlPiuMgrDownloadMapBlockEntry block; + ix_uint32 eodmMarker; +} IxPiuDlPiuMgrDownloadMapEntry; + +typedef struct +{ + /* 1st entry in the download map (there may be more than one) */ + IxPiuDlPiuMgrDownloadMapEntry entry[1]; +} IxPiuDlPiuMgrDownloadMap; + + +/* used to access an instruction or data block in a microcode image */ +typedef struct +{ + ix_uint32 piuMemAddress; + ix_uint32 size; + ix_uint32 data[1]; +} IxPiuDlPiuMgrCodeBlock; + +/* used to access each Context Reg entry state-information block */ +typedef struct +{ + ix_uint32 addressInfo; + ix_uint32 value; +} IxPiuDlPiuMgrStateInfoCtxtRegEntry; + +/* used to access a state-information block in a microcode image */ +typedef struct +{ + ix_uint32 size; + IxPiuDlPiuMgrStateInfoCtxtRegEntry ctxtRegEntry[1]; +} IxPiuDlPiuMgrStateInfoBlock; + +/* used to store some useful PIU information for easy access */ +typedef struct +{ +#if defined(__ep805xx) + ix_uint32 physicalBaseAddress; +#endif + ix_uint32 baseAddress; + ix_uint32 insMemSize; + ix_uint32 dataMemSize; +} IxPiuDlPiuInfo; + +/* used to distinguish instruction and data memory operations */ +typedef enum +{ + IX_PIUDL_MEM_TYPE_INSTRUCTION = 0, + IX_PIUDL_MEM_TYPE_DATA +} IxPiuDlPiuMemType; + +/* used to hold a reset value for a particular ECS register */ +typedef struct +{ + ix_uint32 regAddr; + ix_uint32 regResetVal; +} IxPiuDlEcsRegResetValue; + +/* prototype of function to write either Instruction or Data memory */ +typedef ix_error (*IxPiuDlPiuMgrMemWrite) (ix_uint32 piuBaseAddress, + ix_uint32 piuMemAddress, + ix_uint32 piuMemData, + BOOL verify); + +/* module statistics counters */ +typedef struct +{ + ix_uint32 instructionBlocksLoaded; + ix_uint32 dataBlocksLoaded; + ix_uint32 instructionMemInit; + ix_uint32 dataMemInit; + ix_uint32 stateInfoBlocksLoaded; + ix_uint32 criticalPiuErrors; + ix_uint32 criticalMicrocodeErrors; + ix_uint32 piuStarts; + ix_uint32 piuStops; + ix_uint32 piuResets; +} IxPiuDlPiuMgrStats; + + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ +static IxPiuDlPiuInfo ixPiuDlPiuInfo[IX_PIUDL_PIUID_MAX] = +{ + { +#if defined(__ep805xx) + 0, +#endif + 0, + IX_PIUDL_INS_MEMSIZE_WORDS_PIU0, + IX_PIUDL_DATA_MEMSIZE_WORDS_PIU0 + } +#if !defined(__ep805xx) + , + { + 0, + IX_PIUDL_INS_MEMSIZE_WORDS_PIU1, + IX_PIUDL_DATA_MEMSIZE_WORDS_PIU1 + } +#endif +}; + +/* contains Reset values for Context Store Registers */ +static ix_uint32 ixPiuDlCtxtRegResetValues[] = +{ + IX_PIUDL_CTXT_REG_RESET_STEVT, + IX_PIUDL_CTXT_REG_RESET_STARTPC, + IX_PIUDL_CTXT_REG_RESET_REGMAP, + IX_PIUDL_CTXT_REG_RESET_CINDEX, +}; + +/* contains Reset values for Context Store Registers */ +static IxPiuDlEcsRegResetValue ixPiuDlEcsRegResetValues[] = +{ + {IX_PIUDL_ECS_BG_CTXT_REG_0, IX_PIUDL_ECS_BG_CTXT_REG_0_RESET}, + {IX_PIUDL_ECS_BG_CTXT_REG_1, IX_PIUDL_ECS_BG_CTXT_REG_1_RESET}, + {IX_PIUDL_ECS_BG_CTXT_REG_2, IX_PIUDL_ECS_BG_CTXT_REG_2_RESET}, + {IX_PIUDL_ECS_PRI_1_CTXT_REG_0, IX_PIUDL_ECS_PRI_1_CTXT_REG_0_RESET}, + {IX_PIUDL_ECS_PRI_1_CTXT_REG_1, IX_PIUDL_ECS_PRI_1_CTXT_REG_1_RESET}, + {IX_PIUDL_ECS_PRI_1_CTXT_REG_2, IX_PIUDL_ECS_PRI_1_CTXT_REG_2_RESET}, + {IX_PIUDL_ECS_PRI_2_CTXT_REG_0, IX_PIUDL_ECS_PRI_2_CTXT_REG_0_RESET}, + {IX_PIUDL_ECS_PRI_2_CTXT_REG_1, IX_PIUDL_ECS_PRI_2_CTXT_REG_1_RESET}, + {IX_PIUDL_ECS_PRI_2_CTXT_REG_2, IX_PIUDL_ECS_PRI_2_CTXT_REG_2_RESET}, + {IX_PIUDL_ECS_DBG_CTXT_REG_0, IX_PIUDL_ECS_DBG_CTXT_REG_0_RESET}, + {IX_PIUDL_ECS_DBG_CTXT_REG_1, IX_PIUDL_ECS_DBG_CTXT_REG_1_RESET}, + {IX_PIUDL_ECS_DBG_CTXT_REG_2, IX_PIUDL_ECS_DBG_CTXT_REG_2_RESET}, + {IX_PIUDL_ECS_INSTRUCT_REG, IX_PIUDL_ECS_INSTRUCT_REG_RESET} +}; + +static IxPiuDlPiuMgrStats ixPiuDlPiuMgrStats; + +/* Set when PIU register memory has been mapped */ +static BOOL ixPiuDlMemInitialised = FALSE; + + +/* + * static function prototypes. + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrMemLoad (IxPiuDlPiuId piuId, ix_uint32 piuBaseAddress, + IxPiuDlPiuMgrCodeBlock *codeBlockPtr, + BOOL verify, IxPiuDlPiuMemType piuMemType); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrMemInit (IxPiuDlPiuId piuId, ix_uint32 piuBaseAddress, + BOOL verify, IxPiuDlPiuMemType piuMemType); +PIU_PRIVATE ix_error +ixPiuDlPiuMgrStateInfoLoad (ix_uint32 piuBaseAddress, + IxPiuDlPiuMgrStateInfoBlock *codeBlockPtr, + BOOL verify); +PIU_PRIVATE BOOL +ixPiuDlPiuMgrBitsSetCheck (ix_uint32 piuBaseAddress, ix_uint32 regOffset, + ix_uint32 expectedBitsSet); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrBaseAddressGet (IxPiuDlPiuId piuId, ix_uint32* piuBaseAddressPtr); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrResetContextStores(ix_uint32 piuBaseAddress); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrAllMemInit (IxPiuDlPiuId piuId, + ix_uint32 piuBaseAddress); + +PIU_PRIVATE void +ixPiuDlPiuMgrClearFifos (ix_uint32 piuBaseAddress); + +PIU_PRIVATE ix_error +ixPiuDlPiuMgrPhyRegsReset (ix_uint32 piuBaseAddress); + +PIU_PRIVATE void +ixPiuDlPiuMgrRegistersClear (ix_uint32 piuBaseAddress); + + +/* + * Function definition: ixPiuDlPiuMgrBaseAddressGet + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrBaseAddressGet (IxPiuDlPiuId piuId, ix_uint32* piuBaseAddressPtr) +{ + ix_error status = IX_SUCCESS; + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrBaseAddressGet\n"); + if (!ixPiuDlMemInitialised) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrBaseAddressGet: " + "Memory not initialised\n"); + status = IX_FAIL; + } + else + { + *piuBaseAddressPtr = ixPiuDlPiuInfo[piuId].baseAddress; + } + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrBaseAddressGet\n"); + return status; +} + +#if defined(__ep805xx) +/* + * Function definition: ixPiuDlPiuMgrPhysicalAddressSet + */ +ix_error +ixPiuDlPiuMgrPhysicalAddressSet ( + IxPiuDlPiuId piuId, + ix_uint32 address) +{ + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPhysicalAddressSet\n"); + + if (ixPiuDlMemInitialised) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPhysicalAddressSet: " + "Cannot set physical address after memory has been initialised\n"); + return IX_FAIL; + } + else + { + ixPiuDlPiuInfo[piuId].physicalBaseAddress = address; + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPhysicalAddressSet : address = 0x%08X\n", + ixPiuDlPiuInfo[piuId].physicalBaseAddress); + } + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPhysicalAddressSet\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuDlPiuMgrAppDualSet + */ +ix_error +ixPiuDlPiuMgrAppDualSet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction ) +{ + ix_error status = IX_SUCCESS; + ix_uint32 appDualRegAddress = IX_PIUDL_APPDUAL_REG_OFFSET; + ix_uint32 appDualRegValue = 0; + ix_uint32 piuBaseAddress = 0; + ix_uint32 copr0 = appDualInstruction->copr0; + ix_uint32 inst0 = appDualInstruction->inst0; + ix_uint32 copr1 = appDualInstruction->copr1; + ix_uint32 inst1 = appDualInstruction->inst1; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrAppDualSet\n"); + + if (!ixPiuDlMemInitialised) + { + ixPiuDlPiuMgrInit(); + } + + /* Check input parameters */ + if ((appDualId > IX_PIUDL_APPDUAL_ID_MAX) || (appDualId < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid appDualId " + "parameter\n"); + } + if ((copr0 > IX_PIUDL_APPDUAL_COPR_ID_MAX) || (copr0 < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid copr0 " + "parameter\n"); + } + if ((inst0 > IX_PIUDL_APPDUAL_INST_ID_MAX) || (inst0 < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid inst0 " + "parameter\n"); + } + if ((copr1 > IX_PIUDL_APPDUAL_COPR_ID_MAX) || (copr1 < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid copr1 " + "parameter\n"); + } + if ((inst1 > IX_PIUDL_APPDUAL_INST_ID_MAX) || (inst1 < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - invalid inst1 " + "parameter\n"); + } + + if (IX_SUCCESS == status) + { + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + /* map the appDualId to the correct register address */ + appDualRegAddress += appDualId; + + /* construct the value to be written to the appDual register - + note that because the input parameters have been range checked, this + guarantees that all reserved bits in the register value are 0 */ + appDualRegValue |= copr0 << IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET; + appDualRegValue |= inst0 << IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET; + appDualRegValue |= copr1 << IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET; + appDualRegValue |= inst1 << IX_PIUDL_APPDUAL_REG_INST1_BIT_OFFSET; + + + /* to configure appDuals the PIU must be stopped */ + if (ixPiuDlPiuMgrPiuStop(piuId) != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - failed to " + "stop PIU\n"); + return IX_FAIL; + } + + /* write the register and verify */ + if (ixPiuDlPiuMgrAppDualRegWrite(piuBaseAddress, appDualRegAddress, + appDualRegValue, TRUE) != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - failed to " + "write appDual register\n"); + return IX_FAIL; + } + + /* restart the PIU */ + if (ixPiuDlPiuMgrPiuStart(piuId) != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualSet - failed to " + "restart PIU\n"); + return IX_FAIL; + } + + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrAppDualSet : status = %d\n", + status); + return status; +} + +/* + * Function definition: ixPiuDlPiuMgrAppDualGet + */ +ix_error +ixPiuDlPiuMgrAppDualGet ( + IxPiuDlPiuId piuId, + ix_uint32 appDualId, + IxPiuDlAppDualInstruction *appDualInstruction ) +{ + ix_error status = IX_SUCCESS; + ix_uint32 appDualRegAddress = IX_PIUDL_APPDUAL_REG_OFFSET; + ix_uint32 appDualRegValue = 0; + ix_uint32 piuBaseAddress = 0; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrAppDualGet\n"); + + if (!ixPiuDlMemInitialised) + { + ixPiuDlPiuMgrInit(); + } + /* Check input parameters */ + if ((appDualId > IX_PIUDL_APPDUAL_ID_MAX) || (appDualId < 0)) + { + status = IX_PIUDL_PARAM_ERR; + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrAppDualGet - invalid appDualId " + "parameter\n"); + } + + if (IX_SUCCESS == status) + { + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + /* map the appDualId to the correct register address */ + appDualRegAddress += appDualId; + + /* read the app dual register value */ + appDualRegValue = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + appDualRegAddress); + + /* extract instruction fields from the register value */ + appDualInstruction->copr0 = (appDualRegValue >> + IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET) & + IX_PIUDL_APPDUAL_COPR_ID_MAX; + appDualInstruction->inst0 = (appDualRegValue >> + IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET) & + IX_PIUDL_APPDUAL_INST_ID_MAX; + appDualInstruction->copr1 = (appDualRegValue >> + IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET) & + IX_PIUDL_APPDUAL_COPR_ID_MAX; + appDualInstruction->inst1 = (appDualRegValue >> + IX_PIUDL_APPDUAL_REG_INST1_BIT_OFFSET) & + IX_PIUDL_APPDUAL_INST_ID_MAX; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrAppDualGet : status = %d\n", + status); + return status; +} + +#endif /* #if defined(__ep805xx) */ + +/* + * Function definition: ixPiuDlPiuMgrInit + */ +void +ixPiuDlPiuMgrInit (void) +{ + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrInit\n"); + /* Only map the memory once */ + if (!ixPiuDlMemInitialised) + { + /* + * The base address is defined here because for Linux the base may be + * obtained dynamically + */ +#if defined(__ep805xx) + + /* PIU-0 register address space */ + ix_uint32 physAddr = + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].physicalBaseAddress; + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress = + (ix_uint32) ioremap (physAddr, 0x1000); + /* TODO remove printk */ + printk("PIU Virtual Address is 0x%x - Physical Address is 0x%x\n", + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress, physAddr); + +#else + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress = + (ix_uint32) IX_PIUDL_PIUBASEADDRESS_PIU0_MAP(IX_PIU_PIU0_PHYS); + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU1].baseAddress = + (ix_uint32) IX_PIUDL_PIUBASEADDRESS_PIU1_MAP(IX_PIU_PIU1_PHYS); +#endif /* #if defined(__ep805xx) */ + + ixPiuDlMemInitialised = TRUE; + } + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrInit\n"); +} + + +/* + * Function definition: ixPiuDlPiuMgrUninit + */ +ix_error +ixPiuDlPiuMgrUninit (void) +{ + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrUninit\n"); + if (!ixPiuDlMemInitialised) + { + return IX_FAIL; + } + + iounmap((void *)ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress); + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress = 0; +#if !defined(__ep805xx) + IX_PIUDL_PIUBASEADDRESS_UNMAP( + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU1].baseAddress); + ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU1].baseAddress = 0; +#endif + +#if defined(__ep805xx) && defined(IX_PIUDL_READ_MICROCODE_FROM_FILE) + ixPiuDlFwLoaderCleanup(); +#endif + + ixPiuDlMemInitialised = FALSE; + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrUninit\n"); + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuDlPiuMgrImageLoad + */ +ix_error +ixPiuDlPiuMgrImageLoad ( + IxPiuDlPiuId piuId, + ix_uint32 *imageCodePtr, + BOOL verify) +{ + ix_uint32 piuBaseAddress; + IxPiuDlPiuMgrDownloadMap *downloadMap; + ix_uint32 *blockPtr; + ix_uint32 mapIndex = 0; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrImageLoad\n"); + + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + /* check execution status of PIU to verify PIU Stop was successful */ + if (!ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, + IX_PIUDL_EXCTL_STATUS_STOP)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrImageDownload - " + "PIU was not stopped before download\n"); + status = IX_FAIL; + } + else + { + + /* + * Read Download Map, checking each block type and calling + * appropriate function to perform download + */ + downloadMap = (IxPiuDlPiuMgrDownloadMap *) imageCodePtr; + + while ((downloadMap->entry[mapIndex].eodmMarker != + IX_PIUDL_END_OF_DOWNLOAD_MAP) + && (status == IX_SUCCESS)) + { + /* calculate pointer to block to be downloaded */ + blockPtr = imageCodePtr + + downloadMap->entry[mapIndex].block.offset; + + switch (downloadMap->entry[mapIndex].block.type) + { + case IX_PIUDL_BLOCK_TYPE_INSTRUCTION: + status = ixPiuDlPiuMgrMemLoad (piuId, piuBaseAddress, + (IxPiuDlPiuMgrCodeBlock *)blockPtr, + verify, + IX_PIUDL_MEM_TYPE_INSTRUCTION); + break; + case IX_PIUDL_BLOCK_TYPE_DATA: + status = ixPiuDlPiuMgrMemLoad (piuId, piuBaseAddress, + (IxPiuDlPiuMgrCodeBlock *)blockPtr, + verify, IX_PIUDL_MEM_TYPE_DATA); + break; + case IX_PIUDL_BLOCK_TYPE_STATE: + status = ixPiuDlPiuMgrStateInfoLoad (piuBaseAddress, + (IxPiuDlPiuMgrStateInfoBlock *) blockPtr, + verify); + break; + default: + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrImageLoad: " + "unknown block type in download map\n"); + status = IX_PIUDL_CRITICAL_MICROCODE_ERR; + ixPiuDlPiuMgrStats.criticalMicrocodeErrors++; + break; + } + mapIndex++; + }/* loop: for each entry in download map, while status == SUCCESS */ + }/* condition: PIU stopped before attempting download */ + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrImageLoad : status = %u\n", + status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrMemLoad + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrMemLoad ( + IxPiuDlPiuId piuId, + ix_uint32 piuBaseAddress, + IxPiuDlPiuMgrCodeBlock *blockPtr, + BOOL verify, + IxPiuDlPiuMemType piuMemType) +{ + ix_uint32 piuMemAddress; + ix_uint32 blockSize; + ix_uint32 memSize = 0; + IxPiuDlPiuMgrMemWrite memWriteFunc = NULL; + ix_uint32 localIndex = 0; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrMemLoad\n"); + + /* + * select PIU EXCTL reg read/write commands depending on memory + * type (instruction/data) to be accessed + */ + if (piuMemType == IX_PIUDL_MEM_TYPE_INSTRUCTION) + { + memSize = ixPiuDlPiuInfo[piuId].insMemSize; + memWriteFunc = (IxPiuDlPiuMgrMemWrite) ixPiuDlPiuMgrInsMemWrite; + } + else if (piuMemType == IX_PIUDL_MEM_TYPE_DATA) + { + memSize = ixPiuDlPiuInfo[piuId].dataMemSize; + memWriteFunc = (IxPiuDlPiuMgrMemWrite) ixPiuDlPiuMgrDataMemWrite; + } + + /* + * PIU memory is loaded contiguously from each block, so only address + * of 1st word in block is needed + */ + piuMemAddress = blockPtr->piuMemAddress; + /* number of words of instruction/data microcode in block to download */ + blockSize = blockPtr->size; + + if ((piuMemAddress + blockSize) > memSize) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrMemLoad: " + "Block size too big for PIU memory\n"); + status = IX_PIUDL_CRITICAL_MICROCODE_ERR; + ixPiuDlPiuMgrStats.criticalMicrocodeErrors++; + } + else + { + for (localIndex = 0; localIndex < blockSize; localIndex++) + { + status = memWriteFunc (piuBaseAddress, piuMemAddress, + blockPtr->data[localIndex], verify); + + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrMemLoad: " + "write to PIU memory failed\n"); + status = IX_PIUDL_CRITICAL_PIU_ERR; + ixPiuDlPiuMgrStats.criticalPiuErrors++; + break; /* abort download */ + } + /* increment target (word)address in PIU memory */ + piuMemAddress++; + } + }/* condition: block size will fit in PIU memory */ + + if (status == IX_SUCCESS) + { + if (piuMemType == IX_PIUDL_MEM_TYPE_INSTRUCTION) + { + ixPiuDlPiuMgrStats.instructionBlocksLoaded++; + } + else if (piuMemType == IX_PIUDL_MEM_TYPE_DATA) + { + ixPiuDlPiuMgrStats.dataBlocksLoaded++; + } + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrMemLoad : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrStateInfoLoad + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrStateInfoLoad ( + ix_uint32 piuBaseAddress, + IxPiuDlPiuMgrStateInfoBlock *blockPtr, + BOOL verify) +{ + ix_uint32 blockSize; + ix_uint32 ctxtRegAddrInfo; + ix_uint32 ctxtRegVal; + IxPiuDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ + ix_uint32 ctxtNum; /* identifies Context number (0-16) */ + ix_uint32 i; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrStateInfoLoad\n"); + + /* block size contains number of words of state-info in block */ + blockSize = blockPtr->size; + + ixPiuDlPiuMgrDebugInstructionPreExec (piuBaseAddress); + + /* for each state-info context register entry in block */ + for (i = 0; i < (blockSize/IX_PIUDL_STATE_INFO_ENTRY_SIZE); i++) + { + /* each state-info entry is 2 words (address, value) in length */ + ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo; + ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value; + + ctxtReg = (ctxtRegAddrInfo & IX_PIUDL_MASK_STATE_ADDR_CTXT_REG); + ctxtNum = (ctxtRegAddrInfo & IX_PIUDL_MASK_STATE_ADDR_CTXT_NUM) >> + IX_PIUDL_OFFSET_STATE_ADDR_CTXT_NUM; + + /* error-check Context Register No. and Context Number values */ + /* NOTE that there is no STEVT register for Context 0 */ + if ((ctxtReg < 0) || + (ctxtReg >= IX_PIUDL_CTXT_REG_MAX) || + (ctxtNum > IX_PIUDL_CTXT_NUM_MAX) || + ((ctxtNum == 0) && (ctxtReg == IX_PIUDL_CTXT_REG_STEVT))) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrStateInfoLoad: " + "invalid Context Register Address\n"); + status = IX_PIUDL_CRITICAL_MICROCODE_ERR; + ixPiuDlPiuMgrStats.criticalMicrocodeErrors++; + break; /* abort download */ + } + + status = ixPiuDlPiuMgrCtxtRegWrite (piuBaseAddress, ctxtNum, ctxtReg, + ctxtRegVal, verify); + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrStateInfoLoad: " + "write of state-info to PIU failed\n"); + status = IX_PIUDL_CRITICAL_PIU_ERR; + ixPiuDlPiuMgrStats.criticalPiuErrors++; + break; /* abort download */ + } + }/* loop: for each context reg entry in State Info block */ + + ixPiuDlPiuMgrDebugInstructionPostExec (piuBaseAddress); + + if (status == IX_SUCCESS) + { + ixPiuDlPiuMgrStats.stateInfoBlocksLoaded++; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrStateInfoLoad : status = %u\n", + status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPiuReset + */ +ix_error +ixPiuDlPiuMgrPiuReset ( + IxPiuDlPiuId piuId) +{ + ix_uint32 piuBaseAddress; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuReset\n"); + + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + status = ixPiuDlPiuMgrAllMemInit (piuId,piuBaseAddress); + if ( status != IX_SUCCESS) + { + return status; + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG,"Interrupts unlocked\n"); + + ixPiuDlPiuMgrDebugInstructionPreExec (piuBaseAddress); + + + ixPiuDlPiuMgrClearFifos (piuBaseAddress); + + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuReset: read inFIFO step exec\n"); + + /* + * Reset the mailbox reg + */ + /* ...from XScale side */ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_MBST, + IX_PIUDL_REG_RESET_MBST); + /* ...from PIU side */ + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, + IX_PIUDL_INSTR_RESET_MBOX, 0, 0); + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG,"ixPiuDlPiuMgrPiuReset: Mail Box Reset\n"); + + /* + * Reset the PIU Co-Processors + */ + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, + 0, /*reg d0*/ + IX_PIUDL_CP_RESET_VALUE, + IX_PIUDL_CP_RESET_SIZE, + 0, /*context 0*/ + TRUE); + if (status == IX_SUCCESS) + { + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, + IX_PIUDL_INSTR_RESET_COPROCS, + 0, /*context 0*/ + 0); /*LDUR*/ + } + else + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuReset: error writing d0 with " + "IX_PIUDL_CP_RESET_VALUE for Co-Processor " + "reset\n"); + return status; /* abort reset */ + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuReset: Co-processors reset\n"); + + /* + * Take Co-Processors out of Reset + */ + if (status == IX_SUCCESS) + { + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, + 0, /*reg d0*/ + 0, /*take coprocs out of reset*/ + IX_PIUDL_CP_RESET_SIZE, + 0, /*context 0*/ + TRUE); + if (status == IX_SUCCESS) + { + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, + IX_PIUDL_INSTR_RESET_COPROCS, + 0, /*context 0*/ + 0); /*LDUR*/ + } + else + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuReset: error writing d0 " + "with 0 for Co-Processor out of reset\n"); + return status; /* abort reset */ + } + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG,"ixPiuDlPiuMgrPiuReset: Co-processors " + "taken out of reset\n"); + + + status = ixPiuDlPiuMgrPhyRegsReset (piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuReset: phy registers reset\n"); + + + status = ixPiuDlPiuMgrResetContextStores(piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + + ixPiuDlPiuMgrRegistersClear (piuBaseAddress); + + ixPiuDlPiuMgrStats.piuResets++; + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuReset : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPiuStart + */ +ix_error +ixPiuDlPiuMgrPiuStart ( + IxPiuDlPiuId piuId) +{ + ix_uint32 piuBaseAddress; + ix_uint32 ecsRegVal; + BOOL piuRunning; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuStart\n"); + + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + if (status != IX_SUCCESS) + { + return status; + } + + /* + * ensure only Background Context Stack Level is Active by turning off + * the Active bit in each of the other Executing Context Stack levels + */ + ecsRegVal = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_PRI_1_CTXT_REG_0); + ecsRegVal &= ~IX_PIUDL_MASK_ECS_REG_0_ACTIVE; + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_PRI_1_CTXT_REG_0, + ecsRegVal); + + ecsRegVal = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_PRI_2_CTXT_REG_0); + ecsRegVal &= ~IX_PIUDL_MASK_ECS_REG_0_ACTIVE; + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_PRI_2_CTXT_REG_0, + ecsRegVal); + + ecsRegVal = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_DBG_CTXT_REG_0); + ecsRegVal &= ~IX_PIUDL_MASK_ECS_REG_0_ACTIVE; + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_0, + ecsRegVal); + + /* clear the pipeline */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE); + + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuStart : about to start piu%u\n", + (unsigned)piuId); + + /* start PIU execution by issuing command through EXCTL register on PIU */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_START); + + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuStart : started piu %u\n", + (unsigned)piuId); + /* + * check execution status of PIU to verify PIU Start operation was + * successful + */ + piuRunning = ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, + IX_PIUDL_REG_OFFSET_EXCTL, + IX_PIUDL_EXCTL_STATUS_RUN); + if (piuRunning) + { + ixPiuDlPiuMgrStats.piuStarts++; + } + else + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuStart: " + "failed to start PIU execution\n"); + status = IX_FAIL; + } + + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuStart : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPiuStop + */ +ix_error +ixPiuDlPiuMgrPiuStop ( + IxPiuDlPiuId piuId) +{ + ix_uint32 piuBaseAddress; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuStop\n"); + + /* First verify that the PIU is out of reset */ + status = ixPiuDlPiuMgrPiuResetDeassert (piuId); + + if (status != IX_SUCCESS) + { + return status; + } + + /* get base memory address of PIU from piuId */ + status = ixPiuDlPiuMgrBaseAddressGet (piuId, &piuBaseAddress); + + if (status != IX_SUCCESS) + { + return status; + } + + /* stop PIU execution by issuing command through EXCTL register on PIU */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_STOP); + + /* verify that PIU Stop was successful */ + if (!ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, + IX_PIUDL_EXCTL_STATUS_STOP)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuStop: " + "failed to stop PIU execution\n"); + status = IX_FAIL; + } + + ixPiuDlPiuMgrStats.piuStops++; + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuStop : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrBitsSetCheck + */ +PIU_PRIVATE BOOL +ixPiuDlPiuMgrBitsSetCheck ( + ix_uint32 piuBaseAddress, + ix_uint32 regOffset, + ix_uint32 expectedBitsSet) +{ + ix_uint32 regVal; + IX_PIUDL_REG_READ (piuBaseAddress, regOffset, ®Val); + + return expectedBitsSet == (expectedBitsSet & regVal); +} + + +/* + * Function definition: ixPiuDlPiuMgrStatsShow + */ +void +ixPiuDlPiuMgrStatsShow (void) +{ + printf ("\nixPiuDlPiuMgrStatsShow:\n"); + + printf ("\tInstruction Blocks loaded: %u\n", + ixPiuDlPiuMgrStats.instructionBlocksLoaded); + printf ("\tData Blocks loaded: %u\n", + ixPiuDlPiuMgrStats.dataBlocksLoaded); + printf ("\tInstruction Mem Initialisations: %u\n", + ixPiuDlPiuMgrStats.instructionMemInit); + printf ("\tData Mem Initialisations: %u\n", + ixPiuDlPiuMgrStats.dataMemInit); + printf ("\tState Information Blocks loaded: %u\n", + ixPiuDlPiuMgrStats.stateInfoBlocksLoaded); + printf ("\tCritical PIU errors: %u\n", + ixPiuDlPiuMgrStats.criticalPiuErrors); + printf ("\tCritical Microcode errors: %u\n", + ixPiuDlPiuMgrStats.criticalMicrocodeErrors); + printf ("\tSuccessful PIU Starts: %u\n", + ixPiuDlPiuMgrStats.piuStarts); + printf ("\tSuccessful PIU Stops: %u\n", + ixPiuDlPiuMgrStats.piuStops); + printf ("\tSuccessful PIU Resets: %u\n", + ixPiuDlPiuMgrStats.piuResets); + + printf ("\n"); + + ixPiuDlPiuMgrUtilsStatsShow (); +} + + +/* + * Function definition: ixPiuDlPiuMgrStatsReset + */ +void +ixPiuDlPiuMgrStatsReset (void) +{ + ixPiuDlPiuMgrStats.instructionBlocksLoaded = 0; + ixPiuDlPiuMgrStats.dataBlocksLoaded = 0; + ixPiuDlPiuMgrStats.instructionMemInit = 0; + ixPiuDlPiuMgrStats.dataMemInit = 0; + ixPiuDlPiuMgrStats.stateInfoBlocksLoaded = 0; + ixPiuDlPiuMgrStats.criticalPiuErrors = 0; + ixPiuDlPiuMgrStats.criticalMicrocodeErrors = 0; + ixPiuDlPiuMgrStats.piuStarts = 0; + ixPiuDlPiuMgrStats.piuStops = 0; + ixPiuDlPiuMgrStats.piuResets = 0; + + ixPiuDlPiuMgrUtilsStatsReset (); +} + + + +/* + * Function definition: ixPiuDlPiuMgrMemInit + */ +PIU_PRIVATE ix_error +ixPiuDlPiuMgrMemInit ( + IxPiuDlPiuId piuId, + ix_uint32 piuBaseAddress, + BOOL verify, + IxPiuDlPiuMemType piuMemType) +{ + ix_uint32 piuMemAddress; + ix_uint32 memSize = 0; + IxPiuDlPiuMgrMemWrite memWriteFunc = NULL; + ix_uint32 localIndex = 0; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrMemInit\n"); + + /* + * select PIU EXCTL reg read/write commands depending on memory + * type (instruction/data) to be accessed + */ + if (piuMemType == IX_PIUDL_MEM_TYPE_INSTRUCTION) + { + memSize = ixPiuDlPiuInfo[piuId].insMemSize; + memWriteFunc = (IxPiuDlPiuMgrMemWrite) ixPiuDlPiuMgrInsMemWrite; + } + else if (piuMemType == IX_PIUDL_MEM_TYPE_DATA) + { + memSize = ixPiuDlPiuInfo[piuId].dataMemSize; + memWriteFunc = (IxPiuDlPiuMgrMemWrite) ixPiuDlPiuMgrDataMemWrite; + } + + + /* Start at address 0 */ + piuMemAddress = 0; + + for (localIndex = 0; localIndex < memSize; localIndex++) + { + status = memWriteFunc (piuBaseAddress, piuMemAddress, + 0, verify); + + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrMemLoad: " + "write to PIU memory failed\n"); + status = IX_PIUDL_CRITICAL_PIU_ERR; + ixPiuDlPiuMgrStats.criticalPiuErrors++; + break; /* abort download */ + } + /* increment target (word)address in PIU memory */ + piuMemAddress++; + + } + + /* SCR #1936 - In case of parity error, need to do one more write + * to clear it + */ + memWriteFunc (piuBaseAddress, 0, 0, verify); + + if (status == IX_SUCCESS) + { + if (piuMemType == IX_PIUDL_MEM_TYPE_INSTRUCTION) + { + ixPiuDlPiuMgrStats.instructionMemInit++; + } + else if (piuMemType == IX_PIUDL_MEM_TYPE_DATA) + { + ixPiuDlPiuMgrStats.dataMemInit++; + } + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrMemInit : status = %u\n", status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPiuResetAssert + */ +ix_error +ixPiuDlPiuMgrPiuResetAssert ( + IxPiuDlPiuId piuId) +{ + ix_uint32 resetReg = 0; + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuResetAssert\n"); + +#if !defined(__ep805xx) + IX_PIUDL_REG_READ (IXP23XX_RESET1_REG, 0, &resetReg); +#endif + if (piuId == IX_PIUDL_PIUID_PIU0) + { + resetReg &= ~(1 << IX_PIUDL_PIU0_RESET_BIT_OFFSET); + } +#if !defined(__ep805xx) + else if (piuId == IX_PIUDL_PIUID_PIU1) + { + resetReg &= ~(1 << IX_PIUDL_PIU1_RESET_BIT_OFFSET); + } +#endif + else + { + return IX_FAIL; + } +#if !defined(__ep805xx) + IX_PIUDL_REG_WRITE (IXP23XX_RESET1_REG, 0, resetReg); +#endif + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuResetAssert\n"); + return IX_SUCCESS; +} + + + + +/* + * Function definition: ixPiuDlPiuMgrPiuResetDeassert + */ +ix_error +ixPiuDlPiuMgrPiuResetDeassert (IxPiuDlPiuId piuId) +{ + ix_uint32 resetReg = 0; + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPiuResetDeassert\n"); + +#if !defined(__ep805xx) + IX_PIUDL_REG_READ (IXP23XX_RESET1_REG, 0, &resetReg); +#endif + if (piuId == IX_PIUDL_PIUID_PIU0) + { + resetReg |= 1 << IX_PIUDL_PIU0_RESET_BIT_OFFSET; + } +#if !defined(__ep805xx) + else if (piuId == IX_PIUDL_PIUID_PIU1) + { + resetReg |= 1 << IX_PIUDL_PIU1_RESET_BIT_OFFSET; + } +#endif + else + { + return IX_FAIL; + } +#if !defined(__ep805xx) + IX_PIUDL_REG_WRITE (IXP23XX_RESET1_REG, 0, resetReg); +#endif + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPiuResetDeassert\n"); + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuDlPiuMgrTriggerInterruptReset + */ +void +ixPiuDlPiuMgrTriggerInterruptReset (void) +{ +#if defined(__ep805xx) + ixPiuDlPiuMgrCommandIssue (ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU0].baseAddress, + IX_PIUDL_EXCTL_CMD_CLR_TRIGGER); +#else + ixPiuDlPiuMgrCommandIssue (ixPiuDlPiuInfo[IX_PIUDL_PIUID_PIU1].baseAddress, + IX_PIUDL_EXCTL_CMD_CLR_TRIGGER); +#endif + +} + + +ix_error +ixPiuDlPiuMgrResetContextStores(ix_uint32 piuBaseAddress) +{ + IxPiuDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ + ix_uint32 ctxtNum; /* identifies Context number (0-16) */ + ix_uint32 regVal; + ix_error status = IX_SUCCESS; + /* + * Reset the context store: + */ + for (ctxtNum = IX_PIUDL_CTXT_NUM_MIN; + ctxtNum <= IX_PIUDL_CTXT_NUM_MAX; ctxtNum++) + { + /* set each context's Context Store registers to reset values: */ + for (ctxtReg = 0; ctxtReg < IX_PIUDL_CTXT_REG_MAX; ctxtReg++) + { + /* NOTE that there is no STEVT register for Context 0 */ + if (!((ctxtNum == 0) && (ctxtReg == IX_PIUDL_CTXT_REG_STEVT))) + { + regVal = ixPiuDlCtxtRegResetValues[ctxtReg]; + status = ixPiuDlPiuMgrCtxtRegWrite (piuBaseAddress, ctxtNum, + ctxtReg, regVal, TRUE); + if (status != IX_SUCCESS) + { + return status; /* abort reset */ + } + } + } + } + return status; + +} + +ix_error +ixPiuDlPiuMgrAllMemInit (IxPiuDlPiuId piuId, + ix_uint32 piuBaseAddress) +{ + ix_error status = IX_SUCCESS; + ix_uint32 key; + + /* + * We must disable interrupts for this to succeed as there will be an + * interrupt triggered by the PIU when trying to do this + */ + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG,"Lock Interrupts\n"); + key = ixOsalIrqLock(); + + if (IX_SUCCESS != ixPiuDlPiuMgrMemInit(piuId, piuBaseAddress,FALSE, + IX_PIUDL_MEM_TYPE_INSTRUCTION)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuReset - " + "PIU Memory could not be initialised\n"); + status = IX_FAIL; + } + if (IX_SUCCESS != ixPiuDlPiuMgrMemInit(piuId, piuBaseAddress,FALSE, + IX_PIUDL_MEM_TYPE_DATA)) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPiuReset - " + "PIU Memory could not be initialised\n"); + status = IX_FAIL; + } + + ixOsalIrqUnlock(key); + return status; +} + + +void +ixPiuDlPiuMgrClearFifos (ix_uint32 piuBaseAddress) +{ + ix_uint32 regVal; + /* + * clear the FIFOs + */ + while (ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, + IX_PIUDL_REG_OFFSET_WFIFO, + IX_PIUDL_MASK_WFIFO_VALID)) + { + IX_PIUDL_TRACE1 (IX_PIUDL_DEBUG, + "Watch-point FIFO 0x%x\n", + *(ix_uint32*)(piuBaseAddress+IX_PIUDL_REG_OFFSET_WFIFO)); + /* read from the Watch-point FIFO until empty */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_WFIFO, + ®Val); + } + + IX_PIUDL_TRACE0 (IX_PIUDL_DEBUG, + "ixPiuDlPiuMgrPiuReset: Watch-point FIFO Empty\n"); + + while (ixPiuDlPiuMgrBitsSetCheck (piuBaseAddress, + IX_PIUDL_REG_OFFSET_STAT, + IX_PIUDL_MASK_STAT_IFNE)) + { + /* + * step execution of the PIU intruction to read inFIFO using + * the Debug Executing Context stack + */ + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, + IX_PIUDL_INSTR_RD_FIFO, 0, 0); + } +} + + +ix_error +ixPiuDlPiuMgrPhyRegsReset (ix_uint32 piuBaseAddress) +{ + ix_error status = IX_SUCCESS; + ix_uint32 regAddr; + /* + * Reset the physical registers in the PIU register file: + * Note: no need to save/restore REGMAP for Context 0 here + * since all Context Store regs are reset in subsequent code + */ + for (regAddr = 0; + (regAddr < IX_PIUDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL); + regAddr++) + { + /* for each physical register in the PIU reg file, write 0 : */ + status = ixPiuDlPiuMgrPhysicalRegWrite (piuBaseAddress, regAddr, + 0, TRUE); + if (status != IX_SUCCESS) + { + return status; /* abort reset */ + } + } + return status; +} + + + +void +ixPiuDlPiuMgrRegistersClear (ix_uint32 piuBaseAddress) +{ + ix_uint32 regAddr; + ix_uint32 regVal; + ix_uint32 localIndex; + ix_uint32 indexMax; + + ixPiuDlPiuMgrDebugInstructionPostExec (piuBaseAddress); + + /* write Reset values to Execution Context Stack registers */ + indexMax = sizeof (ixPiuDlEcsRegResetValues) / + sizeof (IxPiuDlEcsRegResetValue); + for (localIndex = 0; localIndex < indexMax; localIndex++) + { + regAddr = ixPiuDlEcsRegResetValues[localIndex].regAddr; + regVal = ixPiuDlEcsRegResetValues[localIndex].regResetVal; + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, regAddr, regVal); + } + + /* clear the profile counter */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_CLR_PROFILE_CNT); + + /* clear registers EXCT, AP0, AP1, AP2 and AP3 */ + for (regAddr = IX_PIUDL_REG_OFFSET_EXCT; + regAddr <= IX_PIUDL_REG_OFFSET_AP3; + regAddr += IX_PIUDL_BYTES_PER_WORD) + { + IX_PIUDL_REG_WRITE (piuBaseAddress, regAddr, 0); + } + + /* Reset the Watch-count register */ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_WC, 0); +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgrUtils.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgrUtils.c new file mode 100644 index 0000000..398c315 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlPiuMgrUtils.c @@ -0,0 +1,809 @@ +/** + * @file IxPiuDlPiuMgrUtils.c + * + * @author Intel Corporation + * @date 13 August 2003 + * + * @description Contents are the implementation of the private API for the + * PIU Downloader PiuMgr Utils module + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +/* + * Put the system defined include files required. + */ + +#include "IxPiuTypes.h" +/* + * Put the user defined include files required. + */ +#include "IxPiuDl.h" +#include "IxPiuDlPiuMgrUtils_p.h" +#include "IxPiuDlPiuMgrEcRegisters_p.h" +#include "IxPiuDlMacros_p.h" + + +/* + * #defines and macros used in this file. + */ + +/* used to bit-mask a number of bytes */ +#define IX_PIUDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF +#define IX_PIUDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF +#define IX_PIUDL_MASK_FULL_WORD 0xFFFFFFFF + +#define IX_PIUDL_BYTES_PER_WORD 4 +#define IX_PIUDL_BYTES_PER_SHORT 2 + +#define IX_PIUDL_REG_SIZE_BYTE 8 +#define IX_PIUDL_REG_SIZE_SHORT 16 +#define IX_PIUDL_REG_SIZE_WORD 32 + +/* + * Introduce extra read cycles after issuing read command to PIU + * so that we read the register after the PIU has updated it + * This is to overcome race condition between XScale and PIU + */ +#define IX_PIUDL_DELAY_READ_CYCLES 2 + +/* + * The following needed to mask off the top 3 bits in an PIU instruction word + * since the PIU instruction word is 29 bits + */ +#define IX_PIUDL_INSTRUCTION_WORD_MASK 0x1FFFFFFF + +/* + * typedefs + */ +typedef struct +{ + ix_uint32 regAddress; + ix_uint32 regSize; +} IxPiuDlCtxtRegAccessInfo; + +/* module statistics counters */ +typedef struct +{ + ix_uint32 insMemWrites; + ix_uint32 insMemWriteFails; + ix_uint32 dataMemWrites; + ix_uint32 dataMemWriteFails; + ix_uint32 ecsRegWrites; + ix_uint32 ecsRegReads; + ix_uint32 dbgInstructionExecs; + ix_uint32 contextRegWrites; + ix_uint32 physicalRegWrites; + ix_uint32 nextPcWrites; +#if defined(__ep805xx) + ix_uint32 appDualWrites; + ix_uint32 appDualWriteFails; +#endif +} IxPiuDlPiuMgrUtilsStats; + + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +/* + * contains useful address and function pointers to read/write Context Regs, + * eliminating some switch or if-else statements in places + */ +static IxPiuDlCtxtRegAccessInfo ixPiuDlCtxtRegAccInfo[IX_PIUDL_CTXT_REG_MAX] = +{ + { + IX_PIUDL_CTXT_REG_ADDR_STEVT, + IX_PIUDL_REG_SIZE_BYTE + }, + { + IX_PIUDL_CTXT_REG_ADDR_STARTPC, + IX_PIUDL_REG_SIZE_SHORT + }, + { + IX_PIUDL_CTXT_REG_ADDR_REGMAP, + IX_PIUDL_REG_SIZE_SHORT + }, + { + IX_PIUDL_CTXT_REG_ADDR_CINDEX, + IX_PIUDL_REG_SIZE_BYTE + } +}; + +static ix_uint32 ixPiuDlSavedExecCount = 0; +static ix_uint32 ixPiuDlSavedEcsDbgCtxtReg2 = 0; + +static IxPiuDlPiuMgrUtilsStats ixPiuDlPiuMgrUtilsStats; + + +/* + * static function prototypes. + */ +PIU_PRIVATE __inline__ void +ixPiuDlPiuMgrWriteCommandIssue (ix_uint32 piuBaseAddress, ix_uint32 cmd, + ix_uint32 addr, ix_uint32 data); + +PIU_PRIVATE __inline__ ix_uint32 +ixPiuDlPiuMgrReadCommandIssue (ix_uint32 piuBaseAddress, ix_uint32 cmd, + ix_uint32 addr); + +PIU_PRIVATE ix_uint32 +ixPiuDlPiuMgrLogicalRegRead (ix_uint32 piuBaseAddress, ix_uint32 regAddr, + ix_uint32 regSize, ix_uint32 ctxtNum); + +/* + * Function definition: ixPiuDlPiuMgrWriteCommandIssue + */ +PIU_PRIVATE __inline__ void +ixPiuDlPiuMgrWriteCommandIssue ( + ix_uint32 piuBaseAddress, + ix_uint32 cmd, + ix_uint32 addr, + ix_uint32 data) +{ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXDATA, data); + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXAD, addr); + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, cmd); +} + + +/* + * Function definition: ixPiuDlPiuMgrReadCommandIssue + */ +PIU_PRIVATE __inline__ ix_uint32 +ixPiuDlPiuMgrReadCommandIssue ( + ix_uint32 piuBaseAddress, + ix_uint32 cmd, + ix_uint32 addr) +{ + ix_uint32 data = 0; + int i; + + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXAD, addr); + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, cmd); + for (i = 0; i <= IX_PIUDL_DELAY_READ_CYCLES; i++) + { + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXDATA, &data); + } + + return data; +} + +/* + * Function definition: ixPiuDlPiuMgrInsMemWrite + */ +ix_error +ixPiuDlPiuMgrInsMemWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 insMemAddress, + ix_uint32 insMemData, + BOOL verify) +{ + ix_uint32 readData = 0; + + ixPiuDlPiuMgrWriteCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_WR_INS_MEM, + insMemAddress, insMemData); + if (verify) + { + /* write invalid data to this reg, so we can see if we're reading + the EXDATA register too early */ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXDATA, + ~insMemData); + + readData = ixPiuDlPiuMgrReadCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_RD_INS_MEM, + insMemAddress); + +#if defined(__ep805xx) + /* when data is read back, it has the top 3 bits set to 0 */ + insMemData &= IX_PIUDL_INSTRUCTION_WORD_MASK; + readData &= IX_PIUDL_INSTRUCTION_WORD_MASK; +#endif + + if (insMemData != readData) + { + ixPiuDlPiuMgrUtilsStats.insMemWriteFails++; + return IX_FAIL; + } + } + + ixPiuDlPiuMgrUtilsStats.insMemWrites++; + return IX_SUCCESS; +} + + +/* + * Function definition: ixPiuDlPiuMgrDataMemWrite + */ +ix_error +ixPiuDlPiuMgrDataMemWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 dataMemAddress, + ix_uint32 dataMemData, + BOOL verify) +{ + ixPiuDlPiuMgrWriteCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_WR_DATA_MEM, + dataMemAddress, dataMemData); + if (verify) + { + /* write invalid data to this reg, so we can see if we're reading + the EXDATA register too early */ + IX_PIUDL_REG_WRITE (piuBaseAddress, + IX_PIUDL_REG_OFFSET_EXDATA, + ~dataMemData); + + if (dataMemData != + ixPiuDlPiuMgrReadCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_RD_DATA_MEM, + dataMemAddress)) + { + ixPiuDlPiuMgrUtilsStats.dataMemWriteFails++; + return IX_FAIL; + } + } + + ixPiuDlPiuMgrUtilsStats.dataMemWrites++; + return IX_SUCCESS; +} + + +/* + * Function definition: ixPiuDlPiuMgrExecAccRegWrite + */ +void +ixPiuDlPiuMgrExecAccRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddress, + ix_uint32 regData) +{ + ixPiuDlPiuMgrWriteCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_WR_ECS_REG, + regAddress, regData); + ixPiuDlPiuMgrUtilsStats.ecsRegWrites++; +} + +#if defined(__ep805xx) +/* + * Function definition: ixPiuDlPiuMgrAppDualRegWrite + */ +ix_uint32 +ixPiuDlPiuMgrAppDualRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 appDualRegAddress, + ix_uint32 appDualRegData, + BOOL verify) +{ + ixPiuDlPiuMgrWriteCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_WR_ECS_REG, + appDualRegAddress, + appDualRegData); + if (verify) + { + if (appDualRegData != + ixPiuDlPiuMgrReadCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_RD_ECS_REG, + appDualRegAddress)) + { + ixPiuDlPiuMgrUtilsStats.appDualWriteFails++; + return IX_FAIL; + } + } + + ixPiuDlPiuMgrUtilsStats.appDualWrites++; + return IX_SUCCESS; +} +#endif /* #if defined(__ep805xx) */ + +/* + * Function definition: ixPiuDlPiuMgrExecAccRegRead + */ +ix_uint32 +ixPiuDlPiuMgrExecAccRegRead ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddress) +{ + ixPiuDlPiuMgrUtilsStats.ecsRegReads++; + return ixPiuDlPiuMgrReadCommandIssue (piuBaseAddress, + IX_PIUDL_EXCTL_CMD_RD_ECS_REG, + regAddress); +} + + +/* + * Function definition: ixPiuDlPiuMgrCommandIssue + */ +void +ixPiuDlPiuMgrCommandIssue ( + ix_uint32 piuBaseAddress, + ix_uint32 command) +{ + + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCTL, command); + +} + + +/* + * Function definition: ixPiuDlPiuMgrDebugInstructionPreExec + */ +void +ixPiuDlPiuMgrDebugInstructionPreExec( + ix_uint32 piuBaseAddress) +{ + /* turn off the halt bit by clearing Execution Count register. */ + /* save reg contents 1st and restore later */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCT, + &ixPiuDlSavedExecCount); + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCT, 0); + + /* ensure that IF and IE are on (temporarily), so that we don't end up + * stepping forever */ + ixPiuDlSavedEcsDbgCtxtReg2 = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_DBG_CTXT_REG_2); + + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_2, + (ixPiuDlSavedEcsDbgCtxtReg2 | + IX_PIUDL_MASK_ECS_DBG_REG_2_IF | + IX_PIUDL_MASK_ECS_DBG_REG_2_IE)); +} + + +/* + * Function definition: ixPiuDlPiuMgrDebugInstructionExec + */ +void +ixPiuDlPiuMgrDebugInstructionExec( + ix_uint32 piuBaseAddress, + ix_uint32 piuInstruction, + ix_uint32 ctxtNum, + ix_uint32 ldur) +{ + ix_uint32 ecsDbgRegVal; + ix_uint32 oldWatchcount, newWatchcount; + + /* set the Active bit, and the LDUR, in the debug level */ + ecsDbgRegVal = IX_PIUDL_MASK_ECS_REG_0_ACTIVE | + (ldur << IX_PIUDL_OFFSET_ECS_REG_0_LDUR); + + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_0, + ecsDbgRegVal); + + /* + * set CCTXT at ECS DEBUG L3 to specify in which context to execute the + * instruction, and set SELCTXT at ECS DEBUG Level to specify which context + * store to access. + * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number + */ + ecsDbgRegVal = (ctxtNum << IX_PIUDL_OFFSET_ECS_REG_1_CCTXT) | + (ctxtNum << IX_PIUDL_OFFSET_ECS_REG_1_SELCTXT); + + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_1, + ecsDbgRegVal); + + /* clear the pipeline */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE); + + /* load PIU instruction into the instruction register */ + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_INSTRUCT_REG, + piuInstruction); + + /* we need this value later to wait for completion of PIU execution step */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_WC, &oldWatchcount); + + /* issue a Step One command via the Execution Control register */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_STEP); + + /* + * force the XScale to wait until the PIU has finished execution step + * NOTE that this delay will be very small, just long enough to allow a + * single PIU instruction to complete execution + */ + do + { + /* Watch Count register increments when PIU completes an instruction */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_WC, + &newWatchcount); + } + while (newWatchcount == oldWatchcount); + + ixPiuDlPiuMgrUtilsStats.dbgInstructionExecs++; + +} + + +/* + * Function definition: ixPiuDlPiuMgrDebugInstructionPostExec + */ +void +ixPiuDlPiuMgrDebugInstructionPostExec( + ix_uint32 piuBaseAddress) +{ + /* clear active bit in debug level */ + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_0, + 0); + + /* clear the pipeline */ + ixPiuDlPiuMgrCommandIssue (piuBaseAddress, IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE); + + /* restore Execution Count register contents. */ + IX_PIUDL_REG_WRITE (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXCT, + ixPiuDlSavedExecCount); + + /* restore IF and IE bits to original values */ + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, IX_PIUDL_ECS_DBG_CTXT_REG_2, + ixPiuDlSavedEcsDbgCtxtReg2); +} + + +/* + * Function definition: ixPiuDlPiuMgrLogicalRegRead + */ +PIU_PRIVATE ix_uint32 +ixPiuDlPiuMgrLogicalRegRead ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regSize, + ix_uint32 ctxtNum) +{ + ix_uint32 regVal; + ix_uint32 piuInstruction = 0; + ix_uint32 mask = 0; + + switch (regSize) + { + case IX_PIUDL_REG_SIZE_BYTE: + piuInstruction = IX_PIUDL_INSTR_RD_REG_BYTE; + mask = IX_PIUDL_MASK_LOWER_BYTE_OF_WORD; + break; + case IX_PIUDL_REG_SIZE_SHORT: + piuInstruction = IX_PIUDL_INSTR_RD_REG_SHORT; + mask = IX_PIUDL_MASK_LOWER_SHORT_OF_WORD; + break; + case IX_PIUDL_REG_SIZE_WORD: + piuInstruction = IX_PIUDL_INSTR_RD_REG_WORD; + mask = IX_PIUDL_MASK_FULL_WORD; + break; + default: + break; + } + + /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */ + piuInstruction |= (regAddr << IX_PIUDL_OFFSET_INSTR_SRC) | + (regAddr << IX_PIUDL_OFFSET_INSTR_DEST); + + /* step execution of PIU intruction using Debug Executing Context stack */ + ixPiuDlPiuMgrDebugInstructionExec (piuBaseAddress, piuInstruction, + ctxtNum, IX_PIUDL_RD_INSTR_LDUR); + + /* read value of register from Execution Data register */ + IX_PIUDL_REG_READ (piuBaseAddress, IX_PIUDL_REG_OFFSET_EXDATA, ®Val); + + /* align value from left to right */ + regVal = (regVal >> (IX_PIUDL_REG_SIZE_WORD - regSize)) & mask; + + return regVal; +} + + +/* + * Function definition: ixPiuDlPiuMgrLogicalRegWrite + */ +ix_error +ixPiuDlPiuMgrLogicalRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regVal, + ix_uint32 regSize, + ix_uint32 ctxtNum, + BOOL verify) +{ + ix_uint32 piuInstruction = 0; + ix_uint32 mask = 0; + ix_error status = IX_SUCCESS; + + if (regSize == IX_PIUDL_REG_SIZE_WORD) + { + /* PIU register addressing is left-to-right: e.g. |d0|d1|d2|d3| */ + /* Write upper half-word (short) to |d0|d1| */ + ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, regAddr, + regVal >> IX_PIUDL_REG_SIZE_SHORT, + IX_PIUDL_REG_SIZE_SHORT, + ctxtNum, verify); + /* Write lower half-word (short) to |d2|d3| */ + ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, + regAddr + IX_PIUDL_BYTES_PER_SHORT, + regVal & IX_PIUDL_MASK_LOWER_SHORT_OF_WORD, + IX_PIUDL_REG_SIZE_SHORT, + ctxtNum, verify); + /* NOTE that we did not need the return status here from these calls. + The seperate "verify" step below allows for this */ + + } + else + { + switch (regSize) + { + case IX_PIUDL_REG_SIZE_BYTE: + piuInstruction = IX_PIUDL_INSTR_WR_REG_BYTE; + mask = IX_PIUDL_MASK_LOWER_BYTE_OF_WORD; + break; + case IX_PIUDL_REG_SIZE_SHORT: + piuInstruction = IX_PIUDL_INSTR_WR_REG_SHORT; + mask = IX_PIUDL_MASK_LOWER_SHORT_OF_WORD; + break; + default: + break; + } + /* mask out any redundant bits, so verify will work later */ + regVal &= mask; + + /* fill dest operand field of instruction with destination reg addr */ + piuInstruction |= (regAddr << IX_PIUDL_OFFSET_INSTR_DEST); + + /* fill src operand field of instruction with least-sig 5 bits of val*/ + piuInstruction |= ((regVal & IX_PIUDL_MASK_IMMED_INSTR_SRC_DATA) << + IX_PIUDL_OFFSET_INSTR_SRC); + + /* fill coprocessor field of instruction with most-sig 11 bits of val*/ + piuInstruction |= ((regVal & IX_PIUDL_MASK_IMMED_INSTR_COPROC_DATA) << + IX_PIUDL_DISPLACE_IMMED_INSTR_COPROC_DATA); + + /* step execution of PIU intruction using Debug ECS */ + ixPiuDlPiuMgrDebugInstructionExec(piuBaseAddress, piuInstruction, + ctxtNum, IX_PIUDL_WR_INSTR_LDUR); + }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */ + + if (verify) + { + if (regVal != ixPiuDlPiuMgrLogicalRegRead (piuBaseAddress, regAddr, + regSize, ctxtNum)) + { + status = IX_FAIL; + } + } + + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrPhysicalRegWrite + */ +ix_error +ixPiuDlPiuMgrPhysicalRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 regAddr, + ix_uint32 regValue, + BOOL verify) +{ + ix_error status; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrPhysicalRegWrite\n"); + +/* + * There are 32 physical registers used in an PIU. These are + * treated as 16 pairs of 32-bit registers. To write one of the pair, + * write the pair number (0-16) to the REGMAP for Context 0. Then write + * the value to register 0 or 4 in the regfile, depending on which + * register of the pair is to be written + */ + + /* + * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16) + * of physical registers to write + */ + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, + IX_PIUDL_CTXT_REG_ADDR_REGMAP, + (regAddr >> + IX_PIUDL_OFFSET_PHYS_REG_ADDR_REGMAP), + IX_PIUDL_REG_SIZE_SHORT, 0, verify); + if (status == IX_SUCCESS) + { + /* regAddr = 0 or 4 */ + regAddr = (regAddr & IX_PIUDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) * + IX_PIUDL_BYTES_PER_WORD; + + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, regAddr, regValue, + IX_PIUDL_REG_SIZE_WORD, 0, verify); + } + + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrPhysicalRegWrite: " + "error writing to physical register\n"); + } + + ixPiuDlPiuMgrUtilsStats.physicalRegWrites++; + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrPhysicalRegWrite : status = %u\n", + status); + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrCtxtRegWrite + */ +ix_error +ixPiuDlPiuMgrCtxtRegWrite ( + ix_uint32 piuBaseAddress, + ix_uint32 ctxtNum, + IxPiuDlCtxtRegNum ctxtReg, + ix_uint32 ctxtRegVal, + BOOL verify) +{ + ix_uint32 tempRegVal; + ix_uint32 ctxtRegAddr; + ix_uint32 ctxtRegSize; + ix_error status = IX_SUCCESS; + + IX_PIUDL_TRACE0 (IX_PIUDL_FN_ENTRY_EXIT, + "Entering ixPiuDlPiuMgrCtxtRegWrite\n"); + + /* + * Context 0 has no STARTPC. Instead, this value is used to set + * NextPC for Background ECS, to set where PIU starts executing code + */ + if ((ctxtNum == 0) && (ctxtReg == IX_PIUDL_CTXT_REG_STARTPC)) + { + /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */ + tempRegVal = ixPiuDlPiuMgrExecAccRegRead (piuBaseAddress, + IX_PIUDL_ECS_BG_CTXT_REG_0); + tempRegVal &= ~IX_PIUDL_MASK_ECS_REG_0_NEXTPC; + tempRegVal |= (ctxtRegVal << IX_PIUDL_OFFSET_ECS_REG_0_NEXTPC) & + IX_PIUDL_MASK_ECS_REG_0_NEXTPC; + + ixPiuDlPiuMgrExecAccRegWrite (piuBaseAddress, + IX_PIUDL_ECS_BG_CTXT_REG_0, tempRegVal); + + ixPiuDlPiuMgrUtilsStats.nextPcWrites++; + } + else + { + ctxtRegAddr = ixPiuDlCtxtRegAccInfo[ctxtReg].regAddress; + ctxtRegSize = ixPiuDlCtxtRegAccInfo[ctxtReg].regSize; + status = ixPiuDlPiuMgrLogicalRegWrite (piuBaseAddress, ctxtRegAddr, + ctxtRegVal, ctxtRegSize, + ctxtNum, verify); + if (status != IX_SUCCESS) + { + IX_PIUDL_ERROR_REPORT ("ixPiuDlPiuMgrCtxtRegWrite: " + "error writing to context store register\n"); + } + + ixPiuDlPiuMgrUtilsStats.contextRegWrites++; + } + + IX_PIUDL_TRACE1 (IX_PIUDL_FN_ENTRY_EXIT, + "Exiting ixPiuDlPiuMgrCtxtRegWrite : status = %u\n", + status); + + return status; +} + + +/* + * Function definition: ixPiuDlPiuMgrUtilsStatsShow + */ +void +ixPiuDlPiuMgrUtilsStatsShow (void) +{ + printf ("\nixPiuDlPiuMgrUtilsStatsShow:\n"); + + printf ("\tInstruction Memory writes: %u\n", + ixPiuDlPiuMgrUtilsStats.insMemWrites); + printf ("\tInstruction Memory writes failed: %u\n", + ixPiuDlPiuMgrUtilsStats.insMemWriteFails); + printf ("\tData Memory writes: %u\n", + ixPiuDlPiuMgrUtilsStats.dataMemWrites); + printf ("\tData Memory writes failed: %u\n", + ixPiuDlPiuMgrUtilsStats.dataMemWriteFails); + printf ("\tExecuting Context Stack Register writes: %u\n", + ixPiuDlPiuMgrUtilsStats.ecsRegWrites); + printf ("\tExecuting Context Stack Register reads: %u\n", + ixPiuDlPiuMgrUtilsStats.ecsRegReads); + printf ("\tPhysical Register writes: %u\n", + ixPiuDlPiuMgrUtilsStats.physicalRegWrites); + printf ("\tContext Store Register writes: %u\n", + ixPiuDlPiuMgrUtilsStats.contextRegWrites); + printf ("\tExecution Backgound Context NextPC writes: %u\n", + ixPiuDlPiuMgrUtilsStats.nextPcWrites); + printf ("\tDebug Instructions Executed: %u\n", + ixPiuDlPiuMgrUtilsStats.dbgInstructionExecs); +#if defined(__ep805xx) + printf ("\tApplication Specific Dual Instruction Writes: %u\n", + ixPiuDlPiuMgrUtilsStats.appDualWrites); + printf ("\tApplication Specific Dual Instruction Write Fails: %u\n", + ixPiuDlPiuMgrUtilsStats.appDualWriteFails); +#endif + + printf ("\n"); +} + + +/* + * Function definition: ixPiuDlPiuMgrUtilsStatsReset + */ +void +ixPiuDlPiuMgrUtilsStatsReset (void) +{ + ixPiuDlPiuMgrUtilsStats.insMemWrites = 0; + ixPiuDlPiuMgrUtilsStats.insMemWriteFails = 0; + ixPiuDlPiuMgrUtilsStats.dataMemWrites = 0; + ixPiuDlPiuMgrUtilsStats.dataMemWriteFails = 0; + ixPiuDlPiuMgrUtilsStats.ecsRegWrites = 0; + ixPiuDlPiuMgrUtilsStats.ecsRegReads = 0; + ixPiuDlPiuMgrUtilsStats.physicalRegWrites = 0; + ixPiuDlPiuMgrUtilsStats.contextRegWrites = 0; + ixPiuDlPiuMgrUtilsStats.nextPcWrites = 0; + ixPiuDlPiuMgrUtilsStats.dbgInstructionExecs = 0; +#if defined(__ep805xx) + ixPiuDlPiuMgrUtilsStats.appDualWrites = 0; + ixPiuDlPiuMgrUtilsStats.appDualWriteFails = 0; +#endif +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlSymbols.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlSymbols.c new file mode 100644 index 0000000..f5b122c --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuDlSymbols.c @@ -0,0 +1,96 @@ +/** + * @file IxPiuDlSymbols.c + * + * @description Contents are declarations of exported symbols for linux kernel + * module builds. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +#ifdef __linux + + +#include <linux/module.h> +#include <IxPiuDl.h> + +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(ixPiuDlPhysicalAddressSet); +EXPORT_SYMBOL(ixPiuDlPiuInitAndStart); +EXPORT_SYMBOL(ixPiuDlCustomImagePiuInitAndStart); +EXPORT_SYMBOL(ixPiuDlPiuStopAndReset); +EXPORT_SYMBOL(ixPiuDlUnload); +EXPORT_SYMBOL(ixPiuDlStatsShow); +EXPORT_SYMBOL(ixPiuDlStatsReset); +EXPORT_SYMBOL(ixPiuDlLoadedImageGet); +EXPORT_SYMBOL(ixPiuDlAvailableImagesListGet); +EXPORT_SYMBOL(ixPiuDlPiuMgrPiuResetAssert); +EXPORT_SYMBOL(ixPiuDlPiuMgrPiuResetDeassert); +EXPORT_SYMBOL(ixPiuDlPiuMgrTriggerInterruptReset); + +#if defined(__ep805xx) +EXPORT_SYMBOL(ixPiuDlAppDualSet); +EXPORT_SYMBOL(ixPiuDlAppDualGet); +#endif + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuMicrocode.c b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuMicrocode.c new file mode 100644 index 0000000..d45e72e --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/source/IxPiuMicrocode.c @@ -0,0 +1,2212 @@ +/** + * @date February 25, 2009 + * + * @brief IXP400 PIU Microcode Image file + * + * This file was generated by the IxPiuDlImageGen tool. + * It contains a PIU microcode image suitable for use + * with the PIU Downloader (IxPiuDl) component in the + * IXP400 Access Driver software library. + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* Need to include the following header file for the + * image #defines used in the code below + */ +#define IX_PIUFW_VERSION_ID "2_4_0" +#include "IxPiuMicrocode.h" + + +#ifndef IX_PIUDL_READ_MICROCODE_FROM_FILE +/* NOTE - Only the IxPiuDl component should reference this array */ + +const unsigned IxPiuMicrocode_array[]={ + + +/* --- PIU FIRMWARE IMAGE --- */ +#if defined(IX_PIUDL_PIUIMAGE_PIU_HSS_TOLAPAI) +/* Image Description: Common HSS Build for Tolapai platform */ +0xfeedf00d, /* Image Marker */ +0x30010000, /* Image Identifier */ +0x00002066, /* Image Size */ + +/* DOWNLOAD MAP (for Image ID: 0x30010000) */ +0x00000000, /* block type (instruction) */ +0x0000000d, /* offset to block */ +0x00000001, /* block type (data) */ +0x00000a59, /* offset to block */ +0x00000001, /* block type (data) */ +0x000014a6, /* offset to block */ +0x00000001, /* block type (data) */ +0x000014b3, /* offset to block */ +0x00000001, /* block type (data) */ +0x00001eb8, /* offset to block */ +0x00000001, /* block type (data) */ +0x00001f3c, /* offset to block */ +0x0000000f, /* end of Download Map */ + +/* instruction block */ +0x00000000, /* location in PIU memory */ +0x00000a4a, /* number of words in the block */ +0xb002be03, 0xf0007020, 0xf0007020, 0xb000000b, +0xb000000b, 0x7044000b, 0x67b8fce0, 0xb000000b, +0xb000000b, 0xb000000b, 0x804ce800, 0x900074f0, +0xb000000b, 0xb000000b, 0x7048000b, 0x6000f9a0, +0xa01c7770, 0x308c000b, 0xc014ac00, 0xb000000b, +0xa048a820, 0xb000000b, 0xd0006986, 0x9002f9fd, +0x90007400, 0xd002ffe8, 0x7044000b, 0x67b8fce0, +0xb000000b, 0xb000000b, 0xb000000b, 0x7044000b, +0x801c77f0, 0xafd0000b, 0x3080000b, 0x7048000b, +0xa07cc1f0, 0xa048c500, 0x05048210, 0x7044000b, +0x20044020, 0x45380000, 0x7044000b, 0x40004000, +0x85400000, 0xd0004000, 0xc5440000, 0xd0004000, +0xf0004200, 0x056c0000, 0x45680210, 0x7084000b, +0x7048000b, 0xa07cc1f0, 0xe040c500, 0x05048210, +0x7044000b, 0x20044020, 0x45380000, 0x7044000b, +0x40004000, 0x85400000, 0xd0004000, 0xc5440000, +0xd0004000, 0xf0004200, 0x056c0000, 0x45680210, +0xb09c000b, 0x7048000b, 0xa01cc1f0, 0xc040c400, +0x05048210, 0x7044000b, 0x20044130, 0x45380000, +0xd0004000, 0x85400000, 0xd0004000, 0xc5440000, +0xd0004000, 0xf0004200, 0x056c0000, 0x45680210, +0x3080000b, 0xb0007410, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x27bcfce0, 0x2128f840, +0xa01076a0, 0xb0007420, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e70, 0x47b8fca0, 0x0124f9b0, +0x000077f0, 0x90007430, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e70, 0x47b8fca0, 0xc0dcf9d0, +0x20007710, 0xb0007440, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x67b8fce0, 0x4000f800, +0x801c77f0, 0x90007450, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e70, 0x67b8fcd0, 0x80b8f920, +0xc0147700, 0x90007460, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e10, 0x67b8fcb0, 0x40acf9b0, +0x00007790, 0xb0007470, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x47b8fcc0, 0xe0b0f810, +0x20007780, 0xb0007480, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x039cfc60, 0xc13cf910, +0xa01c7780, 0x90007490, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e00, 0x67b8fce0, 0x4000f800, +0x801c77f0, 0x900074a0, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e20, 0xa4a0fc20, 0x2068f8d0, +0x801c7730, 0xb00074b0, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e20, 0xa4a0fc10, 0x2064f9f0, +0xa01c7720, 0x900074c0, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e20, 0x84a0fc00, 0x0068f9b0, +0xe0147600, 0xb00074d0, 0xb000000b, 0xb000000b, +0xb000000b, 0x704c7e30, 0x4398fc50, 0xe02cf930, +0xa01c7710, 0xb00074e0, 0xb000000b, 0xb000000b, +0xb000000b, 0x504c7e20, 0x6398fc40, 0xc02cf860, +0x801c7700, 0x900074f0, 0xb000000b, 0xb000000b, +0xb000000b, 0x4fa04030, 0xf0007e00, 0xa9444010, +0xe92c4020, 0x093c4830, 0x7044000b, 0x000441e0, +0xc9280000, 0xd0007e10, 0xa9444010, 0xe92c4020, +0xa9284040, 0x293c4820, 0xd0007e20, 0xa9444010, +0xe92c4020, 0x293c4820, 0x7044000b, 0x60004160, +0xc9280000, 0xf0007e30, 0xa9444010, 0xe92c4020, +0x293c4820, 0x7044000b, 0x20044080, 0xc9280000, +0xd0007e40, 0xa9444010, 0xe92c4020, 0x293c4820, +0x89284000, 0xf0007e50, 0xa9444010, 0xe92c4020, +0x293c4820, 0x7044000b, 0x40004120, 0xc9280000, +0xf0007e60, 0xa9444010, 0xe92c4020, 0x293c4820, +0x7044000b, 0x20044040, 0xc9280000, 0xd0007e70, +0xa9444010, 0xe92c4020, 0x093c4830, 0x7044000b, +0x20044160, 0xc9280000, 0x7044000b, 0x200441f0, +0x89400000, 0x90005c00, 0x68701ce0, 0xb000000b, +0xb000000b, 0xb0005e00, 0x28181ef0, 0xe80c1ef0, +0xd000d000, 0x081c9090, 0x08109090, 0x9000d980, +0xe83c98d0, 0xa83898d0, 0x9000d800, 0x7044000b, +0x600c71f0, 0xe83c98d0, 0x7044000b, 0x600c71f0, +0xa83898d0, 0xd000d180, 0x081c9090, 0x08109090, +0x9000d800, 0xd0007180, 0xe83c98d0, 0xd0007180, +0xa83898d0, 0xb0005e11, 0xb0005e27, 0xb002f9e7, +0x7044000b, 0xc020d000, 0x9000d800, 0xd0005580, +0x081c9090, 0x08109090, 0xd000d011, 0xe83c98d0, +0xa83898d0, 0xd0005412, 0xb002f9fa, 0x90005c11, +0x90005c47, 0x9002f9d5, 0x308c000b, 0x403c8000, +0x10487e20, 0x4398fc30, 0x80107700, 0xb0033e4d, +0x6848ac20, 0x7048000b, 0x6004d880, 0x0af0c180, +0xb0003160, 0xd00080d1, 0x90018c1b, 0x90006e13, +0x90003170, 0xd0004c21, 0x90019a1c, 0xd0012414, +0x70449010, 0x6a6cc500, 0xf0018420, 0x9001951c, +0xf0006650, 0xf0006612, 0xd002b61f, 0xd000c800, +0xf0000ac0, 0x9000da4a, 0x9000da4a, 0xb0019511, +0xb001ab91, 0xf000641a, 0xb002fbf7, 0xf000c81a, +0xb0008831, 0xf0018840, 0xd000e000, 0xf0002340, +0x9000a0b1, 0xd00129d0, 0xd000e000, 0xd0002350, +0x9000a0b1, 0xf0012bd0, 0xd000e000, 0xd0002360, +0x9000a0b1, 0x90012dd0, 0xd000e000, 0xf0002370, +0x9000a0b1, 0x70452fd0, 0x90008871, 0xd001ea40, +0xd002ffe1, 0x9002be1c, 0x6848ac20, 0x7048000b, +0x6004e900, 0xca14c180, 0xb0003160, 0xd0008151, +0xf0018415, 0x90006e13, 0x90003170, 0x90004421, +0x90018017, 0x90007620, 0x9002be2f, 0x6848ac20, +0x7048000b, 0x6004e900, 0xca14c180, 0xb0003160, +0xd0008151, 0xf0018415, 0x90006e13, 0x90003170, +0x90004421, 0x90018018, 0xb0007630, 0xb002be22, +0xd002ffb4, 0x6848ac20, 0x7048000b, 0x6004e900, +0xca14c180, 0xb0003160, 0xd0008151, 0xf0018415, +0x90006e13, 0x90003170, 0x90004421, 0xb001201f, +0xf0006600, 0xb0006007, 0xd002b60e, 0x5045661f, +0x6a6cd100, 0x9001aa80, 0xb000000b, 0xb001ec80, +0xd001e881, 0x7044d810, 0xaa2cd480, 0xd001d8a0, +0x68702d60, 0xe804000b, 0xf0007e00, 0xa010000b, +0xb0018016, 0x50887610, 0xe028000b, 0x60a8000b, +0x7084000b, 0xb000c007, 0xf002b6b7, 0x70452e00, +0x6a6cc900, 0xf0018840, 0x90006c00, 0xf000ec1a, +0xb0008971, 0xf0018840, 0xd001ac1d, 0xb0008831, +0xb0006c07, 0xf002b933, 0xf0010c1f, 0xd0019009, +0xf001141c, 0xb0006e17, 0xf002bb0b, 0x2241a600, +0xf0005407, 0xf002b891, 0xb0006e17, 0xf002b708, +0xf000d007, 0xf002b6b4, 0xb0000e60, 0xb0005007, +0x1046b803, 0x90000e97, 0x50440e9e, 0x40046140, +0xb0000f07, 0xe9e80f0e, 0x9001201e, 0x09a9ae04, +0xb0006007, 0xa23c000b, 0x897dee04, 0x09073602, +0xb0033e69, 0xd0019009, 0xd0005400, 0x2241a600, +0xf000d057, 0xf002ba12, 0x1200a220, 0xd000d042, +0xf0004e42, 0x9001d009, 0xb00029f0, 0xf0007ec0, +0xd0007050, 0xb000000b, 0xb0028c2f, 0xb0003f40, +0x0221c744, 0xd0004c42, 0xf002b650, 0x90000e70, +0x9002f7de, 0xf000d057, 0xf002fdf0, 0xe2045212, +0x1200a220, 0xf0004e42, 0xd00070f0, 0xb000000b, +0x02d8aa20, 0xd000d000, 0xf0006af3, 0xb0002950, +0xf000682a, 0x9001d009, 0xb0000d47, 0xd002ba07, +0xb0003150, 0x0221c744, 0xb0000d42, 0xd002b87e, +0xb0018004, 0xe23effb0, 0x0221c744, 0xf0006a12, +0xf0005440, 0xd0004c42, 0xd002b607, 0x0221c744, +0xd0004c42, 0x6221fe0c, 0xb001541c, 0xb0018004, +0xc23effa5, 0x6221fe0c, 0xf0006a12, 0xf002b603, +0x4221fe10, 0xd0005441, 0xb001541c, 0xb0018004, +0xe23eff9d, 0xb0003f40, 0xb000000b, 0xb000000b, +0x02d8aa20, 0xb000000b, 0xf0006af3, 0xd0006a37, +0x9002bc0a, 0xd0004c42, 0x0221c744, 0xd002b613, +0x0221c744, 0xd0004c42, 0xf002b618, 0x90000e70, +0x9002f7a6, 0xd002ffb7, 0xd0004c42, 0x0221c744, +0xd002b60e, 0x0221c744, 0xd0004c42, 0xd002b607, +0x0221c744, 0xd0004c42, 0xf002b60c, 0x90000e70, +0x9002f79a, 0xf002ffab, 0x6221fe0c, 0xd0005441, +0xb001541c, 0xb002be05, 0x6221fe0c, 0x4221fe10, +0xd0005481, 0xb001541c, 0xb001aa09, 0xf000e200, +0x90002670, 0xd000ab12, 0xf001ea09, 0xb0018004, +0xc23eff71, 0x2241a600, 0xb000000b, 0xd0019009, +0x9000d800, 0x90001a70, 0x5208a220, 0xd0007050, +0xb000000b, 0x022dc744, 0xf0004e42, 0x9002f9fb, +0x90000cd2, 0xf002b605, 0x900090d2, 0x9001d009, +0x9002f97a, 0x9002be2c, 0x900090d2, 0x9001d009, +0xb0018004, 0xc23eff5c, 0xb001aa1b, 0xd001a21c, +0xf001eb51, 0xd0004c42, 0xf002b60a, 0xd0005442, +0xf002b605, 0xb001e351, 0xd0004c42, 0xf002b605, +0xd0005442, 0xb001541c, 0xb0012e1b, 0xd002ff63, +0xd0005442, 0xb001541c, 0xb001e21b, 0xb0018004, +0xe23eff49, 0x108872f7, 0x1046b80a, 0x200c7710, +0xb000000b, 0x90030201, 0x7044000b, 0x000c7700, +0xb0030001, 0x10447e20, 0x80107700, 0x885b7f1d, +0x801c7700, 0xf00072d7, 0xf002b603, 0x2030000b, +0x108b7efe, 0xe0b4000b, 0x7044000b, 0xa01c7710, +0x708f7f07, 0x9001a803, 0xb0012c1a, 0xd0006811, +0xd001e803, 0x9001980f, 0xb000000b, 0x9000d811, +0xd002b602, 0xd001d80f, 0x9001101e, 0x50445210, +0xa528e080, 0x50445017, 0xa528e09e, 0xf00153d0, +0x90006c27, 0xd002b67c, 0x90002b47, 0xf002b622, +0xb0019a0a, 0xd0012601, 0xa9e86480, 0xf000d200, +0x70441740, 0x90001733, 0xb000d44a, 0xd0009a91, +0x09a89ad0, 0x293c6e30, 0xb000000b, 0xa23c000b, +0x49073e01, 0x093c6e20, 0x49309a20, 0x0930a220, +0xb001dc07, 0x9001dc09, 0xb0000e60, 0xb0005c07, +0x1046b803, 0x90000ef7, 0x50440efe, 0x00046940, +0x90000f47, 0xc9e80f4e, 0x69a8a310, 0x9001201e, +0xb000000b, 0xb0006007, 0x897dee04, 0x6907772a, +0xf0037f91, 0x90006220, 0xf0005810, 0x9001201e, +0x9001581b, 0xb0006007, 0xd002b626, 0x90012e04, +0xb0012c15, 0x90006e07, 0xd002b809, 0xb0006227, +0xf002b807, 0x9001a803, 0x90006220, 0xf001621b, +0xd0006812, 0x90016806, 0xf002ffce, 0xf0002160, +0xd0002360, 0xd000a510, 0xe208a310, 0xd0007050, +0xb000000b, 0x022dc744, 0xd0004c42, 0x9002f9fb, +0xa23c000b, 0xb0018004, 0xc23efee3, 0x9001a803, +0xd001a219, 0x90002b47, 0xd002b604, 0xd0005a20, +0xb0015a1b, 0xd002ffbb, 0x2241a600, 0x9001201e, +0x90006210, 0xd0005400, 0xb0006007, 0x9002f9dc, +0xa2f0000b, 0xd00070a0, 0xb000000b, 0x02d8aa20, +0x0221c744, 0xd0006a23, 0xd002b805, 0xd0004c42, +0x9002f9f8, 0xb0018004, 0xc23efecb, 0xd0004c42, +0xf002b603, 0x0221c744, 0xd002fff9, 0x6221fe0c, +0xd0005441, 0xb001541c, 0xb0018004, 0xc23efec2, +0x90006c17, 0xf002b816, 0x2241a600, 0x9001a80a, +0xd000ec00, 0x02d4ab50, 0xd0012403, 0x9000d800, +0x42142520, 0xd001d809, 0x90015a1c, 0x6270ec10, +0x5049ec1d, 0xca2ce000, 0x40086c60, 0xd0002ff0, +0xd0016cc0, 0x90012c00, 0xf0007e00, 0xe0116cc1, +0xb0003f70, 0xf0010c1f, 0xd002ffd1, 0xb0006e27, +0x9002f6b6, 0x90006c00, 0xb0006e00, 0x5049ec1d, +0xea2ce040, 0x60086c70, 0xd0002ff0, 0xd0016cc0, +0x90012c00, 0xf0007e00, 0xe0116cc1, 0xb0003f70, +0xb0018004, 0xe23efe9c, 0x68408c20, 0x7048000b, +0x6004c080, 0x4af0c980, 0x90003060, 0x90008811, +0x90019a5b, 0xb001aa5a, 0xd0004e13, 0xb0003070, +0xd0006821, 0xb0003070, 0x90006c21, 0x30450c54, +0x4a6cc540, 0xf0018420, 0xf0004c07, 0xf002b627, +0xf000d200, 0xd0008030, 0xf00012c0, 0x900016d0, +0xd000d21a, 0xb0009211, 0xf0019080, 0x900194a0, +0xb000000b, 0xb0009351, 0xd001a280, 0xf0004c1a, +0xd002ba02, 0x9001e350, 0xd000c841, 0xf001a2a0, +0xf0004c1a, 0xd002ba02, 0x9001e350, 0xf000d200, +0xd00012e0, 0xb00016f0, 0xd000d21a, 0xb0009211, +0xf0019080, 0x900194a0, 0xb000000b, 0xb0009351, +0xd000c841, 0xd001a280, 0xf0004c1a, 0xd002ba02, +0x9001e350, 0xd000c841, 0xf001a2a0, 0xf0004c1a, +0xd002ba02, 0x9001e350, 0xb002be1e, 0x2840ac20, +0x7048000b, 0x6004e900, 0xca14c180, 0xb0003160, +0xd0008151, 0xd0018414, 0x90006e13, 0x90003170, +0x90004421, 0xb001801a, 0xb0007650, 0x90944c50, +0xb002be56, 0x2840ac20, 0x7048000b, 0x6004e900, +0xca14c180, 0xb0003160, 0xd0008151, 0xd0018414, +0x90006e13, 0x90003170, 0x90004421, 0x5045801b, +0x20007660, 0x90984c60, 0xb002be48, 0xf002ffab, +0x2840ac20, 0x10487e10, 0x6004e900, 0xca14c180, +0xb0003160, 0xd0008151, 0xd0018414, 0x90006e13, +0x90003170, 0x90004421, 0xd001a21f, 0x90005000, +0xf0002124, 0xd002b619, 0xd0006417, 0xf002b810, +0xb0006212, 0xf001621d, 0xd002b814, 0x7044d810, +0x8a2cd4a0, 0xd001d8a0, 0xf0007e00, 0xa010000b, +0x1045501e, 0x4a6cd140, 0x9001aa80, 0xd0007e10, +0xb001ec80, 0xd001e881, 0x9002be08, 0x68702d60, +0xf001501c, 0xb0005010, 0xd001501e, 0xb0005020, +0xd001501d, 0xe864000b, 0xf0028402, 0xb002be0a, +0x7044000b, 0x2530e500, 0xb001a8fd, 0xd001a0fc, +0xf0009550, 0xf0009512, 0xb000d517, 0xd002ba02, +0x6038000b, 0x10447e10, 0xa52ce500, 0xb001a8fd, +0xb000000b, 0xd0028602, 0x9002be07, 0xd001a0fc, +0xf0009550, 0xf0009512, 0xb000d517, 0xd002ba02, +0x203c000b, 0x7088000b, 0xa010000b, 0xe014000b, +0xb0018019, 0x90007640, 0xf0904c40, 0xb002be03, +0x90018005, 0xb000000b, 0xb000c007, 0xf002b68b, +0xf001ac1c, 0x7044000b, 0xe020ec07, 0xf002b91e, +0x6245a600, 0x70452e00, 0x4a6cc940, 0xf0018840, +0x90006c00, 0xf000ec1a, 0x30808971, 0xf0018840, +0x9001201e, 0xb0008831, 0x90006017, 0xd002b689, +0xb0a282c9, 0xd0010e1f, 0xf002902a, 0xb0003e60, +0xd0005400, 0x29a9ae00, 0xd001901b, 0x82358744, +0xf0004e42, 0x89e85441, 0xf0011a05, 0xd0005800, +0xd0007e80, 0xd0007030, 0xb000000b, 0xd092903f, +0xb000000b, 0xa26ca020, 0xb000000b, 0xf000e073, +0xf000e007, 0xf002b614, 0xb0003e60, 0x1204aa20, +0xd000d042, 0xd002bb78, 0x5045d01b, 0x20085407, +0xf002b605, 0xd0004e07, 0x9002f9e9, 0xf0005407, +0xd002b607, 0x227c000b, 0xa97dee00, 0x49073e01, +0x6245a600, 0xd0004e07, 0xb002f9de, 0xb0003e60, +0x627effc4, 0xb0003e60, 0x89e85442, 0xf002fff2, +0xf0011614, 0xb000000b, 0xf0005617, 0xd002b604, +0x9002beb6, 0xf0004e42, 0x9002f7f5, 0x82358744, +0xf0011a05, 0xd0005800, 0xd0007e40, 0xd0007060, +0xb000000b, 0xa26ca020, 0xb000000b, 0xf000e073, +0xf000e007, 0xb002f7f4, 0xb0003e60, 0xa9e85440, +0x29a9ae00, 0xd0007e80, 0xd0019006, 0xf0004e42, +0xd002900a, 0xb0003e60, 0x1204aa20, 0xd000d042, +0x9001d01b, 0xd0004e07, 0xb002f9bd, 0x227c000b, +0xa97dee00, 0x09077f9f, 0xd0007e80, 0xe26ca420, +0x9002b14f, 0xb0003e60, 0xd001a006, 0x1204aa20, +0xb000e473, 0x42249132, 0xf002bb3b, 0x6904a092, +0x9000a0d2, 0x9001e01b, 0x027f3e79, 0x093c6e20, +0x3080000b, 0x455caa20, 0xb000000b, 0xf0006886, +0xd002b91a, 0x9001aa1a, 0xa510a020, 0xf0005600, +0x6551eac0, 0xd0012418, 0xb0003e60, 0xf0006407, +0xf002b606, 0xb001980e, 0xb000000b, 0x9000d811, +0xd002b602, 0xf001d80e, 0xb0015614, 0xd0004e07, +0xb002f77c, 0xf0006407, 0xb002f77a, 0x9002be73, +0x7044000b, 0xa01c7720, 0x203b7f15, 0x7044000b, +0x801c7730, 0x603f7f20, 0x30882190, 0x900060b7, +0xb002f7f8, 0xb00060a7, 0x9002f7f9, 0x7044000b, +0x200c7720, 0xf0030401, 0x7044000b, 0x000c7730, +0xd0030601, 0x7044000b, 0xe0147600, 0xe8537f20, +0x7084000b, 0xd0010e1f, 0xf0019008, 0x9002823e, +0xb0003e60, 0xf000d007, 0xd002b651, 0x29a9ae00, +0x6245a600, 0x9000d400, 0x50481670, 0x00085607, +0x0008560e, 0x90005017, 0x9002bc03, 0x90001697, +0x9000169e, 0xc9e816b0, 0xb0000eb2, 0x900090b2, +0xf00057ea, 0x82398744, 0xd0007030, 0xb000000b, +0xf0005612, 0x520caa20, 0x9002f9fb, 0x227dd008, +0xa97dee00, 0x49073e01, 0xf0019008, 0xb000000b, +0xf000d007, 0xd002b62a, 0xd0004e07, 0xb002f9e2, +0x90018005, 0xd002ff41, 0x69a9be00, 0xd001901b, +0xf002ffdf, 0x093c6e20, 0x7084000b, 0x455caa20, +0xb000000b, 0xf0006886, 0xd002b8ac, 0xa510a020, +0x9001aa1a, 0xb000000b, 0x6551eac0, 0xb0003e60, +0xb001980e, 0xb000000b, 0x9000d811, 0xd002b602, +0xf001d80e, 0x90006000, 0xd0016014, 0xd000d000, +0xf001ac1c, 0xb001d008, 0xb0006c07, 0x9002f9e3, +0xd002ff24, 0x90012014, 0xb0019a18, 0xb0006007, +0xf002b605, 0xd001da08, 0xd001901b, 0x90005000, +0xb001d008, 0xb0003e60, 0xf002ff1a, 0x49a9be08, +0xb000000b, 0xd0012800, 0xf0012a1d, 0xd001ac1b, +0xd001241e, 0xc920ab50, 0x89e85640, 0x293c6e30, +0x29046407, 0xb00379d4, 0xd0037f7d, 0x10447e10, +0x2530e500, 0xb000000b, 0xb000000b, 0xf002842c, +0xb0003e60, 0x9002be07, 0x10447e10, 0xa52ce500, +0xb000000b, 0xb000000b, 0xd0028625, 0xb0003e60, +0xd001a0fc, 0xb001a8fd, 0xd00190e1, 0xb0019afc, +0xf000a917, 0xd002b646, 0xd000d012, 0xb000ea00, +0x5044ad10, 0x9000ac93, 0xf000ec4a, 0xf0009b51, +0xd000e011, 0x9001e0fc, 0x293c6e30, 0xe9e86310, +0x09a89ad0, 0x49073e01, 0x093c6e20, 0x4930aa20, +0x4930aa20, 0x90006000, 0xf001ea18, 0xd001ea08, +0x4930aa20, 0x4930aa20, 0xd001601d, 0xd001ea1a, +0xd001241e, 0xb0006010, 0xd0016014, 0xf0006407, +0x9002f9a2, 0x6245a600, 0xf002ff25, 0xa2503e60, +0x427efedc, 0x90006e07, 0x9002f6da, 0xb0006e17, +0xd002b812, 0x6245a600, 0xd001a00a, 0x9000e400, +0x6278a310, 0xc255a602, 0xb0006c10, 0xb0006e00, +0xa251ec1c, 0x7048000b, 0xaa2ce420, 0x40086c60, +0xf0016ce0, 0x90012c00, 0xf0007e00, 0xc0116ce1, +0xb0003e60, 0x427efec7, 0x90006c00, 0xb0006e00, +0xb001ec1c, 0x7048000b, 0x8a2ce460, 0x60086c70, +0xf0016ce0, 0x90012c00, 0xf0007e00, 0xc0116ce1, +0x90011014, 0xb0003e60, 0x90005017, 0xb002f8b9, +0xb0006010, 0xd001601d, 0xf002ff9d, 0xd001281e, +0xb000000b, 0xd0006817, 0xf002b614, 0x7044000b, +0xa520e5a0, 0xf00162e1, 0x900122e0, 0xb000000b, +0xb0006211, 0x104562e0, 0x8520e400, 0xf001a0e0, +0x7044000b, 0x4000e044, 0xb001e0e0, 0xd00023f0, +0xf0007e00, 0x8010a000, 0xb0003f10, 0x7084000b, +0xe014000b, 0xf002ffc2, 0x7044000b, 0x8520e580, +0xf00162e1, 0x900122e0, 0xb000000b, 0xb0006211, +0x104562e0, 0x8520e400, 0xf001a0e0, 0x7044000b, +0x4000e084, 0xb001e0e0, 0xd00023f0, 0xf0007e00, +0x8010a000, 0xb0003f10, 0x7084000b, 0xa010000b, +0xb0003e60, 0xf002fe8b, 0x7044000b, 0x8520e540, +0xf00162e1, 0x900122e0, 0xb000000b, 0xb0006211, +0x104562e0, 0x8520e400, 0xf001a0e0, 0x7044000b, +0x4000e024, 0xb001e0e0, 0xd00023f0, 0xf0007e00, +0x8010a000, 0xb0003f10, 0x7084000b, 0x60a8000b, +0xb0003e60, 0xb0019a18, 0xd001901b, 0xd001da08, +0xb001d008, 0xd002fe73, 0x7044000b, 0xa520e560, +0xf00162e1, 0x900122e0, 0xb000000b, 0xb0006211, +0x104562e0, 0x8520e400, 0xf001a0e0, 0x7044000b, +0x4000e014, 0xb001e0e0, 0xd00023f0, 0xf0007e00, +0x8010a000, 0xb0003f10, 0x3080000b, 0x60a8000b, +0xb0003e60, 0xb0019a18, 0xb000000b, 0xd001da08, +0xf002fe5c, 0xd0007e80, 0x7044000b, 0xc528e4c0, +0xf0012a00, 0xd001ace4, 0x90016ae0, 0xd000ec11, +0x9001980c, 0x9001ece4, 0x9000d811, 0xd002b602, +0xd001d80c, 0x02269022, 0xa252be21, 0xa26cac20, +0x30452a00, 0xc528e4c0, 0x90016ae0, 0x62246ce3, +0x62246c26, 0xf002b813, 0xb0006c46, 0xd002b809, +0xf001ace5, 0xb001980d, 0xd000ec11, 0xb001ece5, +0x9000d811, 0xf002b612, 0xf001d80d, 0x9002be10, +0xf001ace3, 0xb001980b, 0xd000ec11, 0xb001ece3, +0x9000d811, 0xf002b60a, 0xf001d80b, 0x9002be08, +0xd001ace2, 0xb001980b, 0xd000ec11, 0x9001ece2, +0x9000d811, 0xd002b602, 0xf001d80b, 0xb0003e60, +0xa9e86a00, 0x6904000b, 0xb0019a18, 0xd0004e07, +0xd001da08, 0xb002f867, 0x427efe26, 0xf00007b0, +0x304405f0, 0x2530c100, 0xf0004f20, 0xd0004c00, +0xb002be06, 0xf00007b0, 0x304405f0, 0xa52cc100, +0xd0004e20, 0xd0004c00, 0x9001aa1f, 0xb0019801, +0x9000ad52, 0x9000acd7, 0x9002bc30, 0xd0004c00, +0xe5149c20, 0xa510a020, 0xb00088d0, 0xb0008972, +0x7044a0f2, 0xe07ce1f3, 0xd000e1ea, 0xb0008917, +0x7044891e, 0x40087790, 0x10833e01, 0x3080000b, +0xa9e86840, 0x90003e20, 0xe514a020, 0xf000d200, +0xb001941f, 0xb001a401, 0xb0019a1d, 0x9000e412, +0xf0009533, 0x5080d22a, 0x09a89a91, 0xa921a6c0, +0xb0007600, 0x49073e01, 0x6961901f, 0x90003e20, +0xc54cd011, 0xb001d01f, 0xd000c812, 0x9002f9ec, +0xd0019000, 0xf0005410, 0xb0015590, 0xe0489020, +0xb000000b, 0xd0001273, 0xf002b606, 0x055c9220, +0xb000000b, 0xb0005043, 0xf002b802, 0xe0b4000b, +0xf0003630, 0xf0037fcd, 0xd0004c17, 0xb00377cb, +0xb001a802, 0x9001a403, 0xd000e000, 0xf001a0e0, +0xb000000b, 0xd000e011, 0x7045e0e0, 0xa520e420, +0xf001a0e0, 0xb000000b, 0x9000a154, 0xb001e0e0, +0xd00023f0, 0xf0007e00, 0x8010a000, 0xb0003f10, +0xf0004c10, 0xf0037fb9, 0x30487e00, 0xc0147700, +0x8528e0c0, 0x2051a6cc, 0x10447e70, 0x8528e0c0, +0x504d8ada, 0xc010c400, 0x4538c000, 0x00007670, +0xb000ea00, 0x9000ac30, 0xf000ed27, 0xc9e86f2e, +0x69a88a50, 0x69048b51, 0x90033e01, 0xc948a220, +0x09309220, 0xd000c442, 0x50455607, 0x6008c0c1, +0x70455407, 0x6008c0c1, 0x10455207, 0x6008c0c1, +0x30455007, 0x6008c0c1, 0xd0006442, 0xb002f9f5, +0x90008430, 0xb002f9eb, 0x7044000b, 0x6530c900, +0x69a9a648, 0xe9e85080, 0x49073e01, 0x0930a220, +0x49309a20, 0xf001e45d, 0x7045dc5e, 0xe52cc900, +0x69a9a648, 0xe9e85080, 0x49073e01, 0x0930a220, +0x49309a20, 0xf001e45d, 0xb001dc5e, 0x7044000b, +0x8528e0c0, 0x9000e800, 0x9001a4de, 0xd001e8de, +0xf001e4dc, 0x30498adb, 0xc010c400, 0x4538c000, +0xb000ea00, 0x9000d920, 0x9000ac30, 0x9000acd7, +0xa9e82ede, 0x69a88a50, 0xb0008b51, 0x30451606, +0x6008c0c1, 0x10451406, 0x6008c0c1, 0x70451206, +0x6008c0c1, 0x50451006, 0x6008c0c1, 0xa9209290, +0xd000c442, 0xd000ec42, 0xb002f9f5, 0x49048430, +0x900379ec, 0x90033e01, 0x10446800, 0x8528e0c0, +0xf00124df, 0xb00168df, 0x900164db, 0xf000e200, +0x7044da00, 0x6530c900, 0x49a9a64c, 0xe9e85080, +0xd0019c5c, 0x9001a45f, 0xc9209ad0, 0xa920a310, +0x49073e01, 0x10446800, 0x8528e0c0, 0xd00124de, +0x900168de, 0xb00164da, 0xf000e200, 0x7044da00, +0xe52cc900, 0x49a9a64c, 0xe9e85080, 0xd0019c5c, +0x9001a45f, 0xc9209ad0, 0xa920a310, 0x49073e01, +0x7044000b, 0x8528e0c0, 0xf00192dd, 0xb0019ade, +0xb000000b, 0xf0009a93, 0xf002b605, 0x2fc86410, +0xf000d200, 0x9001d2dc, 0xb002be0a, 0xd000d207, +0xd002b608, 0x104992dc, 0x0000d800, 0x6030dd00, +0xf000d211, 0xb00092d7, 0xf002fdf5, 0x9001d2dc, +0x7044000b, 0xc0147700, 0xf0037f7c, 0xb002beca, +0x9002becb, 0x68700420, 0xb000000b, 0xb000000b, +0x30800230, 0x0874422a, 0xd0004207, 0xf002b617, +0x7044000b, 0x40087790, 0x90033e01, 0x69a88a50, +0xb0007600, 0xb000ea00, 0xd0002e10, 0xf0004287, +0xb0006e8e, 0x90000372, 0xa9e82f70, 0x69048b51, +0x90033e01, 0xc948a220, 0x49309a20, 0xb000000b, +0xc8f09ad0, 0xd0006442, 0xd002b602, 0xf002fffb, +0x2960000b, 0xf002ffe9, 0xd002ffe2, 0x68700420, +0xb000000b, 0xb000000b, 0x28749470, 0xb000000b, +0x88f4aa20, 0xb0004612, 0xd001ebb1, 0x9002f9fd, +0xd002ffd8, 0x68700420, 0xb000000b, 0xb000000b, +0xc86effd4, 0x68700420, 0xb000000b, 0xb000000b, +0x6874000b, 0x7044000b, 0xfbd4d8d0, 0xd000dc00, +0xc8f09ad0, 0xf002ffcb, 0x68700420, 0xb000000b, +0xb000000b, 0x70804380, 0x48449000, 0x0810d400, +0xd0001035, 0xe80c1080, 0xc8549000, 0x081cd400, +0xd0001035, 0x28181080, 0xd0004207, 0x9002f7bd, +0x7044000b, 0x40087790, 0x90033e01, 0x69a88a50, +0xb0007600, 0xf0004212, 0xc9e85280, 0x2904ca81, +0x90033e01, 0x90005280, 0x49309a20, 0xb000000b, +0xa83898d0, 0xe83c98d0, 0xb0005242, 0x9002f9fb, +0x2960000b, 0xd0004347, 0x9002f9ec, 0x0810d580, +0x081cd580, 0xf002ffe9, 0x68700420, 0xb000000b, +0xb000a070, 0x48449000, 0x0810d400, 0xd0001035, +0xe80c1080, 0xb0005380, 0xf0007020, 0xb000000b, +0x2814a820, 0x2814a820, 0xb0005212, 0x90016bd1, +0x9002f9fd, 0x0810d580, 0xb0005380, 0xf0007020, +0xb000000b, 0x2814a820, 0x2814a820, 0xb0005212, +0x90016bd1, 0x9002f9fd, 0xc8549000, 0x081cd400, +0xd0001035, 0x28181080, 0xb0005380, 0xf0007020, +0xb000000b, 0x2828a820, 0x2828a820, 0xb0005212, +0x90016bd1, 0x9002f9fd, 0x081cd580, 0xb0005380, +0xf0007020, 0xb000000b, 0x2828a820, 0x2828a820, +0xb0005212, 0x90016bd1, 0x9002f9fd, 0xf002ff79, +0x7048000b, 0xca14d580, 0x2004e100, 0xb0003020, +0xf0009511, 0xf0005810, 0xb00158bc, 0xb00158bf, +0xf002ff70, 0xf002ff6e, 0x7048000b, 0xca14d580, +0x2004e100, 0xb0003020, 0xf0009511, 0xb00106b8, +0xd0004216, 0xf002b808, 0xd0004226, 0xf002b808, +0xd0004246, 0xf002b808, 0xd0004286, 0xf002b808, +0xd002ff60, 0xd0018aa1, 0xf002ff5e, 0xd0018aa2, +0xd002ff5c, 0xf0018aa0, 0xd002ff5a, 0xf0018aa3, +0xf002ff58, 0x8f888220, 0xcf888a20, 0x90005000, +0x90002800, 0xf00069f3, 0xf0006917, 0xf002b60a, +0xf0006927, 0xf002b60f, 0xf0006987, 0xf002b609, +0xf0006947, 0xd002b60e, 0xd00069a7, 0xf002b60f, +0xb002be11, 0x90002800, 0xd00068f3, 0xf003a876, +0x90002800, 0xd00068f3, 0xd0006841, 0xf003a876, +0x90002800, 0xd00068f3, 0xd003a877, 0x90002800, +0xd00068f3, 0xd003a878, 0x90002800, 0xd00068f3, +0xf003a879, 0x90005000, 0xb002be14, 0x90005180, +0xb0005187, 0xd09eb811, 0xf0007e30, 0x60a89200, +0xb000000b, 0x90005207, 0xd002b822, 0xb09c000b, +0x455caa20, 0xb000000b, 0xf0006886, 0xd002b80a, +0xe5109420, 0xb000000b, 0xf001c2a0, 0x0551caa1, +0x308c000b, 0xe0b4000b, 0x7044000b, 0x20007710, +0xd0037fc9, 0x7044000b, 0x400477f0, 0x7044000b, +0x8524e000, 0x90016ac1, 0xf0012ac0, 0xb000000b, +0xf0006a11, 0x70456ac0, 0xe520e020, 0x9001a8c0, +0x7044000b, 0x0000e884, 0xd001e8c0, 0x90002bf0, +0xf0007e00, 0xc010a800, 0x90003f50, 0xf0037fe5, +0x7044000b, 0x000c7750, 0xd0037fd8, 0xd0018a20, +0xf002ffd3, 0x9001ca20, 0x9002be04, 0xb001c820, +0x9002be02, 0xf0014820, 0xd0004207, 0x9002f7ca, +0xb0004600, 0xd002ffca, 0xb000000b, 0xb000000b, +0xb000000b, 0xb000000b, 0xb000000b, 0xb000000b, +0xb000000b, 0xb000000b, 0xb000000b, 0xb000000b, +0xd002ffed, 0xd002ffee, 0xf002ffef, 0xd002ffe8, +0xf002ffb9, 0x9002be3d, 0xd002ffb7, 0xf002ffb6, +0xf002ffb5, 0xd002ffb4, 0xf002ffb3, 0xd002ffb2, +0xd002ffb1, 0xf002ffb0, 0xd002ffaf, 0xf002ffae, +0xd002fee5, 0xd002ff0c, 0xd002ff0f, 0xd002ff17, +0xf002ff68, 0xd002ff71, 0xd002fefd, 0xd002ffa6, +0xd002ffa5, 0xf002ffa4, 0xd002ffa3, 0xf002ffa2, +0xf002ffa1, 0xd002ffa0, 0xd002ff9f, 0xf002ff2f, +0x9002be2f, 0x9002be5b, 0xb002be7b, 0xb002be69, +0x9002be8a, 0x9002be9e, 0xb002bea5, 0x9002beb0, +0xb002bf26, 0xb002bf2a, 0x9002bf2e, 0xb002bebb, +0x9002bed6, 0x9002beec, 0xb002bf0b, 0x9002bf17, +0xb002bf3b, 0x9002bf44, 0x9002bf4d, 0x9002bf56, +0x9002bf59, 0x9002bf5c, 0x9002bf63, 0xb002bf5e, +0x9002bf65, 0xb002bf68, 0xb002bf6e, 0x9002bf72, +0xb002bf8f, 0xf002ff80, 0xf002ff7f, 0xd002ff7e, +0xd002ff7d, 0xd002ff7e, 0xd0001220, 0x9000e800, +0x50442a10, 0x8520d4c0, 0xb000e81a, 0xd0009551, +0xd00184a0, 0xb000000b, 0x90005207, 0x9002f7f6, +0x90005000, 0xd00150a0, 0xd002fff3, 0x7048000b, +0x8a14d180, 0x6004d500, 0xb0003010, 0x900090b1, +0x9000d400, 0x90004a07, 0xd002b806, 0xd0005400, +0x90001640, 0x7044d41a, 0x69f4d401, 0x900194a0, +0xf0038c7c, 0xb000000b, 0xb000000b, 0xb000000b, +0x9002be10, 0xb002be11, 0xb002be12, 0x9002be13, +0xb002be14, 0x9002be15, 0xf002ffda, 0xf002ffd9, +0xd002ffd8, 0xd002ffd7, 0xf002ffd6, 0xf002ffd5, +0xd002ffd4, 0xf002ffd3, 0xd002ffd2, 0xd002ffd1, +0xd001d496, 0xf002ffd0, 0xf001d497, 0xf002ffce, +0xf001d498, 0xd002ffcc, 0xd001d499, 0xd002ffca, +0xd001d49a, 0xf002ffc8, 0xf001d49b, 0xd002ffc6, +0x90005000, 0xd0001210, 0x3044d01a, 0x29f4d001, +0xf0019080, 0xb000000b, 0xf001449e, 0x90001430, +0xf000542a, 0x9001549f, 0xb001c88a, 0x9000d400, +0xf001d485, 0xd001d484, 0xb0015486, 0xf002ffb6, +0x90005000, 0xd0001210, 0x3044d01a, 0x29f4d001, +0xf0019080, 0x7044000b, 0xc528d4c0, 0xf00118a2, +0xd0014895, 0xf0014a84, 0xf001cc9b, 0xd0005a10, +0x900030c0, 0xd0005a1a, 0xf0005a12, 0xb0015a81, +0xd002ffa5, 0x90005000, 0xd0001210, 0x3044d01a, +0x29f4d001, 0xf0019080, 0x7044000b, 0xc528d4c0, +0xd00118a3, 0xf0014a82, 0xb0014c83, 0x90014e85, +0xd0005a10, 0x900030c0, 0xd0005a1a, 0xf0005a12, +0xb0015a81, 0xf002ff94, 0x90005000, 0xd0001210, +0x3044d01a, 0x29f4d001, 0xf0019080, 0x9000d400, +0x90004a07, 0xd002b806, 0xd0005400, 0x90001640, +0x7044d41a, 0x69f4d401, 0x900194a0, 0xd0004c17, +0xd002b803, 0xf001d485, 0xf002ff83, 0xf0004c07, +0xb002f981, 0xd001d484, 0xf002ff7f, 0x90005000, +0xd0001210, 0x3044d01a, 0x29f4d001, 0xf0019080, +0xb000000b, 0xb001c886, 0xd002ff77, 0x7044da00, +0xca2ce000, 0xf001dbd0, 0x90005000, 0xd0001210, +0x3044d01a, 0x29f4d001, 0xf0019080, 0xf0005410, +0x90015499, 0x9001549a, 0xd002ff6a, 0x7044da00, +0xea2ce040, 0xf001dbd0, 0x7044000b, 0xca2ce000, +0xf001dbd0, 0x90005000, 0xd0001210, 0x3044d01a, +0x29f4d001, 0xf0019080, 0xf0005420, 0x90015499, +0x9001549a, 0xf002ff5b, 0x7048000b, 0x6004d480, +0x6af0d080, 0xb0003010, 0x900090b1, 0xb0003020, +0xd000d011, 0xf001469c, 0xf0014880, 0x90005000, +0xd0001240, 0x3044d01a, 0x29f4d001, 0xf0019080, +0xf0005420, 0x9001549a, 0x7048000b, 0x6004d480, +0x6af0d080, 0xb0003010, 0x900090b1, 0xf0011684, +0xd0005580, 0xb0003020, 0xf00055fa, 0x900016a4, +0xb0015684, 0xf002ff40, 0x7048000b, 0x6004d480, +0x6af0d080, 0xb0003010, 0x900090b1, 0xf0011684, +0xd0005580, 0xb0003020, 0xf00055fa, 0xb00014a8, +0xb00016a3, 0xb0015684, 0xb0003020, 0xd000d011, +0xb0010880, 0x90005000, 0xd0001240, 0x3044d01a, +0x29f4d001, 0xf0019080, 0xf0005410, 0x9001549a, +0xf002ff29, 0x7048000b, 0x8020d400, 0xca70d000, +0x90003030, 0x900090b1, 0x3080d407, 0xd002b619, +0x7044000b, 0x40087790, 0x90033e01, 0x69a88a50, +0x093c6e20, 0xb0007600, 0xb000ea00, 0xb000acb0, +0x9000d487, 0xd000ec8e, 0xf0009572, 0xa9e82f70, +0x69048b51, 0x90033e01, 0xc948a220, 0xb000000b, +0xf0006407, 0xd002b604, 0x0931c784, 0xd0006442, +0xd002fffc, 0x293c6e30, 0x2960000b, 0xd002ffe7, +0xd002ff09, 0x7048000b, 0x6004d480, 0x6af0d100, +0xb0003010, 0x900090b1, 0xb000441a, 0x30481221, +0x8020d400, 0x8a70cc00, 0x90003030, 0xd0008cb1, +0xf001cc80, 0xf002fefc, 0x90005000, 0xd0001210, +0x3044d01a, 0x29f4d001, 0xf0019080, 0xb000000b, +0x9001ca8a, 0xd002fef4, 0x7044da00, 0x8528d0c0, +0xf0018a81, 0xf001da81, 0xd002feef, 0x7044da00, +0x8528d0c0, 0xf0018a82, 0xf001da82, 0xd002feea, +0xf000ca00, 0x90004657, 0xd002fce7, 0x90005000, +0xd0001210, 0x3044d01a, 0x29f4d001, 0xf0019080, +0x7044000b, 0x2000d560, 0xf0009491, 0x90003030, +0x9000d421, 0x9000d800, 0xb0004407, 0x90018db0, +0x9002f6d9, 0xd001d9b0, 0xf002fed7, 0x7044000b, +0x8528d0c0, 0xf0014483, 0xf0014682, 0xb001ca99, +0xb0001420, 0xf0000627, 0xb000143e, 0x90015481, +0xd002fecd, 0x7044000b, 0xe52cd100, 0x9001c481, +0xb001ca9c, 0xb000da00, 0x90009c30, 0x9000da4a, +0xd0009a51, 0xd001da9d, 0xf002fec3, 0x7044000b, +0x6530d100, 0x9001c481, 0xb001ca9c, 0xb000da00, +0x90009c30, 0x9000da4a, 0xd0009a51, 0xd001da9d, +0xd002feb9, 0x7044000b, 0x8528d0c0, 0xb001ca9a, +0xd002feb5, 0x7044000b, 0x8528d0c0, 0x9001ca9b, +0xf002feb1, 0x7044000b, 0xe52cd100, 0xb001ca82, +0xd002fead, 0x7044000b, 0x6530d100, 0xb001ca82, +0xf002fea9, 0x7044000b, 0xe52cd100, 0x9001ca83, +0xf002fea5, 0x7044000b, 0x6530d100, 0x9001ca83, +0xd002fea1, 0x7044000b, 0x8528d0c0, 0xf0014894, +0xf0014a96, 0x90014c95, 0x90014e97, 0xf002fe9a, +0x7044000b, 0x8528d0c0, 0x9001ca83, 0x20508a50, +0xf002fe95, 0x7044000b, 0x4a6cc520, 0x30458420, +0x8020c000, 0x3080000b, 0x7044000b, 0x40087790, +0x90033e01, 0x69a88a50, 0xb0007600, 0xb000ea00, +0xb000ac10, 0x9000c087, 0xd000ec8e, 0xf0008172, +0xa9e82f70, 0x69048b51, 0x90033e01, 0xc948a220, +0x0931c724, 0xd0006442, 0xd002b602, 0xf002fffd, +0x2960000b, 0xb000c007, 0xd002b602, 0xd002ffeb, +0x7044000b, 0xa01440b0, 0xf002fe77, 0xd0004207, +0xd002b608, 0x7044000b, 0x4a6cd120, 0xf0019080, +0xb000000b, 0x90009071, 0xd0018a80, 0x9002be07, +0x7044000b, 0x6a6cd100, 0xf0019080, 0xb000000b, +0x90009071, 0xd0018a80, 0xd002fe67, 0x7044000b, +0x20007720, 0x90033e01, 0xe514a020, 0x7044000b, +0x000077f0, 0xef85a6c0, 0xcf85a6c4, 0xe54f7ff8, +0x6038000b, 0x7044000b, 0xca2ce000, 0x30458ac0, +0xea2ce040, 0xd000ca07, 0xf002b81f, 0xf0018ac0, +0xb000000b, 0xd000ca07, 0xd002b81b, 0xb002be3f, +0x7044000b, 0x400477f0, 0x7044000b, 0x8524e000, +0x90016ac1, 0xf0012ac0, 0xb000000b, 0xf0006a11, +0x70456ac0, 0xe520e020, 0x9001a8c0, 0x7044000b, +0x0000e884, 0xd001e8c0, 0x90002bf0, 0xf0007e00, +0xc010a800, 0x90003f50, 0xb0033e11, 0x7044000b, +0x000c7750, 0x90033e04, 0x308c000b, 0x80b4a800, +0x9002be26, 0x308c000b, 0x00a8a800, 0xb000000b, +0xf0006807, 0xb002f9f6, 0xb09c000b, 0x455caa20, +0xb000000b, 0xf0006886, 0xb002f9de, 0x7044c200, +0xca2ce000, 0xf0018ac0, 0xb000000b, 0xd000ca07, +0xf002b606, 0x90008877, 0x9002f9ec, 0xf001c2c0, +0xd0008050, 0x9002be0b, 0x7044000b, 0xea2ce040, +0xf0018ac0, 0xb000000b, 0xb000cc07, 0xb002f7e3, +0x90008877, 0xb002f9e1, 0xf001c2c0, 0xf0008070, +0xa510a020, 0xb000000b, 0xf001c2c0, 0x4551eac1, +0x308c000b, 0x80b4a800, 0x7044000b, 0xa01076a0, +0x7044000b, 0xea2ce080, 0xb00182c0, 0xb000000b, +0xb000c007, 0xd002b62f, 0xf000c407, 0xf002b62d, +0x308c000b, 0x40a8a000, 0xb000000b, 0xb0006007, +0xf002b825, 0xb09c000b, 0x455caa20, 0xb000000b, +0xf0006886, 0xf002b80d, 0x7044ea00, 0xea2ce080, +0xb00182c0, 0x3045eac0, 0x20044040, 0xa510a020, +0xb000000b, 0xf001c2c0, 0x4551eac1, 0x308c000b, +0x80b4a800, 0xb002be17, 0x7044000b, 0x400477f0, +0x7044000b, 0x8524e000, 0x90016ac1, 0xf0012ac0, +0xb000000b, 0xf0006a11, 0x70456ac0, 0xe520e020, +0x9001a8c0, 0x7044000b, 0x0000e884, 0xd001e8c0, +0x90002bf0, 0xf0007e00, 0xc010a800, 0x90003f50, +0xd0037fe2, 0x7044000b, 0x000c7750, 0xf0037fd5, +0x7044000b, 0xa01076a0, 0x7044000b, 0xc520c800, +0x90018240, 0xb0019a41, 0xb000000b, 0xf00082d7, +0xf002b807, 0x7044000b, 0xe520c880, 0x90018240, +0xb000000b, 0x9000c207, 0x10837772, 0x308c000b, +0x40a89000, 0xb000000b, 0xb0005007, 0xd002b817, +0x7044000b, 0x400477f0, 0x909f3e01, 0x7048da00, +0xa01076a0, 0xc520c800, 0xe5108c20, 0x50458240, +0xb000000b, 0xf001c241, 0x7044000b, 0xe520c880, +0x90019a40, 0xb000000b, 0xd0005980, 0xf001da60, +0x4551c261, 0xb000c200, 0xd001c240, 0x308c000b, +0xe0b4000b, 0x70837f57, 0x7044000b, 0x000c7750, +0xf0037fe3, 0xc8609400, 0x7048000b, 0x6004cd00, +0x8a14d180, 0x900030a0, 0x90009071, 0xf0005600, +0x88689a20, 0xb000000b, 0xf0005886, 0xd002b80c, +0xf0005846, 0xd002b811, 0xf0005826, 0xf002b816, +0xf0005816, 0xd002b81b, 0xf0005b86, 0xf002b820, +0xf0005b46, 0xf002b825, 0x9002be2a, 0x90018283, +0xf000c880, 0xb000c211, 0xd001c283, 0x9001c89c, +0xf0005684, 0xf002ffef, 0x90018280, 0xf000c840, +0xb000c211, 0xd001c280, 0x9001c89c, 0xf0005644, +0xf002ffea, 0xb0018282, 0xf000c820, 0xb000c211, +0xf001c282, 0x9001c89c, 0xf0005624, 0xf002ffe5, +0xb0018281, 0xf000c810, 0xb000c211, 0xf001c281, +0x9001c89c, 0xf0005614, 0xf002ffe0, 0xb0018284, +0xd000c920, 0xb000c211, 0xf001c284, 0x9001c89c, +0xd0005724, 0xd002ffdb, 0x90018285, 0xd000c910, +0xb000c211, 0xd001c285, 0x9001c89c, 0xd0005714, +0xb000da00, 0xd0001eb0, 0xd0005433, 0xf0005407, +0xf002b605, 0x9000da4a, 0x9000da2a, 0xd0005412, +0x9002f9fd, 0x7044000b, 0xe520c480, 0xd0018a20, +0xb000000b, 0xb0008ad4, 0x9001ca20, 0xd00007f0, +0xf0007e00, 0x80108400, 0xb0003e30, 0xa86c000b, +0xf0037fad, 0xb000000b, 0xb000000b, 0xf002fffe, +0xb000000b, 0xb000000b, + +/* data block */ +0x00000000, /* location in PIU memory */ +0x00000a4b, /* number of words in the block */ +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, 0x7e7e7e7e, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0xb0000000, 0x00000000, + +/* data block */ +0x00000a4c, /* location in PIU memory */ +0x0000000b, /* number of words in the block */ +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00002710, + +/* data block */ +0x00000a58, /* location in PIU memory */ +0x00000a03, /* number of words in the block */ +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x294a0000, 0x00042912, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x294b0000, 0x00022910, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x01000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x02000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x03000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x04000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x05000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x06000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x07000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x08000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x09000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x0a000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x0b000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x0c000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x0d000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x0e000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x0f000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x10000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x11000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x12000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x13000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x14000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x15000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x16000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x17000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x18000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x19000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x1a000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x1b000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x1c000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x1d000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x1e000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x1f000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x20000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x21000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x22000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x23000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x24000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x25000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x26000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x27000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x28000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x29000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x2a000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x2b000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x2c000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x2d000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x2e000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x2f000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x30000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x31000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x32000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x33000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x34000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x35000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x36000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x37000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x38000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x39000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x3a000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x3b000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x3c000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x3d000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x3e000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x3f000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x40000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x41000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x42000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x43000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x44000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x45000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x46000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x47000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x48000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x49000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x4a000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x4b000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x4c000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x4d000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x4e000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x4f000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x50000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x51000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x52000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x53000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x54000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x55000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x56000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x57000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x58000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x59000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x5a000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x5b000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x5c000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x5d000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x5e000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x5f000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x60000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x61000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x62000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x63000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x64000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x65000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x66000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x67000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x68000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x69000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x6a000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x6b000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x6c000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x6d000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x6e000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x6f000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x70000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x71000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x72000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x73000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x74000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x75000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x76000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x77000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x78000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x79000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x7a000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x7b000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000050, 0x00000000, 0x00000000, +0x7c000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000050, 0x00000000, 0x00000000, 0x7d000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000050, +0x00000000, 0x00000000, 0x7e000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000050, 0x00000000, +0x00000000, 0x7f000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x29c02a0c, 0x2a582aa4, 0x2af02b3c, 0x2b882bd4, +0x2c202c6c, 0x2cb82d04, 0x2d502d9c, 0x2de82e34, +0x2e802ecc, 0x2f182f64, 0x2fb02ffc, 0x30483094, +0x30e0312c, 0x317831c4, 0x3210325c, 0x32a832f4, +0x3340338c, 0x33d83424, 0x347034bc, 0x35083554, +0x35a035ec, 0x36383684, 0x36d0371c, 0x376837b4, +0x3800384c, 0x389838e4, 0x3930397c, 0x39c83a14, +0x3a603aac, 0x3af83b44, 0x3b903bdc, 0x3c283c74, +0x3cc03d0c, 0x3d583da4, 0x3df03e3c, 0x3e883ed4, +0x3f203f6c, 0x3fb84004, 0x4050409c, 0x40e84134, +0x418041cc, 0x42184264, 0x42b042fc, 0x43484394, +0x43e0442c, 0x447844c4, 0x4510455c, 0x45a845f4, +0x4640468c, 0x46d84724, 0x477047bc, 0x48084854, +0x48a048ec, 0x49384984, 0x49d04a1c, 0x4a684ab4, +0x4b004b4c, 0x4b984be4, 0x4c304c7c, 0x4cc84d14, +0x4d604dac, 0x4df84e44, 0x4e904edc, 0x4f284f74, +0x04000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x0c000800, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x14001000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x1c001800, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, + +/* data block */ +0x0000145c, /* location in PIU memory */ +0x00000082, /* number of words in the block */ +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x51705270, 0x51705270, + +/* data block */ +0x000014e0, /* location in PIU memory */ +0x00000128, /* number of words in the block */ +0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, +0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f, +0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, +0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, +0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, +0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, +0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, +0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f, +0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, +0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, +0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, +0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, +0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, +0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf, +0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, +0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, +0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, +0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f, +0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, +0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, +0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, +0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, +0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, +0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f, +0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, +0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, +0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, +0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, +0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, +0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf, +0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, +0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, +0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, +0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f, +0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, +0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, +0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, +0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, +0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, +0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f, +0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, +0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, +0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, +0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, +0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, +0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf, +0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, +0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, +0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, +0x10111213, 0x14151617, 0x18191a1b, 0x1c1d1e1f, +0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, +0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, +0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, +0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, +0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, +0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f, +0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, +0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, +0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, +0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, +0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, +0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf, +0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, +0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, +0x04000400, 0x00000000, 0x00000000, 0x00000000, +0x53805480, 0x55805680, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x0c000c00, 0x00000000, +0x00000000, 0x00000800, 0x53805480, 0x55805680, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x14001400, 0x00000000, 0x00000000, 0x00001000, +0x53805480, 0x55805680, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x1c001c00, 0x00000000, +0x00000000, 0x00001800, 0x53805480, 0x55805680, +0x00000000, 0x00000000, 0x00000000, 0x00000000, + +#endif /* IX_PIUDL_PIUIMAGE_PIU_HSS_TOLAPAI */ +/* END OF PIU FIRMWARE IMAGE */ + + +/* END OF IMAGE LIBRARY MARKER */ + +0xfeedf00d, 0xfeedf00d + + +}; /* END OF MICROCODE IMAGE */ + + +#endif /* IX_PIUDL_READ_MICROCODE_FROM_FILE */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMh.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMh.c new file mode 100644 index 0000000..b0e9bff --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMh.c @@ -0,0 +1,692 @@ +/** + * @file IxPiuMh.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the public API for the + * PIU Message Handler component. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + +/* + * Put the user defined include files required. + */ + +#include "IxOsal.h" +#include "IxPiuMhMacros_p.h" + +#include "IxPiuMh.h" + +#include "IxPiuMhConfig_p.h" +#include "IxPiuMhReceive_p.h" +#include "IxPiuMhSend_p.h" +#include "IxPiuMhSolicitedCbMgr_p.h" +#include "IxPiuMhUnsolicitedCbMgr_p.h" + +/* + * #defines and macros used in this file. + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE BOOL ixPiuMhInitialized = FALSE; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ + +#if defined(__ep805xx) +/* + * Function definition: ixPiuMhPhysicalAddressSet + */ + +PUBLIC IX_STATUS ixPiuMhPhysicalAddressSet ( + IxPiuMhPiuId piuId, + UINT32 address) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhPhysicalAddressSet\n"); + + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* ensure that the compoonent is not initialized */ + if (ixPiuMhInitialized) + { + return IX_FAIL; + } + + /* set the address */ + ixPiuMhConfigPhysicalAddressSet(piuId, address); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhPhysicalAddressSet\n"); + + return IX_SUCCESS; +} +/* + * Function definition: ixPiuMhInterruptIdSet + */ + +PUBLIC IX_STATUS ixPiuMhInterruptIdSet ( + IxPiuMhPiuId piuId, + UINT32 interruptId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhInterruptIdSet\n"); + + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* ensure that the compoonent is not initialized */ + if (ixPiuMhInitialized) + { + return IX_FAIL; + } + + /* set the address */ + ixPiuMhConfigInterruptIdSet(piuId, interruptId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhInterruptIdSet\n"); + + return IX_SUCCESS; +} +#endif /* #if defined(__ep805xx) */ + +/* + * Function definition: ixPiuMhInitialize + */ + +PUBLIC IX_STATUS ixPiuMhInitialize ( + IxPiuMhPiuInterrupts piuInterrupts) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhInitialize\n"); + + /* check the piuInterrupts parameter */ + if ((piuInterrupts != IX_PIUMH_PIUINTERRUPTS_NO) && + (piuInterrupts != IX_PIUMH_PIUINTERRUPTS_YES)) + { + IX_PIUMH_ERROR_REPORT ("Illegal piuInterrupts parameter value\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* initialize the Receive module */ + ixPiuMhReceiveInitialize (); + + + /* initialize the Solicited Callback Manager module */ + ixPiuMhSolicitedCbMgrInitialize (); + + /* initialize the Unsolicited Callback Manager module */ + ixPiuMhUnsolicitedCbMgrInitialize (); + + /* initialize the Configuration module + * + * NOTE: This module was originally configured before the + * others, but the sequence was changed so that interrupts + * would only be enabled after the handler functions were + * set up. The above modules need to be initialised to + * handle the PIU interrupts. See SCR #2231. + */ + ixPiuMhConfigInitialize (piuInterrupts); + + ixPiuMhInitialized = TRUE; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhInitialize\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhUnload + */ + +PUBLIC IX_STATUS ixPiuMhUnload (void) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnload\n"); + + if (!ixPiuMhInitialized) + { + return IX_FAIL; + } + + /* Uninitialize the Configuration module */ + ixPiuMhConfigUninit (); + /* Reset the PiuMhShow */ +#if defined(__ixp23xx) + ixPiuMhShowReset (IX_PIUMH_PIUID_PIU0); + ixPiuMhShowReset (IX_PIUMH_PIUID_PIU1); +#endif +#if defined(__ep805xx) + ixPiuMhShowReset (IX_PIUMH_PIUID_PIU0); +#endif +#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp5XX) + ixPiuMhShowReset (IX_PIUMH_PIUID_PIUA); + ixPiuMhShowReset (IX_PIUMH_PIUID_PIUB); +#endif +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) + ixPiuMhShowReset (IX_PIUMH_PIUID_PIUC); +#endif + + ixPiuMhUnsolicitedCbMgrUninitialize (); + ixPiuMhSolicitedCbMgrUninitialize (); + ixPiuMhReceiveUninitialize (); + ixPiuMhInitialized = FALSE; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnload\n"); + + return IX_SUCCESS; +} + + +/* + * Function definition: ixPiuMhUnsolicitedCallbackRegister + */ + +PUBLIC IX_STATUS ixPiuMhUnsolicitedCallbackRegister ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId messageId, + IxPiuMhCallback unsolicitedCallback) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCallbackRegister\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* check the messageId parameter */ + if ((messageId < IX_PIUMH_MIN_MESSAGE_ID) + || (messageId > IX_PIUMH_MAX_MESSAGE_ID)) + { + IX_PIUMH_ERROR_REPORT ("Message ID is out of range\n"); + return IX_FAIL; + } + + /* the unsolicitedCallback parameter is allowed to be NULL */ + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* save the unsolicited callback for the message ID */ + ixPiuMhUnsolicitedCbMgrCallbackSave ( + piuId, messageId, unsolicitedCallback); + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCallbackRegister\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhUnsolicitedCallbackForRangeRegister + */ + +PUBLIC IX_STATUS ixPiuMhUnsolicitedCallbackForRangeRegister ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId minMessageId, + IxPiuMhMessageId maxMessageId, + IxPiuMhCallback unsolicitedCallback) +{ + IxPiuMhMessageId messageId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCallbackForRangeRegister\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* check the minMessageId parameter */ + if ((minMessageId < IX_PIUMH_MIN_MESSAGE_ID) + || (minMessageId > IX_PIUMH_MAX_MESSAGE_ID)) + { + IX_PIUMH_ERROR_REPORT ("Min message ID is out of range\n"); + return IX_FAIL; + } + + /* check the maxMessageId parameter */ + if ((maxMessageId < IX_PIUMH_MIN_MESSAGE_ID) + || (maxMessageId > IX_PIUMH_MAX_MESSAGE_ID)) + { + IX_PIUMH_ERROR_REPORT ("Max message ID is out of range\n"); + return IX_FAIL; + } + + /* check the semantics of the message range parameters */ + if (minMessageId > maxMessageId) + { + IX_PIUMH_ERROR_REPORT ("Min message ID greater than max message " + "ID\n"); + return IX_FAIL; + } + + /* the unsolicitedCallback parameter is allowed to be NULL */ + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* for each message ID in the range ... */ + for (messageId = minMessageId; messageId <= maxMessageId; messageId++) + { + /* save the unsolicited callback for the message ID */ + ixPiuMhUnsolicitedCbMgrCallbackSave ( + piuId, messageId, unsolicitedCallback); + } + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCallbackForRangeRegister\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhMessageSend + */ + +PUBLIC IX_STATUS ixPiuMhMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries) +{ + IX_STATUS status = IX_SUCCESS; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhMessageSend\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* send the message */ + status = ixPiuMhSendMessageSend (piuId, message, maxSendRetries); + if (status != IX_SUCCESS) + { + IX_PIUMH_ERROR_REPORT ("Failed to send message\n"); + } + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE1 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhMessageSend" + " : status = %d\n", status); + + return status; +} + +/* + * Function definition: ixPiuMhMessageWithResponseSend + */ + +PUBLIC IX_STATUS ixPiuMhMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries) +{ + IX_STATUS status = IX_SUCCESS; + IxPiuMhCallback unsolicitedCallback = NULL; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhMessageWithResponseSend\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* the solicitecCallback parameter is allowed to be NULL. this */ + /* signifies the client is not interested in the response message */ + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* check the solicitedMessageId parameter */ + if ((solicitedMessageId < IX_PIUMH_MIN_MESSAGE_ID) + || (solicitedMessageId > IX_PIUMH_MAX_MESSAGE_ID)) + { + IX_PIUMH_ERROR_REPORT ("Solicited message ID is out of range\n"); + return IX_FAIL; + } + + /* check the solicitedMessageId parameter. if an unsolicited */ + /* callback has been registered for the specified message ID then */ + /* report an error and return failure */ + ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + piuId, solicitedMessageId, &unsolicitedCallback); + if (unsolicitedCallback != NULL) + { + IX_PIUMH_ERROR_REPORT ("Solicited message ID conflicts with " + "unsolicited message ID\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* send the message */ + status = ixPiuMhSendMessageWithResponseSend ( + piuId, message, solicitedMessageId, solicitedCallback, + maxSendRetries); + if (status != IX_SUCCESS) + { + IX_PIUMH_ERROR_REPORT ("Failed to send message\n"); + } + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE1 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhMessageWithResponseSend" + " : status = %d\n", status); + + return status; +} + +/* + * Function definition: ixPiuMhMessagesReceive + */ + +PUBLIC IX_STATUS ixPiuMhMessagesReceive ( + IxPiuMhPiuId piuId) +{ + IX_STATUS status = IX_SUCCESS; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhMessagesReceive\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* get the lock to prevent other clients from entering */ + ixPiuMhConfigLockGet (piuId); + + /* receive messages from the PIU */ + status = ixPiuMhReceiveMessagesReceive (piuId); + + if (status != IX_SUCCESS) + { + IX_PIUMH_ERROR_REPORT ("Failed to receive message\n"); + } + + /* release the lock to allow other clients back in */ + ixPiuMhConfigLockRelease (piuId); + + IX_PIUMH_TRACE1 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhMessagesReceive" + " : status = %d\n", status); + + return status; +} + +/* + * Function definition: ixPiuMhShow + */ + +PUBLIC IX_STATUS ixPiuMhShow ( + IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhShow\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* note we don't get the lock here as printing the statistics */ + /* to a console may take some time and we don't want to impact */ + /* system performance. this means that the statistics displayed */ + /* may be in a state of flux and make not represent a consistent */ + /* snapshot. */ + + /* display a header */ + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "Current state of PIU ID %d:\n\n", piuId, 0, 0, 0, 0, 0); + + /* show the current state of each module */ + + /* show the current state of the Configuration module */ + ixPiuMhConfigShow (piuId); + + /* show the current state of the Receive module */ + ixPiuMhReceiveShow (piuId); + + /* show the current state of the Send module */ + ixPiuMhSendShow (piuId); + + /* show the current state of the Solicited Callback Manager module */ + ixPiuMhSolicitedCbMgrShow (piuId); + + /* show the current state of the Unsolicited Callback Manager module */ + ixPiuMhUnsolicitedCbMgrShow (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhShow\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhShowReset + */ + +PUBLIC IX_STATUS ixPiuMhShowReset ( + IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhShowReset\n"); + + /* check that we are initialized */ + if (!ixPiuMhInitialized) + { + IX_PIUMH_ERROR_REPORT ("IxPiuMh component is not initialized\n"); + return IX_FAIL; + } + + /* check the piuId parameter */ + if (!ixPiuMhConfigPiuIdIsValid (piuId)) + { + IX_PIUMH_ERROR_REPORT ("PIU ID invalid\n"); + return IX_FAIL; + } + + /* parameters are ok ... */ + + /* note we don't get the lock here as resetting the statistics */ + /* shouldn't impact system performance. */ + + /* reset the current state of each module */ + + /* reset the current state of the Configuration module */ + ixPiuMhConfigShowReset (piuId); + + /* reset the current state of the Receive module */ + ixPiuMhReceiveShowReset (piuId); + + /* reset the current state of the Send module */ + ixPiuMhSendShowReset (piuId); + + /* reset the current state of the Solicited Callback Manager module */ + ixPiuMhSolicitedCbMgrShowReset (piuId); + + /* reset the current state of the Unsolicited Callback Manager module */ + ixPiuMhUnsolicitedCbMgrShowReset (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhShowReset\n"); + + return IX_SUCCESS; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhConfig.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhConfig.c new file mode 100644 index 0000000..0c9061a --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhConfig.c @@ -0,0 +1,776 @@ +/** + * @file IxPiuMhConfig.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for the + * Configuration module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ + +#include "IxOsal.h" + +#include "IxPiuMhMacros_p.h" + +#include "IxPiuMhConfig_p.h" + + +#if defined(__ixp23xx) +#define IX_PIUMH_PIU0_INT (IX_PIU_IRQ_DBG0) +#define IX_PIUMH_PIU1_INT (IX_PIU_IRQ_DBG1) +#endif +#if defined(__ep805xx) +#define IX_PIUMH_PIU0_INT (IX_PIU_IRQ_DBG0) +#endif + + +PRIVATE IxPiuMhPiuInterrupts ixPiuMhConfigInterrupts; + +/* + * #defines and macros used in this file. + */ +#define IX_PIU_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of + * retries before + * timeout + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhConfigStats + * + * @brief This structure is used to maintain statistics for the + * Configuration module. + */ + +typedef struct +{ + UINT32 outFifoReads; /**< outFifo reads */ + UINT32 inFifoWrites; /**< inFifo writes */ + UINT32 maxInFifoFullRetries; /**< max retries if inFIFO full */ + UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */ +} IxPiuMhConfigStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +IxPiuMhConfigPiuInfo ixPiuMhConfigPiuInfo[IX_PIUMH_NUM_PIUS] = +{ +#if defined(__ixp23xx) + { + 0, /*mutex*/ + IX_PIUMH_PIU0_INT, /*interrupt ID*/ + 0, /*register virtual base address*/ + 0, /*status register virtual address*/ + 0, /*control register virtual address*/ + 0, /*inFIFO register virutal address*/ + 0, /*outFIFO register virtual address*/ + NULL, /*isr routine for handling interrupt*/ + FALSE /*old interrupt state (TRUE => enabled)*/ + }, + { + 0, /*mutex*/ + IX_PIUMH_PIU1_INT, /*interrupt ID*/ + 0, /*register virtual base address*/ + 0, /*status register virtual address*/ + 0, /*control register virtual address*/ + 0, /*inFIFO register virutal address*/ + 0, /*outFIFO register virtual address*/ + NULL, /*isr routine for handling interrupt*/ + FALSE /*old interrupt state (TRUE => enabled)*/ + } +#endif +#if defined(__ep805xx) + { + 0, /*mutex*/ + IX_PIUMH_PIU0_INT, /*interrupt ID*/ + IX_PIU_PIU0_PHYS, /*register physical base address*/ + 0, /*register virtual base address*/ + 0, /*status register virtual address*/ + 0, /*control register virtual address*/ + 0, /*inFIFO register virutal address*/ + 0, /*outFIFO register virtual address*/ + NULL, /*isr routine for handling interrupt*/ + FALSE /*old interrupt state (TRUE => enabled)*/ + } +#endif +#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp5XX) + { + 0, + IX_PIUMH_PIUA_INT, + 0, + 0, + 0, + 0, + 0, + NULL, + FALSE + }, + { + 0, + IX_PIUMH_PIUB_INT, + 0, + 0, + 0, + 0, + 0, + NULL, + FALSE + } +#endif +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) + , + { + 0, + IX_PIUMH_PIUC_INT, + 0, + 0, + 0, + 0, + 0, + NULL, + FALSE + } +#endif +}; + +PRIVATE IxPiuMhConfigStats ixPiuMhConfigStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ + +/* + * Function definition: ixPiuMhIsr + */ +void ixPiuMhIsr (void *parameter) +{ + IxPiuMhPiuId piuId = (IxPiuMhPiuId)parameter; + UINT32 ofint; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhIsr\n"); + + /* get the OFINT (OutFifo interrupt) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ofint, IX_PIUMH_PIU_STAT_OFINT); + + /* if the OFINT status bit is set */ + if (ofint) + { + /* if there is an ISR registered for this PIU */ + if (ixPiuMhConfigPiuInfo[piuId].isr != NULL) + { + /* invoke the ISR routine */ + ixPiuMhConfigPiuInfo[piuId].isr (piuId); + } + else + { + /* if we don't service the interrupt the PIU will */ + /* continue to trigger the interrupt indefinitely */ + IX_PIUMH_ERROR_REPORT ("No ISR registered to service " + "interrupt\n"); + } + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhIsr\n"); +} + + +#if defined(__ep805xx) +/* + * Function definition: ixPiuMhConfigPhysicalAddressSet + */ + +void ixPiuMhConfigPhysicalAddressSet( + IxPiuMhPiuId piuId, + UINT32 address) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigPhysicalAddressSet\n"); + + /* set the address for the given PIU in the config structure */ + ixPiuMhConfigPiuInfo[piuId].physicalRegisterBase = address; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigPhysicalAddressSet\n"); +} + +/* + * Function definition: ixPiuMhConfigInterruptIdSet + */ + +void ixPiuMhConfigInterruptIdSet( + IxPiuMhPiuId piuId, + UINT32 interruptId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigInterruptIdSet\n"); + + /* set the interruptID for the given PIU in the config structure */ + ixPiuMhConfigPiuInfo[piuId].interruptId = interruptId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigInterruptIdSet\n"); +} +#endif /* #if defined(__ep805xx) */ + + +/* + * Function definition: ixPiuMhConfigInitialize + */ + +void ixPiuMhConfigInitialize ( + IxPiuMhPiuInterrupts piuInterrupts) +{ + IxPiuMhPiuId piuId; + UINT32 virtualAddr[IX_PIUMH_NUM_PIUS]; +#if defined(__ep805xx) + UINT32 physAddr = 0; +#endif + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigInitialize\n"); + + +#if defined(__ixp23xx) + /* PIU-0 register address space */ + virtualAddr[IX_PIUMH_PIUID_PIU0] = + (UINT32) IX_OSAL_MEM_MAP(IX_PIU_PIU0_PHYS,0); + + /* PIU-1 register address space */ + virtualAddr[IX_PIUMH_PIUID_PIU1] = + (UINT32) IX_OSAL_MEM_MAP(IX_PIU_PIU1_PHYS,0); +#endif + +#if defined(__ep805xx) + /* PIU-0 register address space */ + physAddr = ixPiuMhConfigPiuInfo[IX_PIUMH_PIUID_PIU0].physicalRegisterBase; + + /* no OS agnostic OSAL function available for memory mapping which works + * for linux - using linux ioremap call */ + virtualAddr[IX_PIUMH_PIUID_PIU0] = + (UINT32) ixOsalIoRemap (physAddr, IX_PIU_MAPPED_MEMORY_SIZE); + +#endif + +#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp5XX) + + /* Request a mapping for the PIU-A config register address space */ + virtualAddr[IX_PIUMH_PIUID_PIUA] = + (UINT32) IX_OSAL_MEM_MAP (IX_PIUMH_PIUA_BASE, + IX_OSAL_IXP400_PIUA_MAP_SIZE); + IX_OSAL_ASSERT (virtualAddr[IX_PIUMH_PIUID_PIUA]); + + /* Request a mapping for the PIU-B config register address space */ + virtualAddr[IX_PIUMH_PIUID_PIUB] = + (UINT32) IX_OSAL_MEM_MAP (IX_PIUMH_PIUB_BASE, + IX_OSAL_IXP400_PIUB_MAP_SIZE); + IX_OSAL_ASSERT (virtualAddr[IX_PIUMH_PIUID_PIUB]); +#endif +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) + /* Request a mapping for the PIU-C config register address space */ + virtualAddr[IX_PIUMH_PIUID_PIUC] = + (UINT32) IX_OSAL_MEM_MAP (IX_PIUMH_PIUC_BASE, + IX_OSAL_IXP400_PIUC_MAP_SIZE); + IX_OSAL_ASSERT (virtualAddr[IX_PIUMH_PIUID_PIUC]); +#endif + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* declare a convenience pointer */ + IxPiuMhConfigPiuInfo *piuInfo = &ixPiuMhConfigPiuInfo[piuId]; + + /* store the virtual addresses of the PIU registers for later use */ + piuInfo->virtualRegisterBase = virtualAddr[piuId]; + piuInfo->statusRegister = virtualAddr[piuId] + IX_PIUMH_PIUSTAT_OFFSET; + piuInfo->controlRegister = virtualAddr[piuId] + IX_PIUMH_PIUCTL_OFFSET; + piuInfo->inFifoRegister = virtualAddr[piuId] + IX_PIUMH_PIUFIFO_OFFSET; + piuInfo->outFifoRegister = virtualAddr[piuId] + IX_PIUMH_PIUFIFO_OFFSET; + + /* for test purposes - to verify the register addresses */ + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "PIU %d status register = " + "0x%08X\n", piuId, piuInfo->statusRegister); + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "PIU %d control register = " + "0x%08X\n", piuId, piuInfo->controlRegister); + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "PIU %d inFifo register = " + "0x%08X\n", piuId, piuInfo->inFifoRegister); + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "PIU %d outFifo register = " + "0x%08X\n", piuId, piuInfo->outFifoRegister); + + /* initialise a mutex for this PIU */ + (void) ixOsalMutexInit (&piuInfo->mutex); + + /* if we should service the PIU's "outFIFO not empty" interrupt */ + if (piuInterrupts == IX_PIUMH_PIUINTERRUPTS_YES) + { + /* enable the PIU's "outFIFO not empty" interrupt */ + ixPiuMhConfigPiuInterruptEnable (piuId); + } + else + { + /* disable the PIU's "outFIFO not empty" interrupt */ + ixPiuMhConfigPiuInterruptDisable (piuId); + } + } + + /* This will be used in ixPiuMhConfigUninit() */ + ixPiuMhConfigInterrupts = piuInterrupts; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigInitialize\n"); +} + +/* + * Function definition: ixPiuMhConfigUninit + */ + +void ixPiuMhConfigUninit (void) +{ + IxPiuMhPiuId piuId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigUninit\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* declare a convenience pointer */ + IxPiuMhConfigPiuInfo *piuInfo = &ixPiuMhConfigPiuInfo[piuId]; + + /* Disconnect our ISR to the PIU interrupt */ + if (IX_PIUMH_PIUINTERRUPTS_YES == ixPiuMhConfigInterrupts) + { + ixPiuMhConfigPiuInterruptDisable (piuId); + } + + ixOsalMutexDestroy(&piuInfo->mutex); + +#if defined(__ep805xx) && !defined(UNIT_TEST) + /* no OS agnostic OSAL function available for memory mapping which works + * for linux - using linux iounmap call */ + ixOsalIoUnmap(piuInfo->virtualRegisterBase, IX_PIU_MAPPED_MEMORY_SIZE); +#endif + +#if !defined(__ep805xx) || defined(UNIT_TEST) + IX_OSAL_MEM_UNMAP (piuInfo->virtualRegisterBase); + IX_OSAL_MEM_UNMAP (piuInfo->statusRegister); + IX_OSAL_MEM_UNMAP (piuInfo->controlRegister); + IX_OSAL_MEM_UNMAP (piuInfo->inFifoRegister); + IX_OSAL_MEM_UNMAP (piuInfo->outFifoRegister); +#endif + } + + /* Reset this parameter here which was set during Init */ + if (IX_PIUMH_PIUINTERRUPTS_YES == ixPiuMhConfigInterrupts) + { + ixPiuMhConfigInterrupts = IX_PIUMH_PIUINTERRUPTS_NO; + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigUninit\n"); +} + +/* + * Function definition: ixPiuMhConfigIsrRegister + */ + +void ixPiuMhConfigIsrRegister ( + IxPiuMhPiuId piuId, + IxPiuMhConfigIsr isr) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigIsrRegister\n"); + + /* check if there is already an ISR registered for this PIU */ + if (ixPiuMhConfigPiuInfo[piuId].isr != NULL) + { + IX_PIUMH_TRACE0 (IX_PIUMH_DEBUG, "Over-writing registered PIU ISR\n"); + } + + /* save the ISR routine with the PIU info */ + ixPiuMhConfigPiuInfo[piuId].isr = isr; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigIsrRegister\n"); +} + +void ixPiuMhConfigIsrUnregister (IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigIsrUnregister\n"); + + ixPiuMhConfigPiuInfo[piuId].isr = NULL; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigIsrUnregister\n"); +} + +/* + * Function definition: ixPiuMhConfigPiuInterruptEnable + */ + +BOOL ixPiuMhConfigPiuInterruptEnable ( + IxPiuMhPiuId piuId) +{ + UINT32 ofe; + volatile UINT32 *controlReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].controlRegister; + + /* get the OFE (OutFifoEnable) bit of the control register */ + IX_PIUMH_REGISTER_READ_BITS (controlReg, &ofe, IX_PIUMH_PIU_CTL_OFE); + + /* if the interrupt is disabled then we must enable it */ + if (!ofe) + { + /* set the OFE (OutFifoEnable) bit of the control register */ + /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ + /* time for the write to have effect */ + IX_PIUMH_REGISTER_WRITE_BITS (controlReg, + (IX_PIUMH_PIU_CTL_OFE | + IX_PIUMH_PIU_CTL_OFEWE), + (IX_PIUMH_PIU_CTL_OFE | + IX_PIUMH_PIU_CTL_OFEWE)); + } + + /* return the previous state of the interrupt */ + return (ofe != 0); +} + +/* + * Function definition: ixPiuMhConfigPiuInterruptDisable + */ + +BOOL ixPiuMhConfigPiuInterruptDisable ( + IxPiuMhPiuId piuId) +{ + UINT32 ofe; + volatile UINT32 *controlReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].controlRegister; + + /* get the OFE (OutFifoEnable) bit of the control register */ + IX_PIUMH_REGISTER_READ_BITS (controlReg, &ofe, IX_PIUMH_PIU_CTL_OFE); + + /* if the interrupt is enabled then we must disable it */ + if (ofe) + { + /* unset the OFE (OutFifoEnable) bit of the control register */ + /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ + /* time for the write to have effect */ + IX_PIUMH_REGISTER_WRITE_BITS (controlReg, + (0 | + IX_PIUMH_PIU_CTL_OFEWE), + (IX_PIUMH_PIU_CTL_OFE | + IX_PIUMH_PIU_CTL_OFEWE)); + } + + /* return the previous state of the interrupt */ + return (ofe != 0); +} + +/* + * Function definition: ixPiuMhConfigMessageIdGet + */ + +IxPiuMhMessageId ixPiuMhConfigMessageIdGet ( + IxPiuMhMessage message) +{ + /* return the most-significant byte of the first word of the */ + /* message */ + return ((IxPiuMhMessageId) ((message.data[0] >> + IX_PIUMH_MESSAGE_ID_OFFSET) & 0xFF)); +} + +/* + * Function definition: ixPiuMhConfigPiuIdIsValid + */ + +BOOL ixPiuMhConfigPiuIdIsValid ( + IxPiuMhPiuId piuId) +{ + /* check that the piuId parameter is within the range of valid IDs */ + return (piuId >= 0 && piuId < IX_PIUMH_NUM_PIUS); +} + +/* + * Function definition: ixPiuMhConfigLockGet + */ + +void ixPiuMhConfigLockGet ( + IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigLockGet\n"); + + /* lock the mutex for this PIU */ + (void) ixOsalMutexLock (&ixPiuMhConfigPiuInfo[piuId].mutex, + IX_OSAL_WAIT_FOREVER); + + /* disable the PIU's "outFIFO not empty" interrupt */ + ixPiuMhConfigPiuInfo[piuId].oldInterruptState = + ixPiuMhConfigPiuInterruptDisable (piuId); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigLockGet\n"); +} + +/* + * Function definition: ixPiuMhConfigLockRelease + */ + +void ixPiuMhConfigLockRelease ( + IxPiuMhPiuId piuId) +{ + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhConfigLockRelease\n"); + + /* if the interrupt was previously enabled */ + if (ixPiuMhConfigPiuInfo[piuId].oldInterruptState) + { + /* enable the PIU's "outFIFO not empty" interrupt */ + ixPiuMhConfigPiuInfo[piuId].oldInterruptState = + ixPiuMhConfigPiuInterruptEnable (piuId); + } + + /* unlock the mutex for this PIU */ + (void) ixOsalMutexUnlock (&ixPiuMhConfigPiuInfo[piuId].mutex); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhConfigLockRelease\n"); +} + +/* + * Function definition: ixPiuMhConfigInFifoWrite + */ + +IX_STATUS ixPiuMhConfigInFifoWrite ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message) +{ + volatile UINT32 *piuInFifo = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].inFifoRegister; + UINT32 retriesCount = 0; + + /* write the first word of the message to the PIU's inFIFO */ + IX_PIUMH_REGISTER_WRITE (piuInFifo, message.data[0]); + + /* need to wait for room to write second word - see SCR #493, + poll for maximum number of retries, if exceed maximum + retries, exit from while loop */ + while ((IX_PIU_MH_MAX_NUM_OF_RETRIES > retriesCount) + && ixPiuMhConfigInFifoIsFull (piuId)) + { + retriesCount++; + } + + /* Return TIMEOUT status to caller, indicate that PIU Hang / Halt */ + if (IX_PIU_MH_MAX_NUM_OF_RETRIES == retriesCount) + { + return IX_PIUMH_CRITICAL_PIU_ERR; + } + + /* write the second word of the message to the PIU's inFIFO */ + IX_PIUMH_REGISTER_WRITE (piuInFifo, message.data[1]); + + /* record in the stats the maximum number of retries needed */ + if (ixPiuMhConfigStats[piuId].maxInFifoFullRetries < retriesCount) + { + ixPiuMhConfigStats[piuId].maxInFifoFullRetries = retriesCount; + } + + /* update statistical info */ + ixPiuMhConfigStats[piuId].inFifoWrites++; + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhConfigOutFifoRead + */ + +IX_STATUS ixPiuMhConfigOutFifoRead ( + IxPiuMhPiuId piuId, + IxPiuMhMessage *message) +{ + volatile UINT32 *piuOutFifo = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].outFifoRegister; + + /* read the first word of the message from the PIU's outFIFO */ + IX_PIUMH_REGISTER_READ (piuOutFifo, &message->data[0]); + +#if !defined(__ep805xx) + UINT32 retriesCount = 0; + /* need to wait for PIU to write second word - see SCR #493 + poll for maximum number of retries, if exceed maximum + retries, exit from while loop */ + while ((IX_PIU_MH_MAX_NUM_OF_RETRIES > retriesCount) + && ixPiuMhConfigOutFifoIsEmpty (piuId)) + { + retriesCount++; + } + + /* Return TIMEOUT status to caller, indicate that PIU Hang / Halt */ + if (IX_PIU_MH_MAX_NUM_OF_RETRIES == retriesCount) + { + return IX_PIUMH_CRITICAL_PIU_ERR; + } + + /* record in the stats the maximum number of retries needed */ + if (ixPiuMhConfigStats[piuId].maxOutFifoEmptyRetries < retriesCount) + { + ixPiuMhConfigStats[piuId].maxOutFifoEmptyRetries = retriesCount; + } +#endif /* #if !defined(__ep805xx) */ + + /* read the second word of the message from the PIU's outFIFO */ + IX_PIUMH_REGISTER_READ (piuOutFifo, &message->data[1]); + + /* update statistical info */ + ixPiuMhConfigStats[piuId].outFifoReads++; + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhConfigShow + */ + +void ixPiuMhConfigShow ( + IxPiuMhPiuId piuId) +{ + /* show the message fifo read counter */ + IX_PIUMH_SHOW ("Message FIFO reads", + ixPiuMhConfigStats[piuId].outFifoReads); + + /* show the message fifo write counter */ + IX_PIUMH_SHOW ("Message FIFO writes", + ixPiuMhConfigStats[piuId].inFifoWrites); + + /* show the max retries performed when inFIFO full */ + IX_PIUMH_SHOW ("Max inFIFO Full retries", + ixPiuMhConfigStats[piuId].maxInFifoFullRetries); + + /* show the max retries performed when outFIFO empty */ + IX_PIUMH_SHOW ("Max outFIFO Empty retries", + ixPiuMhConfigStats[piuId].maxOutFifoEmptyRetries); + + /* show the current status of the inFifo */ + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "InFifo is %s and %s\n", + (ixPiuMhConfigInFifoIsEmpty (piuId) ? + (int) "EMPTY" : (int) "NOT EMPTY"), + (ixPiuMhConfigInFifoIsFull (piuId) ? + (int) "FULL" : (int) "NOT FULL"), + 0, 0, 0, 0); + + /* show the current status of the outFifo */ + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, + "OutFifo is %s and %s\n", + (ixPiuMhConfigOutFifoIsEmpty (piuId) ? + (int) "EMPTY" : (int) "NOT EMPTY"), + (ixPiuMhConfigOutFifoIsFull (piuId) ? + (int) "FULL" : (int) "NOT FULL"), + 0, 0, 0, 0); +} + +/* + * Function definition: ixPiuMhConfigShowReset + */ + +void ixPiuMhConfigShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the message fifo read counter */ + ixPiuMhConfigStats[piuId].outFifoReads = 0; + + /* reset the message fifo write counter */ + ixPiuMhConfigStats[piuId].inFifoWrites = 0; + + /* reset the max inFIFO Full retries counter */ + ixPiuMhConfigStats[piuId].maxInFifoFullRetries = 0; + + /* reset the max outFIFO empty retries counter */ + ixPiuMhConfigStats[piuId].maxOutFifoEmptyRetries = 0; +} + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhDll.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhDll.c new file mode 100644 index 0000000..d01b0bb --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhDll.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * + * Use of this source code is subject to the terms of the Microsoft end-user + * license agreement (EULA) under which you licensed this SOFTWARE PRODUCT. + * If you did not accept the terms of the EULA, you are not authorized to use + * this source code. For a copy of the EULA, please see the LICENSE.RTF on your + * install media. +*/ +/** + * @file IxPiuMhDll.c + * + * @date June 23, 2003 + * + * @description Contents are the implementation for the piuMh layer + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifdef __wince + +/* + * System Defined Include Files + */ + +/* + * User Defined Header Files + */ +#include "IxOsalTypes.h" + +/* + * Macro Definitions + */ + +/* + * Type Definitions + */ + +/* + * Variable Declarations + */ + +/* + * Extern Function Prototypes + */ + +/* + * Static Function Prototypes + */ + +/* + * Function Definition + */ + +BOOL APIENTRY +IxPiuMhDllMain( + HANDLE hModule, + DWORD ul_reason_for_call, + LPVOID lpReserved) +{ + switch (ul_reason_for_call) + { + case DLL_PROCESS_ATTACH: + break; + case DLL_THREAD_ATTACH: + break; + case DLL_THREAD_DETACH: + break; + case DLL_PROCESS_DETACH: + break; + } + + return TRUE; +} + +#endif /* def __wince */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhReceive.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhReceive.c new file mode 100644 index 0000000..ee8737f --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhReceive.c @@ -0,0 +1,364 @@ +/** + * @file IxPiuMhReceive.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for + * the Receive module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ +#include "IxOsal.h" +#include "IxPiuMhMacros_p.h" +#include "IxPiuMhConfig_p.h" +#include "IxPiuMhReceive_p.h" +#include "IxPiuMhSolicitedCbMgr_p.h" +#include "IxPiuMhUnsolicitedCbMgr_p.h" + +/* + * #defines and macros used in this file. + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhReceiveStats + * + * @brief This structure is used to maintain statistics for the Receive + * module. + */ + +typedef struct +{ + UINT32 isrs; /**< receive ISR invocations */ + UINT32 receives; /**< receive messages invocations */ + UINT32 messages; /**< messages received */ + UINT32 solicited; /**< solicited messages received */ + UINT32 unsolicited; /**< unsolicited messages received */ + UINT32 callbacks; /**< callbacks invoked */ +} IxPiuMhReceiveStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE IxPiuMhReceiveStats ixPiuMhReceiveStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ +PRIVATE +void ixPiuMhReceiveIsr (int piuId); + +PRIVATE +void ixPiuMhReceiveIsr (int piuId) +{ + int lockKey; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhReceiveIsr\n"); + + lockKey = ixOsalIrqLock (); + + /* invoke the message receive routine to get messages from the PIU */ + ixPiuMhReceiveMessagesReceive (piuId); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].isrs++; + + ixOsalIrqUnlock (lockKey); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhReceiveIsr\n"); +} + +/* + * Function definition: ixPiuMhReceiveInitialize + */ + +void ixPiuMhReceiveInitialize (void) +{ + IxPiuMhPiuId piuId = 0; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhReceiveInitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* register our internal ISR for the PIU to handle "outFIFO not */ + /* empty" interrupts */ + ixPiuMhConfigIsrRegister (piuId, ixPiuMhReceiveIsr); + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhReceiveInitialize\n"); +} + +/* + * Function definition: ixPiuMhReceiveUninitialize + */ +void ixPiuMhReceiveUninitialize (void) +{ + IxPiuMhPiuId piuId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhReceiveUninitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* unregister and set ISR to NULL */ + ixPiuMhConfigIsrUnregister (piuId); + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhReceiveUninitialize\n"); + +} + +/* + * Function definition: ixPiuMhReceiveMessagesReceive + */ + +IX_STATUS ixPiuMhReceiveMessagesReceive ( + IxPiuMhPiuId piuId) +{ + IxPiuMhMessage message = { { 0, 0 } }; + IxPiuMhMessageId messageId = 0; + IxPiuMhCallback callback = NULL; + IX_STATUS status; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhReceiveMessagesReceive\n"); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].receives++; + + /* while the PIU has messages in its outFIFO */ + while (!ixPiuMhConfigOutFifoIsEmpty (piuId)) + { + /* read a message from the PIU's outFIFO */ + status = ixPiuMhConfigOutFifoRead (piuId, &message); + + if (IX_SUCCESS != status) + { + return status; + } + + /* get the ID of the message */ + messageId = ixPiuMhConfigMessageIdGet (message); + + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, + "Received message from PIU %d with ID 0x%02X\n", + piuId, messageId); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].messages++; + + /* try to find a matching unsolicited callback for this message. */ + + /* we assume the message is unsolicited. only if there is no */ + /* unsolicited callback for this message type do we assume the */ + /* message is solicited. it is much faster to check for an */ + /* unsolicited callback, so doing this check first should result */ + /* in better performance. */ + + ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + piuId, messageId, &callback); + + if (callback != NULL) + { + IX_PIUMH_TRACE0 (IX_PIUMH_DEBUG, + "Found matching unsolicited callback\n"); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].unsolicited++; + } + + /* if no unsolicited callback was found try to find a matching */ + /* solicited callback for this message */ + if (callback == NULL) + { + ixPiuMhSolicitedCbMgrCallbackRetrieve ( + piuId, messageId, &callback); + + if (callback != NULL) + { + IX_PIUMH_TRACE0 (IX_PIUMH_DEBUG, + "Found matching solicited callback\n"); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].solicited++; + } + } + + /* if a callback (either unsolicited or solicited) was found */ + if (callback != NULL) + { + /* invoke the callback to pass the message back to the client */ + callback (piuId, message); + + /* update statistical info */ + ixPiuMhReceiveStats[piuId].callbacks++; + } + else /* no callback (neither unsolicited nor solicited) was found */ + { + IX_PIUMH_TRACE2 (IX_PIUMH_WARNING, + "No matching callback for PIU %d" + " and ID 0x%02X, discarding message\n", + piuId, messageId); + + /* the message will be discarded. this is normal behaviour */ + /* if the client passes a NULL solicited callback when */ + /* sending a message. this indicates that the client is not */ + /* interested in receiving the response. alternatively a */ + /* NULL callback here may signify an unsolicited message */ + /* with no appropriate registered callback. */ + } + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhReceiveMessagesReceive\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhReceiveShow + */ + +void ixPiuMhReceiveShow ( + IxPiuMhPiuId piuId) +{ + /* show the ISR invocation counter */ + IX_PIUMH_SHOW ("Receive ISR invocations", + ixPiuMhReceiveStats[piuId].isrs); + + /* show the receive message invocation counter */ + IX_PIUMH_SHOW ("Receive messages invocations", + ixPiuMhReceiveStats[piuId].receives); + + /* show the message received counter */ + IX_PIUMH_SHOW ("Messages received", + ixPiuMhReceiveStats[piuId].messages); + + /* show the solicited message counter */ + IX_PIUMH_SHOW ("Solicited messages received", + ixPiuMhReceiveStats[piuId].solicited); + + /* show the unsolicited message counter */ + IX_PIUMH_SHOW ("Unsolicited messages received", + ixPiuMhReceiveStats[piuId].unsolicited); + + /* show the callback invoked counter */ + IX_PIUMH_SHOW ("Callbacks invoked", + ixPiuMhReceiveStats[piuId].callbacks); + + /* show the message discarded counter */ + IX_PIUMH_SHOW ("Received messages discarded", + (ixPiuMhReceiveStats[piuId].messages - + ixPiuMhReceiveStats[piuId].callbacks)); +} + +/* + * Function definition: ixPiuMhReceiveShowReset + */ + +void ixPiuMhReceiveShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the ISR invocation counter */ + ixPiuMhReceiveStats[piuId].isrs = 0; + + /* reset the receive message invocation counter */ + ixPiuMhReceiveStats[piuId].receives = 0; + + /* reset the message received counter */ + ixPiuMhReceiveStats[piuId].messages = 0; + + /* reset the solicited message counter */ + ixPiuMhReceiveStats[piuId].solicited = 0; + + /* reset the unsolicited message counter */ + ixPiuMhReceiveStats[piuId].unsolicited = 0; + + /* reset the callback invoked counter */ + ixPiuMhReceiveStats[piuId].callbacks = 0; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSend.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSend.c new file mode 100644 index 0000000..5950352 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSend.c @@ -0,0 +1,327 @@ +/** + * @file IxPiuMhSend.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for + * the Send module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ + +#include "IxPiuMhMacros_p.h" + +#include "IxPiuMhConfig_p.h" +#include "IxPiuMhSend_p.h" +#include "IxPiuMhSolicitedCbMgr_p.h" + +/* + * #defines and macros used in this file. + */ + +/** + * @def IX_PIUMH_INFIFO_RETRY_DELAY_US + * + * @brief Amount of time (uSecs) to delay between retries + * while inFIFO is Full when attempting to send a message + */ +#define IX_PIUMH_INFIFO_RETRY_DELAY_US (1) + + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhSendStats + * + * @brief This structure is used to maintain statistics for the Send + * module. + */ + +typedef struct +{ + UINT32 sends; /**< send invocations */ + UINT32 sendWithResponses; /**< send with response invocations */ + UINT32 queueFulls; /**< fifo queue full occurrences */ + UINT32 queueFullRetries; /**< fifo queue full retry occurrences */ + UINT32 maxQueueFullRetries; /**< max fifo queue full retries */ + UINT32 callbackFulls; /**< callback list full occurrences */ +} IxPiuMhSendStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE IxPiuMhSendStats ixPiuMhSendStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ +PRIVATE +BOOL ixPiuMhSendInFifoIsFull( + IxPiuMhPiuId piuId, + UINT32 maxSendRetries); + +/* + * Function definition: ixPiuMhSendInFifoIsFull + */ + +PRIVATE +BOOL ixPiuMhSendInFifoIsFull( + IxPiuMhPiuId piuId, + UINT32 maxSendRetries) +{ + BOOL isFull = FALSE; + UINT32 numRetries = 0; + + /* check the PIU's inFIFO */ + isFull = ixPiuMhConfigInFifoIsFull (piuId); + + /* we retry a few times, just to give the PIU a chance to read from */ + /* the FIFO if the FIFO is currently full */ + while (isFull && (numRetries < maxSendRetries)) + { + numRetries++; + if (numRetries >= IX_PIUMH_SEND_RETRIES_DEFAULT) + { + /* Delay here for as short a time as possible (1 us). */ + /* Adding a delay here should ensure we are not hogging */ + /* the AHB bus while we are retrying */ + ixOsalBusySleep (IX_PIUMH_INFIFO_RETRY_DELAY_US); + } + + /* re-check the PIU's inFIFO */ + isFull = ixPiuMhConfigInFifoIsFull (piuId); + + /* update statistical info */ + ixPiuMhSendStats[piuId].queueFullRetries++; + } + + /* record the highest number of retries that occurred */ + if (ixPiuMhSendStats[piuId].maxQueueFullRetries < numRetries) + { + ixPiuMhSendStats[piuId].maxQueueFullRetries = numRetries; + } + + if (isFull) + { + /* update statistical info */ + ixPiuMhSendStats[piuId].queueFulls++; + } + + return isFull; +} + +/* + * Function definition: ixPiuMhSendMessageSend + */ + +IX_STATUS ixPiuMhSendMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries) +{ + IX_STATUS status; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSendMessageSend\n"); + + /* update statistical info */ + ixPiuMhSendStats[piuId].sends++; + + /* check if the PIU's inFIFO is full - if so return an error */ + if (ixPiuMhSendInFifoIsFull (piuId, maxSendRetries)) + { + IX_PIUMH_TRACE0 (IX_PIUMH_WARNING, "PIU's inFIFO is full\n"); + return IX_FAIL; + } + + /* write the message to the PIU's inFIFO */ + status = ixPiuMhConfigInFifoWrite (piuId, message); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSendMessageSend\n"); + + return status; +} + +/* + * Function definition: ixPiuMhSendMessageWithResponseSend + */ + +IX_STATUS ixPiuMhSendMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries) +{ + IX_STATUS status = IX_SUCCESS; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSendMessageWithResponseSend\n"); + + /* update statistical info */ + ixPiuMhSendStats[piuId].sendWithResponses++; + + /* check if the PIU's inFIFO is full - if so return an error */ + if (ixPiuMhSendInFifoIsFull (piuId, maxSendRetries)) + { + IX_PIUMH_TRACE0 (IX_PIUMH_WARNING, "PIU's inFIFO is full\n"); + return IX_FAIL; + } + + /* save the solicited callback */ + status = ixPiuMhSolicitedCbMgrCallbackSave ( + piuId, solicitedMessageId, solicitedCallback); + if (status != IX_SUCCESS) + { + IX_PIUMH_ERROR_REPORT ("Failed to save solicited callback\n"); + + /* update statistical info */ + ixPiuMhSendStats[piuId].callbackFulls++; + + return status; + } + + /* write the message to the PIU's inFIFO */ + status = ixPiuMhConfigInFifoWrite (piuId, message); + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSendMessageWithResponseSend\n"); + + return status; +} + +/* + * Function definition: ixPiuMhSendShow + */ + +void ixPiuMhSendShow ( + IxPiuMhPiuId piuId) +{ + /* show the message send invocation counter */ + IX_PIUMH_SHOW ("Send invocations", + ixPiuMhSendStats[piuId].sends); + + /* show the message send with response invocation counter */ + IX_PIUMH_SHOW ("Send with response invocations", + ixPiuMhSendStats[piuId].sendWithResponses); + + /* show the fifo queue full occurrence counter */ + IX_PIUMH_SHOW ("Fifo queue full occurrences", + ixPiuMhSendStats[piuId].queueFulls); + + /* show the fifo queue full retry occurrence counter */ + IX_PIUMH_SHOW ("Fifo queue full retry occurrences", + ixPiuMhSendStats[piuId].queueFullRetries); + + /* show the fifo queue full maximum retries counter */ + IX_PIUMH_SHOW ("Maximum fifo queue full retries", + ixPiuMhSendStats[piuId].maxQueueFullRetries); + + /* show the callback list full occurrence counter */ + IX_PIUMH_SHOW ("Solicited callback list full occurrences", + ixPiuMhSendStats[piuId].callbackFulls); +} + +/* + * Function definition: ixPiuMhSendShowReset + */ + +void ixPiuMhSendShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the message send invocation counter */ + ixPiuMhSendStats[piuId].sends = 0; + + /* reset the message send with response invocation counter */ + ixPiuMhSendStats[piuId].sendWithResponses = 0; + + /* reset the fifo queue full occurrence counter */ + ixPiuMhSendStats[piuId].queueFulls = 0; + + /* reset the fifo queue full retry occurrence counter */ + ixPiuMhSendStats[piuId].queueFullRetries = 0; + + /* reset the max fifo queue full retries counter */ + ixPiuMhSendStats[piuId].maxQueueFullRetries = 0; + + /* reset the callback list full occurrence counter */ + ixPiuMhSendStats[piuId].callbackFulls = 0; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSolicitedCbMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSolicitedCbMgr.c new file mode 100644 index 0000000..c8e8fb1 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSolicitedCbMgr.c @@ -0,0 +1,436 @@ +/** + * @file IxPiuMhSolicitedCbMgr.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for + * the Solicited Callback Manager module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ +#ifndef IXPIUMHCONFIG_P_H +# define IXPIUMHSOLICITEDCBMGR_C +#else +# error "Error, IxPiuMhConfig_p.h should not be included before this defn." +#endif + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ + +#include "IxOsal.h" + +#include "IxPiuMhMacros_p.h" +#include "IxPiuMhSolicitedCbMgr_p.h" +#include "IxPiuMhConfig_p.h" +/* + * #defines and macros used in this file. + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhSolicitedCallbackListEntry + * + * @brief This structure is used to store the information associated with + * an entry in the callback list. This consists of the ID of the send + * message (which indicates the ID of the corresponding response message) + * and the callback function pointer itself. + * + */ +typedef struct IxPiuMhSolicitedCallbackListEntry +{ + /** message ID */ + IxPiuMhMessageId messageId; + + /** callback function pointer */ + IxPiuMhCallback callback; + + /** pointer to next entry in the list */ + struct IxPiuMhSolicitedCallbackListEntry *next; +} IxPiuMhSolicitedCallbackListEntry; + +/** + * @struct IxPiuMhSolicitedCallbackList + * + * @brief This structure is used to maintain the list of response + * callbacks. The number of entries in this list will be variable, and + * they will be stored in a linked list fashion for ease of addition and + * removal. The entries themselves are statically allocated, and are + * organised into a "free" list and a "callback" list. Adding an entry + * means taking an entry from the "free" list and adding it to the + * "callback" list. Removing an entry means removing it from the + * "callback" list and returning it to the "free" list. + */ + +typedef struct +{ + /** pointer to the head of the free list */ + IxPiuMhSolicitedCallbackListEntry *freeHead; + + /** pointer to the head of the callback list */ + IxPiuMhSolicitedCallbackListEntry *callbackHead; + + /** pointer to the tail of the callback list */ + IxPiuMhSolicitedCallbackListEntry *callbackTail; + + /** array of entries - the first entry is used as a dummy entry to */ + /* avoid the scenario of having an empty list, hence '+ 1' */ + IxPiuMhSolicitedCallbackListEntry entries[IX_PIUMH_MAX_CALLBACKS + 1]; +} IxPiuMhSolicitedCallbackList; + +/** + * @struct IxPiuMhSolicitedCbMgrStats + * + * @brief This structure is used to maintain statistics for the Solicited + * Callback Manager module. + */ + +typedef struct +{ + UINT32 saves; /**< callback list saves */ + UINT32 retrieves; /**< callback list retrieves */ +} IxPiuMhSolicitedCbMgrStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE IxPiuMhSolicitedCallbackList +ixPiuMhSolicitedCbMgrCallbackLists[IX_PIUMH_NUM_PIUS]; + +PRIVATE IxPiuMhSolicitedCbMgrStats +ixPiuMhSolicitedCbMgrStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ + +/* + * Function definition: ixPiuMhSolicitedCbMgrInitialize + */ + +void ixPiuMhSolicitedCbMgrInitialize (void) +{ + IxPiuMhPiuId piuId; + UINT32 localIndex; + IxPiuMhSolicitedCallbackList *list = NULL; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSolicitedCbMgrInitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* initialise a pointer to the list for convenience */ + list = &ixPiuMhSolicitedCbMgrCallbackLists[piuId]; + + /* for each entry in the list, after the dummy entry ... */ + for (localIndex = 1; localIndex <= IX_PIUMH_MAX_CALLBACKS; localIndex++) + { + /* initialise the entry */ + list->entries[localIndex].messageId = 0x00; + list->entries[localIndex].callback = NULL; + + /* if this entry is before the last entry */ + if (localIndex < IX_PIUMH_MAX_CALLBACKS) + { + /* chain this entry to the following entry */ + list->entries[localIndex].next = + &(list->entries[localIndex + 1]); + } + else /* this entry is the last entry */ + { + /* the last entry isn't chained to anything */ + list->entries[localIndex].next = NULL; + } + } + + /* set the free list pointer to point to the first real entry */ + /* (all real entries begin chained together on the free list) */ + list->freeHead = &(list->entries[1]); + + /* set the callback list pointers to point to the dummy entry */ + /* (the callback list is initially empty) */ + list->callbackHead = &(list->entries[0]); + list->callbackTail = &(list->entries[0]); + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSolicitedCbMgrInitialize\n"); +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrUninitialize + */ +void ixPiuMhSolicitedCbMgrUninitialize (void) +{ + IxPiuMhPiuId piuId; + UINT32 localIndex; + IxPiuMhSolicitedCallbackList *list; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSolicitedCbMgrUninitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* initialise a pointer to the list for convenience */ + list = &ixPiuMhSolicitedCbMgrCallbackLists[piuId]; + + /* for each entry in the list, after the dummy entry ... */ + for (localIndex = 1; localIndex <= IX_PIUMH_MAX_CALLBACKS; localIndex++) + { + /* initialise the entry */ + list->entries[localIndex].messageId = 0x00; + list->entries[localIndex].callback = NULL; + + /* if this entry is before the last entry */ + if (IX_PIUMH_MAX_CALLBACKS > localIndex) + { + /* chain this entry to the following entry */ + list->entries[localIndex].next = + &(list->entries[localIndex + 1]); + } + else /* this entry is the last entry */ + { + /* the last entry isn't chained to anything */ + list->entries[localIndex].next = NULL; + } + } + /* set the free list pointer to point to the first real entry */ + /* (all real entries begin chained together on the free list) */ + list->freeHead = &(list->entries[1]); + + /* set the callback list pointers to point to the dummy entry */ + /* (the callback list is initially empty) */ + list->callbackHead = &(list->entries[0]); + list->callbackTail = &(list->entries[0]); + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSolicitedCbMgrUninitialize\n"); + +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrCallbackSave + */ + +IX_STATUS ixPiuMhSolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback) +{ + IxPiuMhSolicitedCallbackList *list = NULL; + IxPiuMhSolicitedCallbackListEntry *callbackEntry = NULL; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhSolicitedCbMgrCallbackSave\n"); + + /* initialise a pointer to the list for convenience */ + list = &ixPiuMhSolicitedCbMgrCallbackLists[piuId]; + + /* check to see if there are any entries in the free list */ + if (list->freeHead == NULL) + { + IX_PIUMH_ERROR_REPORT ("Solicited callback list is full\n"); + return IX_FAIL; + } + + /* there is an entry in the free list we can use */ + + /* update statistical info */ + ixPiuMhSolicitedCbMgrStats[piuId].saves++; + + /* remove a callback entry from the start of the free list */ + callbackEntry = list->freeHead; + list->freeHead = callbackEntry->next; + + /* fill in the callback entry with the new data */ + callbackEntry->messageId = solicitedMessageId; + callbackEntry->callback = solicitedCallback; + + /* the new callback entry will be added to the tail of the callback */ + /* list, so it isn't chained to anything */ + callbackEntry->next = NULL; + + /* chain new callback entry to the last entry of the callback list */ + list->callbackTail->next = callbackEntry; + list->callbackTail = callbackEntry; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhSolicitedCbMgrCallbackSave\n"); + + return IX_SUCCESS; +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrCallbackRetrieve + */ + +void ixPiuMhSolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback *solicitedCallback) +{ + IxPiuMhSolicitedCallbackList *list = NULL; + IxPiuMhSolicitedCallbackListEntry *callbackEntry = NULL; + IxPiuMhSolicitedCallbackListEntry *previousEntry = NULL; + + /* initialise a pointer to the list for convenience */ + list = &ixPiuMhSolicitedCbMgrCallbackLists[piuId]; + + /* initialise the callback entry to the first entry of the callback */ + /* list - we must skip over the dummy entry, which is the previous */ + if (list != NULL) + { + callbackEntry = list->callbackHead->next; + previousEntry = list->callbackHead; + } + + /* traverse the callback list looking for an entry with a matching */ + /* message ID. note we also save the previous entry's pointer to */ + /* allow us to unchain the matching entry from the callback list */ + while ((callbackEntry != NULL) && + (callbackEntry->messageId != solicitedMessageId)) + { + previousEntry = callbackEntry; + callbackEntry = callbackEntry->next; + } + + /* if we didn't find a matching callback entry */ + if (callbackEntry == NULL) + { + /* return a NULL callback in the outgoing parameter */ + *solicitedCallback = NULL; + } + else /* we found a matching callback entry */ + { + /* update statistical info */ + ixPiuMhSolicitedCbMgrStats[piuId].retrieves++; + + /* return the callback in the outgoing parameter */ + *solicitedCallback = callbackEntry->callback; + + /* unchain callback entry by chaining previous entry to next */ + previousEntry->next = callbackEntry->next; + + /* if the callback entry is at the tail of the list */ + if (list->callbackTail == callbackEntry) + { + /* update the tail of the callback list */ + list->callbackTail = previousEntry; + } + + /* re-initialise the callback entry */ + callbackEntry->messageId = 0x00; + callbackEntry->callback = NULL; + + /* add the callback entry to the start of the free list */ + callbackEntry->next = list->freeHead; + list->freeHead = callbackEntry; + } +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrShow + */ + +void ixPiuMhSolicitedCbMgrShow ( + IxPiuMhPiuId piuId) +{ + /* show the solicited callback list save counter */ + IX_PIUMH_SHOW ("Solicited callback list saves", + ixPiuMhSolicitedCbMgrStats[piuId].saves); + + /* show the solicited callback list retrieve counter */ + IX_PIUMH_SHOW ("Solicited callback list retrieves", + ixPiuMhSolicitedCbMgrStats[piuId].retrieves); +} + +/* + * Function definition: ixPiuMhSolicitedCbMgrShowReset + */ + +void ixPiuMhSolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the solicited callback list save counter */ + ixPiuMhSolicitedCbMgrStats[piuId].saves = 0; + + /* reset the solicited callback list retrieve counter */ + ixPiuMhSolicitedCbMgrStats[piuId].retrieves = 0; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSymbols.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSymbols.c new file mode 100644 index 0000000..e80f806 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhSymbols.c @@ -0,0 +1,110 @@ +/* + * @file IxPiuMhSymbols.c + * + * @author Intel Corporation + * @date 04-Oct-2002 + * + * @brief Contents are declarations for exported symbols for linux kernel + * module builds. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +#ifdef __linux + +#include <linux/module.h> +#include <IxPiuMh.h> + +EXPORT_SYMBOL(ixPiuMhPhysicalAddressSet); + +EXPORT_SYMBOL(ixPiuMhInitialize); +EXPORT_SYMBOL(ixPiuMhUnload); +EXPORT_SYMBOL(ixPiuMhUnsolicitedCallbackRegister); +EXPORT_SYMBOL(ixPiuMhUnsolicitedCallbackForRangeRegister); +EXPORT_SYMBOL(ixPiuMhMessageSend); +EXPORT_SYMBOL(ixPiuMhMessageWithResponseSend); +EXPORT_SYMBOL(ixPiuMhMessagesReceive); +EXPORT_SYMBOL(ixPiuMhShow); +EXPORT_SYMBOL(ixPiuMhShowReset); +EXPORT_SYMBOL(ixPiuMhInterruptIdSet); + +extern void ixPiuMhIsr (void *parameter); +extern BOOL ixPiuMhConfigInFifoIsFull(IxPiuMhPiuId piuId); +extern BOOL ixPiuMhConfigOutFifoIsEmpty (IxPiuMhPiuId piuId); +extern void ixPiuMhConfigLockRelease (IxPiuMhPiuId piuId); +extern void ixPiuMhConfigLockGet (IxPiuMhPiuId piuId); +extern void ixPiuMhConfigOutFifoRead (IxPiuMhPiuId piuId, + IxPiuMhMessage *message); +extern void ixPiuMhConfigInFifoWrite (IxPiuMhPiuId piuId, + IxPiuMhMessage message); + + +EXPORT_SYMBOL(ixPiuMhIsr); +EXPORT_SYMBOL(ixPiuMhConfigInFifoIsFull); +EXPORT_SYMBOL(ixPiuMhConfigOutFifoIsEmpty); +EXPORT_SYMBOL(ixPiuMhConfigLockRelease); +EXPORT_SYMBOL(ixPiuMhConfigLockGet); +EXPORT_SYMBOL(ixPiuMhConfigOutFifoRead); +EXPORT_SYMBOL(ixPiuMhConfigInFifoWrite); + + +#endif /* __linux */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhUnsolicitedCbMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhUnsolicitedCbMgr.c new file mode 100644 index 0000000..468b5e5 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/IxPiuMhUnsolicitedCbMgr.c @@ -0,0 +1,301 @@ +/** + * @file IxPiuMhUnsolicitedCbMgr.c + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @description Contents are the implementation of the private API for + * the Unsolicited Callback Manager module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/* + * Put the system defined include files required. + */ + + +/* + * Put the user defined include files required. + */ +#include "IxOsal.h" + +#include "IxPiuMhMacros_p.h" + +#include "IxPiuMhUnsolicitedCbMgr_p.h" + + +/* + * #defines and macros used in this file. + */ + +/* + * Typedefs whose scope is limited to this file. + */ + +/** + * @struct IxPiuMhUnsolicitedCallbackTable + * + * @brief This structure is used to maintain the list of registered + * callbacks. One entry exists for each message ID, and a NULL entry will + * signify that no callback has been registered for that ID. + */ + +typedef struct +{ + /** array of entries */ + IxPiuMhCallback entries[IX_PIUMH_MAX_MESSAGE_ID + 1]; +} IxPiuMhUnsolicitedCallbackTable; + +/** + * @struct IxPiuMhUnsolicitedCbMgrStats + * + * @brief This structure is used to maintain statistics for the Unsolicited + * Callback Manager module. + */ + +typedef struct +{ + UINT32 saves; /**< callback table saves */ + UINT32 overwrites; /**< callback table overwrites */ +} IxPiuMhUnsolicitedCbMgrStats; + +/* + * Variable declarations global to this file only. Externs are followed by + * static variables. + */ + +PRIVATE IxPiuMhUnsolicitedCallbackTable +ixPiuMhUnsolicitedCallbackTables[IX_PIUMH_NUM_PIUS]; + +PRIVATE IxPiuMhUnsolicitedCbMgrStats +ixPiuMhUnsolicitedCbMgrStats[IX_PIUMH_NUM_PIUS]; + +/* + * Extern function prototypes. + */ + +/* + * Static function prototypes. + */ + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrInitialize + */ + +void ixPiuMhUnsolicitedCbMgrInitialize (void) +{ + IxPiuMhPiuId piuId = 0; + IxPiuMhUnsolicitedCallbackTable *table = NULL; + IxPiuMhMessageId messageId = 0; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCbMgrInitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* initialise a pointer to the table for convenience */ + table = &ixPiuMhUnsolicitedCallbackTables[piuId]; + + /* for each message ID ... */ + for (messageId = IX_PIUMH_MIN_MESSAGE_ID; + messageId <= IX_PIUMH_MAX_MESSAGE_ID; messageId++) + { + /* initialise the callback for this message ID to NULL */ + table->entries[messageId] = NULL; + } + } + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCbMgrInitialize\n"); +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrCallbackSave + */ +void ixPiuMhUnsolicitedCbMgrUninitialize (void) +{ + IxPiuMhPiuId piuId; + IxPiuMhUnsolicitedCallbackTable *table; + IxPiuMhMessageId messageId; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCbMgrUninitialize\n"); + + /* for each PIU ... */ + for (piuId = 0; piuId < IX_PIUMH_NUM_PIUS; piuId++) + { + /* initialise a pointer to the table for convenience */ + table = &ixPiuMhUnsolicitedCallbackTables[piuId]; + + /* for each message ID ... */ + for (messageId = IX_PIUMH_MIN_MESSAGE_ID; + messageId <= IX_PIUMH_MAX_MESSAGE_ID; messageId++) + { + /* initialise the callback for this message ID to NULL */ + table->entries[messageId] = NULL; + } + } + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCbMgrUninitialize\n"); +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrCallbackSave + */ + +void ixPiuMhUnsolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback unsolicitedCallback) +{ + IxPiuMhUnsolicitedCallbackTable *table = NULL; + + /* initialise a pointer to the table for convenience */ + table = &ixPiuMhUnsolicitedCallbackTables[piuId]; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Entering " + "ixPiuMhUnsolicitedCbMgrCallbackSave\n"); + + /* update statistical info */ + ixPiuMhUnsolicitedCbMgrStats[piuId].saves++; + + /* check if there is a callback already registered for this PIU and */ + /* message ID */ + if (table->entries[unsolicitedMessageId] != NULL) + { + /* if we are overwriting an existing callback */ + if (unsolicitedCallback != NULL) + { + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "Unsolicited callback " + "overwriting existing callback for PIU ID %d " + "message ID 0x%02X\n", piuId, unsolicitedMessageId); + } + else /* if we are clearing an existing callback */ + { + IX_PIUMH_TRACE2 (IX_PIUMH_DEBUG, "NULL unsolicited callback " + "clearing existing callback for PIU ID %d " + "message ID 0x%02X\n", piuId, unsolicitedMessageId); + } + + /* update statistical info */ + ixPiuMhUnsolicitedCbMgrStats[piuId].overwrites++; + } + + /* save the callback into the table */ + table->entries[unsolicitedMessageId] = unsolicitedCallback; + + IX_PIUMH_TRACE0 (IX_PIUMH_FN_ENTRY_EXIT, "Exiting " + "ixPiuMhUnsolicitedCbMgrCallbackSave\n"); +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrCallbackRetrieve + */ + +void ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback *unsolicitedCallback) +{ + IxPiuMhUnsolicitedCallbackTable *table = NULL; + + /* initialise a pointer to the table for convenience */ + table = &ixPiuMhUnsolicitedCallbackTables[piuId]; + + /* retrieve the callback from the table */ + if (unsolicitedCallback != NULL) + { + *unsolicitedCallback = table->entries[unsolicitedMessageId]; + } +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrShow + */ + +void ixPiuMhUnsolicitedCbMgrShow ( + IxPiuMhPiuId piuId) +{ + /* show the unsolicited callback table save counter */ + IX_PIUMH_SHOW ("Unsolicited callback table saves", + ixPiuMhUnsolicitedCbMgrStats[piuId].saves); + + /* show the unsolicited callback table overwrite counter */ + IX_PIUMH_SHOW ("Unsolicited callback table overwrites", + ixPiuMhUnsolicitedCbMgrStats[piuId].overwrites); +} + +/* + * Function definition: ixPiuMhUnsolicitedCbMgrShowReset + */ + +void ixPiuMhUnsolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId) +{ + /* reset the unsolicited callback table save counter */ + ixPiuMhUnsolicitedCbMgrStats[piuId].saves = 0; + + /* reset the unsolicited callback table overwrite counter */ + ixPiuMhUnsolicitedCbMgrStats[piuId].overwrites = 0; +} diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/Makefile b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/Makefile new file mode 100644 index 0000000..3d4fcf1 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/Makefile @@ -0,0 +1,144 @@ +######################################################################### +# This Template Makefile will create the libraries, executables and module and place them in the output folder +# Remove the comments around the sections you wish to build for. +# +#Procedure +#1) Copy this template to the location of your source files +#2) "Common variables and defintions" must be filled out +#3) Edit as desired the "Libraries and executable section" and/or the "Linux kernel 2.6 Module section" depending on what you wish to build +#4) Remove the comments around the section and delete the other unnecessary section +#5) Save changes, return to command line and type "make". +# +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears all derived objects +# +# included makefiles +# common.mk - common defintions +# depend.mk - depend and cleandepend rules +# rules.mk - build rules. +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +# Ensure The ICP_BUILDSYSTEM_PATH envorionmental var is defined. +ifndef ICP_BUILDSYSTEM_PATH +$(error ICP_BUILDSYSTEM_PATH is undefined. Please set the path to the top of the build structure \ + "-> setenv ICP_BUILDSYSTEM_PATH <path>") +endif + +#Add your project environment Makefile, extra comment +include $(ICP_ENV_DIR)/environment.mk + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=$(ICP_TDM_MSG_HDLR_NAME) + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES= IxPiuMh.c \ + IxPiuMhConfig.c \ + IxPiuMhSend.c \ + IxPiuMhSolicitedCbMgr.c \ + IxPiuMhReceive.c \ + IxPiuMhDll.c \ + IxPiuMhUnsolicitedCbMgr.c + + +# Setup include directory +INCLUDES += -I $(src)/include \ + -I $(PWD)/include \ + -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_COMP_PATH)/include \ + -I $(ICP_OSAL_DIR)/common/include \ + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES += -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM -DENABLE_BUFFERMGT + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_TDM_MSG_HDLR_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + +# Install the module to the output dir +install: module + + +###################Include rules and dependency makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules and dependency inclusion######################### + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhConfig_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhConfig_p.h new file mode 100644 index 0000000..e4b2482 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhConfig_p.h @@ -0,0 +1,686 @@ +/** + * @file IxPiuMhConfig_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Configuration module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhConfig_p IxPiuMhConfig_p + * + * @brief The private API for the Configuration module. + * + * @{ + */ + +#ifndef IXPIUMHCONFIG_P_H +#define IXPIUMHCONFIG_P_H + +#include "IxOsal.h" + +#include "IxPiuMh.h" +#include "IxPiuMhMacros_p.h" + +/* + * inline definition + */ +/* enable function inlining for performances */ +#ifdef IXPIUMHSOLICITEDCBMGR_C +/* Non-inline functions will be defined in this translation unit. + Reason is that in GNU Compiler, if the Optimization is turn off, all extern inline + functions will not be compiled. +*/ +# ifndef __wince +# ifndef IXPIUMHCONFIG_INLINE +# define IXPIUMHCONFIG_INLINE +# endif +# else +# ifndef IXPIUMHCONFIG_INLINE +# define IXPIUMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN +# endif +# endif /* __wince*/ + +#else + +# ifndef IXPIUMHCONFIG_INLINE +# ifdef _DIAB_TOOL + /* DIAB does not allow both the funtion prototype and + * defintion to use extern + */ +# define IXPIUMHCONFIG_INLINE IX_OSAL_INLINE +# else +# define IXPIUMHCONFIG_INLINE IX_OSAL_INLINE_EXTERN +# endif +# endif /* IXPIUMHCONFIG_INLINE */ +#endif /* IXPIUMHSOLICITEDCBMGR_C */ +/* + * Typedefs and #defines, etc. + */ + +typedef void (*IxPiuMhConfigIsr) (int); /**< ISR function pointer */ + +/** + * @struct IxPiuMhConfigPiuInfo + * + * @brief This structure is used to maintain the configuration information + * associated with an PIU. + */ + +typedef struct +{ + IxOsalMutex mutex; /**< mutex */ + UINT32 interruptId; /**< interrupt ID */ +#if defined(__ep805xx) + UINT32 physicalRegisterBase;/**< register physical base address */ +#endif + UINT32 virtualRegisterBase; /**< register virtual base address */ + UINT32 statusRegister; /**< status register virtual address */ + UINT32 controlRegister; /**< control register virtual address */ + UINT32 inFifoRegister; /**< inFIFO register virutal address */ + UINT32 outFifoRegister; /**< outFIFO register virtual address */ + IxPiuMhConfigIsr isr; /**< isr routine for handling interrupt */ + BOOL oldInterruptState; /**< old interrupt state (TRUE => enabled) */ +} IxPiuMhConfigPiuInfo; + + +/* + * #defines for function return types, etc. + */ + +#define IX_PIUMH_PIUSTAT_OFFSET (0x002C) /**< PIU status register offset */ +#define IX_PIUMH_PIUCTL_OFFSET (0x0030) /**< PIU control register offset */ +#define IX_PIUMH_PIUFIFO_OFFSET (0x0038) /**< PIU FIFO register offset */ + +/* PIU control register bit definitions */ +#define IX_PIUMH_PIU_CTL_OFE (1 << 16) /**< OutFifoEnable */ +#define IX_PIUMH_PIU_CTL_IFE (1 << 17) /**< InFifoEnable */ +#define IX_PIUMH_PIU_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */ +#define IX_PIUMH_PIU_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable */ + +/* PIU status register bit definitions */ +#define IX_PIUMH_PIU_STAT_OFNE (1 << 16) /**< OutFifoNotEmpty */ +#define IX_PIUMH_PIU_STAT_IFNF (1 << 17) /**< InFifoNotFull */ +#define IX_PIUMH_PIU_STAT_OFNF (1 << 18) /**< OutFifoNotFull */ +#define IX_PIUMH_PIU_STAT_IFNE (1 << 19) /**< InFifoNotEmpty */ +#define IX_PIUMH_PIU_STAT_MBINT (1 << 20) /**< Mailbox interrupt */ +#define IX_PIUMH_PIU_STAT_IFINT (1 << 21) /**< InFifo interrupt */ +#define IX_PIUMH_PIU_STAT_OFINT (1 << 22) /**< OutFifo interrupt */ +#define IX_PIUMH_PIU_STAT_WFINT (1 << 23) /**< WatchFifo interrupt */ + +/* message offsets */ +#define IX_PIUMH_MESSAGE_ID_OFFSET (24) + +/* Hardware defs for IXP23XX */ +#if defined(__ixp23xx) +#include <asm/hardware.h> +#include <asm/arch/irqs.h> + +/* PIU-0 interrupt */ +#define IX_PIU_IRQ_DBG0 (IRQ_IXP23XX_DBG0) + +/* PIU-1 interrupt */ +#define IX_PIU_IRQ_DBG1 (IRQ_IXP23XX_DBG1) + +/* PIU-0 Base Physical Address */ +#define IX_PIU_PIU0_PHYS (IXP23XX_PIU0_PHYS) + +/* PIU-1 Base Physical Address */ +#define IX_PIU_PIU1_PHYS (IXP23XX_PIU1_PHYS) + + +#endif /* #if DEVICE == ixp23xx */ + +#if defined(__ixp42X) || defined(__ixp46X) || defined(__ixp5XX) + +/**< PIU register base address */ +#define IX_PIUMH_PIU_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE) + +#define IX_PIUMH_PIUA_OFFSET (0x6000) /**< PIU-A register base offset */ +#define IX_PIUMH_PIUB_OFFSET (0x7000) /**< PIU-B register base offset */ +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) +#define IX_PIUMH_PIUC_OFFSET (0x8000) /**< PIU-C register base offset */ +#endif + +/** PIU-A register base address */ +#define IX_PIUMH_PIUA_BASE (IX_PIUMH_PIU_BASE + IX_PIUMH_PIUA_OFFSET) +/** PIU-B register base address */ +#define IX_PIUMH_PIUB_BASE (IX_PIUMH_PIU_BASE + IX_PIUMH_PIUB_OFFSET) +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) +/** PIU-C register base address */ +#define IX_PIUMH_PIUC_BASE (IX_PIUMH_PIU_BASE + IX_PIUMH_PIUC_OFFSET) +#endif + +/* PIU-A configuration */ + +/** PIU-A interrupt */ +#define IX_PIUMH_PIUA_INT (IX_OSAL_IXP400_PIUA_IRQ_LVL) +/** PIU-A FIFO register */ +#define IX_PIUMH_PIUA_FIFO (IX_PIUMH_PIUA_BASE + IX_PIUMH_PIUFIFO_OFFSET) +/** PIU-A control register */ +#define IX_PIUMH_PIUA_CTL (IX_PIUMH_PIUA_BASE + IX_PIUMH_PIUCTL_OFFSET) +/** PIU-A status register */ +#define IX_PIUMH_PIUA_STAT (IX_PIUMH_PIUA_BASE + IX_PIUMH_PIUSTAT_OFFSET) + +/* PIU-B configuration */ + +/** PIU-B interrupt */ +#define IX_PIUMH_PIUB_INT (IX_OSAL_IXP400_PIUB_IRQ_LVL) +/** PIU-B FIFO register */ +#define IX_PIUMH_PIUB_FIFO (IX_PIUMH_PIUB_BASE + IX_PIUMH_PIUFIFO_OFFSET) +/** PIU-B control register */ +#define IX_PIUMH_PIUB_CTL (IX_PIUMH_PIUB_BASE + IX_PIUMH_PIUCTL_OFFSET) +/** PIU-B status register */ +#define IX_PIUMH_PIUB_STAT (IX_PIUMH_PIUB_BASE + IX_PIUMH_PIUSTAT_OFFSET) + +#if defined(__ixp42X) || defined(__ixp46X) && !defined(__ixp5XX) +/* PIU-C configuration */ + +/** PIU-C interrupt */ +#define IX_PIUMH_PIUC_INT (IX_OSAL_IXP400_PIUC_IRQ_LVL) +/** PIU-C FIFO register */ +#define IX_PIUMH_PIUC_FIFO (IX_PIUMH_PIUC_BASE + IX_PIUMH_PIUFIFO_OFFSET) +/** PIU-C control register */ +#define IX_PIUMH_PIUC_CTL (IX_PIUMH_PIUC_BASE + IX_PIUMH_PIUCTL_OFFSET) +/** PIU-C status register */ +#define IX_PIUMH_PIUC_STAT (IX_PIUMH_PIUC_BASE + IX_PIUMH_PIUSTAT_OFFSET) +#endif + +#endif + +/* Hardware defs for tolapai */ +#if defined(__ep805xx) + +/* PIU-0 interrupt */ +#define IX_PIU_IRQ_DBG0 193 + +// TODO - below is physical address for PIU on FPGA +// now being set by the setup driver +#define IX_PIU_PIU0_PHYS 0 + +/* size of mapped memory block used by PIU */ +#define IX_PIU_MAPPED_MEMORY_SIZE 0x1000 + + + +#endif /* #if defined(__ep805xx) */ + + +/** + * Variable declarations. Externs are followed by static variables. + */ +extern IxPiuMhConfigPiuInfo ixPiuMhConfigPiuInfo[IX_PIUMH_NUM_PIUS]; + + +/* + * Prototypes for interface functions. + */ + +#if defined(__ep805xx) +/** + * @fn void ixPiuMhConfigPhysicalAddressSet( + * IxPiuMhPiuId piuId, + * UINT32 address) + * + * @brief This function sets the physical base address for the given piu + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose physical base + * address will be set + * @param UINT32 address (in) - the address to set the physical address to + * + * @return No return value. + */ +void ixPiuMhConfigPhysicalAddressSet( + IxPiuMhPiuId piuId, + UINT32 address); + +/** + * @fn void ixPiuMhConfigInterruptIdSet( + * IxPiuMhPiuId piuId, + * UINT32 interruptId) + * + * @brief This function sets the interruptId for the given piu + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose physical base + * address will be set + * @param UINT32 interruptId (in) - the interruptId + * + * @return No return value. + */ +void ixPiuMhConfigInterruptIdSet( + IxPiuMhPiuId piuId, + UINT32 interruptId); + +#endif // #if defined(__ep805xx) + +/** + * @fn void ixPiuMhConfigInitialize ( + IxPiuMhPiuInterrupts piuInterrupts) + * + * @brief This function initialises the Configuration module. + * + * @param IxPiuMhPiuInterrupts piuInterrupts (in) - whether or not to + * service the PIU "outFIFO not empty" interrupts. + * + * @return No return value. + */ + +void ixPiuMhConfigInitialize ( + IxPiuMhPiuInterrupts piuInterrupts); + +/** + * @fn void ixPiuMhConfigUninit (void) + * + * @brief This function uninitialises the Configuration module. + * + * @return No return value. + */ + +void ixPiuMhConfigUninit (void); + +/** + * @fn void ixPiuMhConfigIsrRegister ( + IxPiuMhPiuId piuId, + IxPiuMhConfigIsr isr) + * + * @brief This function registers an ISR to handle PIU "outFIFO not + * empty" interrupts. + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose interrupt will + * be handled. + * @param IxPiuMhConfigIsr isr (in) - the ISR function pointer that the + * interrupt will trigger. + * + * @return No return value. + */ + +void ixPiuMhConfigIsrRegister ( + IxPiuMhPiuId piuId, + IxPiuMhConfigIsr isr); + +/** + * @fn void ixPiuMhConfigIsrUnregister (IxPiuMhPiuId piuId) + * + * @brief This function unregisters the ISR. + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose interrupt will + * be unregistered. + * + * @return No return value. + */ +void ixPiuMhConfigIsrUnregister (IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigPiuInterruptEnable ( + IxPiuMhPiuId piuId) + * + * @brief This function enables a PIU's "outFIFO not empty" interrupt. + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose interrupt will + * be enabled. + * + * @return Returns the previous state of the interrupt (TRUE => enabled). + */ + +BOOL ixPiuMhConfigPiuInterruptEnable ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigPiuInterruptDisable ( + IxPiuMhPiuId piuId) + * + * @brief This function disables a PIU's "outFIFO not empty" interrupt + * + * @param IxPiuMhPiuId piuId (in) - the ID of the PIU whose interrupt will + * be disabled. + * + * @return Returns the previous state of the interrupt (TRUE => enabled). + */ + +BOOL ixPiuMhConfigPiuInterruptDisable ( + IxPiuMhPiuId piuId); + +/** + * @fn IxPiuMhMessageId ixPiuMhConfigMessageIdGet ( + IxPiuMhMessage message) + * + * @brief This function gets the ID of a message. + * + * @param IxPiuMhMessage message (in) - the message to get the ID of. + * + * @return the ID of the message + */ + +IxPiuMhMessageId ixPiuMhConfigMessageIdGet ( + IxPiuMhMessage message); + +/** + * @fn BOOL ixPiuMhConfigPiuIdIsValid ( + IxPiuMhPiuId piuId) + * + * @brief This function checks to see if a PIU ID is valid. + * + * @param IxPiuMhPiuId piuId (in) - the PIU ID to validate. + * + * @return True if the PIU ID is valid, otherwise False. + */ + +BOOL ixPiuMhConfigPiuIdIsValid ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhConfigLockGet ( + IxPiuMhPiuId piuId) + * + * @brief This function gets a lock for exclusive PIU interaction, and + * disables the PIU's "outFIFO not empty" interrupt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which to get the + * lock and disable its interrupt. + * + * @return No return value. + */ + +void ixPiuMhConfigLockGet ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhConfigLockRelease ( + IxPiuMhPiuId piuId) + * + * @brief This function releases a lock for exclusive PIU interaction, and + * enables the PIU's "outFIFO not empty" interrupt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which to release + * the lock and enable its interrupt. + * + * @return No return value. + */ + +void ixPiuMhConfigLockRelease ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigInFifoIsEmpty ( + IxPiuMhPiuId piuId) + * + * @brief This inline function checks if a PIU's inFIFO is empty. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the inFIFO + * will be checked. + * + * @return True if the inFIFO is empty, otherwise False. + */ + +IXPIUMHCONFIG_INLINE BOOL ixPiuMhConfigInFifoIsEmpty ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigInFifoIsFull ( + IxPiuMhPiuId piuId) + * + * @brief This inline function checks if a PIU's inFIFO is full. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the inFIFO + * will be checked. + * + * @return True if the inFIFO is full, otherwise False. + */ + +IXPIUMHCONFIG_INLINE BOOL ixPiuMhConfigInFifoIsFull ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigOutFifoIsEmpty ( + IxPiuMhPiuId piuId) + * + * @brief This inline function checks if a PIU's outFIFO is empty. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the outFIFO + * will be checked. + * + * @return True if the outFIFO is empty, otherwise False. + */ + +IXPIUMHCONFIG_INLINE BOOL ixPiuMhConfigOutFifoIsEmpty ( + IxPiuMhPiuId piuId); + +/** + * @fn BOOL ixPiuMhConfigOutFifoIsFull ( + IxPiuMhPiuId piuId) + * + * @brief This inline function checks if a PIU's outFIFO is full. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the outFIFO + * will be checked. + * + * @return True if the outFIFO is full, otherwise False. + */ + +IXPIUMHCONFIG_INLINE BOOL ixPiuMhConfigOutFifoIsFull ( + IxPiuMhPiuId piuId); + +/** + * @fn IX_STATUS ixPiuMhConfigInFifoWrite ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message) + * + * @brief This function writes a message to a PIU's inFIFO. The caller + * must first check that the PIU's inFifo is not full. After writing the first + * word of the message, this function will keep polling PIU's inFIFO is not + * full to write the second word. If inFIFO is not available after maximum + * retries (IX_PIU_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT + * status to indicate PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the inFIFO + * will be written to. + * @param IxPiuMhMessage message (in) - The message to write. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhConfigInFifoWrite ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message); + +/** + * @fn IX_STATUS ixPiuMhConfigOutFifoRead ( + IxPiuMhPiuId piuId, + IxPiuMhMessage *message) + * + * @brief This function reads a message from a PIU's outFIFO. The caller + * must first check that the PIU's outFifo is not empty. After reading the first + * word of the message, this function will keep polling PIU's outFIFO is not + * empty to read the second word. If outFIFO is empty after maximum + * retries (IX_PIU_MH_MAX_NUM_OF_RETRIES), this function will return TIMEOUT + * status to indicate PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU for which the outFIFO + * will be read from. + * @param IxPiuMhMessage message (out) - The message read. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhConfigOutFifoRead ( + IxPiuMhPiuId piuId, + IxPiuMhMessage *message); + +/** + * @fn void ixPiuMhConfigShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Configuration + * module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return value. + */ + +void ixPiuMhConfigShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhConfigShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Configuration + * module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return value. + */ + +void ixPiuMhConfigShowReset ( + IxPiuMhPiuId piuId); + +/* + * Inline functions + */ + +/* + * This inline function checks if a PIU's inFIFO is empty. + */ + +IXPIUMHCONFIG_INLINE +BOOL ixPiuMhConfigInFifoIsEmpty ( + IxPiuMhPiuId piuId) +{ + UINT32 ifne; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + /* get the IFNE (InFifoNotEmpty) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ifne, IX_PIUMH_PIU_STAT_IFNE); + + /* if the IFNE status bit is unset then the inFIFO is empty */ + return (ifne == 0); +} + + +/* + * This inline function checks if a PIU's inFIFO is full. + */ +IXPIUMHCONFIG_INLINE +BOOL ixPiuMhConfigInFifoIsFull ( + IxPiuMhPiuId piuId) +{ + UINT32 ifnf; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + /* get the IFNF (InFifoNotFull) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ifnf, IX_PIUMH_PIU_STAT_IFNF); + + /* if the IFNF status bit is unset then the inFIFO is full */ + return (ifnf == 0); +} + + +/* + * This inline function checks if a PIU's outFIFO is empty. + */ +IXPIUMHCONFIG_INLINE +BOOL ixPiuMhConfigOutFifoIsEmpty ( + IxPiuMhPiuId piuId) +{ + UINT32 ofne; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + /* get the OFNE (OutFifoNotEmpty) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ofne, IX_PIUMH_PIU_STAT_OFNE); + + /* if the OFNE status bit is unset then the outFIFO is empty */ + return (ofne == 0); +} + +/* + * This inline function checks if a PIU's outFIFO is full. + */ +IXPIUMHCONFIG_INLINE +BOOL ixPiuMhConfigOutFifoIsFull ( + IxPiuMhPiuId piuId) +{ + UINT32 ofnf; + volatile UINT32 *statusReg = + (UINT32 *)ixPiuMhConfigPiuInfo[piuId].statusRegister; + + /* get the OFNF (OutFifoNotFull) bit of the status register */ + IX_PIUMH_REGISTER_READ_BITS (statusReg, &ofnf, IX_PIUMH_PIU_STAT_OFNF); + + /* if the OFNF status bit is unset then the outFIFO is full */ + return (ofnf == 0); +} + +#endif /* IXPIUMHCONFIG_P_H */ + +/** + * @} defgroup IxPiuMhConfig_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhMacros_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhMacros_p.h new file mode 100644 index 0000000..e2aea6a --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhMacros_p.h @@ -0,0 +1,319 @@ +/** + * @file IxPiuMhMacros_p.h + * + * @author Intel Corporation + * @date 21 Jan 2002 + * + * @brief This file contains the macros for the IxPiuMh component. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhMacros_p IxPiuMhMacros_p + * + * @brief Macros for the IxPiuMh component. + * + * @{ + */ + +#ifndef IXPIUMHMACROS_P_H +#define IXPIUMHMACROS_P_H + +/* if we are running as a unit test */ +#ifdef IX_UNIT_TEST +#undef NDEBUG +#endif /* #ifdef IX_UNIT_TEST */ + +#include "IxOsal.h" + +/* + * #defines for function return types, etc. + */ + +#define IX_PIUMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */ +#define IX_PIUMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */ + +/** + * @def IX_PIUMH_SHOW + * + * @brief Macro for displaying a stat preceded by a textual description. + */ + +#define IX_PIUMH_SHOW(TEXT, STAT) \ + ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \ + "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0) + +/* + * Prototypes for interface functions. + */ + +/** + * @typedef IxPiuMhTraceTypes + * + * @brief Enumeration defining IxPiuMh trace levels + */ + +typedef enum +{ + IX_PIUMH_TRACE_OFF = IX_OSAL_LOG_LVL_NONE, /**< no trace */ + IX_PIUMH_WARNING = IX_OSAL_LOG_LVL_WARNING, /**< warning */ + IX_PIUMH_DEBUG = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */ + IX_PIUMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3 /**< function entry/exit */ +} IxPiuMhTraceTypes; + +#ifdef IX_UNIT_TEST +#define IX_PIUMH_TRACE_LEVEL (IX_PIUMH_FN_ENTRY_EXIT) /**< trace level */ +#endif +#ifndef IX_UNIT_TEST +#define IX_PIUMH_TRACE_LEVEL (IX_PIUMH_TRACE_OFF) /**< trace level */ +#endif + +/** + * @def IX_PIUMH_TRACE0 + * + * @brief Trace macro taking 0 arguments. + */ + +#define IX_PIUMH_TRACE0(LEVEL, STR) \ + IX_PIUMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0) + +/** + * @def IX_PIUMH_TRACE1 + * + * @brief Trace macro taking 1 argument. + */ + +#define IX_PIUMH_TRACE1(LEVEL, STR, ARG1) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0) + +/** + * @def IX_PIUMH_TRACE2 + * + * @brief Trace macro taking 2 arguments. + */ + +#define IX_PIUMH_TRACE2(LEVEL, STR, ARG1, ARG2) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0) + +/** + * @def IX_PIUMH_TRACE3 + * + * @brief Trace macro taking 3 arguments. + */ + +#define IX_PIUMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0) + +/** + * @def IX_PIUMH_TRACE4 + * + * @brief Trace macro taking 4 arguments. + */ + +#define IX_PIUMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0) + +/** + * @def IX_PIUMH_TRACE5 + * + * @brief Trace macro taking 5 arguments. + */ + +#define IX_PIUMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \ + IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0) + +/** + * @def IX_PIUMH_TRACE6 + * + * @brief Trace macro taking 6 arguments. + */ + +#define IX_PIUMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \ +{ \ + if (LEVEL <= IX_PIUMH_TRACE_LEVEL) \ + { \ + (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \ + (int)(ARG1), (int)(ARG2), (int)(ARG3), \ + (int)(ARG4), (int)(ARG5), (int)(ARG6)); \ + } \ +} + +/** + * @def IX_PIUMH_ERROR_REPORT + * + * @brief Error reporting facility. + */ + +#define IX_PIUMH_ERROR_REPORT(STR) \ +{ \ + (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \ + (STR), 0, 0, 0, 0, 0, 0); \ +} + +/* if we are running on XScale, i.e. real environment */ +#if (defined(__ep805xx) || CPU==XSCALE) && !defined(IX_UNIT_TEST) + +/** + * @def IX_PIUMH_REGISTER_READ + * + * @brief This macro reads a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_READ(registerAddress, value) \ +{ \ + *value = IX_OSAL_READ_LONG(registerAddress); \ +} + +/** + * @def IX_PIUMH_REGISTER_READ_BITS + * + * @brief This macro partially reads a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_READ_BITS(registerAddress, value, mask) \ +{ \ + *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \ +} + +/** + * @def IX_PIUMH_REGISTER_WRITE + * + * @brief This macro writes a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_WRITE(registerAddress, value) \ +{ \ + IX_OSAL_WRITE_LONG(registerAddress, value); \ +} + +/** + * @def IX_PIUMH_REGISTER_WRITE_BITS + * + * @brief This macro partially writes a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \ +{ \ + UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \ + orig &= (~mask); \ + orig |= (value & mask); \ + IX_OSAL_WRITE_LONG(registerAddress, orig); \ +} + + +/* if we are running as a unit test */ +#else /* #if CPU==XSCALE */ + +#include "IxPiuMhTestRegister.h" + +/** + * @def IX_PIUMH_REGISTER_READ + * + * @brief This macro reads a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_READ(registerAddress, value) \ +{ \ + ixPiuMhTestRegisterRead (registerAddress, value); \ +} + +/** + * @def IX_PIUMH_REGISTER_READ_BITS + * + * @brief This macro partially reads a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_READ_BITS(registerAddress, value, mask) \ +{ \ + ixPiuMhTestRegisterReadBits (registerAddress, value, mask); \ +} + +/** + * @def IX_PIUMH_REGISTER_WRITE + * + * @brief This macro writes a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_WRITE(registerAddress, value) \ +{ \ + ixPiuMhTestRegisterWrite (registerAddress, value); \ +} + +/** + * @def IX_PIUMH_REGISTER_WRITE_BITS + * + * @brief This macro partially writes a memory-mapped register. + */ + +#define IX_PIUMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \ +{ \ + ixPiuMhTestRegisterWriteBits (registerAddress, value, mask); \ +} + +#endif /* #if CPU==XSCALE */ + +#endif /* IXPIUMHMACROS_P_H */ + +/** + * @} defgroup IxPiuMhMacros_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhReceive_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhReceive_p.h new file mode 100644 index 0000000..9ee3709 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhReceive_p.h @@ -0,0 +1,173 @@ +/** + * @file IxPiuMhReceive_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Receive module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhReceive_p IxPiuMhReceive_p + * + * @brief The private API for the Receive module. + * + * @{ + */ + +#ifndef IXPIUMHRECEIVE_P_H +#define IXPIUMHRECEIVE_P_H + +#include "IxPiuMh.h" +#include "IxOsalTypes.h" + +/* + * #defines for function return types, etc. + */ + +/* + * Prototypes for interface functions. + */ + +/** + * @fn void ixPiuMhReceiveInitialize (void) + * + * @brief This function registers an internal ISR to handle the PIUs' + * "outFIFO not empty" interrupts and receive messages from the PIUs when + * they become available. + * + * @return No return value. + */ + +void ixPiuMhReceiveInitialize (void); + +/** + * @fn void ixPiuMhReceiveUninitialize (void) + * + * @brief This function unregisters the internal ISR to handle the PIUs' + * "outFIFO not empty" interrupt. + * + * @return No return value. + */ + +void ixPiuMhReceiveUninitialize (void); + + +/** + * @fn void ixPiuMhReceiveMessagesReceive ( + IxPiuMhPiuId piuId) + * + * @brief This function reads messages from a particular PIU's outFIFO + * until the outFIFO is empty, and for each message looks first for an + * unsolicited callback, then a solicited callback, to pass the message + * back to the client. If no callback can be found the message is + * discarded and an error reported. This function will return TIMEOUT + * status if PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to receive + * messages from. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhReceiveMessagesReceive ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhReceiveShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Receive + * module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return status. + */ + +void ixPiuMhReceiveShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhReceiveShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Receive + * module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return status. + */ + +void ixPiuMhReceiveShowReset ( + IxPiuMhPiuId piuId); + +#endif /* IXPIUMHRECEIVE_P_H */ + +/** + * @} defgroup IxPiuMhReceive_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSend_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSend_p.h new file mode 100644 index 0000000..d6a0352 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSend_p.h @@ -0,0 +1,185 @@ +/** + * @file IxPiuMhSend_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Send module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhSend_p IxPiuMhSend_p + * + * @brief The private API for the Send module. + * + * @{ + */ + +#ifndef IXPIUMHSEND_P_H +#define IXPIUMHSEND_P_H + +#include "IxPiuMh.h" +#include "IxOsalTypes.h" + +/* + * #defines for function return types, etc. + */ + +/* + * Prototypes for interface functions. + */ + +/** + * @fn IX_STATUS ixPiuMhSendMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries) + * + * @brief This function writes a message to the specified PIU's inFIFO, + * and must be used when the message being sent does not solicit a response + * from the PIU. This function will return TIMEOUT status if PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to send the message + * to. + * @param IxPiuMhMessage message (in) - The message to send. + * @param UINT32 maxSendRetries (in) - Max num. of retries to perform + * if the PIU's inFIFO is full. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhSendMessageSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + UINT32 maxSendRetries); + +/** + * @fn IX_STATUS ixPiuMhSendMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries) + * + * @brief This function writes a message to the specified PIU's inFIFO, + * and must be used when the message being sent solicits a response from + * the PIU. The ID of the solicited response must be specified so that it + * can be recognised, and a callback provided to pass the response back to + * the client. This function will return TIMEOUT status if PIU hang / halt. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to send the message + * to. + * @param IxPiuMhMessage message (in) - The message to send. + * @param IxPiuMhMessageId solicitedMessageId (in) - The ID of the + * solicited response. + * @param IxPiuMhCallback solicitedCallback (in) - The callback to pass the + * solicited response back to the client. + * @param UINT32 maxSendRetries (in) - Max num. of retries to perform + * if the PIU's inFIFO is full. + * + * @return The function returns a status indicating success, failure or timeout. + */ + +IX_STATUS ixPiuMhSendMessageWithResponseSend ( + IxPiuMhPiuId piuId, + IxPiuMhMessage message, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback, + UINT32 maxSendRetries); + +/** + * @fn void ixPiuMhSendShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Send module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return value. + */ + +void ixPiuMhSendShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhSendShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Send module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return value. + */ + +void ixPiuMhSendShowReset ( + IxPiuMhPiuId piuId); + +#endif /* IXPIUMHSEND_P_H */ + +/** + * @} defgroup IxPiuMhSend_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSolicitedCbMgr_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSolicitedCbMgr_p.h new file mode 100644 index 0000000..8f7ec58 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhSolicitedCbMgr_p.h @@ -0,0 +1,203 @@ +/** + * @file IxPiuMhSolicitedCbMgr_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Solicited Callback + * Manager module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + +/** + * @defgroup IxPiuMhSolicitedCbMgr_p IxPiuMhSolicitedCbMgr_p + * + * @brief The private API for the Solicited Callback Manager module. + * + * @{ + */ + +#ifndef IXPIUMHSOLICITEDCBMGR_P_H +#define IXPIUMHSOLICITEDCBMGR_P_H + +#include "IxPiuMh.h" +#include "IxOsalTypes.h" + +/* + * #defines for function return types, etc. + */ + +/** Maximum number of solicited callbacks that can be stored in the list */ +#define IX_PIUMH_MAX_CALLBACKS (16) + +/* + * Prototypes for interface functions. + */ + +/** + * @fn void ixPiuMhSolicitedCbMgrInitialize (void) + * + * @brief This function initializes the Solicited Callback Manager module, + * setting up a callback data structure for each PIU. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrInitialize (void); + +/** + * @fn void ixPiuMhSolicitedCbMgrUninitialize (void) + * + * @brief This function uninitializes the Solicited Callback Manager module. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrUninitialize (void); + +/** + * @fn IX_STATUS ixPiuMhSolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback) + * + * @brief This function saves a callback in the specified PIU's callback + * list. If the callback list is full the function will fail. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU in whose callback + * list the callback will be saved. + * @param IxPiuMhMessageId solicitedMessageId (in) - The ID of the message + * that this callback is for. + * @param IxPiuMhCallback solicitedCallback (in) - The callback function + * pointer to save. + * + * @return The function returns a status indicating success or failure. + */ + +IX_STATUS ixPiuMhSolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback solicitedCallback); + +/** + * @fn void ixPiuMhSolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback *solicitedCallback) + * + * @brief This function retrieves the first ID-matching callback from the + * specified PIU's callback list. If no matching callback can be found the + * function will fail. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU from whose callback + * list the callback will be retrieved. + * @param IxPiuMhMessageId solicitedMessageId (in) - The ID of the message + * that the callback is for. + * @param IxPiuMhCallback solicitedCallback (out) - The callback function + * pointer retrieved. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId solicitedMessageId, + IxPiuMhCallback *solicitedCallback); + +/** + * @fn void ixPiuMhSolicitedCbMgrShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Solicited + * Callback Manager module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhSolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Solicited + * Callback Manager module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return value. + */ + +void ixPiuMhSolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId); + +#endif /* IXPIUMHSOLICITEDCBMGR_P_H */ + +/** + * @} defgroup IxPiuMhSolicitedCbMgr_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhUnsolicitedCbMgr_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhUnsolicitedCbMgr_p.h new file mode 100644 index 0000000..5e4e187 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/include/IxPiuMhUnsolicitedCbMgr_p.h @@ -0,0 +1,202 @@ +/** + * @file IxPiuMhUnsolicitedCbMgr_p.h + * + * @author Intel Corporation + * @date 18 Jan 2002 + * + * @brief This file contains the private API for the Unsolicited Callback + * Manager module. + * + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + +/** + * @defgroup IxPiuMhUnsolicitedCbMgr_p IxPiuMhUnsolicitedCbMgr_p + * + * @brief The private API for the Unsolicited Callback Manager module. + * + * @{ + */ + +#ifndef IXPIUMHUNSOLICITEDCBMGR_P_H +#define IXPIUMHUNSOLICITEDCBMGR_P_H + +#include "IxPiuMh.h" +#include "IxOsalTypes.h" + +/* + * #defines for function return types, etc. + */ + +/* + * Prototypes for interface functions. + */ + +/** + * @fn void ixPiuMhUnsolicitedCbMgrInitialize (void) + * + * @brief This function initializes the Unsolicited Callback Manager + * module, setting up a callback data structure for each PIU. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrInitialize (void); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrUninitialize (void) + * + * @brief This function uninitializes the Unsolicited Callback Manager + * module. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrUninitialize (void); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback unsolicitedCallback) + * + * @brief This function saves a callback in the specified PIU's callback + * table. If a callback already exists for the specified ID then it will + * be overwritten. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU in whose callback + * table the callback will be saved. + * @param IxPiuMhMessageId unsolicitedMessageId (in) - The ID of the + * messages that this callback is for. + * @param IxPiuMhCallback unsolicitedCallback (in) - The callback function + * pointer to save. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrCallbackSave ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback unsolicitedCallback); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback *unsolicitedCallback) + * + * @brief This function retrieves the callback for the specified ID from + * the specified PIU's callback table. If no callback is registered for + * the specified ID and PIU then a callback value of NULL will be returned. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU from whose callback + * table the callback will be retrieved. + * @param IxPiuMhMessageId unsolicitedMessageId (in) - The ID of the + * messages that the callback is for. + * @param IxPiuMhCallback unsolicitedCallback (out) - The callback function + * pointer retrieved. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrCallbackRetrieve ( + IxPiuMhPiuId piuId, + IxPiuMhMessageId unsolicitedMessageId, + IxPiuMhCallback *unsolicitedCallback); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrShow ( + IxPiuMhPiuId piuId) + * + * @brief This function will display the current state of the Unsolicited + * Callback Manager module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to display state + * information for. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrShow ( + IxPiuMhPiuId piuId); + +/** + * @fn void ixPiuMhUnsolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId) + * + * @brief This function will reset the current state of the Unsolicited + * Callback Manager module. + * + * @param IxPiuMhPiuId piuId (in) - The ID of the PIU to reset state + * information for. + * + * @return No return value. + */ + +void ixPiuMhUnsolicitedCbMgrShowReset ( + IxPiuMhPiuId piuId); + +#endif /* IXPIUMHUNSOLICITEDCBMGR_P_H */ + +/** + * @} defgroup IxPiuMhUnsolicitedCbMgr_p + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..c59e1bd --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_2.6_kernel_space.mk @@ -0,0 +1,80 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + + +SOURCES+= $(ICP_DEVICE)$(ICP_SLASH)linux_kernel_module.c + + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DEP805XX -D__ep805xx -DIX_HW_COHERENT_MEMORY=1 +EXTRA_LDFLAGS+=-whole-archive + + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_kernel_module.c b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_kernel_module.c new file mode 100644 index 0000000..3f05ff0 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_message_handler/linux_kernel_module.c @@ -0,0 +1,85 @@ +/** + * @file linux_kernel_module.c + * + * @author Intel Corporation + * + * @description Contents are the kernel module file. + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ +#include <linux/module.h> + + +MODULE_DESCRIPTION("TDM Infrastructure Driver"); +MODULE_VERSION("1.0"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("Dual BSD/GPL"); + +int init_module(void) +{ + return 0; +} + +void cleanup_module(void) +{ + +} + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgr.c b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgr.c new file mode 100644 index 0000000..7078430 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgr.c @@ -0,0 +1,2192 @@ +/****************************************************************************** + * @file IxQMgr.c + * + * @description Contents of this file provide the Software Queue Manager + * Component implementation. + * + * @ingroup qMgr + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +/** + * Put the system defined include files required. + */ + +/* + * Inlines are compiled as function when this is defined. + * N.B. Must be placed before #include of "IxQMgr.h" + */ +#ifndef IXQMGR_H +# define IXQMGRQACCESS_C +#else +# error +#endif + +/** + * Put the user defined include files required. + */ +#include "IxOsal.h" +#include "IxOsalIoMem.h" +#include "icp.h" +#include "IxQMgr.h" +#include "IxSwQueue.h" +#include "IxQMgrTrace_p.h" + +IxQMgrQueue ixQMgrQueues [IX_QMGR_MAX_NUM_QUEUES]; + +PRIVATE BOOL ixQMgrInitialised = FALSE; +PRIVATE UINT32 numQsConfigured; + +/* list of index to the first/last queue with notif enabled for each group */ +PRIVATE UINT32 ixQMgrFirstQInGrpList [IX_QMGR_MAX_NUM_DISPATCH_GRP]; +PRIVATE UINT32 ixQMgrLastQInGrpList [IX_QMGR_MAX_NUM_DISPATCH_GRP]; + +/* cached memory Info */ +PRIVATE void * ixQMgrGrpMemBaseFlush[IX_QMGR_MAX_NUM_DISPATCH_GRP]; +PRIVATE void * ixQMgrGrpMemBaseInvalid[IX_QMGR_MAX_NUM_DISPATCH_GRP]; +PRIVATE UINT32 ixQMgrGrpMemSize[IX_QMGR_MAX_NUM_DISPATCH_GRP]; + + + +PRIVATE IxOsalMutex qMgrConfigMutex; + +typedef struct +{ + UINT32 success; /* Number of successes */ + UINT32 fail; /* Number of failures */ +} IxQMgrStat; + +typedef struct +{ + IxQMgrStat numCfgs; + IxQMgrStat numReads; + IxQMgrStat numWrites; + IxQMgrStat numNotifEnable; + IxQMgrStat numNotifDisable; + IxQMgrStat numCallbackSet; + IxQMgrStat numWMSets; + IxQMgrStat numQSizeReconfig; +} IxQMgrStats; + +PRIVATE IxQMgrStats ixQMgrComponentStats; + + +#define IX_QMGR_QUEUE_CLEAR(qId) do { \ +ixQMgrQueues[qId].qSize = 0; \ +ixQMgrQueues[qId].qEntrySize = 0; \ +ixQMgrQueues[qId].queue.content = 0; \ +ixQMgrQueues[qId].group = IX_QMGR_MAX_NUM_DISPATCH_GRP; \ +ixQMgrQueues[qId].nextQId = IX_QMGR_MAX_NUM_QUEUES; \ +ixQMgrQueues[qId].prevQId = IX_QMGR_MAX_NUM_QUEUES; \ +ixQMgrQueues[qId].callback = dummyCallback; \ +ixQMgrQueues[qId].callbackId = 0; \ +ixQMgrQueues[qId].waterMark = 0; \ +ixQMgrQueues[qId].notifCond = IX_QMGR_Q_SOURCE_INVALID; \ +ixQMgrQueues[qId].htCountFormat = IX_QMGR_Q_COUNT_INVALID; \ +ixQMgrQueues[qId].htAlignment = IX_QMGR_Q_ALIGN_INVALID; \ +ixQMgrQueues[qId].shadowing = IX_QMGR_Q_NO_SHADOWING; \ +ixQMgrQueues[qId].shadowInfo.byteShadowTailCounter =0; \ +ixQMgrQueues[qId].shadowInfo.wordShadowTailCounter =0; \ +} while (0); + +#define QMGR_WORDS_PER_LINE 8 + +#define QMGR_DEFAULT_Q_NAME_LEN 13 + +/* find the nearest power of 2 of the input val */ +PRIVATE UINT32 +ixQMgrNearestPowerOfTwoGet_p(UINT32 val) +{ + UINT32 adjustedVal = 1; + + while (val > adjustedVal) + { + adjustedVal = adjustedVal << 1; + } + /* ensure the result is consistent with the input values */ + if (!(adjustedVal >= val) && (adjustedVal < (val << 1))) + { + IX_QMGR_REPORT_ERROR ("IxUtilNearestPowerOfTwo failed"); + } + return adjustedVal; +} + + +/* Dummy callback used if no callback has been configured by the client */ +void dummyCallback(IxQMgrQId qId, + IxQMgrCallbackId cbId) +{ + /* do nothing */ + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "Dummy callback Queue %d, cb %d\n", + qId, + cbId); +} + + +/* Reset queue internal structure */ +void +ixQMgrResetQueue_p(IxQMgrQId qId) +{ + IxQMgrQueue *info = &ixQMgrQueues[qId]; + /* + * Queue may or may not have been in use - We can't clear counters if Q + * hasn't been configured. + */ + if(ixQMgrQueues[qId].queue.content) + { + if(info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_WA_CB_HEAD_RESET(info->queue); + IX_SWQ_WA_CB_TAIL_RESET(info->queue); + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_CE_HEAD_RESET(info->queue); + IX_SWQ_WA_CE_TAIL_RESET(info->queue); + if (info->shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + *(info->shadowInfo.wordRealTailCounter) = 0; + } + } + else + { + IX_SWQ_BA_CE_HEAD_RESET(info->queue); + IX_SWQ_BA_CE_TAIL_RESET(info->queue); + if (info->shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + *(info->shadowInfo.byteRealTailCounter) = 0; + } + } + } + } + + IX_QMGR_QUEUE_CLEAR(qId); +} + +/** + * Initialise the QMgr. + */ +icp_status_t +ixQMgrInit (void) +{ + IX_STATUS mutexStatus = IX_SUCCESS; + icp_status_t status = ICP_STATUS_SUCCESS; + UINT32 index = 0; + UINT32 grpIndex = 0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrInit\n"); + if (ixQMgrInitialised) + { + status = ICP_STATUS_SUCCESS; + } + else + { + ixQMgrInitialised = TRUE; + /* Perform Initialisation */ + for (; index < IX_QMGR_MAX_NUM_QUEUES; index ++) + { + IX_QMGR_QUEUE_CLEAR(index); + } + for (;grpIndex < IX_QMGR_MAX_NUM_DISPATCH_GRP; grpIndex ++) + { + ixQMgrFirstQInGrpList[grpIndex] = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrLastQInGrpList[grpIndex] = IX_QMGR_MAX_NUM_QUEUES; + } + memset (&ixQMgrComponentStats, 0, sizeof(ixQMgrComponentStats)); + ixQMgrInitialised = TRUE; + numQsConfigured = 0; + + mutexStatus = ixOsalMutexInit(&qMgrConfigMutex); + if (IX_SUCCESS != mutexStatus) + { + ixQMgrInitialised = FALSE; + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrInit: " + "Mutex unavailable\n"); + status = ICP_STATUS_FAIL; + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrInit\n"); + return status; +} + +/** + * Uninitialise the QMgr. + */ +icp_status_t +ixQMgrUnload (void) +{ + IX_STATUS mutexStatus = IX_SUCCESS; + icp_status_t status = ICP_STATUS_SUCCESS; + UINT32 qId =0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrUnload\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnload: " + "ixQMgr component not initialised\n"); + status = ICP_STATUS_FAIL; + } + else + { + + mutexStatus = ixOsalMutexLock (&qMgrConfigMutex, IX_OSAL_WAIT_NONE); + if (IX_SUCCESS != mutexStatus) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnload: " + "Can not get Mutex - please retry\n"); + return ICP_STATUS_RESOURCE; + } + + /*ensure that there are not queues still configured*/ + for (qId =0; qId <IX_QMGR_MAX_NUM_QUEUES; qId ++) + { + /* + * IX_QMGR_MAX_NUM_DISPATCH_GRP is the default. + * if group == IX_QMGR_MAX_NUM_DISPATCH_GRP, then the queue has not + * been configured + */ + if (ixQMgrQueues[qId].group != IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + ixOsalMutexUnlock (&qMgrConfigMutex); + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnload: ixQMgr component " + "cannot be unloaded as in use\n"); + return ICP_STATUS_FAIL; + } + } + + ixQMgrInitialised = FALSE; + numQsConfigured = 0; + + ixOsalMutexUnlock (&qMgrConfigMutex); + ixOsalMutexDestroy (&qMgrConfigMutex); + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrUnload\n"); + return status; +} + + + + + +/** + * Describe queue configuration and statistics for active queues. + */ +void +ixQMgrShow (void) +{ + UINT32 grpIndex = 0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrShow\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrShow: " + "ixQMgr component not initialised\n"); + } + else + { + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Reads, %d Failed Reads\n", + ixQMgrComponentStats.numReads.success, + ixQMgrComponentStats.numReads.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Writes, %d Failed Writes\n", + ixQMgrComponentStats.numWrites.success, + ixQMgrComponentStats.numWrites.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Notification Enables, " + "%d Failed Notification Enables\n", + ixQMgrComponentStats.numNotifEnable.success, + ixQMgrComponentStats.numNotifEnable.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Notification Disables, " + "%d Failed Notification Disables\n", + ixQMgrComponentStats.numNotifDisable.success, + ixQMgrComponentStats.numNotifDisable.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Callback Sets, " + "%d Failed Callback Sets\n", + ixQMgrComponentStats.numCallbackSet.success, + ixQMgrComponentStats.numCallbackSet.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Watermark Sets, " + "%d Failed Watermark Sets\n", + ixQMgrComponentStats.numWMSets.success, + ixQMgrComponentStats.numWMSets.fail); + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "%d Successful Q Size Reconfigures, " + "%d Failed Q Size Reconfigures\n", + ixQMgrComponentStats.numQSizeReconfig.success, + ixQMgrComponentStats.numQSizeReconfig.fail); + if (numQsConfigured > 1) + { + IX_QMGR_TRACE1 (IX_QMGR_DEBUG, + "Available Configured Queues: QId = 0..%d\n", + numQsConfigured-1); + } + else if (numQsConfigured == 1) + { + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "Single Queue Configured QId = 0\n"); + } + else + { + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "No Queues Confiured\n"); + } + for (grpIndex = 0;grpIndex < IX_QMGR_MAX_NUM_DISPATCH_GRP; grpIndex ++) + { + IX_QMGR_PRINT("First Q = %d for Dispatch grp %d\n", + ixQMgrFirstQInGrpList[grpIndex],grpIndex); + IX_QMGR_PRINT("Last Q = %d for Dispatch grp %d\n", + ixQMgrLastQInGrpList[grpIndex],grpIndex); + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrShow\n"); +} + +/** + * Display Individual Queue Configuration and contents + */ +icp_status_t +ixQMgrQShow (IxQMgrQId qId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + UINT32 index = 0; + UINT32 line = 0; + UINT32 entryIndex = 0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQShow\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQShow: " + "ixQMgr component not initialised\n"); + status = ICP_STATUS_FAIL; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQShow: " + "invalid qId\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else if( !IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQShow: " + "Q not configured\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else + { + UINT32 numEntries; + + IX_QMGR_PRINT ("Queue Info:\n" + " Name: %s\n" + " Id: %d\n", + ixQMgrQueues[qId].qName, + qId); + IX_QMGR_PRINT (" Size = %u\n" + " EntrySize = %u\n" + " Group = %u\n", + (UINT32)ixQMgrQueues[qId].qSize, + (UINT32)ixQMgrQueues[qId].qEntrySize, + (UINT32)ixQMgrQueues[qId].group); + IX_QMGR_PRINT (" Watermark = %u\n" + " Notification Condition = %d\n", + (UINT32)ixQMgrQueues[qId].waterMark, + ixQMgrQueues[qId].notifCond); + IX_QMGR_PRINT (" Head and Tail Alignment = %u\n" + " Head and Tail count format = %u\n", + ixQMgrQueues[qId].htAlignment, + ixQMgrQueues[qId].htCountFormat); + IX_QMGR_PRINT (" Shadowing = %u\n", + ixQMgrQueues[qId].shadowing); + + if(ixQMgrQueues[qId].htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_WA_HEAD_INVALIDATE(ixQMgrQueues[qId].queue); + IX_SWQ_WA_TAIL_INVALIDATE(ixQMgrQueues[qId].queue); + + IX_SWQ_WA_CB_NUM_ENTRIES_GET(ixQMgrQueues[qId].queue, numEntries); + IX_QMGR_PRINT (" Num Entries in Q = %d\n" + " Current Head = 0x%08X at 0x%08X\n" + " Current Tail = 0x%08X at 0x%08X\n", + numEntries, + *(IX_SWQ_WA_CB_HEAD_PTR(ixQMgrQueues[qId].queue)), + (UINT32)IX_SWQ_WA_CB_HEAD_PTR(ixQMgrQueues[qId].queue), + *(IX_SWQ_WA_CB_TAIL_PTR(ixQMgrQueues[qId].queue)), + (UINT32)IX_SWQ_WA_CB_TAIL_PTR(ixQMgrQueues[qId].queue)); + } + else + { + if (ixQMgrQueues[qId].htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_WA_HEAD_INVALIDATE(ixQMgrQueues[qId].queue); + IX_SWQ_WA_TAIL_INVALIDATE(ixQMgrQueues[qId].queue); + + IX_SWQ_WA_CE_NUM_ENTRIES_GET(ixQMgrQueues[qId].queue, + numEntries); + IX_QMGR_PRINT ( + " Num Entries in Q = %d\n" + " Current Head = 0x%08X at 0x%08X\n" + " Current Tail = 0x%08X at 0x%08X\n", + numEntries, + IX_SWQ_WA_CE_HEAD(ixQMgrQueues[qId].queue), + (UINT32)IX_SWQ_WA_CE_HEAD_PTR(ixQMgrQueues[qId].queue), + IX_SWQ_WA_CE_TAIL(ixQMgrQueues[qId].queue), + (UINT32)IX_SWQ_WA_CE_TAIL_PTR(ixQMgrQueues[qId].queue)); + + if (ixQMgrQueues[qId].shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_SWQ_CACHE_INVALIDATE( + (ixQMgrQueues[qId].shadowInfo.wordRealTailCounter), + IX_QMGR_SIZEOF_WORD); + IX_QMGR_PRINT ( + " Real Tail Counter = 0x%08X at 0x%08X\n", + *(ixQMgrQueues[qId].shadowInfo.wordRealTailCounter), + (uint32_t)ixQMgrQueues[qId].shadowInfo.wordRealTailCounter); + } + } + else + { + IX_SWQ_BA_HEAD_INVALIDATE(ixQMgrQueues[qId].queue); + IX_SWQ_BA_TAIL_INVALIDATE(ixQMgrQueues[qId].queue); + IX_SWQ_CACHE_INVALIDATE( + (ixQMgrQueues[qId].shadowInfo.byteRealTailCounter), + IX_QMGR_SIZEOF_BYTE); + + IX_SWQ_BA_CE_NUM_ENTRIES_GET(ixQMgrQueues[qId].queue, + numEntries); + IX_QMGR_PRINT ( + " Num Entries in Q = %d\n" + " Current Head = 0x%02X at 0x%08X\n" + " Current Tail = 0x%02X at 0x%08X\n", + numEntries, + IX_SWQ_BA_CE_HEAD(ixQMgrQueues[qId].queue), + (UINT32)IX_SWQ_BA_CE_HEAD_PTR(ixQMgrQueues[qId].queue), + IX_SWQ_BA_CE_TAIL(ixQMgrQueues[qId].queue), + (UINT32)IX_SWQ_BA_CE_TAIL_PTR(ixQMgrQueues[qId].queue)); + + if (ixQMgrQueues[qId].shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_PRINT ( + " Real Tail Counter = 0x%02X at 0x%08X\n", + *(ixQMgrQueues[qId].shadowInfo.byteRealTailCounter), + (uint32_t)ixQMgrQueues[qId].shadowInfo.byteRealTailCounter); + } + } + } + IX_QMGR_PRINT (" Next Q Id = %d\n" + " Prev Q Id = %d\n" + " Queue Location = 0x%08X\n", + ixQMgrQueues[qId].nextQId, + ixQMgrQueues[qId].prevQId, + (UINT32)IX_SWQ_CONTENT_PTR(ixQMgrQueues[qId].queue)); + + IX_QMGR_PRINT(" Queue Entries:\n"); + /* print out 8 words on each line, reorg order of words depending on + * the entry size + */ + for (index = 0; + index < ((ixQMgrQueues[qId].qSize) * (ixQMgrQueues[qId].qEntrySize)); + index = index+QMGR_WORDS_PER_LINE) + { + IX_QMGR_PRINT ("%u: ", + index); + line = 0; + while ((line+index < + (ixQMgrQueues[qId].qSize) * (ixQMgrQueues[qId].qEntrySize)) + && (line < QMGR_WORDS_PER_LINE)) + + { + IX_QMGR_PRINT (" 0x"); + for (entryIndex = (ixQMgrQueues[qId].qEntrySize); + entryIndex > 0; + entryIndex --) + { + IX_QMGR_PRINT ("%08X", + IX_SWQ_ENTRY_IDXGET(ixQMgrQueues[qId].queue, + index+line+entryIndex-1)); + } + line += (ixQMgrQueues[qId].qEntrySize); + + } + IX_QMGR_PRINT("\n"); + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQShow\n"); + return status; +} + +/** + * Sets the base address and the size of the memory area that will + * be invalidated when the dispatch loop function will run. + */ +icp_status_t +ixQMgrGroupMemoryConfig (IxQMgrDispatchGroup group, + void * baseAddressToFlush, + void * baseAddressToInvalidate, + UINT32 size) +{ + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + + if (size == 0) + { + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "invalid size parameter\n"); + return ICP_STATUS_INVALID_PARAM; + } + if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "invalid group parameter\n"); + return ICP_STATUS_INVALID_PARAM; + } + if (baseAddressToFlush == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "invalid baseAddress parameter\n"); + return ICP_STATUS_INVALID_PARAM; + } + if (baseAddressToInvalidate == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrGroupMemoryConfig: " + "invalid baseAddress parameter\n"); + return ICP_STATUS_INVALID_PARAM; + } + ixQMgrGrpMemBaseFlush[group] = baseAddressToFlush; + ixQMgrGrpMemBaseInvalid[group] = baseAddressToInvalidate; + ixQMgrGrpMemSize[group] = size; + return ICP_STATUS_SUCCESS; +} + + +/* ------------------------------------------------------------ + Configuration related functions + ---------------------------------------------------------- */ + +icp_status_t +ixQMgrQConfig (char *qName, + IxQMgrQId *qId, + IxQMgrQSize qSize, + IxQMgrQEntrySizeInWords qEntrySize, + IxQMgrHeadAndTailCountFormat htCountFormat, + IxQMgrHeadAndTailAlignment htAlignment, + IxQMgrDispatchGroup group, + IxQMgrHeadAndTailShadowing shadowing, + void *qBaseAddress, + void *qHeadCountPtr, + void *qTailCountPtr) +{ + + void * head = NULL; + void * tail = NULL; + void * contentBuffer = NULL; + IX_STATUS status = IX_SUCCESS; + IxQMgrQId newQueueNum =IX_QMGR_MAX_NUM_QUEUES; /*set to invalid number*/ + UINT32 qLoopCounter =0; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQConfig\n"); + + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + + return ICP_STATUS_FAIL; + } + else + { + status = ixOsalMutexLock (&qMgrConfigMutex, IX_OSAL_WAIT_NONE); + if (IX_SUCCESS != status) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Can not get Mutex - please retry\n"); + return ICP_STATUS_RESOURCE; + } + + /*check that the max amount of queue's have not been configured*/ + if (numQsConfigured >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Maximum number of Queues Configured\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_RESOURCE; + } + + /* + * Check to make sure that the qEntry size is not more then the + * max OR is not a power of two (i.e. not 1,2,4,8 etc.) + */ + if ((qEntrySize > IX_QMGR_Q_ENTRY_MAX_SIZE) || + (qEntrySize != ixQMgrNearestPowerOfTwoGet_p(qEntrySize))) + { + + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qEntrySize parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + if (((qSize * (qEntrySize*IX_QMGR_SIZEOF_WORD)) > IX_QMGR_Q_MAX_SIZE) || + (qSize != ixQMgrNearestPowerOfTwoGet_p(qSize))) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qSize parameter, " + "for this entrySize\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid group parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + if (qBaseAddress == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qBaseAddress parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + else + { + contentBuffer = qBaseAddress; + } + if (qHeadCountPtr == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qHeadCountPtr parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + else + { + head = qHeadCountPtr; + } + if (qTailCountPtr == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qTailCountPtr parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*check HtAlignment parameter*/ + if(IX_QMGR_ENUM_IS_INVALID(htAlignment, IX_QMGR_Q_ALIGN_INVALID)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid htAlignment parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*check Htcountformat parameter*/ + if(IX_QMGR_ENUM_IS_INVALID(htCountFormat, IX_QMGR_Q_COUNT_INVALID)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid htCountFormat parameter\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + /*check for unsupported alignment and format combination*/ + if((htAlignment == IX_QMGR_Q_ALIGN_BYTE) && + (htCountFormat == IX_QMGR_Q_COUNT_BYTES)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Byte counting format is not supported with a" + "byte aligned Head and Tail\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*Check for unsupported shadowing parameter */ + if((shadowing != IX_QMGR_Q_NO_SHADOWING) && + (shadowing != IX_QMGR_Q_SHADOW_TAIL_ONLY)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid shadowing option: " + "IX_QMGR_Q_NO_SHADOWING and " + "IX_QMGR_Q_SHADOW_TAIL_ONLY currently " + "supported\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*Check for unsupported shadowing and count format combination */ + if((shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) && + (htCountFormat == IX_QMGR_Q_COUNT_BYTES)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Shadowing is not supported on a queue that" + " has IX_QMGR_Q_COUNT_ENTRIES count format\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + /*find the first unconfigured queue in the array of queues*/ + /*Has to be one free as numQsConfiged < MAX_QUEUES*/ + for (qLoopCounter =0; + qLoopCounter <IX_QMGR_MAX_NUM_QUEUES; + qLoopCounter ++) + { + if(ixQMgrQueues[qLoopCounter].group == IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + /*save the location of it*/ + newQueueNum = qLoopCounter; + /*no need to run the loop again*/ + break; + + } + } + /* + * if newQueueNum doesn't now have a valid q number then serious error. + * numqsconfiged indicated there was at least one unconfigured queue + * but we couldn't find it. + */ + if (newQueueNum == IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "Num of Queues corrupted\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_RESOURCE; + } + + + /* + * Check if head and tail is byte aligned that qSize will not overflow + * the head and tail. Word aligned type queues implicitly tested above. + */ + if ((htAlignment == IX_QMGR_Q_ALIGN_BYTE) + && (qSize > IX_QMGR_MAX_BYTE_COUNT)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qSize parameter - for a byte aligned " + "queue\n"); + ixQMgrComponentStats.numCfgs.fail ++; + ixOsalMutexUnlock (&qMgrConfigMutex); + return ICP_STATUS_INVALID_PARAM; + } + + + /*Check if we should use real tail counter or shadow tail counter*/ + if (shadowing == IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + if (htAlignment == IX_QMGR_Q_ALIGN_BYTE) + { + /*Set the tail to use our shadow tail*/ + tail = + &(ixQMgrQueues[newQueueNum].shadowInfo.byteShadowTailCounter); + /*Store the real tail as need for ixQMgrShadowAdvance/DeltaGet*/ + ixQMgrQueues[newQueueNum].shadowInfo.byteRealTailCounter = + qTailCountPtr; + } + else + { + /*Set the tail to use our shadow tail*/ + tail = + &(ixQMgrQueues[newQueueNum].shadowInfo.wordShadowTailCounter); + /*Store the real tail as need for ixQMgrShadowAdvance/DeltaGet*/ + ixQMgrQueues[newQueueNum].shadowInfo.wordRealTailCounter = + qTailCountPtr; + } + } + else + { + /* Already checked against it being NULL. No shadowing => set the + * tail to user supplied tail + */ + tail = qTailCountPtr; + } + + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "Configure the Queue\n"); + + /* Configure the Queue */ + IX_SWQ_STATIC_INIT(ixQMgrQueues[newQueueNum].queue, + IxQMgrQEntryType, + qSize, + qEntrySize, + contentBuffer, + head, + tail, + htCountFormat, + htAlignment); + + + /* set/reset data for this Queue */ + if (NULL != qName) + { + strncpy(ixQMgrQueues[newQueueNum].qName,qName,IX_QMGR_MAX_QNAME_LEN); + } + else + { + strncpy(ixQMgrQueues[newQueueNum].qName, "No name Queue", + QMGR_DEFAULT_Q_NAME_LEN); + } + ixQMgrQueues[newQueueNum].callback= dummyCallback; + ixQMgrQueues[newQueueNum].callbackId = 0; + ixQMgrQueues[newQueueNum].waterMark = 0; + ixQMgrQueues[newQueueNum].group = group; + ixQMgrQueues[newQueueNum].notifCond = IX_QMGR_Q_SOURCE_INVALID; + ixQMgrQueues[newQueueNum].qSize = qSize; + ixQMgrQueues[newQueueNum].qEntrySize = qEntrySize; + ixQMgrQueues[newQueueNum].nextQId = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrQueues[newQueueNum].prevQId = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrQueues[newQueueNum].htCountFormat = htCountFormat; + ixQMgrQueues[newQueueNum].htAlignment = htAlignment; + ixQMgrQueues[newQueueNum].shadowing = shadowing; + + *qId = newQueueNum; + + numQsConfigured ++; + ixQMgrComponentStats.numCfgs.success ++; + + } + + ixOsalMutexUnlock (&qMgrConfigMutex); + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQConfig\n"); + return ICP_STATUS_SUCCESS; +} + +icp_status_t +ixQMgrQWriteRollbackWithChecks(IxQMgrQId qId, + UINT32 numEntries) +{ + IxQMgrQueue *info = NULL; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQWriteRollbackWithChecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "invalid qId\n"); + return ICP_STATUS_INVALID_PARAM; + } + + info = &ixQMgrQueues[qId]; + if (!IX_SWQ_INITIALISED(info->queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Queue not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (numEntries == 0) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Not possible to rollback by 0 entries\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Queue is not a count by entry queue\n"); + return ICP_STATUS_RESOURCE; + } + + if(numEntries > info->qSize) + { + /* + * Can't rollback by more entries then the max amount of possible + * entries in a queue. + */ + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Not possible to rollback head counter by more " + " than the max possible amount of " + "entries in the queue\n"); + return ICP_STATUS_FAIL; + } + /* + * As this queue is using shadowing, the check in inline function will be + * against the shadow tail counter. We'll add a check against the real tail + * counter in this function + */ + + if (info->htAlignment == IX_QMGR_Q_ALIGN_BYTE) + { + /* + * if numEntries is greater then the (head - realTail), + * then this is not allowed + */ + IX_SWQ_CACHE_INVALIDATE((info->shadowInfo.byteRealTailCounter), + IX_QMGR_SIZEOF_BYTE); + + if(numEntries > + (((IX_SWQ_BE_SHARED_BYTE_READ(IX_SWQ_BA_CE_HEAD_PTR(info->queue)))) - + (*(info->shadowInfo.byteRealTailCounter)))) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Not possible to rollback head counter by " + "more than the delta between the head and " + "real tail\n"); + return ICP_STATUS_FAIL; + } + } + else + { + /* + * if numEntries is greater then the (head - realTail), + * then this is not allowed + */ + IX_SWQ_CACHE_INVALIDATE((info->shadowInfo.wordRealTailCounter), + IX_QMGR_SIZEOF_WORD); + + if(numEntries > + ((IX_SWQ_BE_SHARED_LONG_READ(IX_SWQ_WA_CE_HEAD_PTR(info->queue))) - + (IX_SWQ_BE_SHARED_LONG_READ(info->shadowInfo.wordRealTailCounter)))) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteRollbackWithChecks: " + "Not possible to rollback head counter by " + "more than the delta between the head and " + "real tail\n"); + return ICP_STATUS_FAIL; + } + } + + /*All checks have passed. Call the inline function*/ + return ixQMgrQWriteRollback(qId, numEntries); +} + + +icp_status_t +ixQMgrShadowAdvanceWithChecks(IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 numEntries) +{ + IxQMgrQueue *info = NULL; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrShadowAdvanceWithChecks\n"); + + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "invalid qId\n"); + return ICP_STATUS_INVALID_PARAM; + } + + info = &ixQMgrQueues[qId]; + if (!IX_SWQ_INITIALISED(info->queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Queue not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if(shadowingCounterType != IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "IX_QMGR_Q_SHADOW_TAIL_ONLY is the only " + "valid enum value supported\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (numEntries == 0) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Not possible to advance the shadow " + " register by 0\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Queue is not a count by entry queue\n"); + return ICP_STATUS_RESOURCE; + } + + if (info->shadowing != IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Queue does not use tail shadowing\n"); + return ICP_STATUS_RESOURCE; + } + if(numEntries > info->qSize) + { + /* + * They're can't be more more of delta between the shadow tail + * and the real tail then there are entries + */ + IX_QMGR_REPORT_ERROR ("ixQMgrShadowAdvanceWithChecks: " + "Not possible to advance the shadow " + "register by more than" + " the amount of entries in the queue\n"); + return ICP_STATUS_FAIL; + } + + /*All checks have passed. Call the inline function*/ + return ixQMgrShadowAdvance(qId, shadowingCounterType, numEntries); +} + + +icp_status_t +ixQMgrShadowDeltaGetWithChecks( + IxQMgrQId qId, + IxQMgrHeadAndTailShadowing shadowingCounterType, + UINT32 *numEntries) +{ + IxQMgrQueue *info = NULL; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrShadowDeltaGetWithChecks\n"); + + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "invalid qId\n"); + return ICP_STATUS_INVALID_PARAM; + } + + info = &ixQMgrQueues[qId]; + if (!IX_SWQ_INITIALISED(info->queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "Queue not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if(shadowingCounterType != IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "IX_QMGR_Q_SHADOW_TAIL_ONLY only supported\n"); + return ICP_STATUS_INVALID_PARAM; + } + + if (info->htCountFormat != IX_QMGR_Q_COUNT_ENTRIES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "Queue is not a count by entry queue\n"); + return ICP_STATUS_RESOURCE; + } + + if (info->shadowing != IX_QMGR_Q_SHADOW_TAIL_ONLY) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "Queue does not use tail shadowing\n"); + return ICP_STATUS_RESOURCE; + } + if(numEntries == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrShadowDeltaGetWithChecks: " + "numEntries == NULL \n"); + return ICP_STATUS_INVALID_PARAM; + } + + + /*All checks have passed. Call the inline function*/ + return ixQMgrShadowDeltaGet(qId, shadowingCounterType, numEntries); +} + + + +/** + * Unconfigure a group + */ +icp_status_t +ixQMgrUnconfigGroup(IxQMgrDispatchGroup group) +{ + UINT32 qId =0; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrUnconfigGroup\n"); + + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnconfigGroup: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + + if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrUnconfigGroup: " + "invalid group\n"); + return ICP_STATUS_INVALID_PARAM; + } + + + /*find each queue in the group and reset it */ + for (qId =0; qId < IX_QMGR_MAX_NUM_QUEUES; qId ++) + { + if (ixQMgrQueues[qId].group == group) + { + /*reset the queue*/ + ixQMgrResetQueue_p(qId); + /*decrement the numQsConfigured */ + numQsConfigured --; + } + } + + /*no queues in the group anymore, so reset the group lists*/ + ixQMgrLastQInGrpList[group] = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrFirstQInGrpList[group] = IX_QMGR_MAX_NUM_QUEUES; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrUnconfigGroup\n"); + + return ICP_STATUS_SUCCESS; +} + + + +/* Check the number of entries in the queue depending on its type */ +inline icp_status_t +ixQMgrQEmptyCheck (IxQMgrQueue *info) +{ + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + /*Check to see if the queue is empty */ + if (!IX_SWQ_WA_CB_QUEUE_EMPTY(info->queue)) + { + return ICP_STATUS_RESOURCE; + } + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + + IX_SWQ_WA_HEAD_INVALIDATE(info->queue); + IX_SWQ_WA_TAIL_INVALIDATE(info->queue); + /*Check to see if the queue is empty */ + if (!IX_SWQ_WA_CE_QUEUE_EMPTY(info->queue)) + { + return ICP_STATUS_RESOURCE; + } + } + else + { + IX_SWQ_BA_HEAD_INVALIDATE(info->queue); + IX_SWQ_BA_TAIL_INVALIDATE(info->queue); + /*Check to see if the queue is empty */ + if (!IX_SWQ_BA_CE_QUEUE_EMPTY(info->queue)) + { + return ICP_STATUS_RESOURCE; + } + } + } + return ICP_STATUS_SUCCESS; +} + + +/* Initialise the Queue appropriately depending on the Queue Type */ +inline void +ixQMgrQInit(IxQMgrQueue *info, + IxQMgrQSize qSize) +{ + if (info->htCountFormat == IX_QMGR_Q_COUNT_BYTES) + { + IX_SWQ_STATIC_INIT(info->queue, + IxQMgrQEntryType, + qSize, + info->qEntrySize, + IX_SWQ_CONTENT_PTR(info->queue), + (void *)IX_SWQ_WA_CB_HEAD_PTR(info->queue), + (void *)IX_SWQ_WA_CB_TAIL_PTR(info->queue), + info->htCountFormat, + info->htAlignment); + } + else + { + if(info->htAlignment == IX_QMGR_Q_ALIGN_WORD) + { + IX_SWQ_STATIC_INIT(info->queue, + IxQMgrQEntryType, + qSize, + info->qEntrySize, + IX_SWQ_CONTENT_PTR(info->queue), + (void *)IX_SWQ_WA_CE_HEAD_PTR(info->queue), + (void *)IX_SWQ_WA_CE_TAIL_PTR(info->queue), + info->htCountFormat, + info->htAlignment); + } + else + { + IX_SWQ_STATIC_INIT(info->queue, + IxQMgrQEntryType, + qSize, + info->qEntrySize, + IX_SWQ_CONTENT_PTR(info->queue), + (void *)IX_SWQ_BA_CE_HEAD_PTR(info->queue), + (void *)IX_SWQ_BA_CE_TAIL_PTR(info->queue), + info->htCountFormat, + info->htAlignment); + } + } +} + +icp_status_t +ixQMgrQSizeReconfig (IxQMgrQId qId, IxQMgrQSize qSize) +{ + IxQMgrQueue *info = NULL; + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQSizeReconfig\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_FAIL; + } + + /*check that the QId has already been configured*/ + if ((qId >= IX_QMGR_MAX_NUM_QUEUES) || + (ixQMgrQueues[qId].group == IX_QMGR_MAX_NUM_DISPATCH_GRP)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "Invalid Q \n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + info = &ixQMgrQueues[qId]; + + /*Check to ensure qSize is not too big and is a power of two */ + if (((qSize * (info->qEntrySize)) > IX_QMGR_Q_MAX_SIZE) || + (qSize != ixQMgrNearestPowerOfTwoGet_p(qSize))) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQConfig: " + "invalid qSize parameter\n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + + /* + * Check if head and tail is byte aligned that the qSize will not overflow + * the head and tail. Word aligned type queues implicitly tested above. + */ + if ((info->htAlignment == IX_QMGR_Q_ALIGN_BYTE) + && (qSize > IX_QMGR_MAX_BYTE_COUNT)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "invalid qSize parameter - for a byte " + "aligned queue\n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + + if (ICP_STATUS_SUCCESS != ixQMgrQEmptyCheck(info)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "Q is not empty \n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_RESOURCE; + } + + /*Check to see if notifications are disabled for the queue*/ + if (info->notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeReconfig: " + "Q Notifications are not disabled\n"); + ixQMgrComponentStats.numQSizeReconfig.fail ++; + return ICP_STATUS_RESOURCE; + } + + /*Reset the waterMark and the head and tail*/ + info->waterMark = 0; + + /* + * Call the appropriate MACROS to reonfigure the lowlevel queue with the + * new qSize and all other parameters the same as the previous configure + */ + ixQMgrQInit(info,qSize); + + /*change the high level queue struct qSize*/ + info->qSize = qSize; + + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQSizeReconfig\n"); + ixQMgrComponentStats.numQSizeReconfig.success ++; + return ICP_STATUS_SUCCESS; +} + +/** + * Return the size of a queue in entries + */ +icp_status_t +ixQMgrQSizeGet (IxQMgrQId qId, + IxQMgrQSize *qSize) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQSizeGet\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeGet: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeGet: " + "invalid qId\n"); + return ICP_STATUS_INVALID_PARAM; + } + else if (qSize == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeGet: " + "invalid pointer to a qSize\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQSizeGet: " + "Q not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + *qSize = ixQMgrQueues[qId].qSize; + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQSizeGet\n"); + return ICP_STATUS_SUCCESS; +} + + +/** + * Set the Watermark of a queue + */ +icp_status_t +ixQMgrWatermarkSet (IxQMgrQId qId, + IxQMgrWMLevel waterM) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrWatermarkSet\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrWatermarkSet: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numWMSets.fail ++; + return ICP_STATUS_FAIL; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrWatermarkSet: " + "invalid qId\n"); + ixQMgrComponentStats.numWMSets.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + if( !IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrWatermarkSet: " + "Q not configured\n"); + ixQMgrComponentStats.numWMSets.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if ((waterM >= IX_SWQ_SIZE(ixQMgrQueues[qId].queue)) || + (waterM == 0)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrWatermarkSet: " + "invalid Watermark\n"); + ixQMgrComponentStats.numWMSets.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + ixQMgrQueues[qId].waterMark = waterM; + IX_QMGR_TRACE2 (IX_QMGR_DEBUG, + "Setting WM for Q %d to %d\n", + qId, + ixQMgrQueues[qId].waterMark); + ixQMgrComponentStats.numWMSets.success ++; + + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrWatermarkSet\n"); + return ICP_STATUS_SUCCESS; +} + +/* ------------------------------------------------------------ + Queue access related functions + ------------------------------------------------------------ */ + +/** + * Read an entry from a queue + */ +icp_status_t +ixQMgrQReadWithChecks (IxQMgrQId qId, + IxQMgrQEntryType *entryPtr) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQReadWithChecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "ixQMgr component not initialised\n"); + + ixQMgrComponentStats.numReads.fail ++; + return ICP_STATUS_FAIL; + } + if ( qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "Invalid QId\n"); + ixQMgrComponentStats.numReads.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + if ( entryPtr == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "Invalid entryPtr\n"); + ixQMgrComponentStats.numReads.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + /* Check Q is Initialised, Check Q is not empty */ + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "Queue not initialised\n"); + ixQMgrComponentStats.numReads.fail ++; + return ICP_STATUS_INVALID_PARAM; + + } + else + { + status = ixQMgrQRead (qId, + entryPtr); + } + if (status == ICP_STATUS_SUCCESS) + { + ixQMgrComponentStats.numReads.success ++; + } + else + { + IX_QMGR_REPORT_ERROR ("ixQMgrQReadWithChecks: " + "Queue Empty\n"); + ixQMgrComponentStats.numReads.fail ++; + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQReadWithChecks\n"); + return status; +} + + +/** + * Write an entry to a Software Queue + */ +icp_status_t +ixQMgrQWriteWithChecks (IxQMgrQId qId, + IxQMgrQEntryType *entry) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQWriteWithChecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numWrites.fail ++; + return ICP_STATUS_FAIL; + } + if ( qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Invalid QId\n"); + ixQMgrComponentStats.numWrites.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + if ( entry == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Invalid entry\n"); + ixQMgrComponentStats.numWrites.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Queue not initialised\n"); + ixQMgrComponentStats.numWrites.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + /* Use inline function after checking */ + status = ixQMgrQWrite (qId, entry); + } + + if (status == ICP_STATUS_SUCCESS) + { + ixQMgrComponentStats.numWrites.success ++; + } + else + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Queue Overflow\n"); + ixQMgrComponentStats.numWrites.fail ++; + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQWriteWithChecks\n"); + return status; +} + +/** + * Get a snapshot of the number of entries in a queue + */ +icp_status_t +ixQMgrQNumEntriesGetWithChecks (IxQMgrQId qId, + UINT32 *numEntries) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQNumEntriesGetWithChecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQNumEntriesGetWithChecks: " + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + if ( qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQNumEntriesGetWithChecks: " + "Invalid QId\n"); + return ICP_STATUS_INVALID_PARAM; + } + if ( numEntries == NULL ) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQNumEntriesGetWithChecks: " + "Invalid NumEntries\n"); + return ICP_STATUS_INVALID_PARAM; + } + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQNumEntriesGetWithChecks: " + "Q not configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + /* Read Entry using inline function */ + status = ixQMgrQNumEntriesGet (qId, + numEntries); + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQNumEntriesGetWithChecks\n"); + return status; +} + +/** + * Get a queues status + */ +icp_status_t +ixQMgrQStatusGetWithChecks (IxQMgrQId qId, + IxQMgrQState *qState) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrQStatusGetWithchecks\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrQStatusGetWithChecks:" + "ixQMgr component not initialised\n"); + return ICP_STATUS_FAIL; + } + else if (qState == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Invalid qState Addr\n"); + return ICP_STATUS_INVALID_PARAM; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQStatusGetWithChecks: " + "Invalid QId\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrQWriteWithChecks: " + "Q Not Configured\n"); + return ICP_STATUS_INVALID_PARAM; + } + else + { + status = ixQMgrQStatusGet (qId, + qState); + } + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrQStatusGetWithChecks\n"); + return status; +} + + + +/* ------------------------------------------------------------ + Queue dispatch related functions + ---------------------------------------------------------- */ + +/** + * Enable notification on a queue for a specified queue State + */ +icp_status_t +ixQMgrNotificationEnable (IxQMgrQId qId, + IxQMgrNotificationCondition sourceId) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrNotificationEnable\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationEnable: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_FAIL; + } + else if (IX_QMGR_ENUM_IS_INVALID(sourceId, IX_QMGR_Q_SOURCE_INVALID)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationenable:" + "invalid Condition\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationenable:" + "invalid Q Id\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationEnable:" + "Q not initialised\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if (ixQMgrQueues[qId].notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationEnable:" + "A Condition is already enabled\n"); + ixQMgrComponentStats.numNotifEnable.fail ++; + return ICP_STATUS_FAIL; + } + + /* set condition to trigger a notification */ + ixQMgrQueues[qId].notifCond = sourceId; + + /* add queue to group list for notification */ + ixQMgrQueues[qId].prevQId = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrQueues[qId].nextQId = + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group]; + + if ( ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] != + IX_QMGR_MAX_NUM_QUEUES) + { + /* Group already has queues with notif enabled */ + ixQMgrQueues[ixQMgrQueues[qId].nextQId].prevQId = qId; + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] = qId; + } + else + { + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] = qId; + ixQMgrLastQInGrpList[ixQMgrQueues[qId].group] = qId; + } + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrNotificationEnable: " + "Enabled Notification on Q %d\n belonging to group %d, " + "Starting Q %d\n", + qId, + ixQMgrQueues[qId].group, + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group]); + ixQMgrComponentStats.numNotifEnable.success ++; + + } + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrNotificationEnable\n"); + return ICP_STATUS_SUCCESS; +} + +/** + * Disable notifications on a queue + */ +icp_status_t +ixQMgrNotificationDisable (IxQMgrQId qId) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrNotificationDisable\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationDisable: " + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numNotifDisable.fail ++; + return ICP_STATUS_FAIL; + } + else if ( qId >= IX_QMGR_MAX_NUM_QUEUES) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationDisable: " + "invalid Qid\n"); + ixQMgrComponentStats.numNotifDisable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + + /* Check Q is Initialised*/ + else + { + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationDisable: " + "Q not configured\n"); + ixQMgrComponentStats.numNotifDisable.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if (ixQMgrQueues[qId].notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + /* Notification was enabled on this queue so, + set condition to INVALID, + this will disable notification when Dispatcher runs */ + ixQMgrQueues[qId].notifCond = IX_QMGR_Q_SOURCE_INVALID; + + /* remove Queue from group list */ + if ( ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] == qId) + { + ixQMgrFirstQInGrpList[ixQMgrQueues[qId].group] + = ixQMgrQueues[qId].nextQId; + } + + if (ixQMgrQueues[qId].nextQId != IX_QMGR_MAX_NUM_QUEUES) + { + ixQMgrQueues[ixQMgrQueues[qId].nextQId].prevQId = + ixQMgrQueues[qId].prevQId; + } + + + if ( ixQMgrLastQInGrpList[ixQMgrQueues[qId].group] == qId) + { + ixQMgrLastQInGrpList[ixQMgrQueues[qId].group] + = ixQMgrQueues[qId].prevQId; + } + + if (ixQMgrQueues[qId].prevQId != IX_QMGR_MAX_NUM_QUEUES) + { + ixQMgrQueues[ixQMgrQueues[qId].prevQId].nextQId = + ixQMgrQueues[qId].nextQId; + } + + + ixQMgrComponentStats.numNotifDisable.success ++; + ixQMgrQueues[qId].nextQId = IX_QMGR_MAX_NUM_QUEUES; + ixQMgrQueues[qId].prevQId = IX_QMGR_MAX_NUM_QUEUES; + } + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrNotificationDisable\n"); + return ICP_STATUS_SUCCESS; +} + +/** + * Run the callback dispatcher, + * the first queue enabled for notification will be the first to be serviced. + */ +void +ixQMgrDispatcherLoopRun (IxQMgrDispatchGroup group) +{ + IxQMgrQId qId = 0; + IxQMgrQState qState; + IxQMgrNotificationCondition condition; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrDispatcherLoopRun\n"); + +#ifndef NDEBUG + if (!ixQMgrInitialised) + { + IX_QMGR_REPORT_ERROR ("ixQMgrDispatcherLoopRun: " + "ixQMgr component not initialised\n"); + return; + } + else if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + IX_QMGR_REPORT_ERROR ("ixQMgrDispatcherLoopRun: " + "invalid group\n"); + return; + } +#endif + + /* preload the counters for the group of queues */ + IX_OSAL_CACHE_PRELOAD(ixQMgrGrpMemBaseInvalid[group], + ixQMgrGrpMemSize[group]); + + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: start searching...\n"); + qId = ixQMgrLastQInGrpList[group]; + while ( qId < IX_QMGR_MAX_NUM_QUEUES) + { + /* check if notification is enabled */ + if (ixQMgrQueues[qId].notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: Notif enabled on this " + "queue\n"); + /* check state */ + ixQMgrQStatusGet(qId, &qState); + condition = ixQMgrQueues[qId].notifCond; + + if (condition == qState) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: " + "Notification enabled on Queue %d, State %d, " + "Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, ixQMgrQueues[qId].callbackId); + } + else if (condition == IX_QMGR_Q_SOURCE_ID_NOT_E) + { + if (qState != IX_QMGR_Q_STATE_E) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: " + "Notification enabled on Queue %d, " + "State %d, Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, + ixQMgrQueues[qId].callbackId); + } + } + else if (condition == IX_QMGR_Q_SOURCE_ID_NOT_F) + { + if (qState != IX_QMGR_Q_STATE_F) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRun: " + "Notification enabled on Queue %d, " + "State %d, Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, + ixQMgrQueues[qId].callbackId); + } + } + } + qId = ixQMgrQueues[qId].prevQId; + } + IX_SWQ_CACHE_FLUSH(ixQMgrGrpMemBaseFlush[group], ixQMgrGrpMemSize[group]); + IX_SWQ_CACHE_INVALIDATE(ixQMgrGrpMemBaseInvalid[group], + ixQMgrGrpMemSize[group]); + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrDispatcherLoopRun\n"); +} + + +/** + * Run the callback dispatcher in the reverse order of notif enabling + * the first queue enabled for notification will be the last to be serviced. + */ +void +ixQMgrDispatcherLoopRunReverse (IxQMgrDispatchGroup group) +{ + IxQMgrQId qId = 0; + IxQMgrQState qState; + IxQMgrNotificationCondition condition; + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrDispatcherLoopRunReverse\n"); +#ifndef NDEBUG + if (!ixQMgrInitialised) + { + IX_QMGR_REPORT_ERROR ("ixQMgrDispatcherLoopRunReverse: " + "ixQMgr component not initialised\n"); + return; + } + else if (group >= IX_QMGR_MAX_NUM_DISPATCH_GRP) + { + IX_QMGR_REPORT_ERROR ("ixQMgrDispatcherLoopRunReverse: " + "invalid group\n"); + return; + } +#endif + + /* preload the counters for the group of queues */ + IX_OSAL_CACHE_PRELOAD(ixQMgrGrpMemBaseInvalid[group], + ixQMgrGrpMemSize[group]); + + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: start searching...\n"); + qId = ixQMgrFirstQInGrpList[group]; + while ( qId < IX_QMGR_MAX_NUM_QUEUES) + { + /* check if notification is enabled */ + if (ixQMgrQueues[qId].notifCond != IX_QMGR_Q_SOURCE_INVALID) + { + IX_QMGR_TRACE0 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: Notif enabled on " + "this queue\n"); + /* check state */ + ixQMgrQStatusGet(qId, &qState); + condition = ixQMgrQueues[qId].notifCond; + + if (condition == qState) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: " + "Notification enabled on Queue %d, State %d, " + "Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, ixQMgrQueues[qId].callbackId); + } + else if (condition == IX_QMGR_Q_SOURCE_ID_NOT_E) + { + if (qState != IX_QMGR_Q_STATE_E) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: " + "Notification enabled on Queue %d, " + "State %d, Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, + ixQMgrQueues[qId].callbackId); + } + } + else if (condition == IX_QMGR_Q_SOURCE_ID_NOT_F) + { + if (qState != IX_QMGR_Q_STATE_F) + { + IX_QMGR_TRACE3 (IX_QMGR_DEBUG, + "ixQMgrDispatcherLoopRunReverse: " + "Notification enabled on Queue %d, " + "State %d, Condition %d\n", + qId, + qState, + condition); + /* call callback function */ + ixQMgrQueues[qId].callback (qId, + ixQMgrQueues[qId].callbackId); + } + } + } + qId = ixQMgrQueues[qId].nextQId; + } + IX_SWQ_CACHE_FLUSH(ixQMgrGrpMemBaseFlush[group], ixQMgrGrpMemSize[group]); + IX_SWQ_CACHE_INVALIDATE(ixQMgrGrpMemBaseInvalid[group], + ixQMgrGrpMemSize[group]); + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrDispatcherLoopRunReverse\n"); +} + + +/** + * Set the notification callback for a queue + */ +icp_status_t +ixQMgrNotificationCallbackSet (IxQMgrQId qId, + IxQMgrCallback callback, + IxQMgrCallbackId callbackId) +{ + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Entering ixQMgrNotificationCallbackSet\n"); + if (!ixQMgrInitialised) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationCallbackSet :" + "ixQMgr component not initialised\n"); + ixQMgrComponentStats.numCallbackSet.fail ++; + return ICP_STATUS_FAIL; + } + else if (qId >= IX_QMGR_MAX_NUM_QUEUES) + { + /* Report Error */ + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationCallbackSet :" + "invalid Q Id\n"); + ixQMgrComponentStats.numCallbackSet.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else if (callback == NULL) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationCallbackSet :" + "invalid callback\n"); + ixQMgrComponentStats.numCallbackSet.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + /* Check Q is Initialised, Source parameter is Valid*/ + if (!IX_SWQ_INITIALISED(ixQMgrQueues[qId].queue)) + { + IX_QMGR_REPORT_ERROR ("ixQMgrNotificationCallbackSet :" + "Q not configured\n"); + ixQMgrComponentStats.numCallbackSet.fail ++; + return ICP_STATUS_INVALID_PARAM; + } + else + { + /* set condition to trigger a notification */ + ixQMgrQueues[qId].callback = callback; + ixQMgrQueues[qId].callbackId = callbackId; + ixQMgrComponentStats.numCallbackSet.success ++; + } + } + + IX_QMGR_TRACE0 (IX_QMGR_FN_ENTRY_EXIT, + "Exiting ixQMgrNotificationCallbackSet\n"); + return ICP_STATUS_SUCCESS; +} + diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgrSymbols.c b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgrSymbols.c new file mode 100644 index 0000000..c2f5571 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/IxQMgrSymbols.c @@ -0,0 +1,116 @@ +/***************************************************************************** + * @file IxQMgrSymbols.c + * + * @description Contents of this file provide the Software Queue Manager + * Component exported symbols. + * + * @ingroup qMgr + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ****************************************************************************/ + + +#ifdef __linux + + +#include <IxOsal.h> + +#include <linux/module.h> +#include <IxQMgr.h> + +EXPORT_SYMBOL(ixQMgrInit); +EXPORT_SYMBOL(ixQMgrUnload); +EXPORT_SYMBOL(ixQMgrShow); +EXPORT_SYMBOL(ixQMgrQShow); +EXPORT_SYMBOL(ixQMgrGroupMemoryConfig); +EXPORT_SYMBOL(ixQMgrQConfig); +EXPORT_SYMBOL(ixQMgrQSizeReconfig); +EXPORT_SYMBOL(ixQMgrUnconfigGroup); +EXPORT_SYMBOL(ixQMgrQSizeGet); +EXPORT_SYMBOL(ixQMgrWatermarkSet); +EXPORT_SYMBOL(ixQMgrQReadWithChecks); +EXPORT_SYMBOL(ixQMgrQRead); +EXPORT_SYMBOL(ixQMgrQBurstRead); +EXPORT_SYMBOL(ixQMgrQReadAdvance); +EXPORT_SYMBOL(ixQMgrQWriteWithChecks); +EXPORT_SYMBOL(ixQMgrQWrite); +EXPORT_SYMBOL(ixQMgrQBurstWrite); +EXPORT_SYMBOL(ixQMgrQNumEntriesGetWithChecks); +EXPORT_SYMBOL(ixQMgrQNumEntriesGet); +EXPORT_SYMBOL(ixQMgrQStatusGetWithChecks); +EXPORT_SYMBOL(ixQMgrQStatusGet); +EXPORT_SYMBOL(ixQMgrNotificationEnable); +EXPORT_SYMBOL(ixQMgrNotificationDisable); +EXPORT_SYMBOL(ixQMgrDispatcherLoopRun); +EXPORT_SYMBOL(ixQMgrDispatcherLoopRunReverse); +EXPORT_SYMBOL(ixQMgrNotificationCallbackSet); +EXPORT_SYMBOL(ixQMgrShadowAdvanceWithChecks); +EXPORT_SYMBOL(ixQMgrShadowAdvance); +EXPORT_SYMBOL(ixQMgrShadowDeltaGetWithChecks); +EXPORT_SYMBOL(ixQMgrShadowDeltaGet); +EXPORT_SYMBOL(ixQMgrQWriteRollbackWithChecks); +EXPORT_SYMBOL(ixQMgrQWriteRollback); +EXPORT_SYMBOL(ixQMgrQueues); + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/Makefile b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/Makefile new file mode 100644 index 0000000..5ce26ab --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/Makefile @@ -0,0 +1,123 @@ +######################################################################### +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears derived objects except the .depend files +# distclean- clears all derived objects and the .depend file +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + + +# Ensure The ICP_ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ICP_ENV_DIR <path>") +endif + +#Add your project environment Makefile +include $(ICP_ENV_DIR)/environment.mk + + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=$(ICP_TDM_QMGR_NAME) + + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES=IxQMgr.c \ + + +#common includes between all supported OSes +INCLUDES+= -I $(PWD)/include \ + -I $(src)/include \ + -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_OSAL_DIR)/common/include + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES+= -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM -DENABLE_BUFFERMGT + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_TDM_QMGR_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + + + +# On the line directly below list the outputs you wish to build for, +# e.g "lib_static lib_shared exe module" as show below +install: module + + + +###################Include rules makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules inclusion######################### diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/include/IxQMgrTrace_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/include/IxQMgrTrace_p.h new file mode 100644 index 0000000..1b4572c --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/include/IxQMgrTrace_p.h @@ -0,0 +1,255 @@ +/** + * @file IxQMgrTrace_p.h + * + * @date 01-Mar-04 + * + * @brief Private API for Queue Manager Tracing + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + */ + + +/** + * @defgroup IxQMgr IxQMgrTracing_p + * + * @brief Private API for Queue Manager Error and Debug Tracing + * + * @{ + */ + +#ifndef IXQMGRTRACE_P_H +#define IXQMGRTRACE_P_H + +#include "IxOsal.h" + + +/** + * Prototypes for interface functions. + */ + +/** + * @typedef IxQMgrTraceTypes + * @brief Enumeration defining Queue Manager trace levels + */ + +typedef enum +{ + IX_QMGR_TRACE_OFF, /**< NO TRACE */ + IX_QMGR_DEBUG, /**< Select traces of interest */ + IX_QMGR_FN_ENTRY_EXIT /**< ALL function entry/exit traces */ +} IxQMgrTraceTypes; + +/** + * #defines for function return types, etc. + */ + +/** + * @def IX_QMGR_TRACE_LEVEL + * + * @brief Queue Manager debug trace level + */ +#ifndef IX_CONFIGURATION_unit_test +#define IX_QMGR_TRACE_LEVEL IX_QMGR_TRACE_OFF +#else +#define IX_QMGR_TRACE_LEVEL IX_QMGR_FN_ENTRY_EXIT +#endif + +/** + * @def IX_QMGR_REPORT_ERROR + * + * @brief Mechanism for reporting Queue Manager software errors + * + * @param char* [in] STR - Error string to report + * + * This macro sends the error string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_REPORT_ERROR(STR) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); + +/** + * @def IX_QMGR_REPORT_ERROR_2 + * + * @brief Mechanism for reporting Queue Manager software errors + * with 2 arguments + * + * @param char* [in] STR - Error string to report + * @param argType [in] ARG1 - Argument to trace + * @param argType [in] ARG2 - Argument to trace + * + * This macro sends the error string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_REPORT_ERROR_2(STR,ARG1,ARG2) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, STR, ARG1, ARG2, 0, 0, 0, 0); + +/** + * @def IX_QMGR_TRACE0 + * + * @brief Mechanism for tracing debug for the Queue Manager component, for no + * arguments + * + * @param unsigned [in] LEVEL - one of IxQMgrTraceTypes enumerated values + * @param char* [in] STR - Trace string + * + * This macro sends the trace string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_TRACE0(LEVEL, STR) \ +{ \ + if (LEVEL <= IX_QMGR_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, 0, 0, 0, 0, 0, 0); \ + } \ +} + +/* + * @def IX_QMGR_TRACE1 + * + * @brief Mechanism for tracing debug for the Queue Manager component, with one + * argument + * + * @param unsigned [in] LEVEL - one of IxQMgrTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * + * This macro sends the trace string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_TRACE1(LEVEL, STR, ARG1) \ +{ \ + if (LEVEL <= IX_QMGR_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, (int) ARG1, 0, 0, 0, 0, 0); \ + } \ +} + +/** + * @def IX_QMGR_TRACE2 + * + * @brief Mechanism for tracing debug for the Queue Manager component, with two + * arguments + * + * @param unsigned [in] LEVEL - one of IxQMgrTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * @param argType [in] ARG2 - Argument to trace + * + * This macro sends the trace string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_TRACE2(LEVEL, STR, ARG1, ARG2) \ +{ \ + if (LEVEL <= IX_QMGR_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, (int) ARG1, (int) ARG2, 0, 0, 0, 0); \ + } \ +} + +/** + * @def IX_QMGR_TRACE3 + * + * @brief Mechanism for tracing debug for the Queue Manager component, with two + * arguments + * + * @param unsigned [in] LEVEL - one of IxQMgrTraceTypes enumerated values + * @param char* [in] STR - Trace string + * @param argType [in] ARG1 - Argument to trace + * @param argType [in] ARG2 - Argument to trace + * @param argType [in] ARG3 - Argument to trace + * + * This macro sends the trace string passed to ixOsalLog + * + * @return none + */ +#define IX_QMGR_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \ +{ \ + if (LEVEL <= IX_QMGR_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, STR, (int) ARG1, (int) ARG2, (int) ARG3, 0, 0, 0); \ + } \ +} + + + +/** + * @def IX_QMGR_PRINT + * + * @brief macro to separate the Queue Manager component from the OS specific + * printing function. this is solely for debug purposes during development + * and integration + * + * @return none + */ +#ifdef __KERNEL__ +#define IX_QMGR_PRINT printk +#else +#define IX_QMGR_PRINT printf +#endif /* __KERNEL__ */ + +#endif /* IXQMGRTRACE_H */ + +/** + * @} defgroup IxQMgr + */ diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..f5ad46a --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_queue_manager/linux_2.6_kernel_space.mk @@ -0,0 +1,77 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + + + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += -DEP805XX -D__ep805xx -D__tolapai -DTOLAPAI -DIX_HW_COHERENT_MEMORY=1 $(INCLUDES) +EXTRA_LDFLAGS+=-whole-archive + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/Makefile b/Acceleration/library/icp_telephony/tdm_io_access/Makefile new file mode 100644 index 0000000..04fc632 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/Makefile @@ -0,0 +1,136 @@ +############################################################################ +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears derived objects except the .depend files +# distclean- clears all derived objects and the .depend file +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# Copyright(c) 2010,2011,2012 Avencall +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +############################################################################ + + +# Ensure The ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to your environment makefile \ + "-> setenv ENV_DIR <path>") +endif + +#Add your project environment Makefile, extra comment +include $(ICP_ENV_DIR)/environment.mk + + +#include the makefile with all the default and common Make variable definitions +include $(ICP_BUILDSYSTEM_PATH)/build_files/common.mk + + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME=$(ICP_TDM_IO_NAME) + +# List of Source Files to be compiled (to be in a single line or on different lines separated by a "\" and tab. +SOURCES= icp_hssacc_common.c \ + icp_hssacc_channel_list.c \ + icp_hssacc_channel_config.c \ + icp_hssacc_voice_bypass.c \ + icp_hssacc_service.c \ + icp_hssacc_queues_config.c \ + icp_hssacc_rx_datapath.c \ + icp_hssacc_tx_datapath.c \ + icp_hssacc_port_config.c \ + icp_hssacc_port_hdma_reg_mgr.c \ + icp_hssacc_common_timeslot_allocation.c \ + $(ICP_DEVICE)$(ICP_SLASH)icp_hssacc_timeslot_allocation.c \ + $(ICP_DEVICE)$(ICP_SLASH)icp_hssacc_address_translate.c \ + $(ICP_DEVICE)$(ICP_SLASH)icp_hssacc_param_check.c + + +# Setup include directory +INCLUDES += -I $(src)/include \ + -I $(PWD)/include \ + -I $(ICP_API_DIR) \ + -I $(ICP_API_DIR)/hss \ + -I $(ICP_API_DIR)/accel_infra \ + -I $(ICP_OSAL_DIR)/common/include + +ifeq ($(ICP_INTEL_DEV),YES) +INCLUDES += -I $(ICP_OSAL_DIR)/common/include/modules \ + -I $(ICP_OSAL_DIR)/common/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/include/modules/bufferMgt \ + -I $(ICP_OSAL_DIR)/common/include/modules/ioMem +endif + +EXTRA_CFLAGS += -DENABLE_IOMEM -DENABLE_BUFFERMGT + + +#include your $(ICP_OS)_$(ICP_OS_LEVEL).mk file +include $(ICP_TDM_IO_DIR)/$(ICP_OS)_$(ICP_OS_LEVEL).mk + + +# Install the module to the output dir +install: module + + +###################Include rules and dependency makefiles######################## +include $(ICP_BUILDSYSTEM_PATH)/build_files/rules.mk +###################End of Rules and dependency inclusion######################### + + + + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_address_translate.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_address_translate.c new file mode 100644 index 0000000..73a1269 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_address_translate.c @@ -0,0 +1,178 @@ +/****************************************************************************** + * @file icp_hssacc_address_translate.c + * + * @description Content of this file provides the definition of + * address translation functions from the virtual + * address space to the physical and vice-versa + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_address_translate.h" +#include "icp_hssacc_trace.h" + +uint32_t +HssAccVirtToPhysAddressTranslateAndSwap(void* pVirtAddr) +{ + uint32_t physAddr = 0; + /* Convert the table base address to a physical address */ + physAddr = HssAccVirtToPhysAddressTranslate (pVirtAddr); +#ifdef SW_SWAPPING + /* Now convert the physical address to network order */ + physAddr = IX_OSAL_SWAP_BE_SHARED_LONG(physAddr); +#endif + return physAddr; +} + +void * +HssAccPhysToVirtAddressSwapAndTranslate(uint32_t physAddr) +{ + void * pVirtAddr = NULL; +#ifdef SW_SWAPPING + /* Now convert the physical address back to little endian mode */ + physAddr = IX_OSAL_SWAP_BE_SHARED_LONG(physAddr); +#endif + /* Convert the physical address to a virtual address*/ + pVirtAddr = HssAccPhysToVirtAddressTranslate (physAddr); + + return pVirtAddr; +} + + + +uint32_t +HssAccVirtToPhysAddressTranslate(void * const pVirtAddr) +{ + uint32_t physAddr = 0; + /* Convert the table base address to a physical address */ + physAddr = (uint32_t)IX_OSAL_MMU_VIRT_TO_PHYS (pVirtAddr); + + return physAddr; +} + + +void * +HssAccPhysToVirtAddressTranslate(const uint32_t physAddr) +{ + void * pVirtAddr = NULL; + + /* Convert the physical address to a table base address*/ + pVirtAddr = (void*)IX_OSAL_MMU_PHYS_TO_VIRT (physAddr); + + return pVirtAddr; +} + + + +void * +HssAccDmaMemAllocate(uint32_t sizeBytes, + uint32_t * physOffset) +{ + void * pVirtAddr = NULL; + *physOffset = 0; + pVirtAddr = (void *)IX_OSAL_CACHE_DMA_MALLOC(sizeBytes); + if (NULL != pVirtAddr) + { + *physOffset = HssAccVirtToPhysAddressTranslate(pVirtAddr); + } + return pVirtAddr; + +} + +/* This function perform an endianness swap on each word of the provided buffer + it assumed that the buffer size is a multiple of word size */ +void +HssAccDataEndiannessSwap(IX_OSAL_MBUF * const buffer) +{ +#ifdef SW_SWAPPING + uint32_t index = 0; + uint32_t * dataPtr = (uint32_t*)IX_OSAL_MBUF_MDATA(buffer); +#endif + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccDataEndiannessSwap" + " for Buffer 0x%08X\n", + (uint32_t)buffer); +#ifdef SW_SWAPPING + if ( 0 != (IX_OSAL_MBUF_PKT_LEN(buffer) % ICP_HSSACC_WORD_SIZE)) + { + ICP_HSSACC_REPORT_ERROR("HssAccDataEndiannessSwap - Buffer Provided" + " has a size that is not a multiple of a " + "word size\n"); + } + for (; + index < (IX_OSAL_MBUF_PKT_LEN(buffer) / ICP_HSSACC_WORD_SIZE); + index ++) + { + dataPtr[index] = IX_OSAL_SWAP_BE_SHARED_LONG(dataPtr[index]); + } +#endif + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccDataEndiannessSwap\n"); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_config.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_config.c new file mode 100644 index 0000000..4f4da9b --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_config.c @@ -0,0 +1,2174 @@ +/****************************************************************************** + * + * @file icp_hssacc_channel_config.c + * + * @description Contents of this file is the channel configuration module which + * include the implementation of the channel configuration API. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_channel_list.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_address_translate.h" +#include "icp_hssacc_tx_datapath.h" +#include "icp_hssacc_rx_datapath.h" + + +/* Stats */ +typedef struct icp_hssacc_channel_config_stats_s +{ + icp_hssacc_msg_with_resp_stats_t chanCfg; + icp_hssacc_msg_with_resp_stats_t chanEnable; + icp_hssacc_msg_with_resp_stats_t chanDisable; + icp_hssacc_msg_with_resp_stats_t hdlcChanCfg; + icp_hssacc_msg_with_resp_stats_t voiceChanCfg; + icp_hssacc_msg_with_resp_stats_t offsetTableLoad; + icp_hssacc_msg_with_resp_stats_t hdlcMaxRxCfg; +} icp_hssacc_channel_config_stats_t; + +typedef enum + { + ICP_HSSACC_VOICE_NB_CHAN_SIZE = 1, + ICP_HSSACC_VOICE_NBL_CHAN_SIZE = 2, + ICP_HSSACC_VOICE_WB_CHAN_SIZE = 4, + ICP_HSSACC_VOICE_UWB_CHAN_SIZE = 8 + } icp_hssacc_voice_supported_sizes_t; + + +/* definition in Bytes of the maximum sample size for each type of voice + channel.for example, G711 30msec sample is the factor for determining max + size for a narrowband channel */ + +#define ICP_HSSACC_VOICE_NB_MAX_SAMPLE_SIZE (240) +#define ICP_HSSACC_VOICE_NBL_MAX_SAMPLE_SIZE (480) +#define ICP_HSSACC_VOICE_WB_MAX_SAMPLE_SIZE (960) +#define ICP_HSSACC_VOICE_UWB_MAX_SAMPLE_SIZE (1920) + + +#define ICP_HSSACC_FCS_4_BYTE_WIDTH (4) +#define ICP_HSSACC_FCS_2_BYTE_WIDTH (2) + +/* + * Sets the enable bit in the timeslot word of HSS port provision table. + */ +#define ICP_HSSACC_HDMA_TIMESLOT_ENABLE (BIT_SET(23)) + +/* + * The channel ID must be shifted by this offset in the HSS port + * provision table + */ +#define ICP_HSSACC_HDMA_CHANNEL_OFFSET (16) + + + + +/* + * ---------------------------------------------------------------------------- + * Struct types + * ---------------------------------------------------------------------------- + */ +/* + * ---------------------------------------------------------------------------- + * Global variables + * ---------------------------------------------------------------------------- + */ + +/* Tracks the current channel state and configuration */ +TDM_PRIVATE icp_hssacc_channel_config_t +hssAccChannelConfig[ICP_HSSACC_MAX_NUM_CHANNELS]; + + +/* This variable holds the number of channels currently allocated. */ +TDM_PRIVATE unsigned hssAccNumChansAllocated = 0; + +TDM_PRIVATE icp_hssacc_channel_config_stats_t hssAccChanCfgStats; + +TDM_PRIVATE icp_boolean_t channelConfigModuleInitialised = ICP_FALSE; + + +/* + * ---------------------------------------------------------------------------- + * Static function declarations + * ---------------------------------------------------------------------------- + */ + +TDM_PRIVATE icp_status_t +HssAccChannelConfigHdlcServiceMsgSend (unsigned channelId); + +TDM_PRIVATE icp_status_t +HssAccChannelConfigVoiceServiceMsgSend (unsigned channelId); + + +TDM_PRIVATE icp_status_t +HssAccChannelConfigHdlcMaxFrameSizeSend (unsigned channelId); + +TDM_PRIVATE icp_status_t +HssAccChannelConfigMsgSend (unsigned channelId); + +TDM_PRIVATE void +HssAccChannelConfigStateReset (unsigned channelId); + + +/***************************************************************************** + * Abstract: + * The timeslot map for a given channel cannot span multiple TDM trunks, + * i.e. all timeslots pertaining to a channel must reside solely on + * line0_timeslot_bit_map, line1_timeslot_bit_map, line2_timeslot_bit_map + * or line3_timeslot_bit_map. + * This function enforces this policy as well as checking that at least 1 + * TS as been assigned. + *****************************************************************************/ +inline icp_status_t HssAccTimeslotErrorCheck (icp_hssacc_timeslot_map_t tsMap) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTimeslotErrorCheck\n"); + if (tsMap.line0_timeslot_bit_map != 0) + { + if ( (tsMap.line1_timeslot_bit_map | tsMap.line2_timeslot_bit_map | + tsMap.line3_timeslot_bit_map) != 0 ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTimeslotErrorCheck - The channel " + "timeslot mapping cannot span " + "TDM lines!\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + else if (tsMap.line1_timeslot_bit_map != 0) + { + if ( (tsMap.line2_timeslot_bit_map | + tsMap.line3_timeslot_bit_map) != 0 ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTimeslotErrorCheck - The channel " + "timeslot mapping cannot span " + "TDM lines!\n"); + status = ICP_STATUS_INVALID_PARAM; } + } + else if (tsMap.line2_timeslot_bit_map != 0) + { + if ( (tsMap.line3_timeslot_bit_map) != 0 ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTimeslotErrorCheck - The channel " + "timeslot mapping cannot span " + "TDM lines!\n"); + status = ICP_STATUS_INVALID_PARAM; } + } + else if (tsMap.line3_timeslot_bit_map == 0) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTimeslotErrorCheck - Invalid timeslot" + " configuration, no slots were chosen!\n"); + status = ICP_STATUS_INVALID_PARAM; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTimeslotErrorCheck\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * counts the number of timeslots requested by the channel, + * determines the HSS line that the timeslots reside on and copies the + * appropriate line's TDM map to the variable chanTsMap. at least one TS + * must be assigned for this function to function correctly. + * + ****************************************************************************/ +void HssAccTimeslotConfigGet(icp_hssacc_timeslot_map_t tsMap, + unsigned * numTs, + icp_hssacc_line_t * lineId, + uint32_t * chanTsMap, + unsigned * firstTsPosition, + unsigned * lastTsPosition) +{ + unsigned tempNumTs = 0; + uint32_t bitMap = 0; + icp_boolean_t firstFound = ICP_FALSE; + + (*lastTsPosition) = 0; + (*firstTsPosition) = 0; + if (tsMap.line0_timeslot_bit_map != 0) + { + *lineId = ICP_HSSACC_LINE_0; + *chanTsMap = tsMap.line0_timeslot_bit_map; + } + else if (tsMap.line1_timeslot_bit_map != 0) + { + *lineId = ICP_HSSACC_LINE_1; + *chanTsMap = tsMap.line1_timeslot_bit_map; + } + else if (tsMap.line2_timeslot_bit_map != 0) + { + *lineId = ICP_HSSACC_LINE_2; + *chanTsMap = tsMap.line2_timeslot_bit_map; + } + else if (tsMap.line3_timeslot_bit_map != 0) + { + *lineId = ICP_HSSACC_LINE_3; + *chanTsMap = tsMap.line3_timeslot_bit_map; + } + bitMap = *chanTsMap; + tempNumTs += (bitMap & 1); + if (bitMap & 1) + { + firstFound = ICP_TRUE; + } + bitMap >>= 1; + while (bitMap) + { + tempNumTs += (bitMap & 1); + (*lastTsPosition) ++; + if ((ICP_FALSE == firstFound) && + (bitMap & 1)) + { + firstFound = ICP_TRUE; + (*firstTsPosition) = (*lastTsPosition); + } + bitMap >>= 1; + } + *numTs = tempNumTs; +} + +/****************************************************************************** + * Abstract: + * Initialises all global variables used during channel configuration. + * Allocates memory for the channel offset tables. + * Initialises the channel configuration mutex. + * + *****************************************************************************/ +icp_status_t +HssAccChannelConfigInit(void) +{ + unsigned channelId = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigInit\n"); + + if (ICP_TRUE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccChannelConfigInit - " + "Module is already Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Initialise the channel configuration struct */ + for (channelId = 0; + channelId < ICP_HSSACC_MAX_NUM_CHANNELS; + channelId ++) + { + HssAccChannelConfigStateReset(channelId); + } + + /* All channels are available */ + hssAccNumChansAllocated = 0; + } + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTsAllocInit(); + } + if (ICP_STATUS_SUCCESS == status) + { + /* Reset the Messaging Stats */ + HssAccChannelConfigStatsReset(); + + /* Reset the Timeslot Allocation submodule Stats */ + HssAccTsAllocStatsReset(); + + HssAccChannelListsReset(); + + channelConfigModuleInitialised = ICP_TRUE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigInit\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * shuts down the channel Configuration sub-component of HSS Acc. + * it will reset all internal variables. + * + *****************************************************************************/ +icp_status_t +HssAccChannelConfigShutdown(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigShutdown\n"); + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccChannelConfigShutdown - " + "Service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + HssAccTsAllocShutdown(); + /* just in case, set the number of used channels to the max so that + no one can allocate new channels */ + hssAccNumChansAllocated = ICP_HSSACC_MAX_NUM_CHANNELS; + channelConfigModuleInitialised = ICP_FALSE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigShutdown\n"); + return status; +} + +/****************************************************************************** + * Abstract: + * Allocate a channel on the specified port using the specified + * timeslots. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelAllocate (unsigned *pChannelId, + unsigned portId, + icp_hssacc_timeslot_map_t tsMap, + icp_hssacc_channel_type_t channelType) +{ + unsigned channelSize = 0; + unsigned channelId = ICP_HSSACC_MAX_NUM_CHANNELS; + icp_hssacc_line_t lineId = ICP_HSSACC_LINE_DELIMITER; + uint32_t channelTsMap = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t suitableChanIdFound = ICP_FALSE; + icp_boolean_t mutexLocked = ICP_FALSE; + unsigned lastTsPos = 0; + unsigned firstTsPos = ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelAllocate - " + "\n\tchannelPtr 0x%08X on port %u of type %u\n", + (unsigned)pChannelId, portId, channelType); + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - " + "service not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Sanity check the parameters */ + if ( (NULL == pChannelId) || + (portId >= ICP_HSSACC_MAX_NUM_PORTS) || + ICP_HSSACC_ENUM_INVALID (channelType, + ICP_HSSACC_CHAN_TYPE_DELIMITER) ) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - invalid " + "parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if (HssAccPortStateGet(portId) != ICP_HSSACC_PORT_ENABLED) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccChannelAllocate - specified " + "port %u should be Enabled\n", + portId); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Verify that client requested a valid timeslot configuration */ + status = HssAccTimeslotErrorCheck (tsMap); + } + if (ICP_STATUS_SUCCESS == status) + { + /* + Extract all information from the timeslot mapping for this channel; + this includes the number of timeslots that the channel wants to use, + and the line on which the timeslots reside. + */ + HssAccTimeslotConfigGet (tsMap, &channelSize, + &lineId, &channelTsMap, + &firstTsPos, &lastTsPos); + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "icp_HssAccChannelAllocate -" + " Timeslot Config with Size=%u and lastTsPos=%u\n", + channelSize, + lastTsPos); + + /* Check that the line used and timeslots used are compatible + with the port speed */ + status = HssAccPortLineValidCheck(portId, lineId, + firstTsPos, lastTsPos); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* If this is a voice channel then it can only use + 1, 2 or 4 timeslots */ + if ( (ICP_HSSACC_CHAN_TYPE_VOICE == channelType) && + (channelSize != ICP_HSSACC_VOICE_NB_CHAN_SIZE && + channelSize != ICP_HSSACC_VOICE_NBL_CHAN_SIZE && + channelSize != ICP_HSSACC_VOICE_WB_CHAN_SIZE)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - " + "invalid number of timeslots. " + "A voice channel can only use" + " 1, 2 or 4 timeslots.\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocated - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * All channels may be used, so check before looping + * through each channel ID + */ + if (ICP_HSSACC_MAX_NUM_CHANNELS == hssAccNumChansAllocated) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - " + "All channels have" + " been allocated!\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Verify that the timeslots requested aren't owned by another channel */ + if (ICP_FALSE == HssAccTsAvailableVerify (portId, lineId, channelTsMap)) + { + /* The timeslots are in use by another channel */ + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - The requested " + "timeslots have been reserved by " + "another channel\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * If the code makes it to here there must be + * at least one channel not in use; find it. + * channelId going out of bounds checked for + * paranoias sake. + */ + channelId = 0; + while ((ICP_HSSACC_MAX_NUM_CHANNELS > channelId) && + (ICP_FALSE == suitableChanIdFound)) + { + if (ICP_HSSACC_CHANNEL_UNINITIALISED == + hssAccChannelConfig[channelId].state) + { + hssAccNumChansAllocated ++; + suitableChanIdFound = ICP_TRUE; + } + else + { + channelId ++; + } + } + + /* Save the channel ID to return to the client */ + *pChannelId = channelId; + + + /* Save these timeslots as in use by this channel */ + HssAccTsRegister (channelId, portId, + lineId, channelTsMap); + + hssAccChannelConfig[channelId].size = channelSize; + hssAccChannelConfig[channelId].lineId = lineId; + hssAccChannelConfig[channelId].timeslotMap = channelTsMap; + + } + + if (ICP_STATUS_SUCCESS == status) + { + + /* Update the channel configuration */ + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_ALLOCATED; + hssAccChannelConfig[channelId].type = channelType; + hssAccChannelConfig[channelId].portId = portId; + + HssAccTxDatapathChanTypeUpdate(channelId, + channelType); + + /* Update the channel offset tables with these timeslots */ + status = HssAccTsAllocUpdate (portId, + hssAccChannelConfig); + + if (ICP_STATUS_SUCCESS == status) + { + /* Update the Queue Manager Info */ + status = HssAccQueueConfigQSizeUpdate(channelId, channelType); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccChannelListAdd(portId, channelId, channelSize); + } + if (ICP_STATUS_SUCCESS != status) + { + /* Revert Back */ + HssAccTsUnregister (portId, + hssAccChannelConfig[channelId].lineId, + hssAccChannelConfig[channelId].timeslotMap); + + /* Clear the timeslot allocation but keep the port, we + need it for generating the new tables */ + hssAccChannelConfig[channelId].lineId = ICP_HSSACC_LINE_DELIMITER; + hssAccChannelConfig[channelId].timeslotMap = 0; + hssAccChannelConfig[channelId].size = 0; + + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_UNINITIALISED; + hssAccNumChansAllocated --; + + ICP_HSSACC_REPORT_ERROR("icp_HssAccChannelAllocate - Failure " + "in updating the TDM I/O Unit with " + "the new channel\n"); + } + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelAllocate - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + if (ICP_STATUS_SUCCESS == status) + { + /* In case this channel was previously allocated and has + leftover stats */ + status = icp_HssAccChannelStatsReset(channelId); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelAllocate\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Configure the specified channel with the service agnostic parameters. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelConfigure (unsigned channelId, + icp_hssacc_data_polarity_t channelDataPolarity, + icp_hssacc_bit_endian_t channelBitEndianness, + icp_boolean_t channelByteSwapping, + icp_hssacc_bit_robbing_t rBitEnable, + icp_hssacc_robbed_bit_value_t rBitValue, + icp_hssacc_robbed_bit_location_t rBitLocation) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelConfigure for channel %u\n", + channelId); + + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) || + ICP_HSSACC_ENUM_INVALID (channelBitEndianness, + ICP_HSSACC_BIT_ENDIAN_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (rBitEnable, + ICP_HSSACC_BIT_ROBBING_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (channelDataPolarity, + ICP_HSSACC_DATA_POLARITY_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - invalid " + "parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_BIT_ROBBING_ONE_BIT == rBitEnable) + { + if (ICP_HSSACC_CHAN_TYPE_VOICE == + hssAccChannelConfig[channelId].type) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - robbed " + "Bit cannot be used for a " + "voice channel\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (ICP_HSSACC_ENUM_INVALID (rBitValue, + ICP_HSSACC_ROBBED_BIT_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (rBitLocation, + ICP_HSSACC_ROBBED_BIT_POS_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - invalid " + "robbed Bit parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHANNEL_ALLOCATED != hssAccChannelConfig[channelId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - Channel " + "is not in the correct state " + "for configuration\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].dataPolarity = channelDataPolarity; + hssAccChannelConfig[channelId].bitEndian = channelBitEndianness; + hssAccChannelConfig[channelId].byteSwap = channelByteSwapping; + hssAccChannelConfig[channelId].bitRobbing = rBitEnable; + hssAccChannelConfig[channelId].rBitValue = rBitValue; + hssAccChannelConfig[channelId].rBitLocation = rBitLocation; + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_CONFIGURED; + status = HssAccChannelConfigMsgSend(channelId); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccChannelConfigure - " + "failed to set channel configuration " + "in TDM I/O Unit\n"); + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_ALLOCATED; + } + } + + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelConfigure - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelConfigure\n"); + return status; +} + + + + + +/****************************************************************************** + * Abstract: + * Configure the HDLC service specific parameters for the + * specified channel. + *****************************************************************************/ +icp_status_t +icp_HssAccChannelHdlcServiceConfigure ( + unsigned channelId, + icp_hssacc_hdlc_crc_bit_width_t hdlcCrcBitWidth, + icp_hssacc_hdlc_sof_flag_type_t hdlcSofFlagType, + icp_hssacc_hdlc_idle_pattern_t hdlcRxIdlePattern, + icp_hssacc_hdlc_idle_pattern_t hdlcTxIdlePattern, + unsigned hdlcMaximumFrameSize) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + uint32_t maxHdlcServFrameSize = 0; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelHdlcServiceConfigure " + "for channel %u\n", + channelId); + + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) || + ICP_HSSACC_ENUM_INVALID (hdlcCrcBitWidth, + ICP_HSSACC_HDLC_CRC_BIT_WIDTH_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (hdlcSofFlagType, + ICP_HSSACC_HDLC_SOF_FLAG_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (hdlcRxIdlePattern, + ICP_HSSACC_HDLC_IDLE_PATTERN_DELIMITER) || + ICP_HSSACC_ENUM_INVALID (hdlcTxIdlePattern, + ICP_HSSACC_HDLC_IDLE_PATTERN_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "invalid parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (0 == hdlcMaximumFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Maximum HDLC Frame Size cannot be zero\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + maxHdlcServFrameSize = + HssAccRxDatapathMaxServiceFrameSizeGet(ICP_HSSACC_CHAN_TYPE_HDLC); + if (0 == maxHdlcServFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Maximum HDLC Frame Size for the HDLC " + "Service is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (hdlcMaximumFrameSize > maxHdlcServFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Maximum HDLC Frame Size for this channel" + " is greater than that for the Service\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + } + + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHANNEL_CONFIGURED != + hssAccChannelConfig[channelId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "Channel is not in the appropriate " + "State\n"); + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "icp_HssAccChannelHdlcServiceConfigure - " + "Channel is in State (%u)\n", + hssAccChannelConfig[channelId].state); + status = ICP_STATUS_RESOURCE; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHAN_TYPE_VOICE == hssAccChannelConfig[channelId].type) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "attempting to configure HDLC Service " + "for an allocated Voice Channel\n"); + status = ICP_STATUS_RESOURCE; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + + hssAccChannelConfig[channelId].sofFlagType = hdlcSofFlagType; + hssAccChannelConfig[channelId].hdlcTxIdlePattern = hdlcTxIdlePattern; + hssAccChannelConfig[channelId].hdlcRxIdlePattern = hdlcRxIdlePattern; + hssAccChannelConfig[channelId].hdlcMaxFrSize = hdlcMaximumFrameSize; + hssAccChannelConfig[channelId].hdlcCrcBitWidth = hdlcCrcBitWidth; + + + status = HssAccChannelConfigHdlcServiceMsgSend(channelId); + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccChannelConfigHdlcMaxFrameSizeSend (channelId); + } + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED; + } + } + + /* Free the channel configuration mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelHdlcServiceConfigure - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelHdlcServiceConfigure\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * Configure the Voice service specific parameters for the + * specified channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelVoiceServiceConfigure ( + unsigned channelId, + icp_hssacc_channel_voice_tx_idle_action_t txIdleAction, + uint8_t voiceIdlePattern, + unsigned voicePacketSize) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned maxAllowedPacketSize = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + uint32_t maxVoiceServSampleSize = 0; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelVoiceServiceConfigure " + "for channel %u\n", + channelId); + + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) || + ICP_HSSACC_ENUM_INVALID (txIdleAction, + ICP_HSSACC_VOICE_TX_IDLE_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "invalid parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHANNEL_CONFIGURED != + hssAccChannelConfig[channelId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure -" + " Channel not in the appropriate state\n"); + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "icp_HssAccChannelVoiceServiceConfigure - " + "Channel is in State (%u)\n", + hssAccChannelConfig[channelId].state); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHAN_TYPE_HDLC == hssAccChannelConfig[channelId].type) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "attempting to configure Voice Service " + "for an allocated HDLC Channel\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + switch (hssAccChannelConfig[channelId].size) + { + case ICP_HSSACC_VOICE_NB_CHAN_SIZE: + maxAllowedPacketSize = ICP_HSSACC_VOICE_NB_MAX_SAMPLE_SIZE; + break; + case ICP_HSSACC_VOICE_NBL_CHAN_SIZE: + maxAllowedPacketSize = ICP_HSSACC_VOICE_NBL_MAX_SAMPLE_SIZE; + break; + case ICP_HSSACC_VOICE_WB_CHAN_SIZE: + maxAllowedPacketSize = ICP_HSSACC_VOICE_WB_MAX_SAMPLE_SIZE; + break; + case ICP_HSSACC_VOICE_UWB_CHAN_SIZE: + maxAllowedPacketSize = ICP_HSSACC_VOICE_UWB_MAX_SAMPLE_SIZE; + break; + default: + /* unreachable due to verification in Allocation function */ + break; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (maxAllowedPacketSize < voicePacketSize) + { + ICP_HSSACC_REPORT_ERROR_2 ("icp_HssAccChannelVoiceServiceConfigure -" + " Voice Sample Size (%u) too large for " + "channel (max Allowed is %u)\n", + voicePacketSize, + maxAllowedPacketSize); + status = ICP_STATUS_INVALID_PARAM; + } + if (0 == voicePacketSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure -" + " Voice Sample Size cannot be zero\n"); + status = ICP_STATUS_INVALID_PARAM; + } + maxVoiceServSampleSize = + HssAccRxDatapathMaxServiceFrameSizeGet(ICP_HSSACC_CHAN_TYPE_VOICE); + if (0 == maxVoiceServSampleSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "Maximum Voice Sample Size for the Voice " + "Service is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (voicePacketSize > maxVoiceServSampleSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "Maximum Voice Sample Size for this channel" + " is greater than that for the Service\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + } + + + if (ICP_STATUS_SUCCESS == status) + { + + hssAccChannelConfig[channelId].voiceSampleSize = voicePacketSize; + hssAccChannelConfig[channelId].voiceIdlePattern = voiceIdlePattern; + hssAccChannelConfig[channelId].txIdleAction = txIdleAction; + hssAccChannelConfig[channelId].numBypasses = 0; + + status = HssAccChannelConfigVoiceServiceMsgSend (channelId); + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED; + } + } + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelVoiceServiceConfigure - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelVoiceServiceConfigure\n"); + return status; +} + + + + + + +/***************************************************************************** + * Abstract: + * Bring the specified channel UP, this will enable traffic flow on the + * channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelUp (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelUp for channel %u\n", + channelId); + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelUp - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelUp - invalid " + "channel Number\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED != + hssAccChannelConfig[channelId].state) && + (ICP_HSSACC_CHANNEL_DOWN != + hssAccChannelConfig[channelId].state)) + + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccChannelUp - channel %u " + "is not in an appropriate state " + "for enabling\n", + channelId); + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "icp_HssAccChannelUp - channel %u " + "is state (%u) for enabling\n", + channelId, + hssAccChannelConfig[channelId].state); + status = ICP_STATUS_RESOURCE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelUp - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE, + channelId, + ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_BOTH, + 0, 0, 0, 0, 0, + &message); + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE_RESPONSE, + &(hssAccChanCfgStats.chanEnable), + NULL); + + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_ENABLED; + } + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelUp - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelUp\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * Bring down the specified channel. this will stop all traffic on + * that channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelDown (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelDown for channel %u\n", + channelId); + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - invalid " + "channel\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_CHANNEL_ENABLED != hssAccChannelConfig[channelId].state) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccChannelDown - " + "channel %u is not enabled\n", + channelId); + status = ICP_STATUS_RESOURCE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if (0 != hssAccChannelConfig[channelId].numBypasses) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - channel is " + "used as part of a bypass, " + "disable bypass first\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* change the channel state so that the datapath puts + rx buffers onto the rx free queue and not into the + channel ring */ + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_DOWN_TRANSITION; + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE, + channelId, + ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_BOTH, + 0, 0, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE_RESPONSE, + &(hssAccChanCfgStats.chanDisable), + NULL); + + if (ICP_STATUS_SUCCESS == status) + { + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_DOWN; + } + else + { + /* restore state to enabled as the channel down failed */ + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_ENABLED; + } + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDown - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelDown\n"); + return status; +} + + + + + + + +/***************************************************************************** + * Abstract: + * Delete the specified Channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelDelete (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelDelete for channel %u\n", + channelId); + + if (ICP_FALSE == channelConfigModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - " + "Service is not Initialised\n"); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelDelete\n"); + return ICP_STATUS_FAIL; + } + + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - invalid " + "channel\n"); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelDelete\n"); + return ICP_STATUS_INVALID_PARAM; + } + + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + + if (ICP_STATUS_SUCCESS == status) + { + if (!((ICP_HSSACC_CHANNEL_CONFIGURED == + hssAccChannelConfig[channelId].state) || + (ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED == + hssAccChannelConfig[channelId].state) || + (ICP_HSSACC_CHANNEL_ALLOCATED == + hssAccChannelConfig[channelId].state))) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - channel " + "not available for deletion\n"); + status = ICP_STATUS_RESOURCE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + + status = HssAccChannelListRemove(hssAccChannelConfig[channelId].portId, + channelId, + hssAccChannelConfig[channelId].size); + } + if (ICP_STATUS_SUCCESS == status) + { + /* Reset config, may have to actually send message to the + TDM I/O Unit to completely remove conf */ + HssAccTsUnregister (hssAccChannelConfig[channelId].portId, + hssAccChannelConfig[channelId].lineId, + hssAccChannelConfig[channelId].timeslotMap); + + /* Clear the timeslot allocation but keep the port, we + need it for generating the new tables */ + hssAccChannelConfig[channelId].lineId = ICP_HSSACC_LINE_DELIMITER; + hssAccChannelConfig[channelId].timeslotMap = 0; + hssAccChannelConfig[channelId].size = 0; + + /* Clear Timeslot Allocation for this channel */ + status = HssAccTsAllocDelete(channelId, + hssAccChannelConfig); + + /* Deregister rx callback */ + HssAccChannelRxCallbackDeregister(channelId); + + /* Deregister tx callback */ + HssAccTxDatapathChanTxDoneCallbackDeregister(channelId); + + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccNumChansAllocated --; + + /* Clear the internal state */ + HssAccChannelConfigStateReset(channelId); + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelDelete - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelDelete\n"); + return status; +} + +/***************************************************************************** + * Abstract: + * Sends the channel Common Configuration message to the TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelConfigMsgSend (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint16_t sdcCtrl = 0; + uint8_t sdcCtrlMsB = 0; + uint8_t sdcCtrlLsB = 0; + uint32_t inversion = ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_INVERT_OFF; + uint8_t channelType = 0; + uint8_t bitReverse = ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_NO_REVERSE; + uint8_t byteSwap = ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_NO_SWAP; + uint8_t bitRobbing = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_OFF; + uint8_t rBitValue = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VALUE_ZERO; + uint8_t rBitLocation = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_SEVEN; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigMsgSend for channel %u\n", + channelId); + /* Build SDC Ctrl Register for the TDM I/O Unit */ + if (ICP_HSSACC_DATA_POLARITY_INVERT == + hssAccChannelConfig[channelId].dataPolarity) + { + inversion = ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_INVERT_ON; + } + + if (ICP_HSSACC_CHAN_TYPE_VOICE == hssAccChannelConfig[channelId].type) + { + channelType = ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_VOICE; + } + else + { + channelType = ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_HDLC; + } + + /* if channel endianness is LSB then bit reversion required */ + if (ICP_HSSACC_BIT_ENDIAN_LSB == hssAccChannelConfig[channelId].bitEndian) + { + bitReverse = ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_REVERSE; + } + + if (ICP_TRUE == hssAccChannelConfig[channelId].byteSwap) + { + byteSwap = ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_SWAP; + } + + if (ICP_HSSACC_BIT_ROBBING_ONE_BIT == + hssAccChannelConfig[channelId].bitRobbing) + { + bitRobbing = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_ONE_BIT_ON; + } + + if (ICP_HSSACC_ROBBED_BIT_ONE == hssAccChannelConfig[channelId].rBitValue) + { + rBitValue = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VALUE_ONE; + } + + if (ICP_HSSACC_ROBBED_BIT_POS_0 == + hssAccChannelConfig[channelId].rBitLocation) + { + rBitLocation = ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_ZERO; + } + + sdcCtrl = (bitRobbing << + ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_ROBBING_OFFSET) | + (rBitLocation << + ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_OFFSET) | + (rBitValue << + ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VAL_OFFSET) | + (inversion << ICP_HSSACC_TDM_IO_UNIT_SDC_INVERT_OFFSET) | + (channelType << ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_OFFSET) | + (bitReverse << ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_REVERSE_OFFSET) | + (byteSwap << ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_SWAP_OFFSET); + ICP_HSSACC_TRACE_1(ICP_HSSACC_DEBUG, + "Created SDC Ctrl Register 0x%04X\n", + sdcCtrl); + + sdcCtrlMsB = (sdcCtrl & ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_MSB_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_MSB_OFFSET; + + sdcCtrlLsB = sdcCtrl & ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_LSB_MASK; + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd8byteMsgCreate (ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG, + channelId, + hssAccChannelConfig[channelId].type, + hssAccChannelConfig[channelId].size, + sdcCtrlMsB, + sdcCtrlLsB, + 0, + 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG_RESPONSE, + &(hssAccChanCfgStats.chanCfg), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigMsgSend\n"); + return status; +} + + + + +/***************************************************************************** + * Abstract: + * Create the Transmit HDLC configuration register to be passed to the + * TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE uint8_t +HssAccChannelHdlcTxCfgRegCreate (unsigned channelId) +{ + uint8_t cfgReg = 0; + /* will always post tx-hdlc block bit flip in SDC co-proc */ + uint8_t bitFlip = ICP_HSSACC_TDM_IO_UNIT_HDLC_CFG_BIT_FLIP; + uint8_t sofFlagType = ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_SHARED; + uint8_t hdlcCrcBitWidth = ICP_HSSACC_TDM_IO_UNIT_HDLC_16_BIT_CRC; + uint8_t hdlcTxIdlePattern = ICP_HSSACC_TDM_IO_UNIT_HDLC_IDLE_FLAG; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelHdlcTxCfgRegCreate\n"); + + if (ICP_HSSACC_HDLC_IDLE_PATTERN_ONES == + hssAccChannelConfig[channelId].hdlcTxIdlePattern) + { + hdlcTxIdlePattern = ICP_HSSACC_TDM_IO_UNIT_HDLC_IDLE_ONES; + } + + if (ICP_HSSACC_HDLC_CRC_BIT_WIDTH_32 == + hssAccChannelConfig[channelId].hdlcCrcBitWidth) + { + hdlcCrcBitWidth = ICP_HSSACC_TDM_IO_UNIT_HDLC_32_BIT_CRC; + } + if (ICP_HSSACC_HDLC_SOF_ONE_FLAG == + hssAccChannelConfig[channelId].sofFlagType) + { + sofFlagType = ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_ONE; + } + else if (ICP_HSSACC_HDLC_SOF_TWO_FLAGS == + hssAccChannelConfig[channelId].sofFlagType) + { + sofFlagType = ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_TWO; + } + + cfgReg = + (sofFlagType << + ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_SF_OFFSET) | + (hdlcCrcBitWidth << + ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_FCS_OFFSET) | + (hdlcTxIdlePattern << + ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_IM_OFFSET) | + (bitFlip << + ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_POSTBF_OFFSET); + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccChannelHdlcTxCfgRegCreate 0x%02X\n", + cfgReg); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelHdlcTxCfgRegCreate\n"); + return cfgReg; +} + +/***************************************************************************** + * Abstract: + * Create the Receive HDLC configuration register to be passed to the + * TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE uint8_t +HssAccChannelHdlcRxCfgRegCreate (unsigned channelId) +{ + uint8_t cfgReg = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelHdlcRxCfgRegCreate\n"); + + + cfgReg = + (hssAccChannelConfig[channelId].hdlcCrcBitWidth << + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_FCS_OFFSET) | + (hssAccChannelConfig[channelId].hdlcRxIdlePattern << + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_IM_OFFSET); + + /* always pre rx-hdlc block bit flip in SDC co-proc */ + cfgReg |= (ICP_HSSACC_TDM_IO_UNIT_HDLC_CFG_BIT_FLIP << + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_PREBF_OFFSET); + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccChannelHdlcRxCfgRegCreate 0x%02X\n", cfgReg); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelHdlcRxCfgRegCreate\n"); + return cfgReg; +} + + + +/***************************************************************************** + * Abstract: + * Sends the channel HDLC Service Configuration message to + * the TDM I/O Unit + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelConfigHdlcServiceMsgSend (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint32_t fcsSizeB = ICP_HSSACC_FCS_4_BYTE_WIDTH; + uint8_t txCfg = 0, rxCfg = 0; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigHdlcServiceMsgSend " + "for channel %u\n", + channelId); + + if (ICP_HSSACC_HDLC_CRC_BIT_WIDTH_16 == + hssAccChannelConfig[channelId].hdlcCrcBitWidth) + { + fcsSizeB = ICP_HSSACC_FCS_2_BYTE_WIDTH; + } + + + /* Construct the TxCfg and RxCfg registers for the TDM I/O Unit */ + txCfg = HssAccChannelHdlcTxCfgRegCreate(channelId); + + rxCfg = HssAccChannelHdlcRxCfgRegCreate(channelId); + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd8byteMsgCreate (ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG, + channelId, + 0, + 0, + 0, + rxCfg, + txCfg, + fcsSizeB, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG_RESPONSE, + &(hssAccChanCfgStats.hdlcChanCfg), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigHdlcServiceMsgSend\n"); + return status; +} + + + + + +/***************************************************************************** + * Abstract: + * Sends the channel HDLC Maximum Receive Frame Size configuration message + * to the TDM I/O Unit. + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelConfigHdlcMaxFrameSizeSend (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint32_t hdlcMaximumFrameSize = 0; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigHdlcMaxFrameSizeSend " + "for channel %u\n", + channelId); + + hdlcMaximumFrameSize = + hssAccChannelConfig[channelId].hdlcMaxFrSize << + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET; + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR, + channelId, + 0, + 0, + hdlcMaximumFrameSize, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR_RESPONSE, + &(hssAccChanCfgStats.hdlcMaxRxCfg), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigHdlcMaxFrameSizeSend\n"); + return status; +} + + +/***************************************************************************** + * Abstract: + * Sends the channel Voice Service Configuration message to + * the TDM I/O Unit + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelConfigVoiceServiceMsgSend (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint32_t msgWord = 0; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigVoiceServiceMsgSend " + "for channel %u\n", + channelId); + msgWord = + (hssAccChannelConfig[channelId].voiceIdlePattern << + ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET) | + (hssAccChannelConfig[channelId].txIdleAction << + ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) | + hssAccChannelConfig[channelId].voiceSampleSize; + + /* Construct the message for Channel Voice parameters setting + in the TDM I/O Unit */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG, + channelId, + 0, + 0, + msgWord, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG_RESPONSE, + &(hssAccChanCfgStats.voiceChanCfg), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigVoiceServiceMsgSend\n"); + return status; +} + + + + + + +/***************************************************************************** + * Abstract: + * determines if it is valid to configure a bypass using the + * specified channel. + * + *****************************************************************************/ +icp_boolean_t +HssAccChannelConfigValidBypass(const unsigned channelId, + const unsigned portId) +{ + icp_boolean_t validChannel = ICP_FALSE; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelConfigValidBypass\n"); + + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccChannelConfigValidBypass - " + "Channel %u of size %u and state %u " + "selected for Bypass\n", + channelId, + hssAccChannelConfig[channelId].size, + hssAccChannelConfig[channelId].state); + + if ((ICP_HSSACC_CHAN_TYPE_VOICE == hssAccChannelConfig[channelId].type) && + (ICP_HSSACC_VOICE_NB_CHAN_SIZE == hssAccChannelConfig[channelId].size) && + (ICP_HSSACC_CHANNEL_ENABLED == hssAccChannelConfig[channelId].state) && + (portId == hssAccChannelConfig[channelId].portId)) + { + validChannel = ICP_TRUE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelConfigValidBypass\n"); + return validChannel; +} + + + +/***************************************************************************** + * Abstract: + * reset the Channel configuration stats + * + *****************************************************************************/ +void +HssAccChannelConfigStatsReset (void) +{ + memset (&hssAccChanCfgStats, 0, sizeof(icp_hssacc_channel_config_stats_t)); + HssAccChannelListsStatsReset (); + +} + +/***************************************************************************** + * Abstract: + * Display stats for channel configuration + * + *****************************************************************************/ +void +HssAccChannelConfigStatsShow (void) +{ + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Configuration Statistics:\nChannel Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.chanCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC Channel Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.hdlcChanCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice Channel Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.voiceChanCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\noffset Table Load\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.offsetTableLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC Max Receive Frame Size Cfg messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.hdlcMaxRxCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Enable messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.chanEnable); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Disable messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccChanCfgStats.chanDisable); + + /* Also print out the Timeslot Allocation submodule stats */ + HssAccTsAllocStatsShow (); + +} + + +/***************************************************************************** + * Abstract: + * display the state of the specified channel + * + *****************************************************************************/ +void +HssAccChannelConfigStateShow (unsigned channelId) +{ + if (ICP_HSSACC_CHANNEL_UNINITIALISED == + hssAccChannelConfig[channelId].state) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel %u is Uninitialised.\n", + channelId, 0, 0, 0, 0, 0); + } + else + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel %u is Allocated on port %u Line %u with " + "%u Timeslots\nTimeslot Map is 0x%08X\n", + channelId, + hssAccChannelConfig[channelId].portId, + hssAccChannelConfig[channelId].lineId, + hssAccChannelConfig[channelId].size, + hssAccChannelConfig[channelId].timeslotMap, 0); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel has been Configured with:\n" + "\tData Inversion %u\n" + "\tBit Endianness %u\n" + "\tByte Endianness %u\n", + hssAccChannelConfig[channelId].dataPolarity, + hssAccChannelConfig[channelId].bitEndian, + hssAccChannelConfig[channelId].byteSwap, 0, 0, 0); + if (ICP_HSSACC_BIT_ROBBING_ONE_BIT == + hssAccChannelConfig[channelId].bitRobbing) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Bit Robbing is Enabled with a value of %u and " + "a position of %d\n", + hssAccChannelConfig[channelId].rBitValue, + hssAccChannelConfig[channelId].rBitLocation == + ICP_HSSACC_ROBBED_BIT_POS_7 ? 7 + : (hssAccChannelConfig[channelId].rBitLocation == + ICP_HSSACC_ROBBED_BIT_POS_0 ? 0 : -1), + 0, 0, 0, 0); + } + + if (ICP_HSSACC_CHAN_TYPE_VOICE == hssAccChannelConfig[channelId].type) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel is Allocated for Voice\n", 0, 0, 0, 0, 0, 0); + } + else + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel is Allocated for HDLC\n", 0, 0, 0, 0, 0, 0); + } + switch (hssAccChannelConfig[channelId].state) + { + case ICP_HSSACC_CHANNEL_ALLOCATED: + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel has only been allocated\n", 0, 0, 0, 0, 0, 0); + break; + + } + case ICP_HSSACC_CHANNEL_CONFIGURED: + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel has been allocated and configured with " + "general settings\n", + 0, 0, 0, 0, 0, 0); + break; + + } + case ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED: + case ICP_HSSACC_CHANNEL_DOWN: + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel has been allocated and service " + "specific parameters have been set\n", 0, 0, 0, 0, 0, 0); + break; + + } + case ICP_HSSACC_CHANNEL_ENABLED: + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channel is Enabled\n", 0, 0, 0, 0, 0, 0); + break; + + } + case ICP_HSSACC_CHANNEL_UNINITIALISED: + default: + { + /* This statement is unreachable due to previous error checking */ + ICP_HSSACC_REPORT_ERROR("HssAccChannelConfigStateShow - " + "Invalid Channel State to be printed\n"); + break; + } + } + } +} + +/***************************************************************************** + * Abstract: + * reset all the internal data regarding the specified channel + * + *****************************************************************************/ +TDM_PRIVATE void +HssAccChannelConfigStateReset (unsigned channelId) +{ + hssAccChannelConfig[channelId].state = ICP_HSSACC_CHANNEL_UNINITIALISED; + hssAccChannelConfig[channelId].type = ICP_HSSACC_CHAN_TYPE_DELIMITER; + hssAccChannelConfig[channelId].size = 0; + hssAccChannelConfig[channelId].portId = ICP_HSSACC_MAX_NUM_PORTS; + hssAccChannelConfig[channelId].lineId = ICP_HSSACC_LINE_DELIMITER; + hssAccChannelConfig[channelId].timeslotMap = 0; + hssAccChannelConfig[channelId].sdcCtrlReg = 0; + hssAccChannelConfig[channelId].rxCfg = 0; + hssAccChannelConfig[channelId].txCfg = 0; + hssAccChannelConfig[channelId].dataPolarity = ICP_HSSACC_DATA_POLARITY_SAME; + hssAccChannelConfig[channelId].bitEndian = ICP_HSSACC_BIT_ENDIAN_DELIMITER; + hssAccChannelConfig[channelId].byteSwap = ICP_FALSE; + hssAccChannelConfig[channelId].bitRobbing = ICP_HSSACC_BIT_ROBBING_DELIMITER; + hssAccChannelConfig[channelId].rBitValue = ICP_HSSACC_ROBBED_BIT_DELIMITER; + hssAccChannelConfig[channelId].rBitLocation = + ICP_HSSACC_ROBBED_BIT_POS_DELIMITER; + hssAccChannelConfig[channelId].hdlcMaxFrSize = 0; + hssAccChannelConfig[channelId].numBypasses = 0; + hssAccChannelConfig[channelId].sofFlagType = + ICP_HSSACC_HDLC_SOF_FLAG_TYPE_DELIMITER; + hssAccChannelConfig[channelId].hdlcTxIdlePattern = + ICP_HSSACC_HDLC_IDLE_PATTERN_DELIMITER; + hssAccChannelConfig[channelId].hdlcRxIdlePattern = + ICP_HSSACC_HDLC_IDLE_PATTERN_DELIMITER; + hssAccChannelConfig[channelId].voiceSampleSize = 0; + hssAccChannelConfig[channelId].voiceIdlePattern = 0; + hssAccChannelConfig[channelId].txIdleAction = + ICP_HSSACC_VOICE_TX_IDLE_DELIMITER; + hssAccChannelConfig[channelId].hdlcCrcBitWidth = + ICP_HSSACC_HDLC_CRC_BIT_WIDTH_DELIMITER; +} + +/***************************************************************************** + * Abstract: + * returns the configured channel type for the specified channel + * + *****************************************************************************/ +icp_hssacc_channel_type_t +HssAccChannelConfigTypeQuery (unsigned channelId) +{ + return hssAccChannelConfig[channelId].type; +} + + +/***************************************************************************** + * Abstract: + * set the specified channels as part of a bypass. + * + *****************************************************************************/ +void +HssAccChannelBypassPairSet(unsigned srcChannelId, + unsigned destChannelId) +{ + hssAccChannelConfig[srcChannelId].numBypasses ++; + hssAccChannelConfig[destChannelId].numBypasses ++; +} + + +/***************************************************************************** + * Abstract: + * clear the bypassed state for the specified channels + * + *****************************************************************************/ +void +HssAccChannelBypassPairClear(unsigned srcChannelId, + unsigned destChannelId) +{ + hssAccChannelConfig[srcChannelId].numBypasses --; + hssAccChannelConfig[destChannelId].numBypasses --; +} + + +/***************************************************************************** + * Abstract: + * returns the state of the specified channel + * + *****************************************************************************/ +icp_hssacc_channel_state_t +HssAccChannelConfigStateQuery (unsigned channelId) +{ + return hssAccChannelConfig[channelId].state; +} + + +/***************************************************************************** + * Abstract: + * used by the datapath modules to notify for a change of channel state + * following the retrieval of all buffers in the channel queues. + * + *****************************************************************************/ +void +HssAccChannelConfigBuffersClearedNotify (unsigned channelId) +{ + if (ICP_HSSACC_CHANNEL_DOWN == hssAccChannelConfig[channelId].state) + { + hssAccChannelConfig[channelId].state = + ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED; + } +} + + + + +/***************************************************************************** + * Abstract: + * return ICP_TRUE if there are any allocated channels on + * the specified port. + * + *****************************************************************************/ +icp_boolean_t +HssAccChannelConfigUsedChansOnPortFind (const unsigned portId) +{ + icp_boolean_t chanFound = ICP_FALSE; + unsigned index = 0; + + for (index = 0; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + if ((ICP_HSSACC_CHANNEL_UNINITIALISED != + hssAccChannelConfig[index].state) && + (portId == hssAccChannelConfig[index].portId)) + { + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccChannelConfigUsedChansOnPortFind - " + "Channel %u allocated on port %u\n", + index, + portId); + chanFound = ICP_TRUE; + break; + } + } + + return chanFound; +} + + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_list.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_list.c new file mode 100644 index 0000000..5843de9 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_channel_list.c @@ -0,0 +1,911 @@ +/***************************************************************************** + * + * @file icp_hssacc_channel_list.c + * + * @description Contents of this file is the implementation of the channel + * list manipulation functionality. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_common.h" + + + + + +/** + * Typedefs whose scope is limited to this file. + */ + + +/* Structure holding list configuration data for one channel */ +typedef struct icp_hssacc_channel_list_data_s +{ + uint16_t prevChannelId; + uint16_t nextChannelId; + icp_hssacc_channel_list_t listId; +} icp_hssacc_channel_list_data_t; + + + +/* Stats for List Management*/ +typedef struct icp_hssacc_channel_list_stats_s +{ + icp_hssacc_msg_with_resp_stats_t nextChannelWrite; + icp_hssacc_msg_with_resp_stats_t portCfgChannel; +} icp_hssacc_channel_list_stats_t; + + +/* channel List Data for each channel */ +TDM_PRIVATE icp_hssacc_channel_list_data_t +hssAccChannelData[ICP_HSSACC_MAX_NUM_CHANNELS]; + +/* Track which channel is the last of the list for each list + on each port */ +TDM_PRIVATE uint32_t +hssAccLastChannelOnList[ICP_HSSACC_MAX_NUM_PORTS] +[ICP_HSSACC_CHANNEL_LIST_DELIMITER]; + +/* Internal Messaging Stats for this sub-module */ +TDM_PRIVATE icp_hssacc_channel_list_stats_t hssAccChannelListStats; + +/* Track the amount of IO transactions represented by each + list on each port */ +TDM_PRIVATE uint32_t +hssAccPortChannelListUsage[ICP_HSSACC_MAX_NUM_PORTS] +[ICP_HSSACC_CHANNEL_LIST_DELIMITER]; + +/* Construct and send the NextChanWrite message to the TDM IO Unit */ +TDM_PRIVATE icp_status_t +HssAccChannelNextChanWriteMsgSend (unsigned prevChannelId, + unsigned nextChannelId, + uint8_t txRxIndicator, + uint8_t nullFlag); + + +/* + * Function Prototype: HssAccChanIOUsageCalc + * Description: this function calculates the number + * of IO transactions that a specific channelSize implies + */ +inline unsigned HssAccChanIOUsageCalc(unsigned chanSize) +{ + unsigned channelUsageIO = + chanSize / ICP_HSSACC_TDM_IO_UNIT_MAX_TRANSACTION_SIZE_WRDS; + channelUsageIO ++; + if ( (chanSize % ICP_HSSACC_TDM_IO_UNIT_MAX_TRANSACTION_SIZE_WRDS) > 1 ) + { + channelUsageIO ++; + } + return channelUsageIO; +} + + + + +/* + * Function Prototype: HssAccChannelListMap + * Description: this function maps internal sub-module + * list IDs to TDM I/O Unit list IDs + */ +inline icp_status_t +HssAccChannelListMap (icp_hssacc_channel_list_t listId, + icp_hssacc_tdm_io_unit_channel_list_t *txList, + icp_hssacc_tdm_io_unit_channel_list_t *rxList) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + switch (listId) + { + case ICP_HSSACC_CHANNEL_LIST_PRIMARY: + *txList = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_PRIMARY; + *rxList = ICP_HSSACC_TDM_IO_UNIT_LIST_RX_PRIMARY; + break; + case ICP_HSSACC_CHANNEL_LIST_SECONDARY_0: + *txList = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_0; + *rxList = ICP_HSSACC_TDM_IO_UNIT_LIST_RX_SECONDARY_0; + break; + case ICP_HSSACC_CHANNEL_LIST_SECONDARY_1: + *txList = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_1; + *rxList = ICP_HSSACC_TDM_IO_UNIT_LIST_RX_SECONDARY_1; + break; + case ICP_HSSACC_CHANNEL_LIST_DELIMITER: + default: + ICP_HSSACC_REPORT_ERROR("HssAccChannelListMap - " + "Invalid List ID provided\n"); + status = ICP_STATUS_FAIL; + break; + } + return status; +} + +/* + * Function Prototype: HssAccChannelFirstChanAdd + * Description: this function will add a channel to an empty list of + * channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelFirstChanAdd (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData); + +/* + * Function Prototype: HssAccChannelLastChanAdd + * Description: this function will add a channel to the end of a list of + * channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelLastChanAdd (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData); + +/* + * Function Prototype: HssAccChannelFirstChanDel + * Description: this function will remove a channel that is at + * the start of a list of channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelFirstChanDel (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData); + +/* + * Function Prototype: HssAccChannelLastChanDel + * Description: this function will remove a channel that is at the + * end of a list of channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelLastChanDel (unsigned hssPortId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData); + +/* + * Function Prototype: HssAccChannelMiddleChanDel + * Description: this function will remove a channel that is in + * the middle of a list of channels processed on the port. + */ +TDM_PRIVATE icp_status_t +HssAccChannelMiddleChanDel (icp_hssacc_channel_list_data_t *pListData); + + +/* + * Function Prototype: HssAccChannelListsStatsReset + * Reset the Stats for this sub-module + */ +void +HssAccChannelListsStatsReset (void) +{ + memset (&hssAccChannelListStats,0,sizeof(icp_hssacc_channel_list_stats_t)); +} + + + +/* + * Function Definition: HssAccChannelListsReset + */ +void HssAccChannelListsReset (void) +{ + unsigned index = 0; + icp_hssacc_channel_list_t listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelListsReset\n"); + /* Initialise internal data, + set last channel IDs for each HSS Port to INVALID_CHAN */ + for (index = 0; index < ICP_HSSACC_MAX_NUM_PORTS; index ++) + { + for (listId = 0; listId < ICP_HSSACC_CHANNEL_LIST_DELIMITER; listId ++) + { + hssAccLastChannelOnList[index][listId] = ICP_HSSACC_INVALID_CHAN; + hssAccPortChannelListUsage[index][listId] = 0; + } + } + for (index = 0; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + hssAccChannelData[index].prevChannelId = ICP_HSSACC_INVALID_CHAN; + hssAccChannelData[index].nextChannelId = ICP_HSSACC_INVALID_CHAN; + hssAccChannelData[index].listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelListsReset\n"); +} + + + +/* Function definition: HssAccNextChannelListGet + Description: Figures out the next linked list to use when + commissioning a new channel + ASSUMPTION: The channel data for the specified channel must be valid */ +TDM_PRIVATE icp_hssacc_channel_list_t +HssAccNextChannelListGet (uint32_t hssPortId) +{ + /* Get the List Id (symmetrical for Tx and Rx) */ + + icp_hssacc_channel_list_t smallestList = ICP_HSSACC_CHANNEL_LIST_PRIMARY; + uint16_t smallestSize = + hssAccPortChannelListUsage[hssPortId][ICP_HSSACC_CHANNEL_LIST_PRIMARY]; + + if (smallestSize > + hssAccPortChannelListUsage[hssPortId] + [ICP_HSSACC_CHANNEL_LIST_SECONDARY_0]) + { + smallestList = ICP_HSSACC_CHANNEL_LIST_SECONDARY_0; + smallestSize = + hssAccPortChannelListUsage[hssPortId] + [ICP_HSSACC_CHANNEL_LIST_SECONDARY_0]; + } + +#if !defined(IXP23XX) || defined(UNIT_TEST) + if (smallestSize > + hssAccPortChannelListUsage[hssPortId] + [ICP_HSSACC_CHANNEL_LIST_SECONDARY_1]) + { + smallestList = ICP_HSSACC_CHANNEL_LIST_SECONDARY_1; + } +#endif + return smallestList; + +} + + +icp_status_t +HssAccChannelListAdd (unsigned hssPortId, + unsigned chanId, + unsigned chanSize) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_channel_list_t listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + icp_hssacc_channel_list_data_t *pListData = NULL; + unsigned channelUsageIO = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelListAdd\n"); + + /* check the channel isnt already in a list */ + pListData = &(hssAccChannelData[chanId]); + + if (pListData->listId != ICP_HSSACC_CHANNEL_LIST_DELIMITER) + { + ICP_HSSACC_REPORT_ERROR_2 ("HssAccChannelListAdd - " + "Channel %d already part of list %d\n", + chanId, + pListData->listId); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* find a list to add to */ + listId = HssAccNextChannelListGet(hssPortId); + + ICP_HSSACC_TRACE_4 (ICP_HSSACC_DEBUG, + "HssAccChannelListAdd - Adding Channel %d" + " to List %d on Port %d, current last chan is %d\n", + chanId, + listId, + hssPortId, + hssAccLastChannelOnList[hssPortId][listId]); + + if (hssAccLastChannelOnList[hssPortId][listId] == + ICP_HSSACC_INVALID_CHAN) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccChannelListAdd - List is empty\n"); + + status = HssAccChannelFirstChanAdd (hssPortId, + chanId, + listId, + pListData); + } + else + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccChannelListAdd - Add to end of list\n"); + + status = HssAccChannelLastChanAdd (hssPortId, + chanId, + listId, + pListData); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* list is selected depending on usage. usage is determined depending on + the amount estimated amount of IO transactions generated for that + list. for each channel, IO transactions is defined as + channelSizeInWords/transactionSize + 1 or 2 + (if modulus greater than 1). */ + channelUsageIO = HssAccChanIOUsageCalc(chanSize); + + hssAccPortChannelListUsage[hssPortId][listId] += channelUsageIO; + + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelListAdd\n"); + return status; +} + + + + +icp_status_t +HssAccChannelListRemove (unsigned hssPortId, + unsigned chanId, + unsigned chanSize) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_channel_list_t listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + icp_hssacc_channel_list_data_t *pListData = NULL; + unsigned channelUsageIO = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelListRemove\n"); + /* Get Channel Data and check that it is in a list */ + pListData = &(hssAccChannelData[chanId]); + + listId = pListData->listId; + if (listId == ICP_HSSACC_CHANNEL_LIST_DELIMITER) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccChannelListRemove - " + "Channel %d not part of any list\n", + chanId); + + status = ICP_STATUS_FAIL; + } + + + if (ICP_STATUS_SUCCESS == status) + { + + /* The channel to be deleted is the first channel on this list */ + if (pListData->prevChannelId == ICP_HSSACC_INVALID_CHAN) + { + status = HssAccChannelFirstChanDel (hssPortId, + chanId, + listId, + pListData); + } + /* The channel to be deleted is not the first channel on this list */ + else + { + if (hssAccLastChannelOnList[hssPortId][listId] == chanId) + { + /* we are deleting the last channel of the list */ + status = HssAccChannelLastChanDel (hssPortId, + listId, + pListData); + } + else + { + /* we are deleting a channel from the middle of the list */ + status = HssAccChannelMiddleChanDel (pListData); + } + } + } + + /* for the channel we are deleting, set its next pointer to point to NULL to + * avoid the possibility of an infinite loop when it is added later */ + if (ICP_STATUS_SUCCESS == status) + { + /* first set the tx 'next' pointer to NULL */ + status = + HssAccChannelNextChanWriteMsgSend ( + chanId, + 0, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* now set the rx 'next' pointer to NULL */ + status = + HssAccChannelNextChanWriteMsgSend ( + chanId, + 0, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* list is selected depending on usage. usage is determined depending on + the estimated amount of IO transactions generated for that + list. for each channel, IO transactions is defined as + channelSizeInWords/transactionSize+1 or 2 (if module greater + than 1).*/ + channelUsageIO = HssAccChanIOUsageCalc(chanSize); + + hssAccPortChannelListUsage[hssPortId][listId] -= channelUsageIO; + + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelListRemove\n"); + return status; +} + + + + + + + +/* + * Function definition: HssAccChannelNextChanWriteMsgSend + */ +TDM_PRIVATE icp_status_t +HssAccChannelNextChanWriteMsgSend (unsigned prevChannelId, + unsigned nextChannelId, + uint8_t txRxIndicator, + uint8_t nullFlag) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelNextChanWriteMsgSend\n"); + + /* Create the message for the TDM I/O Unit */ + HssAccComTdmIOUnitCmd8byteMsgCreate (ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE, + prevChannelId, + 0, 0, + nextChannelId, + nullFlag, + txRxIndicator, + 0, + &message); + + + /* Send the message to the TDM I/O Unit */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE_RESPONSE, + &(hssAccChannelListStats.nextChannelWrite), + NULL); + + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccChannelNextChanWriteMsgSend - " + "Messaging failure for channel %d\n", + prevChannelId); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelNextChanWriteMsgSend\n"); + return status; +} + + + + + +/* + * Function definition: HssAccChannelPortCfgMsgSend + */ +TDM_PRIVATE icp_status_t +HssAccChannelPortCfgMsgSend (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + uint8_t nullFlag) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelPortCfgMsgSend\n"); + + /* Create the message for the TDM I/O Unit*/ + HssAccComTdmIOUnitCmd8byteMsgCreate (ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG, + hssPortId, + 0, 0, + channelId, + nullFlag, + listId, + 0, + &message); + /* Send the message to the TDM I/O Unit */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG_RESPONSE, + &(hssAccChannelListStats.portCfgChannel), + NULL); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_2 ("HssAccChannelPortCfgMsgSend - Messaging " + "failure for port %d, channel %d\n", + hssPortId, + channelId); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelPortCfgMsgSend\n"); + return status; +} + + +/* + * Function definition: HssAccChannelFirstChanAdd + */ +TDM_PRIVATE icp_status_t +HssAccChannelFirstChanAdd (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_tdm_io_unit_channel_list_t rxList, txList = + ICP_HSSACC_TDM_IO_UNIT_LIST_DELIMITER; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelFirstChanAdd\n"); + + status = HssAccChannelListMap (listId, &txList, &rxList); + + if (ICP_STATUS_SUCCESS == status) + { + + status = + HssAccChannelPortCfgMsgSend (hssPortId, + channelId, + txList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelPortCfgMsgSend (hssPortId, + channelId, + rxList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + + if (ICP_STATUS_SUCCESS == status) + { + pListData->listId = listId; + pListData->prevChannelId = ICP_HSSACC_INVALID_CHAN; + pListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + + hssAccLastChannelOnList[hssPortId][listId] = channelId; + + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelFirstChanAdd\n"); + return status; +} + +/* + * Function definition: HssAccChannelLastChanAdd + */ +TDM_PRIVATE icp_status_t +HssAccChannelLastChanAdd (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned prevChannelId = 0; + icp_hssacc_channel_list_data_t *pPrevChanList = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelLastChanAdd\n"); + + prevChannelId = hssAccLastChannelOnList[hssPortId][listId]; + + status = + HssAccChannelNextChanWriteMsgSend (prevChannelId, + channelId, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + + if (ICP_STATUS_SUCCESS == status) + { + + status = + HssAccChannelNextChanWriteMsgSend( + prevChannelId, + channelId, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + + if (status == ICP_STATUS_SUCCESS) + { + pListData->listId = listId; + pListData->prevChannelId = prevChannelId; + pListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + pPrevChanList = &(hssAccChannelData[prevChannelId]); + pPrevChanList->nextChannelId = channelId; + + hssAccLastChannelOnList[hssPortId][listId] = channelId; + + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelLastChanAdd\n"); + return status; +} + + + +/* + * Function definition: HssAccChannelFirstChanDel + */ +TDM_PRIVATE icp_status_t +HssAccChannelFirstChanDel (unsigned hssPortId, + unsigned channelId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_tdm_io_unit_channel_list_t rxList, txList = + ICP_HSSACC_TDM_IO_UNIT_LIST_DELIMITER; + unsigned nextChannelId = 0; + icp_hssacc_channel_list_data_t *pNextChanListData = NULL; + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelFirstChanDel\n"); + + status = HssAccChannelListMap(listId, &txList, &rxList); + + if (ICP_STATUS_SUCCESS != status) + { + return status; + } + + /* Check if it is also the only channel processed on this list */ + if (hssAccLastChannelOnList[hssPortId][listId] == channelId) + { + /* ChannelId parameter will be ignored by the TDM I/O Unit in + this case */ + status = + HssAccChannelPortCfgMsgSend (hssPortId, + 0, + txList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelPortCfgMsgSend (hssPortId, + 0, + rxList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + + } + + if (ICP_STATUS_SUCCESS == status) + { + pListData->listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + hssAccLastChannelOnList[hssPortId][listId] = ICP_HSSACC_INVALID_CHAN; + + } + } + else + { + + /* Get information for the next channel on the list */ + nextChannelId = pListData->nextChannelId; + + status = + HssAccChannelPortCfgMsgSend (hssPortId, + nextChannelId, + txList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelPortCfgMsgSend (hssPortId, + nextChannelId, + rxList, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + + if (status == ICP_STATUS_SUCCESS) + { + /* current channel is decoupled from the list */ + pListData->listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + pListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + /* next channel now becomes the first channel on the list */ + pNextChanListData = &(hssAccChannelData[nextChannelId]); + pNextChanListData->prevChannelId = ICP_HSSACC_INVALID_CHAN; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelFirstChanDel\n"); + + return status; +} + +/* + * Function definition: HssAccChannelLastChanDel + */ +TDM_PRIVATE icp_status_t +HssAccChannelLastChanDel (unsigned hssPortId, + icp_hssacc_channel_list_t listId, + icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned prevChannelId = 0; + icp_hssacc_channel_list_data_t *pPrevChanListData = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelLastChanDel\n"); + + prevChannelId = pListData->prevChannelId; + pPrevChanListData = &(hssAccChannelData[prevChannelId]); + + + status = + HssAccChannelNextChanWriteMsgSend (prevChannelId, + 0, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelNextChanWriteMsgSend ( + prevChannelId, + 0, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG); + } + if (status == ICP_STATUS_SUCCESS) + { + pListData->listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + pListData->prevChannelId = ICP_HSSACC_INVALID_CHAN; + + /* The Previous channel in the list now becomes the last */ + pPrevChanListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + hssAccLastChannelOnList[hssPortId][listId] = prevChannelId; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelLastChanDel\n"); + return status; +} + +/* + * Function definition: HssAccChannelMiddleChanDel + */ +TDM_PRIVATE icp_status_t +HssAccChannelMiddleChanDel (icp_hssacc_channel_list_data_t *pListData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned prevChannelId, nextChannelId = ICP_HSSACC_INVALID_CHAN; + icp_hssacc_channel_list_data_t *pPrevChanListData, *pNextChanListData = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelMiddleChanDel\n"); + + prevChannelId = pListData->prevChannelId; + nextChannelId = pListData->nextChannelId; + pPrevChanListData = &(hssAccChannelData[prevChannelId]); + pNextChanListData = &(hssAccChannelData[nextChannelId]); + + + + status = + HssAccChannelNextChanWriteMsgSend (prevChannelId, + nextChannelId, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccChannelNextChanWriteMsgSend ( + prevChannelId, + nextChannelId, + IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX, + ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG); + } + + if (status == ICP_STATUS_SUCCESS) + { + pListData->listId = ICP_HSSACC_CHANNEL_LIST_DELIMITER; + pListData->nextChannelId = ICP_HSSACC_INVALID_CHAN; + pListData->prevChannelId = ICP_HSSACC_INVALID_CHAN; + + pPrevChanListData->nextChannelId = nextChannelId; + pNextChanListData->prevChannelId = prevChannelId; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelMiddleChanDel\n"); + + return status; +} + + +unsigned +HssAccChannelListLastPortChannelGet (uint32_t portId, + icp_hssacc_channel_list_t listId) +{ + return hssAccLastChannelOnList[portId][listId]; +} + + +unsigned +HssAccChannelListPrevChannelOnListGet(uint32_t channelId) +{ + return hssAccChannelData[channelId].prevChannelId; +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common.c new file mode 100644 index 0000000..25dc112 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common.c @@ -0,0 +1,464 @@ +/****************************************************************************** + * @file icp_hssacc_common.c + * + * @description Content of this file provides the implementation of + * common functionality used by all modules of the HSS Access component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" + +/* + * The command ID offset for TDM I/O Unit messages + */ +#define HSSACC_TDM_IO_UNIT_CMD_ID_OFFSET (ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET) + +/* + * The mask for the command ID in TDM I/O Unit messages + */ +#define HSSACC_TDM_IO_UNIT_CMD_ID_MASK \ + (0xFF << HSSACC_TDM_IO_UNIT_CMD_ID_OFFSET) + +/* + * The length of time to sleep while waiting for the TDM I/O Unit to + * respond (in milliseconds) + */ +#define HSSACC_TDM_IO_UNIT_WAIT_SLEEP_TIMEOUT (10) + +/* + * The number of times the HssAcc component will sleep while waiting for a + * response message from the TDM I/O Unit before triggering a time-out. + */ +#define HSSACC_TDM_IO_UNIT_MAX_NUM_SLEEPS (100) + + +/***************************************************************************** + * Abstract: + * This struct is used to notify a function that the TDM I/O unit has + * replied to the message previously submitted to it. + * Typically, the function that submitted the message will poll + * respReceived. When this flag is set (in the context of this callback), + * the polling client knows that a response has been generated for the + * message it submitted. + * + * Fields: + * respMsg - A 2 element array which is used to save the message response. + * respReceived - A boolean flag used to notify the polling client of the + * TDM I/O Unit's response. + * + *****************************************************************************/ +typedef struct icp_hss_acc_tdm_io_unit_resp_msg_s +{ + IxPiuMhMessage respMsg; + volatile icp_boolean_t respReceived; +} icp_hss_acc_tdm_io_unit_resp_msg_t; + + +/***************************************************************************** + * Abstract: + * Static variable used to store the most recent message response from the + * the TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_hss_acc_tdm_io_unit_resp_msg_t tdmIOUnitResponseMessage; + + +/* + * Function prototypes + */ +TDM_PRIVATE +void HssAccTdmIOUnitCmdRespCallback( + IxPiuMhPiuId piuId, + IxPiuMhMessage msg); + +TDM_PRIVATE +icp_status_t +HssAccComTdmIOUnitCmdMsgWait (volatile icp_boolean_t *const flagToWaitFor); + +TDM_PRIVATE +icp_status_t +HssAccComTdmIOUnitCmdMsgSend( + IxPiuMhMessage message, + icp_boolean_t reqResp, + volatile icp_boolean_t *const flagToWaitFor, + IxPiuMhCallback respCallback, + uint8_t solicitedPiuMsgId); + + +/***************************************************************************** + * Abstract: + * Constructs a 4-byte, 1-word TDM I/O Unit message. + * + * + *****************************************************************************/ +void +HssAccComTdmIOUnitCmd4byte1wordMsgCreate (uint32_t byte0, + uint32_t byte1, + uint32_t byte2, + uint32_t byte3, + uint32_t word, + IxPiuMhMessage *pMessage) +{ + /* create the message */ + pMessage->data[0] = + (byte3 << ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET) | + (byte2 << ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) | + (byte1 << ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) | + (byte0 << ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET); + pMessage->data[1] = word; + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmd4byte1wordMsgCreate " + "0x%08X 0x%08X\n", + pMessage->data[0], pMessage->data[1]); +} + + +/***************************************************************************** + * Abstract: + * Constructs an 8-byte TDM I/O Unit message. + * + * + *****************************************************************************/ +void +HssAccComTdmIOUnitCmd8byteMsgCreate (uint32_t byte0, + uint32_t byte1, + uint32_t byte2, + uint32_t byte3, + uint32_t byte4, + uint32_t byte5, + uint32_t byte6, + uint32_t byte7, + IxPiuMhMessage *pMessage) +{ + + + /* Create the TDM I/O Unit message format */ + pMessage->data[0] = + (byte3 << ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET) | + (byte2 << ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) | + (byte1 << ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) | + (byte0 << ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET); + + pMessage->data[1] = + (byte7 << ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET) | + (byte6 << ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) | + (byte5 << ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) | + (byte4 << ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET); + + ICP_HSSACC_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmd8byteMsgCreate 0x%08X 0x%08X\n", + pMessage->data[0], pMessage->data[1]); +} + + + + + +/***************************************************************************** + * Abstract: + * Submits a message to the TDM I/O Unit, waits for a response and verifies + * that the correct response was received, response word is + * passed back to client + * + * + *****************************************************************************/ +icp_status_t +HssAccComTdmIOUnitMsgSendAndRecv(IxPiuMhMessage message, + uint8_t response, + icp_hssacc_msg_with_resp_stats_t * stats, + uint32_t * responseWord) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint8_t cmdType = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitMsgSendAndRecv\n"); + status = + HssAccComTdmIOUnitCmdMsgSend (message, + TRUE, + &(tdmIOUnitResponseMessage.respReceived), + HssAccTdmIOUnitCmdRespCallback, + response); + if (ICP_STATUS_SUCCESS == status) + { + stats->numTdmIOUnitMessagesSent ++; + stats->numTdmIOUnitRespReceived ++; + /* Extract the command ID from the message */ + cmdType = ( (tdmIOUnitResponseMessage.respMsg.data[0] & + HSSACC_TDM_IO_UNIT_CMD_ID_MASK) >> + HSSACC_TDM_IO_UNIT_CMD_ID_OFFSET ); + + if (cmdType != response) + { + stats->numTdmIOUnitInvalidResp ++; + ICP_HSSACC_REPORT_ERROR_2("HssAccComTdmIOUnitmsgSendAndRecv - " + "TDM I/O Unit provided invalid response\n" + "Expected %u Cmd and got %u\n", + cmdType, response); + status = ICP_STATUS_FATAL; + } + } + else if (ICP_STATUS_FATAL == status) + { + stats->numTdmIOUnitMessagesSent ++; + stats->numTdmIOUnitTimeoutErrs ++; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (NULL != responseWord) + { + *responseWord = + tdmIOUnitResponseMessage.respMsg.data[1]; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitMsgSendAndRecv\n"); + return status; +} + + +/***************************************************************************** + * Abstract: + * This callback is triggered by the TDM I/O unit in response to a message. + * + * + *****************************************************************************/ +TDM_PRIVATE +void HssAccTdmIOUnitCmdRespCallback(IxPiuMhPiuId piuId, + IxPiuMhMessage msg) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitCmdRespCallback\n"); + + tdmIOUnitResponseMessage.respMsg = msg; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccTdmIOUnitCmdRespCallback 0x%08X 0x%08X " + "from TDM I/O Unit %u\n", + msg.data[0], msg.data[1], + piuId); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitCmdRespCallback\n"); + + /* This must be the last step in the callback */ + tdmIOUnitResponseMessage.respReceived = TRUE; +} + + +/***************************************************************************** + * Abstract: + * Sleeps until the specified flag is set (this occurs in + * HssAccTdmIOUnitCmdRespCallback), or times out and returns an error. + * + * + *****************************************************************************/ +TDM_PRIVATE +icp_status_t +HssAccComTdmIOUnitCmdMsgWait (volatile icp_boolean_t *const flagToWaitFor) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numSleepsWithNoResp = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccComTdmIOUnitCmdMsgWait\n"); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgWait - " + "Waiting on the TDM I/O Unit to respond...\n"); + + /* wait until a response is received */ + while (numSleepsWithNoResp < HSSACC_TDM_IO_UNIT_MAX_NUM_SLEEPS) + { + if (TRUE == *flagToWaitFor) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgWait - " + "TDM I/O Unit responded\n"); + break; + } + numSleepsWithNoResp ++; + ixOsalSleep (HSSACC_TDM_IO_UNIT_WAIT_SLEEP_TIMEOUT); + } + + /* check for timeout */ + if (HSSACC_TDM_IO_UNIT_MAX_NUM_SLEEPS == numSleepsWithNoResp) + { + ICP_HSSACC_REPORT_ERROR("HssAccComTdmIOUnitCmdMsgWait - " + "TDM I/O Unit failed to respond in time\n"); + status = ICP_STATUS_FATAL; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccComTdmIOUnitCmdMsgWait\n"); + + return status; +} + + +/***************************************************************************** + * Abstract: + * Submits a message to the TDM I/O Unit and waits for the specified + * response from the TDM I/O Unit (if specified). + * + * + *****************************************************************************/ +TDM_PRIVATE +icp_status_t +HssAccComTdmIOUnitCmdMsgSend( + IxPiuMhMessage message, + icp_boolean_t reqResp, + volatile icp_boolean_t *const flagToWaitFor, + IxPiuMhCallback respCallback, + uint8_t solicitedPiuMsgId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_STATUS mhStatus = IX_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccComTdmIOUnitCmdMsgSend\n"); + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgSend\n", + message.data[0], message.data[1]); + + /* check if a response is required */ + if (TRUE == reqResp) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgSend - " + "Calling ixPiuMhMessageWithResponseSend\n"); + + /* Send the message to the Programmable I/O Unit + (TDM I/O Unit in this case) */ + *flagToWaitFor = FALSE; + mhStatus = ixPiuMhMessageWithResponseSend(IX_PIUMH_PIUID_PIU0, + message, + solicitedPiuMsgId, + respCallback, + IX_PIUMH_SEND_RETRIES_DEFAULT); + } + else + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccComTdmIOUnitCmdMsgSend - " + "Calling ixPiuMhMessageSend\n"); + + /* Send the message to the PiuMh */ + mhStatus = ixPiuMhMessageSend (IX_PIUMH_PIUID_PIU0, + message, + IX_PIUMH_SEND_RETRIES_DEFAULT); + } + + /* check the return from the Message Handler and block for response if + requested */ + if (IX_SUCCESS != mhStatus) + { + /* report the error */ + ICP_HSSACC_REPORT_ERROR ("HssAccComTdmIOUnitCmdMsgSend - " + "Message Handler failed to send\n"); + /* set return status */ + status = ICP_STATUS_FAIL; + } + else + { + /* wait for a response from the TDM I/O Unit if one is expected */ + if (TRUE == reqResp) + { + status = HssAccComTdmIOUnitCmdMsgWait (flagToWaitFor); + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccComTdmIOUnitCmdMsgSend\n"); + + return status; +} + + + + +/***************************************************************************** + * Abstract: + * Single message stat struct show + * + * + *****************************************************************************/ +void HssAccSingleMessageStatsShow (icp_hssacc_msg_with_resp_stats_t stat) +{ + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, + IX_OSAL_LOG_DEV_STDOUT, + "\n\t%u messages Sent\n\t%u messages received\n\t" + "%u invalid responses\t\n%u timeouts\n", + stat.numTdmIOUnitMessagesSent, stat.numTdmIOUnitRespReceived, + stat.numTdmIOUnitInvalidResp, stat.numTdmIOUnitTimeoutErrs, 0, 0); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common_timeslot_allocation.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common_timeslot_allocation.c new file mode 100644 index 0000000..074d372 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_common_timeslot_allocation.c @@ -0,0 +1,441 @@ +/****************************************************************************** + * + * @file icp_hssacc_common_timeslot_allocation.c + * + * @description Content of this file is the implementation of the Timeslot + * allocation and de-allocation functionality used for channel Allocation + * and deletion common accross all platforms. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#include "IxOsal.h" + +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_channel_config.h" + + + + +/* Base address of the TDM I/O Unit channel offset table */ +TDM_PRIVATE void * hssAccHdmaProvTableVirtAddr = NULL; + +TDM_PRIVATE void * hssAccTdmIoUnitOffsetTableVirtAddr = NULL; + +/* Tracks which channel is using which timeslot(s). */ +TDM_PRIVATE unsigned +hssAccChanTimeslotUsage[ICP_HSSACC_MAX_NUM_PORTS] +[ICP_HSSACC_MAX_TIMESLOTS_PER_PORT]; + + +void * HssAccTsAllocHdmaProvTableVirtAddrGet (void) +{ + return hssAccHdmaProvTableVirtAddr; +} + + + +void * HssAccTsAllocTdmIoUnitOffsetTableVirtAddrGet (void) +{ + return hssAccTdmIoUnitOffsetTableVirtAddr; +} + + + +/** + * Function Definition + */ +icp_status_t HssAccTsAllocInit (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned portId = ICP_HSSACC_MAX_NUM_PORTS; + unsigned tsIndex = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocInit\n"); + + /* Mark all timeslots as unreserved */ + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + for (tsIndex = 0; + tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_PORT; + tsIndex ++) + { + hssAccChanTimeslotUsage[portId][tsIndex] = + ICP_HSSACC_INVALID_CHAN; + } + } + + hssAccHdmaProvTableVirtAddr = + (void*)IX_OSAL_CACHE_DMA_MALLOC (ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + if (NULL == hssAccHdmaProvTableVirtAddr) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTsAllocInit - TDM I/O Unit Timeslot " + "Provision table allocation failed\n"); + status = ICP_STATUS_FAIL; + } + + + + hssAccTdmIoUnitOffsetTableVirtAddr = + (void*)IX_OSAL_CACHE_DMA_MALLOC (ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ); + + if (NULL == hssAccTdmIoUnitOffsetTableVirtAddr) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTsAllocInit - TDM I/O Unit Channel " + "Offset table allocation failed\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTsAllocPlatformInit (); + } + else + { + /* Best Effort shutdown */ + HssAccTsAllocShutdown(); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocInit\n"); + return status; +} + + +/** + * Function Definition + */ +void HssAccTsAllocShutdown (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocShutdown\n"); + + if (NULL != hssAccHdmaProvTableVirtAddr) + { + IX_OSAL_CACHE_DMA_FREE(hssAccHdmaProvTableVirtAddr); + hssAccHdmaProvTableVirtAddr = NULL; + } + if (NULL != hssAccTdmIoUnitOffsetTableVirtAddr) + { + IX_OSAL_CACHE_DMA_FREE(hssAccTdmIoUnitOffsetTableVirtAddr); + hssAccTdmIoUnitOffsetTableVirtAddr = NULL; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocShutdown\n"); +} + + + + + +/** + * Function definition: HssAccTsAllocTableSwap + */ +icp_status_t HssAccTsAllocTableSwap (unsigned hssPortId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocTableSwap\n"); + + /* Create Message for TDM I/O Unit */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP, + 0, + hssPortId, + 0, + 0, + &message); + /* Send the message */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP_DONE, + HssAccTsAllocSwapStatsGet(), + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocTableSwap\n"); + + return status; +} + + + + + +/** + * Function definition: HssAccTsAllocDelete + */ +icp_status_t +HssAccTsAllocDelete (unsigned channelId, + icp_hssacc_channel_config_t * hssChannelData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocDelete\n"); + + + /* Update the timeslot Allocation tables */ + status = HssAccTsAllocUpdate(hssChannelData[channelId].portId, + hssChannelData); + if (status != ICP_STATUS_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTsAllocDelete -" + " Error updating HDMA Timeslot Tables\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocDelete\n"); + return status; +} + + +/** + * Function definition: HssAccOffsetTableWordRead + */ +icp_status_t +HssAccTsAllocOffsetTableWordRead (icp_boolean_t readShadowTable, + uint16_t tableOffset, + uint32_t *tableWord) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t tableSwitch = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocOffsetTableWordRead\n"); + + if (ICP_TRUE == readShadowTable) + { + tableSwitch = 1; + } + + /* Create Message for TDM I/O Unit */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ, + tableSwitch, + 0, + 0, + tableOffset, + &message); + /* Send the message */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ_RESPONSE, + HssAccTsAllocOffsetTableReadStatsGet(), + tableWord); + + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccTsAllocOffsetTableWordRead - " + "Failed to retrieve Table data from " + "TDM I/O Unit\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocOffsetTableWordRead\n"); + + return status; +} + + + + +/***************************************************************************** + * Abstract: + * Marks the specified timeslots as registered by the specified channel. + * + *****************************************************************************/ +void +HssAccTsRegister(unsigned channelId, + unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap) +{ + unsigned tsIndex = 0; + unsigned offset = 0; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsRegister " + "on port %u line %u tsMap 0x%08X\n", + portId, lineId, tsMap); + + offset = lineId * ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + /* Reserve the timeslot(s) */ + for (tsIndex = 0; + tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + tsIndex ++) + { + if (tsMap & BIT_SET(tsIndex)) + { + ICP_HSSACC_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccTsRegister - " + "Registering timeslot %u on port %u\n", + offset + tsIndex, portId); + hssAccChanTimeslotUsage[portId][offset + tsIndex] = channelId; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsRegister\n"); +} + +/***************************************************************************** + * Abstract: + * Frees the specified timeslots. + * + *****************************************************************************/ +void +HssAccTsUnregister(unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap) +{ + unsigned tsIndex = 0; + unsigned offset = lineId * + ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsUnregister " + "on port %u line %u timeslots 0x%08X\n", + portId, + lineId, + tsMap); + + for (tsIndex = 0; + tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + tsIndex ++) + { + if (tsMap & BIT_SET(tsIndex)) + { + hssAccChanTimeslotUsage[portId] + [offset + tsIndex] = ICP_HSSACC_INVALID_CHAN; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsUnregister\n"); +} + +/***************************************************************************** + * Abstract: + * Checks if the requested timeslots are available for use by a channel. + * + *****************************************************************************/ +icp_boolean_t +HssAccTsAvailableVerify(unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap) +{ + unsigned tsIndex = 0; + unsigned offset = 0; + icp_boolean_t timeslotsAvailable = ICP_TRUE; + + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAvailableVerify" + " on port %u line %u and tsMap 0x%08X\n", + portId, + lineId, + tsMap); + + /* + * There are 4 lines per HSS port and each line has 32 timeslots. Since + * timeslot usage is recorded per port, need to offset by N*32, where + * N is the HSS line number. + */ + offset = lineId * ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + while ((ICP_TRUE == timeslotsAvailable) && + (tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE)) + { + if ( (tsMap & BIT_SET(tsIndex)) && + (ICP_HSSACC_INVALID_CHAN != + hssAccChanTimeslotUsage[portId][offset + tsIndex]) + ) + { + ICP_HSSACC_TRACE_2(ICP_HSSACC_DEBUG, + "Found a Timeslot already used on port %u, " + "TS %u\n", + portId, + offset + tsIndex); + timeslotsAvailable = ICP_FALSE; + } + tsIndex ++; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAvailableVerify\n"); + + return timeslotsAvailable; +} + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_param_check.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_param_check.c new file mode 100644 index 0000000..d8cba6d --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_param_check.c @@ -0,0 +1,95 @@ +/****************************************************************************** + * + * @file icp_hssacc_param_check.c + * + * @description Content of this file is the implementation of parameter checking + * as valid for this specific platform. Other platforms may not support the same + * set of clock modes. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_common.h" + + +icp_boolean_t +HssAccPortConfigTxClkModeInvalid(icp_hssacc_clk_mode_t clkMode) +{ + return ICP_HSSACC_ENUM_INVALID(clkMode,ICP_HSSACC_CLK_MODE_DELIMITER); +} + +icp_boolean_t +HssAccPortConfigRxClkModeInvalid(icp_hssacc_clk_mode_t clkMode) +{ + /* For Tolapai Rx, all listed modes are supported */ + return ICP_HSSACC_ENUM_INVALID(clkMode,ICP_HSSACC_CLK_MODE_DELIMITER); +} + + + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_config.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_config.c new file mode 100644 index 0000000..652c9b1 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_config.c @@ -0,0 +1,1175 @@ +/****************************************************************************** + * @file icp_hssacc_port_config.c + * + * @description Contents of this file provide the implementation of the + * Port Configuration functionality for the HSS Access component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +/* ---------------------------------------------------------------------------- + * Includes + * ---------------------------------------------------------------------------- + */ +#include "IxOsal.h" + +#include "icp_hssacc.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_port_hdma_reg_mgr.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_address_translate.h" + +/* + * ---------------------------------------------------------------------------- + * Macros + * ---------------------------------------------------------------------------- + */ +#define ICP_HSSACC_PORT_API_CONFIG_RESET(cfg) do { \ + cfg.frmSyncType = ICP_HSSACC_FRM_PULSE_SYNC_TYPE_DELIMITER; \ + cfg.frmSyncIO = ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_DELIMITER;\ + cfg.frmSyncClkEdge = ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER;\ + cfg.dataClkEdge = ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER;\ + cfg.clkMode = ICP_HSSACC_CLK_MODE_DELIMITER;\ + cfg.frmPulseUsage = ICP_HSSACC_FRM_PULSE_USAGE_TYPE_DELIMITER;\ + cfg.dataPolarity = ICP_HSSACC_DATA_POLARITY_DELIMITER;\ + cfg.drainMode = ICP_HSSACC_TX_PINS_DRAIN_MODE_TYPE_DELIMITER;\ + cfg.refFrame = ICP_HSSACC_REF_FRAME_DELIMITER;\ + cfg.dataPinsEnable = ICP_HSSACC_DATA_PINS_TYPE_DELIMITER;\ + cfg.loopback = ICP_FALSE;\ + cfg.frm_offset = 0;\ + cfg.fBitType = ICP_HSSACC_TX_FBIT_TYPE_DELIMITER; \ + cfg.fBitEnable = ICP_FALSE;\ + cfg.unassignedType = ICP_HSSACC_UNASSIGNED_DATA_DRIVE_DELIMITER; \ + cfg.interleaving = ICP_HSSACC_INTERLEAVING_TYPE_DELIMITER; \ +} while (0); + +#define ICP_HSSACC_PORT_ADD_CONFIG_RESET(addCfg) do { \ + addCfg.dataRate = ICP_HSSACC_DATA_RATE_EQUALS_CLK_RATE; \ + addCfg.frmPulseWidth = ICP_HSSACC_RX_DFLT_FRM_PULSE_WIDTH; \ +} while (0); + + + +/* + * ---------------------------------------------------------------------------- + * Struct types + * ---------------------------------------------------------------------------- + */ + + +/* Stats */ +typedef struct icp_hssacc_port_config_stats_s +{ + icp_hssacc_msg_with_resp_stats_t configTableLoad; + icp_hssacc_msg_with_resp_stats_t portEnable; + icp_hssacc_msg_with_resp_stats_t portDisable; +} icp_hssacc_port_config_stats_t; + +/* + * ---------------------------------------------------------------------------- + * Global variables + * ---------------------------------------------------------------------------- + */ + +/* Flag used to test whether the Port Config sub-component is initialised */ +TDM_PRIVATE icp_boolean_t portConfigInitialised = ICP_FALSE; + +/* Tracks the current port state and configuration */ +TDM_PRIVATE icp_hssacc_port_internal_config_t +hssAccPortConfig[ICP_HSSACC_MAX_NUM_PORTS]; + +/* Base address of the Port Config tables */ +TDM_PRIVATE void * hssAccPortConfigTablesBaseVirtAddr = NULL; + +TDM_PRIVATE icp_hssacc_port_config_stats_t hssAccPortConfigStats; + + + +/* + * ---------------------------------------------------------------------------- + * Static function declarations + * ---------------------------------------------------------------------------- + */ +TDM_PRIVATE icp_status_t +HssAccPortConfigTableUpdate(unsigned portId); + + +TDM_PRIVATE icp_status_t +HssAccPortConfigTableLoad(unsigned portId, + void * tableVirtAddr, + uint8_t msgId, + uint8_t msgRespId); + + +TDM_PRIVATE icp_status_t +HssAccPortStateSet(unsigned portId, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stats); + + +/* + * ---------------------------------------------------------------------------- + * Function definitions + * ---------------------------------------------------------------------------- + */ +/****************************************************************************** + * Abstract: + * Initialises all global variables used for port configuration. + * Allocates memory for the HDMA port configuration tables. + * Initialises the port configuration mutex. + *****************************************************************************/ +icp_status_t +HssAccPortConfigInit(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned portId = 0; + icp_hssacc_hdma_port_config_t * pHdmaConfigTables = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigInit\n"); + + if (ICP_TRUE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortConfigInit - " + "component has already been initialised\n"); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigInit\n"); + return ICP_STATUS_FAIL; + } + + /* Allocate memory for the port config tables */ + hssAccPortConfigTablesBaseVirtAddr = + (void*)IX_OSAL_CACHE_DMA_MALLOC (ICP_HSSACC_MAX_NUM_PORTS* + sizeof(icp_hssacc_hdma_port_config_t)); + + if (NULL == hssAccPortConfigTablesBaseVirtAddr) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortConfigInit - " + "malloc for port config tables failed\n"); + status = ICP_STATUS_FAIL; + } + else + { + pHdmaConfigTables = + (icp_hssacc_hdma_port_config_t *)hssAccPortConfigTablesBaseVirtAddr; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Initialise the port configuration struct */ + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_UNCONFIGURED; + hssAccPortConfig[portId].hdmaPortCfgTableVirtAddr = + &pHdmaConfigTables[portId]; + hssAccPortConfig[portId].clkSpeed = ICP_HSSACC_CLK_SPEED_DELIMITER; + + /* Rx dir config */ + ICP_HSSACC_PORT_API_CONFIG_RESET(hssAccPortConfig[portId].rx.cfg); + ICP_HSSACC_PORT_ADD_CONFIG_RESET(hssAccPortConfig[portId].rx.addCfg); + + + /* Tx dir config */ + ICP_HSSACC_PORT_API_CONFIG_RESET(hssAccPortConfig[portId].tx.cfg); + ICP_HSSACC_PORT_ADD_CONFIG_RESET(hssAccPortConfig[portId].tx.addCfg); + + } + /* Initialise the internal Stats */ + HssAccPortConfigStatsReset(); + portConfigInitialised = ICP_TRUE; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigInit\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * Shutdown this sub-module: free any memory ... + * + *****************************************************************************/ +icp_status_t +HssAccPortConfigShutdown(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned portId = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigShutdown\n"); + + if (ICP_FALSE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortConfigShutdown - " + "component has not been initialised\n"); + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigShutdown\n"); + return ICP_STATUS_FAIL; + } + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + if (hssAccPortConfig[portId].state == ICP_HSSACC_PORT_ENABLED) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccPortConfigShutdown - " + "port %d is still enabled, " + "shut it down first\n", + portId); + status = ICP_STATUS_FAIL; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Free memory allocated for the port config tables */ + IX_OSAL_CACHE_DMA_FREE(hssAccPortConfigTablesBaseVirtAddr); + hssAccPortConfigTablesBaseVirtAddr = NULL; + + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_UNCONFIGURED; + hssAccPortConfig[portId].hdmaPortCfgTableVirtAddr = NULL; + } + + portConfigInitialised = ICP_FALSE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigShutdown\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * returns the number of supported HSS ports + * + *****************************************************************************/ +unsigned +icp_HssAccNumSupportedPortsGet ( void ) +{ + return ICP_HSSACC_MAX_NUM_PORTS; +} + + + +/****************************************************************************** + * Abstract: + * saves the specified configuration for the specified port + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortConfig (unsigned portId, + icp_hssacc_port_config_params_t *configParams) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + icp_hssacc_port_config_t * pTxPortConfig = &(configParams->txPortConfig); + icp_hssacc_port_config_t * pRxPortConfig = &(configParams->rxPortConfig); + + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortConfig - port %d\n", + portId); + + /* Check if port config component has been initialised */ + if (ICP_FALSE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - port config component " + "has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - " + "port number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + if (NULL == configParams) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - invalid " + "port settings pointer\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + + if (ICP_HSSACC_ENUM_INVALID(configParams->clkSpeed, + ICP_HSSACC_CLK_SPEED_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - " + "port clock speed is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + /* TX Check */ + if (ICP_HSSACC_ENUM_INVALID(pTxPortConfig->frmSyncType, + ICP_HSSACC_FRM_PULSE_SYNC_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->frmSyncIO, + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_DELIMITER)|| + (pTxPortConfig->frmSyncIO == + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INVALID_VALUE) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->frmSyncClkEdge, + ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->dataClkEdge, + ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->frmPulseUsage, + ICP_HSSACC_FRM_PULSE_USAGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->dataPolarity, + ICP_HSSACC_DATA_POLARITY_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->drainMode, + ICP_HSSACC_TX_PINS_DRAIN_MODE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->refFrame, + ICP_HSSACC_REF_FRAME_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->dataPinsEnable, + ICP_HSSACC_DATA_PINS_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->fBitType, + ICP_HSSACC_TX_FBIT_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->unassignedType, + ICP_HSSACC_UNASSIGNED_DATA_DRIVE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pTxPortConfig->interleaving, + ICP_HSSACC_INTERLEAVING_TYPE_DELIMITER) || +#ifdef IXP23xx + (ICP_TRUE == pTxPortConfig->loopback) || +#endif + HssAccPortConfigTxClkModeInvalid(pTxPortConfig->clkMode) ) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - one or more Tx port " + "config parameters is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + + /* RX Check */ + if (ICP_HSSACC_ENUM_INVALID(pRxPortConfig->frmSyncType, + ICP_HSSACC_FRM_PULSE_SYNC_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->frmSyncIO, + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_DELIMITER)|| + (pRxPortConfig->frmSyncIO == + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INVALID_VALUE) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->frmSyncClkEdge, + ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->dataClkEdge, + ICP_HSSACC_CLK_EDGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->frmPulseUsage, + ICP_HSSACC_FRM_PULSE_USAGE_TYPE_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->dataPolarity, + ICP_HSSACC_DATA_POLARITY_DELIMITER) || + ICP_HSSACC_ENUM_INVALID(pRxPortConfig->interleaving, + ICP_HSSACC_INTERLEAVING_TYPE_DELIMITER) || + HssAccPortConfigRxClkModeInvalid(pRxPortConfig->clkMode) ) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - one or more Rx port " + "config parameters is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if ((pRxPortConfig->refFrame != + ICP_HSSACC_REF_FRAME_NOT_SELECTED) && + (pRxPortConfig->frmSyncIO == + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - Rx Reference Frame " + "selection is invalid for the Frame " + "pulse source setting\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if ((pTxPortConfig->refFrame != + ICP_HSSACC_REF_FRAME_NOT_SELECTED) && + (pTxPortConfig->frmSyncIO == + ICP_HSSACC_FRM_PULSE_SYNC_IO_TYPE_INPUT)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - Tx Reference Frame " + "selection is invalid for the Frame " + "pulse source setting\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + if ((ICP_HSSACC_CLK_SPEED_1544KHZ != configParams->clkSpeed) && + (pRxPortConfig->fBitEnable || + pTxPortConfig->fBitEnable)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - " + "FBit is only supported for T1 speed\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if ((pRxPortConfig->fBitEnable && + (ICP_HSSACC_FRM_PULSE_USAGE_DISABLED == + pRxPortConfig->frmPulseUsage)) || + (pTxPortConfig->fBitEnable && + (ICP_HSSACC_FRM_PULSE_USAGE_DISABLED == + pTxPortConfig->frmPulseUsage))) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccPortConfig - " + "fBit and Frameless operation " + "not permitted\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + if ((ICP_TRUE == pRxPortConfig->loopback) && + (ICP_TRUE == pTxPortConfig->loopback)) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccPortConfig -" + " The port cannot be configured for " + "both Remote and Internal loopback\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Lock the HssAcc mutex and update port configuration */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccPortConfig - " + "Mutex Lock Error\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((0 == memcmp(&(hssAccPortConfig[portId].rx.cfg), + pRxPortConfig, + sizeof(icp_hssacc_port_config_t))) && + (0 == memcmp (&(hssAccPortConfig[portId].tx.cfg), + pTxPortConfig, + sizeof(icp_hssacc_port_config_t)))) + { + /* Supplied config is identical to what is already configured */ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "icp_HssAccPortConfig - port already " + "configured with identical settings\n"); + } + else + { + + /* Check if port is in a valid state for configuration */ + if (ICP_HSSACC_PORT_UNCONFIGURED != hssAccPortConfig[portId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortConfig - " + "port has already been " + "configured at some stage\n"); + status = ICP_STATUS_FAIL; + } + else + { + /* Store Port Config Parameters in static memory */ + hssAccPortConfig[portId].clkSpeed = configParams->clkSpeed; + /* Rx dir config */ + memcpy (&(hssAccPortConfig[portId].rx.cfg), + pRxPortConfig, + sizeof(icp_hssacc_port_config_t)); + + /* Tx dir config */ + memcpy (&(hssAccPortConfig[portId].tx.cfg), + pTxPortConfig, + sizeof(icp_hssacc_port_config_t)); + + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_CONFIGURED; + + } + } + } + + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccPortConfig - " + "Mutex Unlock Error\n"); + status = ICP_STATUS_MUTEX; + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortConfig\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Enable traffic on the specified TDM port + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortUp (unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortUp - port %d\n", + portId); + + /* Check if port config component has been initialised */ + if (ICP_FALSE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - port config component " + "has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - " + "port number is invalid\n"); + + status = ICP_STATUS_INVALID_PARAM; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Lock the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Check if port is already enabled */ + if (ICP_HSSACC_PORT_ENABLED == hssAccPortConfig[portId].state) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - " + "failed to unlock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + + /* this port is already enabled so we dont need to do anything */ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortUp\n"); + return status; + } + + if (ICP_HSSACC_PORT_UNCONFIGURED == hssAccPortConfig[portId].state) + { + ICP_HSSACC_REPORT_ERROR_2 ("icp_HssAccPortUp - " + "port is not in an appropriate State - " + "port %d, state %d\n", + portId, + hssAccPortConfig[portId].state); + status = ICP_STATUS_FAIL; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccPortConfigTableUpdate(portId); + + } + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTsAllocInitialAllocationUpdate(portId); + } + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccPortStateSet(portId, + ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE, + ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE_RESPONSE, + &(hssAccPortConfigStats.portEnable)); + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_ENABLED; + } + + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortUp - " + "failed to unlock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortUp\n"); + return status; + +} + + +/****************************************************************************** + * Abstract: + * Disables traffic on the specified TDM port. + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortDown (unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortDown - port %d\n", + portId); + + /* Check if port config component has been initialised */ + if (ICP_FALSE == portConfigInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - port config component " + "has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - " + "port number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + /* Check if port is enabled */ + if (ICP_STATUS_SUCCESS == status) + { + + /* Lock the HssAcc mutex and update port loopback configuration */ + if (ICP_STATUS_SUCCESS == ICP_HSSACC_MUTEX_LOCK()) + { + if ((ICP_HSSACC_PORT_ENABLED == hssAccPortConfig[portId].state) && + (!HssAccChannelConfigUsedChansOnPortFind(portId))) + { + status = + HssAccPortStateSet(portId, + ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE, + ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE_RESPONSE, + &(hssAccPortConfigStats.portDisable)); + + if (ICP_STATUS_SUCCESS == status) + { + + hssAccPortConfig[portId].state = ICP_HSSACC_PORT_CONFIGURED; + } + else + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccPortDown - " + "unable to bring down port %d\n", + portId); + } + } + else if (ICP_HSSACC_PORT_CONFIGURED != + hssAccPortConfig[portId].state) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - " + "there are still allocated channels on" + " this port\n"); + status = ICP_STATUS_RESOURCE; + } + + /* Unlock the HssAcc configuration mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - " + "failed to unlock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + + } + else + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortDown - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortDown\n"); + return status; + +} + + +/****************************************************************************** + * Abstract: + * Update the port configuration table in the TDM I/O Unit for this port. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccPortConfigTableUpdate(unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_hdma_port_config_t * pPortCfgTable = NULL; + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigTableUpdate for " + "port %d at speed %d\n", + portId, + hssAccPortConfig[portId].clkSpeed); + /* Get the base address of the port config tables */ + pPortCfgTable = hssAccPortConfig[portId].hdmaPortCfgTableVirtAddr; + + /* Clear the contents of the HDMA port config table */ + memset (pPortCfgTable, 0, + sizeof(icp_hssacc_hdma_port_config_t)); + +#ifdef IXP23XX + /* Need to Create the LUT for IXP23XX as it is part of the + Port Config Table,creating tables with all TimeSlots assigned */ + status = HssAccHdmaMgrLUTCreate(hssAccPortConfig[portId].clkSpeed, + pPortCfgTable->tx_LUT); + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccHdmaMgrLUTCreate(hssAccPortConfig[portId].clkSpeed, + pPortCfgTable->rx_LUT); + } + HssAccHdmaMgrVCRCreate(&(pPortCfgTable->tx_vcr)); + HssAccHdmaMgrVCRCreate(&(pPortCfgTable->rx_vcr)); +#endif + + if (ICP_STATUS_SUCCESS == status) + { + HssAccHdmaMgrPCRCreate (ICP_HSSACC_HDMA_TX_REG_TYPE, + &(hssAccPortConfig[portId].tx), + &(pPortCfgTable->tx_pcr)); + HssAccHdmaMgrICRCreate (ICP_HSSACC_HDMA_TX_REG_TYPE, + portId, + &(pPortCfgTable->tx_icr)); + HssAccHdmaMgrClkCRCreate (hssAccPortConfig[portId].clkSpeed, + &(pPortCfgTable->clkcr)); + + status = HssAccHdmaMgrFCRCreate (ICP_HSSACC_HDMA_TX_REG_TYPE, + hssAccPortConfig[portId].clkSpeed, + &(hssAccPortConfig[portId].tx), + &(pPortCfgTable->tx_fcr)); + } + if (ICP_STATUS_SUCCESS == status) + { + HssAccHdmaMgrPCRCreate (ICP_HSSACC_HDMA_RX_REG_TYPE, + &(hssAccPortConfig[portId].rx), + &(pPortCfgTable->rx_pcr)); + + HssAccHdmaMgrICRCreate (ICP_HSSACC_HDMA_RX_REG_TYPE, + portId, + &(pPortCfgTable->rx_icr)); + + if ((hssAccPortConfig[portId].tx.cfg.frmPulseUsage != + ICP_HSSACC_FRM_PULSE_USAGE_ENABLED) || + (hssAccPortConfig[portId].rx.cfg.frmPulseUsage != + ICP_HSSACC_FRM_PULSE_USAGE_ENABLED)) + { + HssAccHdmaMgrCWRCreate (hssAccPortConfig[portId].clkSpeed, + &(pPortCfgTable->cwr)); + } + + status = HssAccHdmaMgrFCRCreate (ICP_HSSACC_HDMA_RX_REG_TYPE, + hssAccPortConfig[portId].clkSpeed, + &(hssAccPortConfig[portId].rx), + &(pPortCfgTable->rx_fcr)); + + } + + if (ICP_STATUS_SUCCESS == status) + { + + /* Flush the new table to memory */ + IX_OSAL_CACHE_FLUSH (pPortCfgTable, + sizeof(icp_hssacc_hdma_port_config_t)); + + /* Load the new HDMA port config table for this port */ + status = + HssAccPortConfigTableLoad ( + portId, + pPortCfgTable, + ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD, + ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD_RESPONSE); + } + + if (ICP_STATUS_FATAL == status) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortConfigTableUpdate - HDMA port " + "config table update - Fatal Error " + "communicating with the TDM I/O unit\n"); + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigTableUpdate\n"); + return status; +} + +/****************************************************************************** + * Abstract: + * Send Port Configuration message to the TDM I/O Unit + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccPortConfigTableLoad(unsigned portId, + void * tableVirtAddr, + uint8_t msgId, + uint8_t msgRespId) +{ + uint32_t physAddr = 0; + IxPiuMhMessage message; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigTableLoad\n"); + + + + /* Convert the table base address to a physical address */ + physAddr = + HssAccVirtToPhysAddressTranslate(tableVirtAddr); + + if (0 == physAddr) + { + ICP_HSSACC_REPORT_ERROR("HssAccPortConfigTableLoad - Translation of " + "Virtual Address resulted in NULL value\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + msgId, + 0, + portId, + (sizeof(icp_hssacc_hdma_port_config_t) / ICP_HSSACC_WORD_SIZE), + physAddr, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + msgRespId, + &(hssAccPortConfigStats.configTableLoad), + NULL); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigTableLoad\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * Set the state of the TDM port within the TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccPortStateSet(unsigned portId, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stats) +{ + IxPiuMhMessage message; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortStateSet\n"); + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate (msgId, + 0, + portId, + 0, + 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv(message, + msgRespId, + stats, + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortStateSet\n"); + + return status; +} + + + +/****************************************************************************** + * Abstract: + * check the validity of the line and last timeslot to be used using + * the known internal port configuration. + * + *****************************************************************************/ +icp_status_t +HssAccPortLineValidCheck (unsigned portId, + icp_hssacc_line_t lineId, + unsigned firstTsPos, + unsigned lastTsPos) +{ + icp_status_t status = ICP_STATUS_RESOURCE; + ICP_HSSACC_TRACE_3 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortLineValidCheck for " + "Port %d, line %d and TS %d\n", + portId, + lineId, + lastTsPos); + + if (ICP_HSSACC_LINE_0 != lineId) + { + if (((ICP_HSSACC_LINE_1 == lineId) || + (ICP_HSSACC_LINE_3 == lineId) || + (ICP_HSSACC_LINE_2 == lineId)) && + (ICP_HSSACC_CLK_SPEED_8192KHZ == hssAccPortConfig[portId].clkSpeed)) + { + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccPortLineValidCheck - " + "Line %d config Valid\n", + lineId); + status = ICP_STATUS_SUCCESS; + } + else + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortLineValidCheck - Line specified " + "is not valid for current Clock speed\n"); + } + } + else + { + if ((ICP_HSSACC_CLK_SPEED_1544KHZ == + hssAccPortConfig[portId].clkSpeed) && + ((lastTsPos > ICP_HSSACC_TIMESLOTS_PER_T1_LINE) || + (firstTsPos == 0))) + { + ICP_HSSACC_REPORT_ERROR ("HssAccPortLineValidCheck - " + "Attempting to allocate Invalid " + "Timeslots for a T1 line\n"); + } + else + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccPortLineValidCheck - " + "Line 0 config Valid\n"); + status = ICP_STATUS_SUCCESS; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortLineValidCheck\n"); + return status; +} + +/****************************************************************************** + * Abstract: + * return the current state of the specified port + * + *****************************************************************************/ +icp_hssacc_port_state_t +HssAccPortStateGet ( unsigned portId) +{ + return hssAccPortConfig[portId].state; +} + + +/****************************************************************************** + * Abstract: + * Reset the internal stats for this sub-module + * + *****************************************************************************/ +void +HssAccPortConfigStatsReset (void) +{ + memset (&hssAccPortConfigStats, 0, sizeof(icp_hssacc_port_config_stats_t)); +} + + + +/****************************************************************************** + * Abstract: + * display all the internal stats for this sub-module + * + *****************************************************************************/ +void +HssAccPortConfigStatsShow (void) +{ + unsigned portId = 0; + icp_hssacc_hdma_port_config_t * portConfig = NULL; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccPortConfigStatsShow\n"); + if (ICP_TRUE == portConfigInitialised) + { + for (portId = 0; portId < ICP_HSSACC_MAX_NUM_PORTS; portId ++) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort %d:\n", + portId, + 0, 0, 0, 0, 0); + + if (ICP_HSSACC_PORT_UNCONFIGURED == hssAccPortConfig[portId].state) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\tnot configured\n", + 0, 0, 0, 0, 0, 0); + } + else + { + portConfig = (hssAccPortConfig[portId].hdmaPortCfgTableVirtAddr); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort %d in State %d, Configuration:" + "\n\ttx_pcr 0x%08X" + "\n\trx_pcr 0x%08X" + "\n\ttx_fcr 0x%08X" + "\n\trx_fcr 0x%08X", + portId, hssAccPortConfig[portId].state, + portConfig->tx_pcr, + portConfig->rx_pcr, + portConfig->tx_fcr, + portConfig->rx_fcr); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n\ttx_icr 0x%08X\n\trx_icr 0x%08X" + "\n\tclkcr 0x%08X\n\tcwr 0x%08X\n", + portConfig->tx_icr, + portConfig->rx_icr, + portConfig->clkcr, + portConfig->cwr, 0, 0); + + switch (hssAccPortConfig[portId].clkSpeed) + { + case ICP_HSSACC_CLK_SPEED_1544KHZ: + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\tPort Speed Configured For 1.544MHZ\n", + 0, 0, 0, 0, 0, 0); + break; + case ICP_HSSACC_CLK_SPEED_2048KHZ: + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\tPort Speed Configured For 2.048MHZ\n", + 0, 0, 0, 0, 0, 0); + break; + case ICP_HSSACC_CLK_SPEED_8192KHZ: + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\tPort Speed Configured For 8.192MHZ\n", + 0, 0, 0, 0, 0, 0); + break; + default: + break; + } + } + } + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort Configuration Statistics:\n" + "Config Table Load Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccPortConfigStats.configTableLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort Up Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccPortConfigStats.portEnable); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nPort Down Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccPortConfigStats.portDisable); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccPortConfigStatsShow\n"); + +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_hdma_reg_mgr.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_hdma_reg_mgr.c new file mode 100644 index 0000000..66ea618 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_port_hdma_reg_mgr.c @@ -0,0 +1,546 @@ +/****************************************************************************** + * @file icp_hssacc_port_hdma_reg_mgr.c + * + * @description Contents of this file is the implementation of the HSS + * Port registers Creation from API parameters and internal settings. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#include "IxOsal.h" + +#include "icp_hssacc.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_port_hdma_reg_mgr.h" + + +/** + * Typedefs whose scope is limited to this file. + */ + +/* Structure holding HDMA Co-p system clock divider definitions */ +typedef struct icp_hssacc_hdma_sys_clk_s +{ + uint16_t main; + uint16_t num; + uint16_t denom; +} icp_hssacc_hdma_sys_clk_t; + + + +/* HSS Co-p clock divider from the TDM I/O Unit system clk */ +TDM_PRIVATE icp_hssacc_hdma_sys_clk_t +hssAccHdmaSysClk[ICP_HSSACC_CLK_SPEED_DELIMITER] = + { + ICP_HSSACC_HDMA_SYSCLK_1544KHZ, + ICP_HSSACC_HDMA_SYSCLK_2048KHZ, + ICP_HSSACC_HDMA_SYSCLK_8192KHZ + }; + +TDM_PRIVATE uint32_t +tdmPbaAddresses[ICP_HSSACC_HDMA_REG_TYPE_DELIMITER] + [ICP_HSSACC_MAX_NUM_PORTS] = + { + { + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_0, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_1, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_2 +#ifdef IXP23XX +, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_3 +#endif + }, + { + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_0, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_1, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_2 +#ifdef IXP23XX +, + ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_3 +#endif + } + } ; + + + +/** + * Function definition: HssAccHdmaMgrPCRCreate + */ +void +HssAccHdmaMgrPCRCreate (icp_hssacc_hdma_reg_trans_t type, + const icp_hssacc_port_full_config_t *portConfig, + uint32_t *pcr) +{ + + + uint32_t offsetInReg = ICP_HSSACC_TDM_IO_UNIT_HDMA_RX_PCR_LB_OFFSET; + uint32_t clkDirection = ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_OUTPUT; +#ifdef EP805XX + uint32_t clkSelect = ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_INT; +#endif + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrPCRCreate\n"); + + *pcr = 0; + + if (ICP_HSSACC_CLK_MODE_INPUT_EXTERNAL == portConfig->cfg.clkMode) + { + clkDirection = ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_INPUT; + } +#ifdef EP805XX + /* A single API parameter maps to 2 fields of this register + map 1 to 2 here starting with default values above */ + if (ICP_HSSACC_CLK_MODE_OUTPUT_REF == portConfig->cfg.clkMode) + { + clkSelect = ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_EXT_REF; + } +#endif + + + + /* create the common parts of the HSS co-p pcr register */ + /* note: portDataBitEndianness is now ICP_HSSACC_BIT_ENDIAN_MSB + at all times */ + *pcr = + (portConfig->cfg.frmSyncType << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FT_OFFSET) | + (portConfig->cfg.frmSyncIO << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FS_OFFSET) | + (portConfig->cfg.frmSyncClkEdge << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FE_OFFSET) | + (portConfig->cfg.dataClkEdge << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_DE_OFFSET) | + (clkDirection << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_OFFSET)| + (portConfig->cfg.frmPulseUsage << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FR_OFFSET) | + (portConfig->addCfg.dataRate << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_RATE_OFFSET) | + (portConfig->cfg.dataPolarity << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_DP_OFFSET) | + (ICP_HSSACC_BIT_ENDIAN_MSB << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_BITEND_OFFSET)| +#ifdef EP805XX + (portConfig->cfg.refFrame << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_REFF_OFFSET) | + (clkSelect << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_OFFSET) | +#endif + (portConfig->addCfg.frmPulseWidth - 1); + /* width varies from 1 to 8 but input value to co-proc is 0 to 7*/ + + + /* check the tx specific parameters */ + if (ICP_HSSACC_HDMA_TX_REG_TYPE == type) + { + offsetInReg = ICP_HSSACC_TDM_IO_UNIT_HDMA_TX_PCR_LB_OFFSET; + /* create the tx specific parts of the HSS co-p pcr register */ + *pcr |= + (portConfig->cfg.drainMode << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_OD_OFFSET) | + (portConfig->cfg.dataPinsEnable << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_EN_OFFSET) | + (portConfig->cfg.fBitType << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FB_OFFSET) | + (0 << ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KTYPE_OFFSET) | + (portConfig->cfg.unassignedType << + ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_UTYPE_OFFSET) | + (0 << ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KEND_OFFSET ) | + (0 << ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KSEL_OFFSET ); + } + if (ICP_TRUE == portConfig->cfg.loopback) + { + *pcr |= (ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_LB_ON + << offsetInReg); + } + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrPCRCreate - " + "PCR = 0x%08X\n", *pcr); + +#ifdef SW_SWAPPING + *pcr = IX_OSAL_SWAP_BE_SHARED_LONG(*pcr); +#endif + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrPCRCreate\n"); +} + +/** + * Function definition: HssAccHdmaMgrFCRCreate + */ +icp_status_t +HssAccHdmaMgrFCRCreate (icp_hssacc_hdma_reg_trans_t type, + icp_hssacc_clk_speed_t clkSpeed, + const icp_hssacc_port_full_config_t *portConfig, + uint32_t *fcr) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint8_t size = 0; + uint16_t offsetMaxVal = 0; + uint32_t offset = 0; + uint32_t fBitEnable = 0; + /* Used to indicate if this Hss Port is using MVIP or not */ + icp_hssacc_hdma_mvip_switch_t mvipSwitch = + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_DELIMITER; + /* Used to indicate if this Hss Port is using quad MVIP or not */ + icp_hssacc_hdma_mvip_setting_t mvipSetting = + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_DELIMITER; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrFCRCreate\n"); + + switch (clkSpeed) + { + case ICP_HSSACC_CLK_SPEED_1544KHZ: + size = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_T1_IN_TS; + mvipSwitch = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFF; + offsetMaxVal = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_T1_IN_BITS; + if (portConfig->cfg.frm_offset >= offsetMaxVal) + { + ICP_HSSACC_REPORT_ERROR ("HssAccHdmaMgrFCRCreate - frmOffset >=" + " T1 frame size\n"); + status = ICP_STATUS_INVALID_PARAM; + } + break; + + case ICP_HSSACC_CLK_SPEED_2048KHZ: + size = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_TS; + mvipSwitch = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFF; + offsetMaxVal = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_BITS; + if (portConfig->cfg.frm_offset >= offsetMaxVal) + { + ICP_HSSACC_REPORT_ERROR ("HssAccHdmaMgrFCRCreate - frmOffset >=" + " E1 frame size\n"); + status = ICP_STATUS_INVALID_PARAM; + } + break; + + + case ICP_HSSACC_CLK_SPEED_8192KHZ: + size = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_TS; + mvipSwitch = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_ON; + mvipSetting = ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_QUAD; + offsetMaxVal = + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_QUAD_MVIP_IN_BITS; + /* No need to check if (offset > offsetMaxVal), the service I/F has + done this already. */ + break; + + default: + /* clkSpeed is already error checked so this default is unreachable */ + ICP_HSSACC_REPORT_ERROR_1 ("HssAccHdmaMgrFCRCreate - Invalid clock " + "speed (%d) in clkSpeed struct\n", + clkSpeed); + status = ICP_STATUS_INVALID_PARAM; + } + + if ( ICP_STATUS_SUCCESS == status ) + { + offset = portConfig->cfg.frm_offset; + if (ICP_HSSACC_HDMA_TX_REG_TYPE == type) + { + if (ICP_HSSACC_DATA_RATE_EQUALS_CLK_RATE == + portConfig->addCfg.dataRate) + { + offset += + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_TX_ADD_CLK_RATE; + } + else if (ICP_HSSACC_DATA_RATE_HALF_CLK_RATE == + portConfig->addCfg.dataRate) + { + offset += + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_TX_ADD_HALF_CLK_RATE; + } + /* + It is the modulus of the frame size that the frame pulse + delineates, which is expected to fit into the offset bits + of the FCR + */ + offset %= offsetMaxVal; + + /* With FBit Enabled, offset values of 0-7 are illegal */ + if (ICP_TRUE == portConfig->cfg.fBitEnable) + { + offset += ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_FBIT_ADDITION; + } + } + + } + + + if (ICP_STATUS_SUCCESS == status) + { + + if (ICP_TRUE == portConfig->cfg.fBitEnable) + { + fBitEnable = 1; + } + + *fcr = 0; + /* create the HSS co-proc 32bit register format */ + *fcr = + (fBitEnable << ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FBIT_OFFSET) | + (size << ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_OFFSET) | + (mvipSwitch << ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFFSET) | + (portConfig->cfg.interleaving << + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_INT_OFFSET) | + (offset << ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_OFFSET); + + if (ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_ON == mvipSwitch) + { + *fcr |= mvipSetting << + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_OFFSET; + } + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrFCRCreate - " + "FCR = 0x%08X\n", *fcr); + +#ifdef SW_SWAPPING + *fcr = IX_OSAL_SWAP_BE_SHARED_LONG(*fcr); +#endif + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrFCRCreate\n"); + return status; +} + + + +/** + * Function definition: HssAccHdmaMgrICRCreate + */ +void +HssAccHdmaMgrICRCreate (icp_hssacc_hdma_reg_trans_t type, + unsigned hssPortId, + uint32_t *icr) +{ + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrICRCreate\n"); + + *icr = + (ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_PID_SHIFT << + ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PID_OFFSET) | + (tdmPbaAddresses[type][hssPortId] << + ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PBA_OFFSET); + +#ifdef IXP23XX + *icr |= + (ICP_HSSACC_TDM_IO_UNIT_HSS_PING_PONG_ENABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PINGPONG_OFFSET) | + (ICP_HSSACC_TDM_IO_UNIT_HSS_VCH_ENABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_VOICE_CHANNELISATION_OFFSET); +#endif + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrICRCreate - ICR = 0x%08X\n", + *icr); + +#ifdef SW_SWAPPING + *icr = IX_OSAL_SWAP_BE_SHARED_LONG(*icr); +#endif + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrICRCreate\n"); +} + + +/** + * Function definition: HssAccHdmaMgrClkCRCreate + */ +void +HssAccHdmaMgrClkCRCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *clkCR) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrClkCRCreate\n"); + *clkCR = + (hssAccHdmaSysClk[clkSpeed].main << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_MAIN_OFFSET) | + (hssAccHdmaSysClk[clkSpeed].num << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_NUM_OFFSET) | + (hssAccHdmaSysClk[clkSpeed].denom << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_DENOM_OFFSET); + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrClkCRCreate - CLKCR = 0x%08X\n", + *clkCR); + +#ifdef SW_SWAPPING + *clkCR = IX_OSAL_SWAP_BE_SHARED_LONG(*clkCR); +#endif + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrClkCRCreate\n"); +} + + +#ifdef IXP23XX +/** + * Function definition: HssAccHdmaMgrVCRCreate + */ +void +HssAccHdmaMgrVCRCreate (uint32_t *vcr) +{ + uint8_t voiceOffset = 0; + uint8_t lineIndex = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrVCRCreate\n"); + + for(lineIndex = 0; + lineIndex < ICP_HSSACC_MAX_TDM_LINES_PER_PORT; + lineIndex ++) + { + if(lineIndex != 0 ) + { + (*vcr) |= + (voiceOffset << + ((lineIndex - 1) * + ICP_HSSACC_TDM_IO_UNIT_HDMA_VCR_FRAME_BASE_OFFSET)); + } + voiceOffset += ICP_HSSACC_TDM_IO_UNIT_HSS_SUB_FRAME_DELTA_OFFSET; + + } + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrVCRCreate VCR = 0x%08X\n", + *vcr); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrVCRCreate\n"); +} +#endif + + +/** + * Function definition: HssAccHdmaMgrCWRCreate + */ +void +HssAccHdmaMgrCWRCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *cwr) +{ + uint8_t timeslotsOnLastLine = 0; + uint8_t numOfActiveLines = 0; + uint32_t cwLocation = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccHdmaMgrCWRCreate\n"); + switch (clkSpeed) + { + case ICP_HSSACC_CLK_SPEED_1544KHZ: + timeslotsOnLastLine = ICP_HSSACC_TIMESLOTS_PER_T1_LINE; + numOfActiveLines = 1; + break; + case ICP_HSSACC_CLK_SPEED_2048KHZ: + timeslotsOnLastLine = ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + numOfActiveLines = 1; + break; + case ICP_HSSACC_CLK_SPEED_8192KHZ: + timeslotsOnLastLine = ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + numOfActiveLines = ICP_HSSACC_MAX_TDM_LINES_PER_PORT; + break; + default: + /* Code is not reachable under normal operation */ + ICP_HSSACC_REPORT_ERROR ("HssAccHdmaMgrCWRCreate - invalid" + " clock speed\n"); + return; + } + + + *cwr = /* first, shift in the enabling of the CW conditions */ + (ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW1_ENABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW1_ENABLE_OFFSET) | + (ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW2_DISABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW2_ENABLE_OFFSET) | + (ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW1_ENABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW1_ENABLE_OFFSET) | + (ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW2_DISABLED << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW2_ENABLE_OFFSET) ; + + /* Calculate the location where the TDM I/O Unit is to be woken up, + it is at the last timeslot used on the last active line (timeslot + location start from 0) */ + cwLocation = (timeslotsOnLastLine - 1) + + ((numOfActiveLines - 1) * ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE); + /* Now shift in the addresses of the CW offsets */ + *cwr |= + (cwLocation << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW1_ADDRESS_OFFSET) | + (cwLocation << + ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW1_ADDRESS_OFFSET); + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccHdmaMgrCWRCreate CWR = 0x%08X\n", + *cwr); + +#ifdef SW_SWAPPING + *cwr = IX_OSAL_SWAP_BE_SHARED_LONG(*cwr); +#endif + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccHdmaMgrCWRCreate\n"); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_queues_config.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_queues_config.c new file mode 100644 index 0000000..93766d5 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_queues_config.c @@ -0,0 +1,1501 @@ +/****************************************************************************** + * @file icp_hssacc_queues_config.c + * + * @description Contents of this file provide the implementation of the + * Tx and Rx Queues Configuration functionality + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#include "IxOsal.h" + +#include "IxQMgr.h" +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_rx_datapath.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_address_translate.h" + +/* + * ---------------------------------------------------------------------------- + * Macros + * ---------------------------------------------------------------------------- + */ + +/* + * Macros that are used to distinguish between the voice and HDLC callback + * routines. The same macros are used for both the Rx queues and the Rx free + * queues. + */ +#define ICP_HSSACC_VOICE_RX_QMGR_CB_ID (0) +#define ICP_HSSACC_HDLC_RX_QMGR_CB_ID (1) + + + +#define ICP_HSSACC_CACHE_MASK (IX_OSAL_CACHE_LINE_SIZE-1) + +#define ICP_HSSACC_Q_NAME_SIZE 16 +#define ICP_HSSACC_Q_TYPE_NAME_SIZE 12 + + + +/* Defines Virtual and Physical values for the same memory block */ +typedef struct icp_hssacc_mem_base_addr_s +{ + void * virt; + uint32_t physOffset; +} icp_hssacc_mem_base_addr_t; + +/* + * ---------------------------------------------------------------------------- + * Static variable declarations + * ---------------------------------------------------------------------------- + */ +/* Flag used to test whether the queues have been initialised or not. */ +TDM_PRIVATE icp_boolean_t queuesConfigured = FALSE; + + +/* + * Holds the address of the memory allocated for the queue counters. + */ +TDM_PRIVATE icp_hssacc_mem_base_addr_t readCountersBaseAddress = + { + NULL, 0 + }; + +TDM_PRIVATE icp_hssacc_mem_base_addr_t writeCountersBaseAddress = + { + NULL, 0 + }; + +/* + * the virtual Addresses of each block that will have its physical + * address sent to the TDM I/O Unit + */ +/* Block containing the Tx Queues for ALL channels */ +TDM_PRIVATE icp_hssacc_mem_base_addr_t +txQsAddrArray[ICP_HSSACC_MAX_NUM_CHANNELS]; + +/* Block with Rx and RxFree for HDLC */ +TDM_PRIVATE icp_hssacc_mem_base_addr_t rxHdlcQsBlockAddr = + { + NULL, 0 + }; +/* Block with Rx and RxFree for VOICE */ +TDM_PRIVATE icp_hssacc_mem_base_addr_t rxVoiceQsBlockAddr = + { + NULL, 0 + }; + +/* Stores the list of Queue IDs as provided by the QMgr + this will be used to access the queues later. + we have 1 queue for each channel on Tx and 2 queues on Rx per + service supported */ +TDM_PRIVATE IxQMgrQId +hssAccQueueIds[ICP_HSSACC_MAX_NUM_CHANNELS + ICP_HSSACC_NUM_RECEIVE_QS]; + + +TDM_PRIVATE icp_hssacc_queues_config_stats_t hssAccQueuesCfgStats; + +/* + * ---------------------------------------------------------------------------- + * Static function declarations + * ---------------------------------------------------------------------------- + */ +TDM_PRIVATE void +HssAccQueueMemoryAlloc(icp_hssacc_mem_base_addr_t * txQsMemBaseArray, + icp_hssacc_mem_base_addr_t * pRxHdlcQsMemBase, + icp_hssacc_mem_base_addr_t * pRxVoiceQsMemBase, + icp_hssacc_mem_base_addr_t * pReadCounterMemBase, + icp_hssacc_mem_base_addr_t * pWriteCounterMemBase); + +TDM_PRIVATE icp_status_t +HssAccQueuesConfig(void); + +TDM_PRIVATE icp_status_t +HssAccQueueConfigMsgSubmit(uint32_t qBasePhysOffset, + uint32_t qDepth, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stat); + +TDM_PRIVATE icp_status_t +HssAccTxQueuesConfigMsgsSubmit(icp_hssacc_mem_base_addr_t * qTxQBaseAddresses, + icp_hssacc_msg_with_resp_stats_t * stat); + +TDM_PRIVATE icp_status_t +HssAccQueueCounterConfigMsgSubmit(uint32_t qCounterPhysOffset, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stat); + +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitQueuesConfig(void); + +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitQueueCountersConfig(void); + + +/* + * ---------------------------------------------------------------------------- + * Public function definitions + * ---------------------------------------------------------------------------- + */ +/****************************************************************************** + * Abstract: + * Allocates memory for all of the queues shared between the access layer + * and the TDM I/O unit. Also allocates memory for the head and tail + * counters for each queue. + * Verifies that the memory allocated is aligned on a cache line boundary. + * Registers each queue with QMgr and configures the queue watermark, etc. + * Submits the queue details to the TDM I/O unit. + * + * + *****************************************************************************/ +icp_status_t +HssAccQueuesInit(void) +{ + unsigned channel = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueuesInit\n"); + + if (TRUE == queuesConfigured) + { + ICP_HSSACC_REPORT_ERROR ("HssAccQueuesInit - Queues already " + "configured\n"); + return ICP_STATUS_SUCCESS; + } + + /* Allocate a block of memory for the queues and the head & tail counters */ + HssAccQueueMemoryAlloc (txQsAddrArray, + &rxHdlcQsBlockAddr, + &rxVoiceQsBlockAddr, + &readCountersBaseAddress, + &writeCountersBaseAddress); + + /* Check if the memory was correctly allocated */ + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + if (NULL == txQsAddrArray[channel].virt) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesInit - " + "Failed to allocate Tx queue memory" + " for channel %d\n", + channel); + status = ICP_STATUS_FAIL; + break; + } + } + + if ((NULL == rxHdlcQsBlockAddr.virt) || + (NULL == rxVoiceQsBlockAddr.virt)) + { + ICP_HSSACC_REPORT_ERROR ("HssAccQueuesInit - " + "Failed to allocate Rx queues memory\n"); + + status = ICP_STATUS_FAIL; + } + + if ((NULL == readCountersBaseAddress.virt) || + (NULL == writeCountersBaseAddress.virt)) + { + ICP_HSSACC_REPORT_ERROR ("HssAccQueuesInit - " + "Failed to allocate queue counter memory\n"); + + status = ICP_STATUS_FAIL; + } + + if (status == ICP_STATUS_SUCCESS) + { + /* Allocated memory must start on a cache boundary */ + for (channel = 0; + channel < ICP_HSSACC_MAX_NUM_CHANNELS; + channel ++) + { + if ((((uint32_t)txQsAddrArray[channel].virt & + ICP_HSSACC_CACHE_MASK) != 0)) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesInit - " + "Allocated Tx queue memory" + " for channel %d is NOT on" + " a cache line boundary\n", + channel); + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "\tTx queue " + "base memory 0x%08X\n\t", + (uint32_t)txQsAddrArray[channel].virt); + + status = ICP_STATUS_RESOURCE; + break; + } + } + + if ((((uint32_t)rxHdlcQsBlockAddr.virt & ICP_HSSACC_CACHE_MASK) != 0) || + (((uint32_t)rxVoiceQsBlockAddr.virt & ICP_HSSACC_CACHE_MASK) != 0) || + (((uint32_t)readCountersBaseAddress.virt & + ICP_HSSACC_CACHE_MASK) != 0) || + (((uint32_t)writeCountersBaseAddress.virt & + ICP_HSSACC_CACHE_MASK) != 0) ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccQueuesInit - Allocated Memory " + "must start on a cache line boundary\n"); + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "\tqueue " + "read counter memory 0x%x\n\t" + "write counter memory 0x%x\n\t", + (uint32_t)readCountersBaseAddress.virt, + (uint32_t)writeCountersBaseAddress.virt); + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "\tRx Hdlc queue memory 0x%x and Rx " + "Voice queue memory 0x%x\n\t ", + (uint32_t)rxHdlcQsBlockAddr.virt, + (uint32_t)rxVoiceQsBlockAddr.virt); + + status = ICP_STATUS_RESOURCE; + } + } + + if (status == ICP_STATUS_SUCCESS) + { + /* + * Carve up the memory between the queues and submit the queue + * configuration (for each queue) to the QMgr. + */ + status = HssAccQueuesConfig (); + + } + if (ICP_STATUS_SUCCESS == status) + { + /* + * Now that the Qmgr queues have been initialised, inform the + * TDM I/O Unit of the base address and size of each of the queues. + */ + status = HssAccTdmIOUnitQueuesConfig (); + } + if (ICP_STATUS_SUCCESS == status) + { + /* + * Now that the Qmgr queues have been initialised, and the queue base + * addresses submitted to the TDM I/O unit, submit the base address + * of each of the counters to TDM I/O unit. + */ + status = HssAccTdmIOUnitQueueCountersConfig (); + } + + /* This statement verifies that all queue initialisation steps succeeded */ + if (ICP_STATUS_SUCCESS == status) + { + /* all queues initialised and configured */ + queuesConfigured = TRUE; + } + else + { + ICP_HSSACC_REPORT_ERROR( "HssAccQueuesInit - Cleanup\n"); + HssAccQueuesShutdown(); + } + + /* Reset the Stats */ + HssAccQueuesConfigStatsReset(); + + ICP_HSSACC_TRACE_0( ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueuesInit\n" ); + + return status; +} + + +/***************************************************************************** + * Abstract: + * Frees the memory allocated for the queues and the queue counters, and + * resets the queue configuration flag. + * + * + *****************************************************************************/ +icp_status_t +HssAccQueuesShutdown(void) +{ + unsigned channel = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0(ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueuesShutdown\n" ); + + + /* Best Effort cleanup, we dont care about success or failure + at this stage. we still try to cleanup everything. */ + status = ixQMgrUnconfigGroup(IX_QMGR_DISPATCH_TX_HSS); + + status |= ixQMgrUnconfigGroup(IX_QMGR_DISPATCH_VOICE_RX_HSS); + + status |= ixQMgrUnconfigGroup(IX_QMGR_DISPATCH_HDLC_RX_HSS); + + /* Only Free the memory that was allocated */ + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + if (NULL != txQsAddrArray[channel].virt) + { + /* Free the memory allocated for the queues */ + IX_OSAL_CACHE_DMA_FREE(txQsAddrArray[channel].virt); + txQsAddrArray[channel].virt = NULL; + + ICP_HSSACC_TRACE_1(ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free memory" + " for Tx Channel %d\n", + channel); + + } + } + + if (NULL != rxHdlcQsBlockAddr.virt) + { + IX_OSAL_CACHE_DMA_FREE (rxHdlcQsBlockAddr.virt); + rxHdlcQsBlockAddr.virt = NULL; + ICP_HSSACC_TRACE_0(ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free Rx Hdlc memory\n"); + + } + + if (NULL != rxVoiceQsBlockAddr.virt) + { + IX_OSAL_CACHE_DMA_FREE (rxVoiceQsBlockAddr.virt); + rxVoiceQsBlockAddr.virt = NULL; + ICP_HSSACC_TRACE_0(ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free Rx Voice memory\n"); + + } + + if (NULL != readCountersBaseAddress.virt) + { + /* Free the memory allocated for the queue counters */ + IX_OSAL_CACHE_DMA_FREE (readCountersBaseAddress.virt); + readCountersBaseAddress.virt = NULL; + ICP_HSSACC_TRACE_0(ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free Read Counter memory\n"); + + } + + + if (NULL != writeCountersBaseAddress.virt) + { + /* Free the memory allocated for the queue counters */ + IX_OSAL_CACHE_DMA_FREE (writeCountersBaseAddress.virt); + writeCountersBaseAddress.virt = NULL; + ICP_HSSACC_TRACE_0( ICP_HSSACC_DEBUG, + "HssAccQueuesShutdown - Free Write Counter memory\n"); + + } + + /* Reset the queue configuration flag */ + queuesConfigured = FALSE; + + + ICP_HSSACC_TRACE_0( ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueuesShutdown\n" ); + return status; +} + +/***************************************************************************** + * Abstract: + * Allocates memory for all of the queues shared between the access layer + * and the TDM I/O unit. Also allocates memory for the head and tail + * counters for each queue. + * The memory is allocated on a cache line boundary, and each queue is an + * integer multiple of the cache line size. This guarantees that each queue + * is cache-aligned. + * The counter memory is also allocated on a cache boundary, and each set + * of counters is cache-aligned. + * + *****************************************************************************/ +TDM_PRIVATE void +HssAccQueueMemoryAlloc(icp_hssacc_mem_base_addr_t * txQsMemBaseArray, + icp_hssacc_mem_base_addr_t * pRxHdlcQsMemBase, + icp_hssacc_mem_base_addr_t * pRxVoiceQsMemBase, + icp_hssacc_mem_base_addr_t * pReadCounterMemBase, + icp_hssacc_mem_base_addr_t * pWriteCounterMemBase) +{ + /* + * Malloc enough memory for the following queues: + * Voice RX free Q + * Voice RX Q + * HDLC RX free Q + * HDLC RX Q + * Max Num Chan TX Qs (1 per channel) + * And the Following Counters: + * Max Num Chan Tx Tail 8 bit ctrs (1 per chan) + * Max Num Chan Tx Head 8 bit ctrs (1 per chan) + * Voice Rx Free Head and Tail (32 bits each) + * HDLC Rx Free Head and Tail (32 bits each) + * Voice Rx Head and Tail (32 bits each) + * HDLC Rx Head and Tail (32 bits each) + */ + + + /* + * Note 1: the rx free Q and the rx Q must be contiguous in memory. + * Note 2: the rx free Q and the rx Q must have the same depth. + * Note 3: a TX queue for an HDLC channel may be deeper than a TX queue for + * a Voice channel. Thus, the default TX queue depth will be that of an + * HDLC channel. The watermark will be moved accordingly to accomodate + * both depths. + * Each queue should be aligned on a cache line boundary, and should be a + * multiple of the cache line size. + */ + + uint32_t bytesToAlloc = 0; + unsigned channel = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueueMemoryAlloc\n"); + + + /* Calculate the total amount of memory needed for each Tx queue */ + bytesToAlloc = ICP_HSSACC_TX_QUEUE_SIZE_IN_BYTES; + + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + /* All queues must use memory that is aligned on a cache line boundary */ + txQsMemBaseArray[channel].virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(txQsMemBaseArray[channel].physOffset)); + ICP_HSSACC_TRACE_4 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Tx Queue Mem from " + "0x%08X (phys 0x%08X) with Size %d bytes" + " for chan %d\n", + (uint32_t)(txQsMemBaseArray[channel].virt), + txQsMemBaseArray[channel].physOffset, + bytesToAlloc, + channel); + } + + /* Calculate the total amount of memory needed for Rx Hdlc queues */ + bytesToAlloc = ICP_HSSACC_HDLC_RX_QUEUE_SIZE_IN_BYTES + + ICP_HSSACC_HDLC_RX_FREE_QUEUE_SIZE_IN_BYTES; + + /* All queues must use memory that is aligned on a cache line boundary */ + pRxHdlcQsMemBase->virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(pRxHdlcQsMemBase->physOffset)); + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Rx Hdlc Queue Mem " + "from 0x%08X (phys 0x%08X) with Size %d bytes\n", + (uint32_t)pRxHdlcQsMemBase->virt, + pRxHdlcQsMemBase->physOffset, + bytesToAlloc); + + + /* Calculate the total amount of memory needed for the Rx Voice queues */ + bytesToAlloc = ICP_HSSACC_VOICE_RX_QUEUE_SIZE_IN_BYTES + + ICP_HSSACC_VOICE_RX_FREE_QUEUE_SIZE_IN_BYTES; + + /* All queues must use memory that is aligned on a cache line boundary */ + pRxVoiceQsMemBase->virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(pRxVoiceQsMemBase->physOffset)); + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Rx Voice Queue Mem " + "from 0x%08X (phys 0x%08X) with Size %d bytes\n", + (uint32_t)pRxVoiceQsMemBase->virt, + pRxVoiceQsMemBase->physOffset, + bytesToAlloc); + + /* + * Allocate memory in DRAM for the queue head & tail counters. + * The read (from the access layer perspective) counters need to be arranged + * as follows: + * "max num chans" bytes (packed) for the Tx tail counters. These + * "max num chans" bytes must be contiguous in memory. + * 4-byte Voice Rx free tail and 4-byte Rx head counters, which must be + * contiguous in memory and aligned on a cache line boundary. + * 4-byte HDLC Rx free tail and 4-byte Rx head counters, which must + * be contiguous in memory and aligned on a cache line boundary. + * + * The write counters need to be arranged as follows: + * "max num chans" bytes (packed) for the Tx head counters. + * 4-byte Voice Rx free head and 4-byte Rx tail counters, which must be + * contiguous in memory and aligned on a cache line boundary. + * 4-byte HDLC Rx free head and 4-byte Rx tail counters, which must + * be contiguous in memory and aligned on a cache line boundary. + * + */ + bytesToAlloc = sizeof(icp_hssacc_queue_reader_counters_t); + + pReadCounterMemBase->virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(pReadCounterMemBase->physOffset)); + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Read Counter Memory " + "from 0x%08X (phys 0x%08X) with Size %d bytes\n", + (uint32_t)pReadCounterMemBase->virt, + pReadCounterMemBase->physOffset, + bytesToAlloc); + + bytesToAlloc = sizeof(icp_hssacc_queue_write_counters_t); + + pWriteCounterMemBase->virt = + HssAccDmaMemAllocate(bytesToAlloc, + &(pWriteCounterMemBase->physOffset)); + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccQueueMemoryAlloc - Allocated Write Counter Memory " + "from 0x%08X (phys 0x%08X) with Size %d bytes\n", + (uint32_t)pWriteCounterMemBase->virt, + pWriteCounterMemBase->physOffset, + bytesToAlloc); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueueMemoryAlloc\n"); + return; +} + + +/***************************************************************************** + * Abstract: + * Divides the queue memory between each of the queues and does likewise + * with the queue counter memory. + * Registers each queue with the QMgr and configures each queue. + * Configures the address of the counters to flush and invalidate for each + * iteration of the dispatcher loop. The counters read by the access layer + * will be invalidated and the counters written by the access layer will be + * flushed. + * + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccQueuesConfig(void) +{ + uint32_t channel, qBaseOffset = 0; + IxQMgrQId qId = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_queue_write_counters_t *pWriteCounters = NULL; + icp_hssacc_queue_reader_counters_t *pReadCounters = NULL; + uint8_t *pTxQueueHead = NULL; + uint8_t *pTxQueueTail = NULL; + uint32_t *pRxQueueHead = NULL; + uint32_t *pRxQueueTail = NULL; + uint32_t invalidateAddress = 0; + uint32_t flushAddress = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueuesConfig\n "); + + /* Cast the counter structure to the memory allocated for the counters */ + pWriteCounters = + (icp_hssacc_queue_write_counters_t *)writeCountersBaseAddress.virt; + pReadCounters = + (icp_hssacc_queue_reader_counters_t *)readCountersBaseAddress.virt; + + invalidateAddress = (uint32_t)(pReadCounters->txTail); + flushAddress = (uint32_t)(pWriteCounters->txHead); + + /* + * This function sets the address of the counters to be + * flushed/invalidated each time the QMgrDispatcher runs. + * The QMgr dispatcher will only check the queues that have been + * registered with it. In this case only the Rx queues will be serviced + * by the dispatcher. + */ + + /* configure the address and size to be flushed/invalidated */ + if (ixQMgrGroupMemoryConfig (IX_QMGR_DISPATCH_TX_HSS, + (void *)flushAddress, + (void *)invalidateAddress, + sizeof(pReadCounters->txTail)) + != ICP_STATUS_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR("HssAccQueuesConfig - Failed Tx Queue group " + "configuration\n"); + return ICP_STATUS_FAIL; + } + + invalidateAddress = (uint32_t)&(pReadCounters->voiceRxCounters); + flushAddress = (uint32_t)&(pWriteCounters->voiceRxCounters); + + /* configure the address and size to be flushed/invalidated for + voice receive q's */ + if (ixQMgrGroupMemoryConfig (IX_QMGR_DISPATCH_VOICE_RX_HSS, + (void *)flushAddress, + (void *)invalidateAddress, + sizeof(pReadCounters->voiceRxCounters)) + != ICP_STATUS_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR("HssAccQueuesConfig - Failed Voice Rx " + "Queue group configuration\n"); + return ICP_STATUS_FAIL; + } + + /* + * Increment addresses by size of receive queue counter block + */ + invalidateAddress = (uint32_t)&(pReadCounters->hdlcRxCounters); + flushAddress = (uint32_t)&(pWriteCounters->hdlcRxCounters); + + /* configure the address and size to be flushed/invalidated for HDLC + receive q's */ + if (ixQMgrGroupMemoryConfig (IX_QMGR_DISPATCH_HDLC_RX_HSS, + (void *)flushAddress, + (void *)invalidateAddress, + sizeof(pReadCounters->hdlcRxCounters)) + != ICP_STATUS_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR("HssAccQueuesConfig - Failed HDLC Rx Queue group " + "configuration\n"); + return ICP_STATUS_FAIL; + } + + + /* + * The queues are allocated in memory in the following blocks: + * 1: "max num chans" Tx queues + * 2:Voice Rx Free queue + * Voice Rx queue + * 3:HDLC Rx Free queue + * HDLC Rx queue + * 4:Read Counters + * 5: Write Counters + */ + + /* + * Configure the Tx queues + */ + for (channel = 0; + channel < ICP_HSSACC_MAX_NUM_CHANNELS; + channel ++) + { + + char qName[ICP_HSSACC_Q_NAME_SIZE] = "HssAcc Tx Q "; + + /* Append the queue number to its string identifier */ + snprintf (&qName[ICP_HSSACC_Q_TYPE_NAME_SIZE], + ICP_HSSACC_Q_NAME_SIZE - ICP_HSSACC_Q_TYPE_NAME_SIZE, + "%u", channel); + + /* Set the address of the head and tail counters for this queue */ + pTxQueueHead = &(pWriteCounters->txHead[channel]); + pTxQueueTail = &(pReadCounters->txTail[channel]); + + status = + ixQMgrQConfig (qName, + &qId, + ICP_HSSACC_TX_QUEUE_DEPTH, + ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_BYTE, + IX_QMGR_DISPATCH_TX_HSS, + IX_QMGR_Q_SHADOW_TAIL_ONLY, + txQsAddrArray[channel].virt, + pTxQueueHead, + pTxQueueTail); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_2 ("HssAccQueuesConfig - Failed to configure " + "Tx Q %u. ixQMgrQConfig() returned %u\n", + channel, status); + return ICP_STATUS_FAIL; + } + + hssAccQueueIds[channel] = qId; + status = ixQMgrWatermarkSet (qId, ICP_HSSACC_TX_WATERMARK); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_2 ("HssAccQueuesConfig - Failed to set " + "watermark for Tx Q " + "%u. ixQMgrWatermarkSet() returned %u\n", + channel, status); + + return ICP_STATUS_FAIL; + } + } + /* + * The TDM I/O Unit expects the voice Rx & Rx free queues to be contiguous + * in memory, with the Rx free queue preceeding the Rx queue. However, the + * voice Rx queue should be serviced before the voice Rx free queue. + * The order in which a queue is registered with the dispatcher determines + * the order in which it will be serviced by the QMgr dispatcher. + * hence all Receive Queues are first allocated then registered. registration + * is done at a later stage. + */ + + /* + * Voice Rx free queue + */ + + pRxQueueHead = &(pWriteCounters->voiceRxCounters.rxFreeHead); + pRxQueueTail = &(pReadCounters->voiceRxCounters.rxFreeTail); + + status = ixQMgrQConfig ("Voice Rx Free Q", + &qId, + ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH, + ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_WORD, + IX_QMGR_DISPATCH_VOICE_RX_HSS, + IX_QMGR_Q_NO_SHADOWING, + (void*)rxVoiceQsBlockAddr.virt, + pRxQueueHead, + pRxQueueTail); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to configure " + "voice Rx free queue." + " ixQMgrQConfig() returned %u\n", status); + return ICP_STATUS_FAIL; + } + hssAccQueueIds[ICP_HSSACC_VOICE_RX_FREE_Q] = qId; + + /* + * Voice Rx queue + */ + qBaseOffset = ICP_HSSACC_VOICE_RX_FREE_QUEUE_SIZE_IN_BYTES; + + pRxQueueHead = &(pReadCounters->voiceRxCounters.rxHead); + pRxQueueTail = &(pWriteCounters->voiceRxCounters.rxTail); + + status = + ixQMgrQConfig ("Voice Rx Q", + &qId, + ICP_HSSACC_VOICE_RX_QUEUE_DEPTH, + ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_WORD, + IX_QMGR_DISPATCH_VOICE_RX_HSS, + IX_QMGR_Q_NO_SHADOWING, + (void*)(qBaseOffset + (uint32_t)rxVoiceQsBlockAddr.virt), + pRxQueueHead, + pRxQueueTail); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to configure " + "voice Rx queue." + " ixQMgrQConfig() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + hssAccQueueIds[ICP_HSSACC_VOICE_RX_Q] = qId; + status = ixQMgrWatermarkSet (qId, ICP_HSSACC_VOICE_RX_WATERMARK); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to set watermark " + "for voice Rx queue." + " ixQMgrWatermarkSet() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + /* Register the callback for this Q */ + status = ixQMgrNotificationCallbackSet (qId, + HssAccRxQServiceCallback, + ICP_HSSACC_VOICE_RX_QMGR_CB_ID); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to set " + "Notification callback function for voice " + "Rx Q. ixQMgrWatermarkSet() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + /* + * HDLC Rx free queue + */ + + pRxQueueHead = &(pWriteCounters->hdlcRxCounters.rxFreeHead); + pRxQueueTail = &(pReadCounters->hdlcRxCounters.rxFreeTail); + + status = ixQMgrQConfig ("HDLC Rx Free Q", + &qId, + ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH, + ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_WORD, + IX_QMGR_DISPATCH_HDLC_RX_HSS, + IX_QMGR_Q_NO_SHADOWING, + (void*)rxHdlcQsBlockAddr.virt, + pRxQueueHead, + pRxQueueTail); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to configure " + "HDLC Rx free queue." + " ixQMgrQConfig() returned %u\n", status); + return ICP_STATUS_FAIL; + } + + hssAccQueueIds[ICP_HSSACC_HDLC_RX_FREE_Q] = qId; + + + /* + * HDLC Rx queue + */ + qBaseOffset = ICP_HSSACC_HDLC_RX_FREE_QUEUE_SIZE_IN_BYTES; + + pRxQueueHead = &(pReadCounters->hdlcRxCounters.rxHead); + pRxQueueTail = &(pWriteCounters->hdlcRxCounters.rxTail); + + status = + ixQMgrQConfig ("HDLC Rx Q", + &qId, + ICP_HSSACC_HDLC_RX_QUEUE_DEPTH, + ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_WORDS, + IX_QMGR_Q_COUNT_ENTRIES, + IX_QMGR_Q_ALIGN_WORD, + IX_QMGR_DISPATCH_HDLC_RX_HSS, + IX_QMGR_Q_NO_SHADOWING, + (void*)(qBaseOffset + (uint32_t)rxHdlcQsBlockAddr.virt), + pRxQueueHead, + pRxQueueTail); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to configure " + "HDLC Rx queue." + " ixQMgrQConfig() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + hssAccQueueIds[ICP_HSSACC_HDLC_RX_Q] = qId; + status = ixQMgrWatermarkSet (qId, ICP_HSSACC_HDLC_RX_WATERMARK); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to set watermark " + "for HDLC Rx queue." + " ixQMgrWatermarkSet() returned %u\n", + status); + return ICP_STATUS_FAIL; + } + + + /* Register the callback for this Q */ + status = ixQMgrNotificationCallbackSet (qId, + HssAccRxQServiceCallback, + ICP_HSSACC_HDLC_RX_QMGR_CB_ID); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccQueuesConfig - Failed to set " + "Notification callback function for HDLC " + "Rx Q. ixQMgrWatermarkSet() returned %u\n", + status); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueuesConfig\n"); + + return status; +} + + + +/****************************************************************************** + * Abstract: + * Enables Notification on the Receive Queues. order of is critical here + * as it will determine the order of servicing in the Queue Manager Dispatcher. + * + *****************************************************************************/ +icp_status_t +HssAccRxQueuesNotificationEnable(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxQueuesNotificationEnable\n"); + + status = ixQMgrNotificationEnable (hssAccQueueIds[ICP_HSSACC_VOICE_RX_Q], + IX_QMGR_Q_SOURCE_ID_NOT_E); + if (ICP_STATUS_SUCCESS == status) + { + status = ixQMgrNotificationEnable (hssAccQueueIds[ICP_HSSACC_HDLC_RX_Q], + IX_QMGR_Q_SOURCE_ID_NOT_E); + } + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQueuesNotificationEnable - " + "Failed to enable notifications\n"); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxQueuesNotificationEnable\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: + * Configures all the receive queues used by the TDM I/O unit, + * i.e. it converts the virtual base address of the queue into a + * physical address and passes this address down to the TDM I/O unit. + * It also configures the depth of the queue. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccQueueConfigMsgSubmit(uint32_t qBasePhysOffset, + uint32_t qDepth, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stat) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t qSizeByte1, qSizeByte0 = 0; + + ICP_HSSACC_TRACE_4 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueueConfigMsgSubmit - Offset=0x%08X " + "qDepth=0x%04X msg=0x%02X msgResp=0x%02X\n", + (uint32_t)qBasePhysOffset, qDepth, msgId, msgRespId); + + qSizeByte1 = (qDepth&ICP_HSSACC_TDM_IO_UNIT_BYTE2_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET; + + qSizeByte0 = qDepth&ICP_HSSACC_TDM_IO_UNIT_BYTE3_MASK; + + /* Construct the message to configure the queue */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate (msgId, + 0, + qSizeByte1, + qSizeByte0, + qBasePhysOffset, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv(message, + msgRespId, + stat, + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueueConfigMsgSubmit\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * Configures all the base addresses for the Tx Queues. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTxQueuesConfigMsgsSubmit(icp_hssacc_mem_base_addr_t * pTxQBaseAddresses, + icp_hssacc_msg_with_resp_stats_t * stat) +{ + + unsigned channel = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxQueuesConfigMsgsSubmit\n"); + + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccTxQueuesConfigMsgsSubmit - configuring " + "channel %d with Offset=0x%08X\n", + channel, + pTxQBaseAddresses[channel].physOffset); + + /* Construct the message to configure the queue */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG, + channel, + 0, + 0, + pTxQBaseAddresses[channel].physOffset, + &message); + + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG_RESPONSE, + stat, + NULL); + + if (ICP_STATUS_SUCCESS != status) + { + /* Error will reported in calling function */ + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccTxQueuesConfigMsgsSubmit - Failed " + "configuring channel %d\n", + channel); + break; + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxQueuesConfigMsgsSubmit\n"); + + return status; + +} + + +/****************************************************************************** + * Abstract: + * Converts the virtual address of the queue counter into a physical + * address and submits this address to the TDM I/O unit. + * + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccQueueCounterConfigMsgSubmit(uint32_t qCounterPhysOffset, + uint8_t msgId, + uint8_t msgRespId, + icp_hssacc_msg_with_resp_stats_t * stat) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccQueueCounterConfigMsgSubmit - " + "msg 0x%02X offset 0x%08X\n", + msgId, qCounterPhysOffset); + + + /* Construct the message to configure the queue */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate (msgId, + 0, + 0, + 0, + qCounterPhysOffset, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv(message, + msgRespId, + stat, + NULL); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccQueueCounterConfigMsgSubmit\n"); + + return status; +} + +/***************************************************************************** + * Abstract: + * Configures all of the queues used by the TDM I/O unit, i.e. it + * passes the phys address down to the TDM I/O unit. It also configures the + * depth of each queue. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitQueuesConfig (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t qDepth = 0; + + ICP_HSSACC_TRACE_0(ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitQueuesConfig\n"); + + /* + * Configure the address and depth of all of the queues shared between + * the HssAcc I/O library and the TDM I/O unit. + */ + + /* configure Tx queues */ + qDepth = ((ICP_HSSACC_HDLC_TX_QUEUE_DEPTH_POW_2) << + ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) + | (ICP_HSSACC_VOICE_TX_QUEUE_DEPTH_POW_2); + + status = + HssAccQueueConfigMsgSubmit (0, + qDepth, + ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG, + ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG_RESPONSE, + &(hssAccQueuesCfgStats.txQCfg)); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit Tx queue Depths " + "status = %u\n", + status); + } + + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccTxQueuesConfigMsgsSubmit(txQsAddrArray, + &(hssAccQueuesCfgStats.txChanQAddrCfg)); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit Tx queue Base " + "Addresses status = %u\n", + status); + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Configure the base address of the Voice Rx free & Rx queues */ + status = + HssAccQueueConfigMsgSubmit( + rxVoiceQsBlockAddr.physOffset, + ICP_HSSACC_VOICE_RX_QUEUE_DEPTH, + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG, + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG_RESPONSE, + &(hssAccQueuesCfgStats.voiceRxQCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit voice Rx queue base " + "address. status = %u\n", status); + } + } + + /* Configure the base address of the HDLC Rx free & Rx queues */ + if (ICP_STATUS_SUCCESS == status) + { + status = + HssAccQueueConfigMsgSubmit( + rxHdlcQsBlockAddr.physOffset, + ICP_HSSACC_HDLC_RX_QUEUE_DEPTH, + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG, + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG_RESPONSE, + &(hssAccQueuesCfgStats.hdlcRxQCfg)); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HDLC Rx queue base " + "address. status = %u\n", status); + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitQueuesConfig\n"); + return status; +} + + +/***************************************************************************** + * Abstract: + * Submits the base address of each of the queue counters to the TDM I/O + * unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitQueueCountersConfig (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_queue_write_counters_t *pWriteCounters = NULL; + icp_hssacc_queue_reader_counters_t *pReadCounters = NULL; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitQueueCountersConfig\n"); + + /* + * Map the counter struct to the address of the memory allocated for the + * counters. + */ + pWriteCounters = + (icp_hssacc_queue_write_counters_t *)writeCountersBaseAddress.physOffset; + pReadCounters = + (icp_hssacc_queue_reader_counters_t *)readCountersBaseAddress.physOffset; + + /* Configure the address of the TX head counters */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pReadCounters->txTail), + ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG, + ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG_RESPONSE, + &(hssAccQueuesCfgStats.txQTailCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit Tx Tail counter base " + "address. status = %u\n", status); + } + else + { + + /* Configure the address of the TX tail counters */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pWriteCounters->txHead), + ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG, + ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG_RESPONSE, + &(hssAccQueuesCfgStats.txQHeadCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit Tx Head counter base " + "address. status = %u\n", status); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * Configure the address of the Voice Rx Free head counter and the voice + * Rx tail counter. + */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pWriteCounters->voiceRxCounters), + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG, + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG_RESPONSE, + &(hssAccQueuesCfgStats.voiceRxQReaderCfg)); + + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HssAcc Voice Rx Write " + "counters base address. status = %u\n", + status); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * Configure the address of the Voice Rx Free tail counter and the voice + * Rx head counter. + */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pReadCounters->voiceRxCounters), + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG, + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG_RESPONSE, + &(hssAccQueuesCfgStats.voiceRxQWriterCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HssAcc Voice Rx read " + "counters base address. status = %u\n", + status); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * Configure the address of the HDLC Rx Free head counter and the HDLC + * Rx tail counter. + */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pWriteCounters->hdlcRxCounters), + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG, + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG_RESPONSE, + &(hssAccQueuesCfgStats.hdlcRxQReaderCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HssAcc HDLC Rx write " + "counters base address. status = %u\n", + status); + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* + * Configure the address of the HDLC Rx Free tail counter and the HDLC + * Rx head counter. + */ + status = + HssAccQueueCounterConfigMsgSubmit ( + (uint32_t)&(pReadCounters->hdlcRxCounters), + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG, + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG_RESPONSE, + &(hssAccQueuesCfgStats.hdlcRxQWriterCfg)); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("Failed to submit HssAcc HDLC Rx read " + "counters base address. status = %u\n", + status); + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitQueueCountersConfig\n"); + + return status; +} + +/***************************************************************************** + * Abstract: + * Updates the TDM I/O Unit with a new Q depth for a specific Q. + * + *****************************************************************************/ +icp_status_t +HssAccQueueConfigQSizeUpdate(uint32_t channelId, + icp_hssacc_channel_type_t type) +{ + IxQMgrQSize depth = 0; + + if (ICP_HSSACC_CHAN_TYPE_VOICE == type) + { + depth = ICP_HSSACC_VOICE_TX_QUEUE_DEPTH; + } + else + { + depth = ICP_HSSACC_HDLC_TX_QUEUE_DEPTH; + } + return ixQMgrQSizeReconfig (channelId, depth); +} + + +/***************************************************************************** + * Abstract: + * Retrieves the QMgr Q Id for a specific HSS Acc Queue. + * + *****************************************************************************/ +IxQMgrQId +HssAccQueueIdGet (uint32_t qIndexId) +{ + return hssAccQueueIds[qIndexId]; +} + + +/***************************************************************************** + * Abstract: + * Reset the Stats for this module. + * + *****************************************************************************/ +void +HssAccQueuesConfigStatsReset (void) +{ + memset (&hssAccQueuesCfgStats, 0, sizeof(icp_hssacc_queues_config_stats_t)); +} + + + +/***************************************************************************** + * Abstract: + * Displays stats for this module. + * + *****************************************************************************/ +void +HssAccQueuesConfigStatsShow (void) +{ + unsigned channel = 0; + if (TRUE == queuesConfigured) + { + for (channel = 0; channel < ICP_HSSACC_MAX_NUM_CHANNELS; channel++) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Tx Queue %d Base Address Location: 0x%08X\n", + channel, + (uint32_t)txQsAddrArray[channel].virt, + 0, 0, + 0, 0); + } + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Rx Hdlc Queues Base Address Location: 0x%08X\n" + "Rx Voice Queues Base Address Location: 0x%08X\n" + "Queue Read Counter Address Location: 0x%08X\n" + "Queue Write Counter Address Location: 0x%08X\n", + (uint32_t)rxHdlcQsBlockAddr.virt, + (uint32_t)rxVoiceQsBlockAddr.virt, + (uint32_t)readCountersBaseAddress.virt, + (uint32_t)writeCountersBaseAddress.virt, + 0, 0); + + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nQueue Configuration Statistics:\n" + "TX Queue Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.txQCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC RX Queue Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.hdlcRxQCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice RX Queue Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.voiceRxQCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTX Q Head Counters Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.txQHeadCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTX Q Tail Counters Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.txQTailCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice Rx Q Reader Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.voiceRxQReaderCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice Rx Q Writer Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.voiceRxQWriterCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC Rx Q Reader Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.hdlcRxQReaderCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nHDLC Rx Q Writer Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccQueuesCfgStats.hdlcRxQWriterCfg); + } + +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_rx_datapath.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_rx_datapath.c new file mode 100644 index 0000000..94bba23 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_rx_datapath.c @@ -0,0 +1,2014 @@ +/****************************************************************************** + * @file icp_hssacc_rx_datapath.c + * + * @description Contents of this file provide the Receive Datapath + * functionality for the HSS Access component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_rings.h" +#include "icp_hssacc_tdm_io_queue_entry.h" +#include "icp_hssacc_address_translate.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_rx_datapath.h" + +#include "IxQMgr.h" + + +/* Mutex which controls access to receive datapath service functions */ +TDM_PRIVATE IxOsalMutex hssAccRxServiceMutex[ICP_HSSACC_CHAN_TYPE_DELIMITER]; +TDM_PRIVATE +IxOsalMutex hssAccRxFreeQServiceMutex[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +/* Data for the descriptor to mbuf mapping queue */ +TDM_PRIVATE uint32_t +HssAccRxDpDescPtrRingData[ICP_HSSACC_MAX_NUM_CHANNELS] +[ICP_HSSACC_RX_DP_CHAN_DESC_PTR_RING_SZ]; + +TDM_PRIVATE icp_hssacc_dataplane_ring_t +HssAccRxDpDescRing[ICP_HSSACC_MAX_NUM_CHANNELS]; + +/* Data for the descriptor to mbuf mapping queue */ +TDM_PRIVATE uint32_t +HssAccRxDpFreeQRingData[ICP_HSSACC_CHAN_TYPE_DELIMITER] +[ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH]; + +TDM_PRIVATE icp_hssacc_dataplane_ring_t +HssAccRxDpFreeQRing[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE icp_hssacc_rx_callback_t +HssAccRxChannelCallbacks[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_user_context_t +HssAccRxChannelCallbackUserContexts[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE uint32_t +maxRxDatapathFrameSize[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE icp_boolean_t +hssAccRxServiceInitialised = ICP_FALSE; + +TDM_PRIVATE uint32_t +hssAccRxDatapathNumPendPkts[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t +hssAccRxDatapathLastReceiveSuccess[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t +hssAccRxDatapathWatermarkLevelReached[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE int32_t +hssAccRxDatapathNumUserBuffersInRxSystem[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +/* Stats */ +#ifndef NDEBUG +TDM_PRIVATE uint32_t hssAccRxNumPktsAged[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t hssAccRxNumPktsReceived[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t +hssAccRxNumPktsReplenished[ICP_HSSACC_CHAN_TYPE_DELIMITER]; +TDM_PRIVATE uint32_t hssAccRxNumReceiveFailures[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t +hssAccRxNumReplenishFailures[ICP_HSSACC_CHAN_TYPE_DELIMITER]; +#endif + + + +/* + * Initialises the service mutex. + */ +#define ICP_HSSACC_RX_DP_SERVICE_MUTEX_INIT(service) \ + (ixOsalMutexInit(&(hssAccRxServiceMutex[service]))) + +/* + * Locks the service mutex. + */ +#define ICP_HSSACC_RX_DP_SERVICE_MUTEX_LOCK(service) \ + (ixOsalMutexLock(&(hssAccRxServiceMutex[service]),ICP_HSSACC_MUTEX_TIMEOUT)) + +/* + * Unlocks the service mutex. + */ +#define ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(service) \ + (ixOsalMutexUnlock(&(hssAccRxServiceMutex[service]))) + +/* + * Destroys the service mutex. + */ +#define ICP_HSSACC_RX_DP_SERVICE_MUTEX_DESTROY(service) \ + (ixOsalMutexDestroy(&(hssAccRxServiceMutex[service]))) + +/* + * Initialises the rx free q service mutex. + */ +#define ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_INIT(service) \ + (ixOsalMutexInit(&(hssAccRxFreeQServiceMutex[service]))) + +/* + * Locks the rx free q service mutex. + */ +#define ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_LOCK(service) \ + (ixOsalMutexLock(&(hssAccRxFreeQServiceMutex[service]), \ + ICP_HSSACC_MUTEX_TIMEOUT)) + +/* + * Unlocks the rx free q service mutex. + */ +#define ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_UNLOCK(service) \ + (ixOsalMutexUnlock(&(hssAccRxFreeQServiceMutex[service]))) + +/* + * Destroys the rx free q service mutex. + */ +#define ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_DESTROY(service) \ + (ixOsalMutexDestroy(&(hssAccRxFreeQServiceMutex[service]))) + + + + +/****************************************************************************** + * Abstract: + * Return type of channel (voice or HDLC) + * + ******************************************************************************/ +TDM_PRIVATE icp_hssacc_channel_type_t +HssAccChanTypeGet (IxQMgrQId qId) +{ + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChanTypeGet\n"); + + if (qId == HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_Q)) + { + chanType = ICP_HSSACC_CHAN_TYPE_HDLC; + } + else if (qId == HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_Q)) + { + chanType = ICP_HSSACC_CHAN_TYPE_VOICE; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChanTypeGet\n"); + return chanType; +} + +/****************************************************************************** + * Abstract: + * Add hssAcc-supplied buffer to Rx Free Q for use by TDM I/O Unit + * + ******************************************************************************/ +icp_status_t +icp_HssAccRxFreeChecklessReplenish( + icp_hssacc_channel_type_t channelType, + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo + ) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_tdm_io_queue_entry_t qEntry; + icp_hssacc_tdm_io_queue_entry_t *pEntry = &qEntry; + IxQMgrQEntryType entry = 0; + IxQMgrQId qId = 0; + IX_OSAL_MBUF *pBuffer = NULL; + uint32_t buffer_len = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccRxFreeChecklessReplenish\n"); + pBuffer = + (IX_OSAL_MBUF*) ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + + buffer_len = IX_OSAL_MBUF_MLEN(pBuffer); + + /* Set qId based on whether buffer is Voice or HDLC */ + if (channelType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + qId = HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_FREE_Q); + } + else if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + qId = HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_FREE_Q); + } + else + { + status = ICP_STATUS_INVALID_PARAM; + return status; + } + + /* Fill out Rx Free Q Entry */ + ICP_TDM_IO_Q_ENTRY_CHANNEL_ID(pEntry) = 0; + ICP_TDM_IO_Q_ENTRY_STATUS(pEntry) = 0; + + ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_MSB(pEntry) = + ICP_OSAL_MBUF_PKT_LEN_MSB((uint16_t) buffer_len); + + ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_LSB(pEntry) = + ICP_OSAL_MBUF_PKT_LEN_LSB((uint16_t) buffer_len); + + ICP_TDM_IO_Q_ENTRY_DATA(pEntry) = + (void *) HssAccVirtToPhysAddressTranslateAndSwap( + (void *) ICP_OSAL_MBUF_TDM_SECT_DATA(pMBufTdmIo)); + + ICP_TDM_IO_Q_ENTRY_PKT_LEN(pEntry) = 0; + + ICP_TDM_IO_Q_ENTRY_OSAL_MBUF(pEntry) = + (IX_OSAL_MBUF *) HssAccVirtToPhysAddressTranslateAndSwap( + (void *) pMBufTdmIo); + + /* Acquire service mutex */ + if (ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_LOCK(channelType) == IX_SUCCESS) + { + /* Add entry to Rx Free Q */ + status = ixQMgrQWrite(qId, (IxQMgrQEntryType *) pEntry); + /* Check for overflow (only possible error returned by a Q write) */ + if (status == ICP_STATUS_OVERFLOW) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Q overflow writing to Rx Free Q\n", + 0); + } + else + { + if ICP_HSSACC_DATAPLANE_RING_FULL( + HssAccRxDpFreeQRing[channelType]) + { + /* If the internal ring is full, remove the oldest + entry before adding another one */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + HssAccRxDpFreeQRing[channelType], entry); + } + + entry = (IxQMgrQEntryType) + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + + /* Add buffer to internal ring also */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD( + HssAccRxDpFreeQRing[channelType], entry); + } + + if (ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_UNLOCK(channelType) != + IX_SUCCESS) + { + if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Mutex Unlock Error for " + "voice service\n", 0); + } + else + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Mutex Unlock Error for " + "HDLC service\n", 0); + } + status = ICP_STATUS_MUTEX; + } + } + else + { + if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Mutex Lock Error for " + "voice service\n", 0); + } + else + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeChecklessReplenish - " + "Mutex Lock Error for " + "HDLC service\n", 0); + } + + status = ICP_STATUS_MUTEX; + } + +#ifndef NDEBUG + /* Log packet */ + if (status != ICP_STATUS_SUCCESS) + { + hssAccRxNumReplenishFailures[channelType] ++; + } + else + { + hssAccRxNumPktsReplenished[channelType] ++; + } +#endif + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccRxFreeChecklessReplenish\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * Register rx callback and user context + * + ******************************************************************************/ +void +HssAccChannelRxCallbackRegister(uint32_t channelId, + icp_hssacc_rx_callback_t rxCallback, + icp_user_context_t userContext) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelRxCallbackRegister\n"); + + HssAccRxChannelCallbacks[channelId] = rxCallback; + HssAccRxChannelCallbackUserContexts[channelId] = userContext; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelRxCallbackRegister\n"); +} + +/****************************************************************************** + * Abstract: + * Register rx callback and user context + * + ******************************************************************************/ +void +HssAccChannelRxCallbackDeregister(uint32_t channelId) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelRxCallbackDeregister\n"); + + HssAccRxChannelCallbacks[channelId] = NULL; + HssAccRxChannelCallbackUserContexts[channelId] = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelRxCallbackDeregister\n"); +} + +/****************************************************************************** + * Abstract: + * Service Rx Q and call a callback for every entry received + * Process receive Q, calling callbacks for each received buffer. + * Called from the queue processing function. The Q manager callbacks are + * triggered by HssAccRxDatapathService + * + ******************************************************************************/ +void +HssAccRxQServiceCallback (IxQMgrQId qId, + IxQMgrCallbackId cbId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numEntries = 0; + uint32_t k = 0; + uint32_t chId = 0; + IxQMgrQEntryType qEntry = 0; + IxQMgrQEntryType physQEntry = 0; + unsigned callbacksToDo = 0; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo = NULL; + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + unsigned chanCallbackNeeded[ICP_HSSACC_MAX_NUM_CHANNELS]; + + + ICP_HSSACC_DP_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxQServiceCallback for " + "Q %d and CB Id %d\n", + qId, cbId); + + /* Retrieve channel type */ + chanType = HssAccChanTypeGet(qId); + + memset(chanCallbackNeeded,0,ICP_HSSACC_MAX_NUM_CHANNELS*sizeof(unsigned)); + + /* Acquire service mutex */ + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_LOCK(chanType)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Lock Error for service %d\n", + chanType); + return; + } + + /* Get number of entries in q */ + status = ixQMgrQNumEntriesGetWithChecks ( qId, &numEntries); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQService - " + "Error Reading Num Entries " + "from the Queue\n"); + + if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != IX_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Unlock Error for service %d\n", + chanType); + } + + return; + } + + for (k = 0; k < numEntries; k ++) + { + status = ixQMgrQReadWithChecks (qId, &physQEntry); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQServiceCallback - Error" + " Reading from the Queue\n"); + continue; + } + + /* Convert physical address (that TDM I/O Unit uses) to + virtual address (that Access layer uses) */ + qEntry = (IxQMgrQEntryType) + HssAccPhysToVirtAddressSwapAndTranslate(physQEntry); + + ICP_HSSACC_DP_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccRxQServiceCallback - " + "got Phys Entry 0x%08X to Virt 0x%08X\n", + physQEntry, + qEntry); + + /* Convert q Entry to a pointer to TDM I/O-specific + portion of OSAL MBUF */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) qEntry; + /* Retrieve channel Id */ + chId = ICP_OSAL_MBUF_TDM_SECT_CHANNEL_ID(pMBufTdmIo); + + if (ICP_HSSACC_CHANNEL_ENABLED != + HssAccChannelConfigStateQuery(chId)) + { + /* if channel is not enabled put the buffer on the + rx free q and not on the channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish(chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQServiceCallback - " + " Rx Free Replenish failed for channel type %d\n", + chanType); + } + } + else + { + if (!ICP_HSSACC_DATAPLANE_RING_FULL( + HssAccRxDpDescRing[chId])) + { + /* VOICE PACKET AGING: check the channel type and + queue Level. Reject if above level and + previous buffer was accepted onto ring */ + if (ICP_HSSACC_CHAN_TYPE_VOICE == + HssAccChannelConfigTypeQuery(chId)) + { + if(ICP_HSSACC_RX_Q_WATERMARK_LEVEL <= + hssAccRxDatapathNumPendPkts[chId]) + { + hssAccRxDatapathWatermarkLevelReached[chId] + = ICP_TRUE; + } + else if ((ICP_TRUE == + hssAccRxDatapathWatermarkLevelReached[chId]) && + (0 == hssAccRxDatapathNumPendPkts[chId])) + { + hssAccRxDatapathWatermarkLevelReached[chId] + = ICP_FALSE; + } + } + + if ((ICP_TRUE == + hssAccRxDatapathWatermarkLevelReached[chId]) && + (ICP_TRUE == + hssAccRxDatapathLastReceiveSuccess[chId])) + { + /* can only be true for voice */ + ICP_HSSACC_DP_TRACE_1(ICP_HSSACC_DEBUG, + "HssAccRxQServiceCallback - " + "Regulating Rx Flow for channel %d\n", + chId); + /* put the buffer on the rx free q and not on the + channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish( + chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQServiceCallback - Rx Free" + " Replenish failed for channel type %d\n", + chanType); + } + +#ifndef NDEBUG + hssAccRxNumPktsAged[chId]++; +#endif + hssAccRxDatapathLastReceiveSuccess[chId] + = ICP_FALSE; + } + else + { + /* Put q entry in ring associated with + correct channel */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD( + HssAccRxDpDescRing[chId], + qEntry); + hssAccRxDatapathNumPendPkts[chId] ++; + hssAccRxDatapathLastReceiveSuccess[chId] + = ICP_TRUE; + + /* Log which channel requires a callback and + increment the total num of callbacks to do */ + if (NULL != HssAccRxChannelCallbacks[chId]) + { + chanCallbackNeeded[chId] ++; + callbacksToDo ++; + } + } + } + else + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccRxQServiceCallback - Internal Ring" + " overflow on channel %d\n", + chId); + + /* put the buffer on the rx free q and not on the + channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish( + chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQServiceCallback - Rx Free" + " Replenish failed for channel type %d\n", + chanType); + } + + hssAccRxDatapathLastReceiveSuccess[chId] = ICP_FALSE; + continue; + } + } + } + + if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != IX_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQServiceCallback - " + "Mutex Unlock Error for service %d\n", + chanType); + } + else + { + k = 0; + while (callbacksToDo) + { + while (chanCallbackNeeded[k]) + { + ICP_HSSACC_DP_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccRxQServiceCallback - channel %d, " + " %d callbacks left\n", + k, callbacksToDo-1); + + HssAccRxChannelCallbacks[k]( + HssAccRxChannelCallbackUserContexts[k]); + chanCallbackNeeded[k] --; + callbacksToDo --; + } + k ++; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxQServiceCallback\n"); + +} + + +/****************************************************************************** + * Abstract: + * Process receive Q *without* any calling of callbacks. Called + * from icp_HssAccReceive. If nothing in rx Q, returns ICP_FALSE in + * bufferReceived arg + * + *****************************************************************************/ +icp_status_t +HssAccRxQService (IxQMgrQId qId, + unsigned channelId, + icp_boolean_t *bufferReceived) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numEntries = 0; + uint32_t k = 0; + uint32_t chId = 0; + IxQMgrQEntryType qEntry = 0; + IxQMgrQEntryType physQEntry = 0; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo = NULL; + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + + ICP_HSSACC_DP_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxQService for " + "Q %d and channelId %d\n", + qId, channelId); + + *bufferReceived = ICP_FALSE; + + /* Retrieve channel type */ + chanType = HssAccChanTypeGet(qId); + + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_LOCK(chanType)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Lock Error for service %d\n", + chanType); + status = ICP_STATUS_MUTEX; + return status; + } + + /* Get number of entries in q */ + status = ixQMgrQNumEntriesGetWithChecks ( qId, &numEntries); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQService - " + "Error Reading Num Entries " + "from the Queue\n"); + + if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != IX_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Unlock Error for service %d\n", + chanType); + } + + return status; + } + + for (k = 0; k < numEntries; k ++) + { + status = ixQMgrQReadWithChecks (qId, &physQEntry); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxQService - Error" + " Reading from the Queue\n"); + continue; + } + + /* Convert physical address (that TDM I/O Unit uses) to + virtual address (that Access layer uses) */ + qEntry = (IxQMgrQEntryType) + HssAccPhysToVirtAddressSwapAndTranslate(physQEntry); + + ICP_HSSACC_DP_TRACE_2(ICP_HSSACC_DEBUG, + "HssAccRxQService - " + "got Phys Entry 0x%08X to Virt 0x%08X\n", + physQEntry, + qEntry); + + /* Convert q Entry to a pointer to TDM I/O-specific + portion of OSAL MBUF */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) qEntry; + /* Retrieve channel Id */ + chId = ICP_OSAL_MBUF_TDM_SECT_CHANNEL_ID(pMBufTdmIo); + + if (ICP_HSSACC_CHANNEL_ENABLED != + HssAccChannelConfigStateQuery(chId)) + { + /* if channel is not enabled put the buffer on the + rx free q and not on the channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish(chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQService - " + " Rx Free Replenish failed for channel type %d\n", + chanType); + } + } + else + { + if (!ICP_HSSACC_DATAPLANE_RING_FULL( + HssAccRxDpDescRing[chId])) + { + /* VOICE PACKET AGING: check the channel type and + queue Level. Reject if above level and + previous buffer was accepted onto ring */ + if (ICP_HSSACC_CHAN_TYPE_VOICE == + HssAccChannelConfigTypeQuery(chId)) + { + if(ICP_HSSACC_RX_Q_WATERMARK_LEVEL <= + hssAccRxDatapathNumPendPkts[chId]) + { + hssAccRxDatapathWatermarkLevelReached[chId] + = ICP_TRUE; + } + else if ((ICP_TRUE == + hssAccRxDatapathWatermarkLevelReached[chId]) && + (0 == hssAccRxDatapathNumPendPkts[chId])) + { + hssAccRxDatapathWatermarkLevelReached[chId] + = ICP_FALSE; + } + } + + if ((ICP_TRUE == + hssAccRxDatapathWatermarkLevelReached[chId]) && + (ICP_TRUE == + hssAccRxDatapathLastReceiveSuccess[chId])) + { + /* can only be true for voice */ + ICP_HSSACC_DP_TRACE_1(ICP_HSSACC_DEBUG, + "HssAccRxQService - " + "Regulating Rx Flow for channel %d\n", + chId); + /* put the buffer on the rx free q and not on the + channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish( + chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQService - Rx Free" + " Replenish failed for channel type %d\n", + chanType); + } +#ifndef NDEBUG + hssAccRxNumPktsAged[chId]++; +#endif + hssAccRxDatapathLastReceiveSuccess[chId] + = ICP_FALSE; + } + else + { + /* Put q entry in ring associated with + correct channel */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD( + HssAccRxDpDescRing[chId], + qEntry); + hssAccRxDatapathNumPendPkts[chId] ++; + hssAccRxDatapathLastReceiveSuccess[chId] + = ICP_TRUE; + if (channelId == chId) + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccRxQService - A new " + "buffer was pushed into the " + "internal ring on channel %d\n", + chId); + /* flag a buffer has been received */ + *bufferReceived = ICP_TRUE; + } + } + } + else + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccRxQService - Internal Ring" + " overflow on channel %d\n", + chId); + + /* put the buffer on the rx free q and not on the + channel ring */ + if (ICP_STATUS_SUCCESS != + icp_HssAccRxFreeChecklessReplenish( + chanType, + pMBufTdmIo)) + { + ICP_HSSACC_REPORT_ERROR_1( + "HssAccRxQService - Rx Free" + " Replenish failed for channel type %d\n", + chanType); + } + + hssAccRxDatapathLastReceiveSuccess[chId] = ICP_FALSE; + continue; + } + } + } + + if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != IX_SUCCESS) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxQService - " + "Mutex Unlock Error for service %d\n", + chanType); + status = ICP_STATUS_MUTEX; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxQService\n"); + + return status; + +} + + + +/****************************************************************************** + * Abstract: + * Function called from icp_HssAccReceive which + * checks to see if there's anything in channel's internal ring. + * If there is, this is returned immediately, otherwise calls + * HssAccRxQService + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccRxReceive (IxQMgrQId qId, + uint32_t channelId, + IX_OSAL_MBUF ** buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxQMgrQEntryType qEntry; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo; + icp_boolean_t bufferReceived = ICP_TRUE; + icp_hssacc_channel_type_t chanType = HssAccChannelConfigTypeQuery(channelId); + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxReceive\n"); + + /* Return NULL buffer by default */ + *buffer = NULL; + + /* If there's anything available for channel, return it, */ + if (ICP_HSSACC_DATAPLANE_RING_EMPTY(HssAccRxDpDescRing[channelId])) + { + /* otherwise, process queue and repeat check */ + status = HssAccRxQService(qId, channelId, &bufferReceived); + } + else + { + bufferReceived = ICP_TRUE; + } + + if ( (status == ICP_STATUS_SUCCESS) && (bufferReceived == ICP_TRUE) ) + { + + /* There is definitely something in channel's ring now */ + + /* Get an entry */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(HssAccRxDpDescRing[channelId], + qEntry); + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + hssAccRxDatapathNumPendPkts[channelId] --; + + /* Entry is a pointer to TDM I/O Unit-specific portion of + an OSAL buffer, */ + pMBufTdmIo = (icp_hssacc_osal_mbuf_tdm_io_section_t *) qEntry; + + /* look up where start of buffer is */ + *buffer = ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + /* Set the length of received buffer in OSAL buffer fields */ + + IX_OSAL_MBUF_MLEN(*buffer) = + ( (ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_MSB(pMBufTdmIo) << + ICP_OSAL_MBUF_TDM_SECT_LEN_MSB_OFFSET) | + ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_LSB(pMBufTdmIo) ); + IX_OSAL_MBUF_PKT_LEN(*buffer) = IX_OSAL_MBUF_MLEN(*buffer); + + HssAccDataEndiannessSwap(*buffer); + + }/*if ( (status == ICP_STATUS_SUCCESS) && (bufferReceived == ICP_TRUE) )*/ + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxReceive\n"); + + return status; +} + + + +/****************************************************************************** + * Abstract: + * This function receives a buffer. Simply checks channel type + * and calls HssAccRxReceive. Also logs packets. + * + *****************************************************************************/ +icp_status_t +icp_HssAccReceive (uint32_t channelId, IX_OSAL_MBUF ** buffer) +{ + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + icp_status_t status = ICP_STATUS_SUCCESS; + IxQMgrQId qId = IX_QMGR_MAX_NUM_QUEUES; + + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccReceive for channel %d\n", + channelId); + +#ifndef NDEBUG + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccReceive - channelId " + "out of range\n"); + status = ICP_STATUS_INVALID_PARAM; + } +#endif + if (ICP_STATUS_SUCCESS == status) + { + /* Retrieve qId for channel */ + chanType = HssAccChannelConfigTypeQuery(channelId); + if (chanType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + qId = HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_Q); + } + else if (chanType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + qId = HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_Q); + } + else + { + status = ICP_STATUS_INVALID_PARAM; + } + } + if (status == ICP_STATUS_SUCCESS) + { + status = HssAccRxReceive(qId, channelId, buffer); + } + +#ifndef NDEBUG + /* Log packet */ + if ( (status != ICP_STATUS_SUCCESS) || (*buffer == NULL) ) + { + hssAccRxNumReceiveFailures[channelId] ++; + } + else + { + hssAccRxNumPktsReceived[channelId] ++; + } +#endif + + ICP_HSSACC_DP_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccReceive for channel %d " + "with buffer 0x%08X\n", + channelId, + (uint32_t)*buffer); + return status; +} + + +/****************************************************************************** + * Abstract: + * Function to run the Q Mgr processing function and call + * associated callbacks + * + ******************************************************************************/ +icp_status_t +HssAccRxDatapathService(icp_hssacc_channel_type_t channelType) +{ + IxQMgrDispatchGroup group; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathService\n"); + + /* Just call dispatcher loop for Rx Qs */ + if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + group = IX_QMGR_DISPATCH_VOICE_RX_HSS; + ixQMgrDispatcherLoopRun(group); + } + else if (channelType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + group = IX_QMGR_DISPATCH_HDLC_RX_HSS; + ixQMgrDispatcherLoopRun(group); + } + else + { + status = ICP_STATUS_INVALID_PARAM; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathService\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: +* Reset the per-channel statistics +* +******************************************************************************/ +void +HssAccRxDatapathChanStatsReset(uint32_t channelId) +{ +#ifndef NDEBUG + hssAccRxNumPktsReceived[channelId] = 0; + hssAccRxNumReceiveFailures[channelId] = 0; + hssAccRxNumPktsAged[channelId] = 0; +#endif +} + + + + +/****************************************************************************** + * Abstract: + * Print out the per-channel statistics + * + ******************************************************************************/ +void +HssAccRxDatapathChanStatsShow(uint32_t channelId) +{ +#ifndef NDEBUG + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nRx Datapath Statistics for Channel %d\n", + channelId, 0, 0, 0, 0, 0); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\t\t%d Packets Received\n" + "\t\t%d Packet Receive Failures\n" + "\t\t%d Packets Aged\n", + hssAccRxNumPktsReceived[channelId], + hssAccRxNumReceiveFailures[channelId], + hssAccRxNumPktsAged[channelId], 0, 0, 0); + +#else + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Rx Datapath Statistics Not Supported in this Build\n", + 0, 0, 0, 0, 0, 0); +#endif +} + + + +/****************************************************************************** + * Abstract: + * Function to print out stats on replenishing + * + ******************************************************************************/ +void +HssAccRxDatapathReplenishStatsShow(icp_hssacc_channel_type_t serviceType) +{ +#ifndef NDEBUG + if (serviceType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nRx Datapath Replenish Statistics for HDLC service\n", + 0, 0, 0, 0, 0, 0); + } + else + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nRx Datapath Replenish Statistics for voice service\n", + 0, 0, 0, 0, 0, 0); + } + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\t\t%d Packets Replenished\n" + "\t\t%d Packet Replenish Failures\n", + hssAccRxNumPktsReplenished[serviceType], + hssAccRxNumReplenishFailures[serviceType], 0, 0, 0, 0); +#else + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nRx Datapath Service Statistics Not Supported in this Build\n", + 0, 0, 0, 0, 0, 0); +#endif +} + + + + +/****************************************************************************** + * Abstract: + * Function to reset stats on replenishing + * + *****************************************************************************/ +void +HssAccRxDatapathReplenishStatsReset(icp_hssacc_channel_type_t serviceType) +{ +#ifndef NDEBUG + hssAccRxNumPktsReplenished[serviceType] = 0; + hssAccRxNumReplenishFailures[serviceType] = 0; +#endif +} + + + +/****************************************************************************** + * Abstract: + * Reset all globals + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccRxDatapathReset(void) +{ + int k = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathReset\n"); + + for (k = 0; k < ICP_HSSACC_MAX_NUM_CHANNELS; k ++) + { + + HssAccRxDpDescRing[k].content = &HssAccRxDpDescPtrRingData[k][0]; + HssAccRxDpDescRing[k].size = + ICP_HSSACC_RX_DP_CHAN_DESC_PTR_RING_SZ; + HssAccRxDpDescRing[k].mask = + ICP_HSSACC_RX_DP_CHAN_DESC_PTR_RING_SZ - 1; + HssAccRxDpDescRing[k].tail = 0; + HssAccRxDpDescRing[k].head = 0; + HssAccRxChannelCallbacks[k] = NULL; + HssAccRxChannelCallbackUserContexts[k] = 0; + HssAccRxDatapathChanStatsReset(k); + hssAccRxDatapathNumPendPkts[k] = 0; + hssAccRxDatapathLastReceiveSuccess[k] = ICP_FALSE; + hssAccRxDatapathWatermarkLevelReached[k] = ICP_FALSE; + } + + for (k = 0; k < ICP_HSSACC_CHAN_TYPE_DELIMITER; k ++) + { + HssAccRxDpFreeQRing[k].content = &HssAccRxDpFreeQRingData[k][0]; + HssAccRxDpFreeQRing[k].size = ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH; + HssAccRxDpFreeQRing[k].mask = ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH-1; + HssAccRxDpFreeQRing[k].tail = 0; + HssAccRxDpFreeQRing[k].head = 0; + maxRxDatapathFrameSize[k] = 0; +#ifndef NDEBUG + hssAccRxNumPktsReplenished[k] = 0; + hssAccRxNumReplenishFailures[k] = 0; +#endif + hssAccRxDatapathNumUserBuffersInRxSystem[k] = 0; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathReset\n"); + + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Initialise Rx datapath global variables + * + ******************************************************************************/ +icp_status_t +HssAccRxDatapathInit(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t k = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathInit\n"); + /* Check if component has already been initialised */ + if (ICP_TRUE == hssAccRxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccRxDatapathInit - " + "component has already been initialised\n"); + + status = ICP_STATUS_FAIL; + } + else /* component has never been initialised */ + { + + /* Initialise service mutexes */ + for (k = 0; k < ICP_HSSACC_CHAN_TYPE_DELIMITER; k ++) + { + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_INIT(k)) + { + if (k == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathInit - " + "Mutex Initialisation Error " + "for voice service\n", 0); + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathInit - " + "Mutex Initialisation " + "Error for HDLC service\n", 0); + } + status = ICP_STATUS_MUTEX; + } + + if (IX_SUCCESS != ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_INIT(k)) + { + if (k == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathInit - Rx Free " + "Q Mutex Initialisation Error " + "for voice service\n", 0); + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathInit - Rx Free " + "Q Mutex Initialisation " + "Error for HDLC service\n", 0); + } + status = ICP_STATUS_MUTEX; + } + } + + if (status == ICP_STATUS_SUCCESS) + { + status = HssAccRxDatapathReset(); + if (status == ICP_STATUS_SUCCESS) + { + hssAccRxServiceInitialised = ICP_TRUE; + } + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathInit\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Shut down Rx datapath Module. + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathShutdown(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t k = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathShutdown\n"); + + /* Check if component has not been initialised */ + if (ICP_FALSE == hssAccRxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("HssAccRxDatapathShutdown - " + "component has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + else /* component has been initialised */ + { + status = HssAccRxDatapathReset(); + + if (status == ICP_STATUS_SUCCESS) + { + + /* Destroy service mutexes */ + for (k = 0; k < ICP_HSSACC_CHAN_TYPE_DELIMITER; k ++) + { + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_DESTROY(k)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathShutdown - " + "Mutex Destroy Error for " + "service %d\n", + k); + status = ICP_STATUS_MUTEX; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathShutdown\n"); + return status; + } + + if (IX_SUCCESS != ICP_HSSACC_RX_FREEQ_DP_SERVICE_MUTEX_DESTROY(k)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathShutdown - Rx " + "Free Q Mutex Destroy Error for " + "service %d\n", + k); + status = ICP_STATUS_MUTEX; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathShutdown\n"); + return status; + } + } + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccRxServiceInitialised = ICP_FALSE; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathShutdown\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * Add user-supplied buffer to Rx Free Q for use by TDM I/O Unit + * + ******************************************************************************/ +icp_status_t +icp_HssAccRxFreeReplenish ( + icp_hssacc_channel_type_t channelType, + IX_OSAL_MBUF *buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo; + uint32_t buffer_len = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccRxFreeReplenish\n"); + + if (channelType != ICP_HSSACC_CHAN_TYPE_HDLC + && channelType != ICP_HSSACC_CHAN_TYPE_VOICE) + { + status = ICP_STATUS_INVALID_PARAM; + return status; + } + + /* Check that buffer is not NULL */ + if (buffer == NULL) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccRxFreeReplenish - " + "Buffer pointer is NULL\n"); + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccRxFreeReplenish\n"); + status = ICP_STATUS_INVALID_PARAM; + return status; + } + + /* Check that buffer is not chained. We do not support chaining. */ + if ((IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(buffer) != NULL) || + (IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(buffer) != NULL)) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccRxFreeReplenish - " + "Buffer or Packet Chaining not supported " + "for reception\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (IX_OSAL_MBUF_MDATA(buffer) == NULL) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccRxFreeReplenish - " + "Buffer's data pointer cannot be NULL\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + /* Check if buffer length supplied is ok. + All buffers supplied need to accomodate the max frame size possible */ + buffer_len = IX_OSAL_MBUF_MLEN(buffer); + if ( buffer_len < maxRxDatapathFrameSize[channelType]) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccRxFreeReplenish - " + "Buffer is too small. Buffers supplied " + "must all accomodate max frame size\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + if (status == ICP_STATUS_SUCCESS) + { + + /* check chan type and compare num bufs in rx path to size of rx free q */ + if (channelType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + if(ICP_HSSACC_VOICE_RX_QUEUE_DEPTH + <= hssAccRxDatapathNumUserBuffersInRxSystem + [ICP_HSSACC_CHAN_TYPE_VOICE]) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeReplenish - " + "Voice Rx Datapath Max Buffer Limit Reached\n", + 0); + status = ICP_STATUS_OVERFLOW; + } + } + else + { + if(ICP_HSSACC_HDLC_RX_QUEUE_DEPTH + <= hssAccRxDatapathNumUserBuffersInRxSystem + [ICP_HSSACC_CHAN_TYPE_HDLC]) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccRxFreeReplenish - " + "HDLC Rx Datapath Max Buffer Limit Reached\n", + 0); + status = ICP_STATUS_OVERFLOW; + } + } + + if (status == ICP_STATUS_SUCCESS) + { + /* Add buffer to relevant Rx free Q */ + + /* First, copy info from OSAL buffer to TDM I/O + Unit-specific portion */ + /* Get address of TDM I/O Unit-specific portion of OSAL buffer */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) &(buffer->ix_ne); + + /* Copy current buffer data location */ + ICP_OSAL_MBUF_TDM_SECT_DATA(pMBufTdmIo) = + (void *) IX_OSAL_MBUF_MDATA(buffer); + + /* Copy current buffer location */ + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo) = buffer; + + status = icp_HssAccRxFreeChecklessReplenish (channelType, + pMBufTdmIo); + + if ( ICP_STATUS_SUCCESS == status ) + { + hssAccRxDatapathNumUserBuffersInRxSystem[channelType] ++; + } + + } + + } + + return status; +} + + + +/****************************************************************************** + * Abstract: + * Set max frame size for HDLC, must be done at init + * + *****************************************************************************/ +void +HssAccRxDatapathHdlcInit(uint32_t maxRxFrameSize) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathHdlcInit\n"); + maxRxDatapathFrameSize[ICP_HSSACC_CHAN_TYPE_HDLC] = maxRxFrameSize; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathHdlcInit\n"); +} + + + + +/****************************************************************************** + * Abstract: + * Set max frame size for voice, must be done at init + * + *****************************************************************************/ +void +HssAccRxDatapathVoiceInit(uint32_t maxRxFrameSize) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathVoiceInit\n"); + maxRxDatapathFrameSize[ICP_HSSACC_CHAN_TYPE_VOICE] = maxRxFrameSize; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathVoiceInit\n"); +} + + +/****************************************************************************** + * Abstract: + * Return the Max Rx Sample/Frame size configured for the specified Service + * + *****************************************************************************/ +uint32_t +HssAccRxDatapathMaxServiceFrameSizeGet(icp_hssacc_channel_type_t servType) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Called HssAccRxDatapathMaxServiceFrameSizeGet\n"); + return maxRxDatapathFrameSize[servType]; +} + + + + +/****************************************************************************** + * Abstract: + * Checks to see if any channels exist for a specified service other than + * the one being worked on. + * + *****************************************************************************/ +icp_boolean_t +HssAccRxDatapathServAllChansDisabledQuery(icp_hssacc_channel_type_t chanType, + const unsigned channelId) +{ + uint32_t chanId = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering " + "HssAccRxDatapathServAllChansDisabledQuery\n"); + + for (chanId=0; chanId < ICP_HSSACC_MAX_NUM_CHANNELS; chanId ++) + { + if (chanType == HssAccChannelConfigTypeQuery(chanId) ) + { + if ((HssAccChannelConfigStateQuery(chanId) != + ICP_HSSACC_CHANNEL_UNINITIALISED) && + (chanId != channelId)) + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccRxDatapathServAllChansDisabledQuery -" + " Found channel %u\n", + chanId); + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting " + "HssAccRxDatapathServAllChans" + "DisabledQuery\n"); + return ICP_FALSE; + } + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting " + "HssAccRxDatapathServAllChansDisabledQuery\n"); + return ICP_TRUE; +} + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers left in a specific service RxFree queue + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathServiceSpecificRxFreeEmpty(icp_hssacc_channel_type_t chanType, + IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IX_OSAL_MBUF * pCurrentBuffer = NULL; + IxQMgrQId rxfreeqId = IX_QMGR_MAX_NUM_QUEUES; + IxQMgrQId rxqId = IX_QMGR_MAX_NUM_QUEUES; + unsigned numEntries = 0; + IxQMgrQEntryType freeQEntry; + icp_boolean_t bufferReceived = ICP_FALSE; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathServiceSpecificRxFreeEmpty\n"); + + if (chanType == ICP_HSSACC_CHAN_TYPE_HDLC) + { + rxfreeqId = HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_FREE_Q); + rxqId = HssAccQueueIdGet(ICP_HSSACC_HDLC_RX_Q); + } + else if (chanType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + rxfreeqId = HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_FREE_Q); + rxqId = HssAccQueueIdGet(ICP_HSSACC_VOICE_RX_Q); + } + else + { + status = ICP_STATUS_INVALID_PARAM; + return status; + } + + /* the important part here is to drain the rx queue + into the rx free queue */ + if (ICP_STATUS_SUCCESS != + (status = HssAccRxQService(rxqId, + ICP_HSSACC_MAX_NUM_CHANNELS, + &bufferReceived) )) + { + return status; + } + + /* Acquire service mutex */ + if (IX_SUCCESS != ICP_HSSACC_RX_DP_SERVICE_MUTEX_LOCK(chanType)) + { + if (chanType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR( + "HssAccRxDatapathServiceSpecificRxFreeEmpty - " + "Mutex Lock Error for " + "voice service\n"); + } + else + { + ICP_HSSACC_REPORT_ERROR( + "HssAccRxDatapathServiceSpecificRxFreeEmpty - " + "Mutex Lock Error for " + "HDLC service\n"); + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathServiceSpecificRxFreeEmpty\n"); + return ICP_STATUS_MUTEX; + } + + status = ixQMgrQNumEntriesGet (rxfreeqId, + &numEntries); + + /* Chain all Rx free Q Buffers */ + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccRxDatapathServiceSpecificRxFreeEmpty - " + "Create Chain with Rx Free Buffers\n"); + /* First of all read out useless entries in the ring + that mirrors the Rx Free Q */ + while (ICP_HSSACC_DATAPLANE_RING_NUM_ENTRIES_GET( + HssAccRxDpFreeQRing[chanType]) > + numEntries) + { + ICP_HSSACC_DATAPLANE_RING_TAIL_INCR(HssAccRxDpFreeQRing[chanType]); + } + + /* Wind back write pointer to Rx Free Q by number of + entries in Q */ + status = ixQMgrQWriteRollback(rxfreeqId, numEntries); + } + + if (status == ICP_STATUS_SUCCESS) + { + /* add an entry from free Q to start */ + if ((0 != numEntries) && + (!ICP_HSSACC_DATAPLANE_RING_EMPTY(HssAccRxDpFreeQRing[chanType]))) + { + + /* Remove entry from internal ring mirroring + entries in Rx Free Q */ + /* Difference between ring and Q is that ring holds + pointers to buffers, not Rx Free Q entries */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + HssAccRxDpFreeQRing[chanType], freeQEntry); + + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + numEntries --; + *ppStartChainBuffer = (IX_OSAL_MBUF *) freeQEntry; + pCurrentBuffer = *ppStartChainBuffer; + } + while (!ICP_HSSACC_DATAPLANE_RING_EMPTY(HssAccRxDpFreeQRing[chanType])) + { + /* Remove entry from internal ring mirroring + entries in Rx Free Q */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + HssAccRxDpFreeQRing[chanType], + freeQEntry); + if (NULL == pCurrentBuffer) + { + ICP_HSSACC_REPORT_ERROR( + "HssAccRxDatapathServiceSpecificRxFreeEmpty - " + "Corrupted Internal Receive Free ring\n"); + status = ICP_STATUS_FATAL; + break; + } + + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pCurrentBuffer) = + (IX_OSAL_MBUF *) freeQEntry; + pCurrentBuffer = (IX_OSAL_MBUF *) freeQEntry; + } + } + + + *ppEndChainBuffer = pCurrentBuffer; + + + +if (ICP_HSSACC_RX_DP_SERVICE_MUTEX_UNLOCK(chanType) != + IX_SUCCESS) + { + if (chanType == ICP_HSSACC_CHAN_TYPE_VOICE) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathServiceSpecificRxFreeEmpty -" + " Mutex Unlock Error for " + "voice service\n"); + } + else + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathServiceSpecificRxFreeEmpty -" + " Mutex Unlock Error for " + "HDLC service\n"); + } + status = ICP_STATUS_MUTEX; + } + + +ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathServiceSpecificRxFreeEmpty\n"); +return status; +} + + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers left in a specific service RxFree queue + * if this is the last channel + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathRxFreeEmpty(unsigned channelId, + icp_hssacc_channel_type_t chanType, + IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathRxFreeEmpty\n"); + + /* Are all channels disabled for this service? + (except for channelId) */ + if (HssAccRxDatapathServAllChansDisabledQuery(chanType, + channelId) == ICP_TRUE) + { + /* Retrieve rxfree and rx qIds for channel */ + if (chanType != ICP_HSSACC_CHAN_TYPE_HDLC && + chanType != ICP_HSSACC_CHAN_TYPE_VOICE) + { + status = ICP_STATUS_INVALID_PARAM; + } + else + { + status = HssAccRxDatapathServiceSpecificRxFreeEmpty( + chanType, + ppStartChainBuffer, + ppEndChainBuffer); + +/*unit test code uses ixQMgrWrite() directly - bypassing the + internal hssAcc counter*/ + if (ICP_STATUS_SUCCESS == status) + { + if (0 != hssAccRxDatapathNumUserBuffersInRxSystem[chanType]) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccRxDatapathRxFreeEmpty - " + "Tracked number of user buffers in rx system " + "(%d) != 0\n", + hssAccRxDatapathNumUserBuffersInRxSystem[chanType]); + } + } + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathRxFreeEmpty\n"); + + return status; +} + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers in a chain from both Voice and HDLC Rx Free Qs where + * there are no channels enabled for the particular service + * + *****************************************************************************/ +icp_status_t +HssAccRxFreeQsBufsRetrieve(IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t chainStarted = ICP_FALSE; + IX_OSAL_MBUF * pStartChainRxFreeBuffer = NULL; + IX_OSAL_MBUF * pEndChainRxFreeBuffer = NULL; + int k = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxFreeQsBufsRetrieve "); + + for (k = 0; k < ICP_HSSACC_CHAN_TYPE_DELIMITER; k ++) + { + /* ICP_HSSACC_MAX_NUM_CHANNELS is used so the + internal check is on all channels of type k */ + if (HssAccRxDatapathServAllChansDisabledQuery( + k, + ICP_HSSACC_MAX_NUM_CHANNELS) + == ICP_TRUE) + { + pStartChainRxFreeBuffer = NULL; + pEndChainRxFreeBuffer = NULL; + + status = HssAccRxDatapathServiceSpecificRxFreeEmpty( + k, + &pStartChainRxFreeBuffer, + &pEndChainRxFreeBuffer); + + if (ICP_STATUS_SUCCESS == status) + { + if (NULL != pStartChainRxFreeBuffer) + { + if (ICP_TRUE == chainStarted) + { + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(*ppEndChainBuffer) + = pStartChainRxFreeBuffer; + } + else + { + *ppStartChainBuffer = pStartChainRxFreeBuffer; + } + *ppEndChainBuffer = pEndChainRxFreeBuffer; + + chainStarted = ICP_TRUE; + } + } + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxFreeQsBufsRetrieve\n"); + return status; +} + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers in a chain from Rx Ring for a specified channel + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathChanBufsRetrieve(uint32_t channelId, + IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numEntries = 0; + uint32_t entry = 0; + icp_hssacc_osal_mbuf_tdm_io_section_t *pMBufTdmIo = NULL; + IX_OSAL_MBUF * pCurrentBuffer = NULL; + icp_boolean_t chainStarted = ICP_FALSE; + icp_hssacc_channel_type_t chanType = ICP_HSSACC_CHAN_TYPE_DELIMITER; + IX_OSAL_MBUF * pStartChainRxFreeBuffer = NULL; + IX_OSAL_MBUF * pEndChainRxFreeBuffer = NULL; + + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccRxDatapathChanBufsRetrieve " + "for channel %d\n", + channelId); + + /* Process receive Q */ + chanType = HssAccChannelConfigTypeQuery(channelId); + + if (chanType != ICP_HSSACC_CHAN_TYPE_HDLC && + chanType != ICP_HSSACC_CHAN_TYPE_VOICE) + { + status = ICP_STATUS_INVALID_PARAM; + } + + if (status == ICP_STATUS_SUCCESS) + { + numEntries = + ICP_HSSACC_DATAPLANE_RING_NUM_ENTRIES_GET( + HssAccRxDpDescRing[channelId]); + + /* Special case for starting the Chain */ + if (numEntries != 0) + { + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccRxDatapathChanBufsRetrieve - " + "Start retrieving buffers\n"); + numEntries --; + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(HssAccRxDpDescRing[channelId], + entry); + hssAccRxDatapathNumPendPkts[channelId] --; + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + + /* Entry is a pointer to TDM I/O Unit-specific + portion of an OSAL buffer, */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) entry; + /* look up where start of buffer is */ + if (NULL == pMBufTdmIo) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathChanBufsRetrieve - " + "Corrupted Internal Receive ring\n"); + return ICP_STATUS_FATAL; + } + *ppStartChainBuffer = + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + if (NULL == *ppStartChainBuffer) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathChanBufsRetrieve - " + "Corrupted Receive Entry\n"); + return ICP_STATUS_FATAL; + } + + pCurrentBuffer = *ppStartChainBuffer; + *ppEndChainBuffer = pCurrentBuffer; + chainStarted = ICP_TRUE; +#ifndef NDEBUG + hssAccRxNumPktsReceived[channelId] ++; +#endif + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccRxDatapathChanBufsRetrieve - " + "Create Chain with Rx'ed Buffers\n"); + + while (!ICP_HSSACC_DATAPLANE_RING_EMPTY(HssAccRxDpDescRing[channelId])) + { + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(HssAccRxDpDescRing[channelId], + entry); + numEntries --; + hssAccRxDatapathNumPendPkts[channelId] --; + hssAccRxDatapathNumUserBuffersInRxSystem[chanType] --; + + /* Entry is a pointer to TDM I/O-specific portion + of an OSAL buffer, */ + pMBufTdmIo = + (icp_hssacc_osal_mbuf_tdm_io_section_t *) entry; + if (NULL == pMBufTdmIo) + { + ICP_HSSACC_REPORT_ERROR("HssAccRxDatapathChanBufsRetrieve" + " - Corrupted Internal Receive " + "ring\n"); + status = ICP_STATUS_FATAL; + break; + } + /* look up where start of buffer is */ + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pCurrentBuffer) = + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); + + pCurrentBuffer = + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pMBufTdmIo); +#ifndef NDEBUG + hssAccRxNumPktsReceived[channelId] ++; +#endif + } + *ppEndChainBuffer = pCurrentBuffer; + + } + + + if (ICP_STATUS_SUCCESS == status) + { + + /* Second Stage: If no channel left enabled for this service, + return all buffers in rx Free Q */ + /* Check if we started a chain previously or not */ + status = HssAccRxDatapathRxFreeEmpty(channelId, + chanType, + &pStartChainRxFreeBuffer, + &pEndChainRxFreeBuffer); + if (NULL != pStartChainRxFreeBuffer) + { + if (ICP_TRUE == chainStarted) + { + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(*ppEndChainBuffer) = + pStartChainRxFreeBuffer; + } + else + { + *ppStartChainBuffer = pStartChainRxFreeBuffer; + } + *ppEndChainBuffer = pEndChainRxFreeBuffer; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccRxDatapathChanBufsRetrieve\n"); + + return status; +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_service.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_service.c new file mode 100644 index 0000000..71e0fbd --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_service.c @@ -0,0 +1,2579 @@ +/****************************************************************************** + * @file icp_hssacc_service.c + * + * @description Contents of this file provides the implementation of the + * HSS Service functions + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +/* ---------------------------------------------------------------------------- + * Includes + * ---------------------------------------------------------------------------- + */ +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_channel_list.h" +#include "icp_hssacc_voice_bypass.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_tx_datapath.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_rx_datapath.h" + + + +/* + * ---------------------------------------------------------------------------- + * Global variables + * ---------------------------------------------------------------------------- + */ +/* Mutex which controls access to control path functions */ +IxOsalMutex hssAccControlPathMutex; + +/* Flag to test whether the HssAcc component has been initialised or not. */ +TDM_PRIVATE icp_boolean_t serviceInitialised = ICP_FALSE; + +/* Stats */ +typedef struct icp_hssacc_service_stats_s +{ +/* Internal stats for Timer configuraton messaging */ + icp_hssacc_msg_with_resp_stats_t timerStat; + icp_hssacc_msg_with_resp_stats_t intStat; + icp_hssacc_msg_with_resp_stats_t abtAlnRead; + icp_hssacc_msg_with_resp_stats_t fcsMaxRead; + icp_hssacc_msg_with_resp_stats_t chanStatRead; + icp_hssacc_msg_with_resp_stats_t swErrRead; + icp_hssacc_msg_with_resp_stats_t swErrReset; +} icp_hssacc_service_stats_t; + +TDM_PRIVATE icp_hssacc_service_stats_t hssAccServStats; + +/* Data structure containing all registered callbacks + for all channels and ports */ +TDM_PRIVATE icp_hssacc_port_error_callback_t +hssAccPortErrorCb[ICP_HSSACC_MAX_NUM_PORTS][ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE icp_hssacc_error_callback_t +hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + + +TDM_PRIVATE icp_user_context_t +hssAccPortErrorCtxt[ICP_HSSACC_MAX_NUM_PORTS][ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE icp_user_context_t +hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_DELIMITER]; + +TDM_PRIVATE uint32_t +hssAccStaticErrorBitmask = 0; + +TDM_PRIVATE icp_boolean_t voiceIntEnabled = ICP_FALSE; +TDM_PRIVATE icp_boolean_t hdlcIntEnabled = ICP_FALSE; + +/* + * ---------------------------------------------------------------------------- + * Function definitions + * ---------------------------------------------------------------------------- + */ +TDM_PRIVATE icp_status_t +HssAccTdmIOUnitErrorMhCbRegister (IxPiuMhCallback callback); + +void +HssAccTdmIOUnitErrorCallback(IxPiuMhPiuId piuId, IxPiuMhMessage message); + +void +HssAccPortErrorDummyClientCb (icp_user_context_t userContext, + icp_hssacc_port_error_t errorType); + +void +HssAccErrorDummyClientCb (icp_user_context_t userContext, + icp_hssacc_error_t errorType); + +TDM_PRIVATE icp_status_t +HssAccTdmIOErrorStatsShow (void); + +TDM_PRIVATE icp_status_t +HssAccSwErrorStatsShow (void); + +TDM_PRIVATE icp_status_t +HssAccSwErrorStatsReset (void); + +TDM_PRIVATE icp_status_t +HssAccChannelTdmIOErrorStatsShow(unsigned channelId); + +TDM_PRIVATE icp_status_t +HssAccChannelTdmIOErrorStatsReset(unsigned channelId); + +TDM_PRIVATE void +HssAccServiceStatsReset (void); + +TDM_PRIVATE void +HssAccServiceStatsShow (void); + +TDM_PRIVATE icp_status_t +HssAccServiceIntGenUpdate (void); + +/***************************************************************************** + * Abstract: + * Sets up the Dual coprocessor instructions in the TDM I/O Unit + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTdmUnitDualInstSet (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t appDualId = 0; + IxPiuDlAppDualInstruction appDualInstruction; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmUnitDualInstSet\n"); + +#if defined(__ep805xx) + appDualInstruction.copr0 = ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC; + appDualInstruction.inst0 = ICP_HSSACC_TDM_IO_UNIT_CPP_RD_WORD_INST; + appDualInstruction.copr1 = ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC; + appDualInstruction.inst1 = ICP_HSSACC_TDM_IO_UNIT_SDC_WR_HDLC_INST; + status = ixPiuDlAppDualSet ( + IX_PIUDL_PIUID_PIU0, + appDualId, + &appDualInstruction); + if ( ICP_STATUS_SUCCESS != status ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmUnitDualInstSet - " + "Failed to set Application " + "specific dual in TDM I/O Unit\n"); + + return ICP_STATUS_FATAL; + } + + appDualId++; + appDualInstruction.copr0 = ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC; + appDualInstruction.inst0 = ICP_HSSACC_TDM_IO_UNIT_SDC_RD_HDLC_INST; + appDualInstruction.copr1 = ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC; + appDualInstruction.inst1 = ICP_HSSACC_TDM_IO_UNIT_CPP_WR_WORD_INST; + + status = ixPiuDlAppDualSet ( + IX_PIUDL_PIUID_PIU0, + appDualId, + &appDualInstruction); + if ( ICP_STATUS_SUCCESS != status ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmUnitDualInstSet - " + "Failed to set Application " + "specific dual in TDM I/O Unit\n"); + + return ICP_STATUS_FATAL; + } + + + appDualId++; + appDualInstruction.copr0 = ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC; + appDualInstruction.inst0 = ICP_HSSACC_TDM_IO_UNIT_CPP_RD_WORD_INST; + appDualInstruction.copr1 = ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC; + appDualInstruction.inst1 = ICP_HSSACC_TDM_IO_UNIT_SDC_WR_VOICE_INST; + status = ixPiuDlAppDualSet ( + IX_PIUDL_PIUID_PIU0, + appDualId, + &appDualInstruction); + if ( ICP_STATUS_SUCCESS != status ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmUnitDualInstSet - " + "Failed to set Application " + "specific dual in TDM I/O Unit\n"); + + return ICP_STATUS_FATAL; + } + + appDualId++; + appDualInstruction.copr0 = ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC; + appDualInstruction.inst0 = ICP_HSSACC_TDM_IO_UNIT_SDC_RD_VOICE_INST; + appDualInstruction.copr1 = ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC; + appDualInstruction.inst1 = ICP_HSSACC_TDM_IO_UNIT_CPP_WR_WORD_INST; + + status = ixPiuDlAppDualSet ( + IX_PIUDL_PIUID_PIU0, + appDualId, + &appDualInstruction); + if ( ICP_STATUS_SUCCESS != status ) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmUnitDualInstSet - " + "Failed to set Application " + "specific dual in TDM I/O Unit\n"); + + return ICP_STATUS_FATAL; + } + + +#endif + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmUnitDualInstSet\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: + * Initializes the HSS I/O Access library for the HSS TDM I/O Unit. + * This function is responsible for initialising resources for use by + * this component. It should be called before any other HSS Access + * function is called. Default values for configuration items affecting + * all ports will not be set-up; it is up to the client to call the + * relevant port configuration functions before enabling the port. + * + * + *****************************************************************************/ +icp_status_t +icp_HssAccInit(void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned index = 0; + IxPiuMhMessage message; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccInit\n"); + + /* Check if component is already initialised */ + if (ICP_TRUE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "component has already been initialised\n"); + + status = ICP_STATUS_FAIL; + } + else /* component has never been initialised */ + { + /* Initialise the Service Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_INIT()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed to initialise HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + if (status == ICP_STATUS_SUCCESS) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + HssAccServiceStatsReset(); + + if(ICP_STATUS_SUCCESS == status) + { + if( (ICP_STATUS_SUCCESS == HssAccTdmUnitDualInstSet() ) && + (ICP_STATUS_SUCCESS == HssAccPortConfigInit()) && + (ICP_STATUS_SUCCESS == HssAccChannelConfigInit()) && + (ICP_STATUS_SUCCESS == HssAccQueuesInit() ) && + (ICP_STATUS_SUCCESS == HssAccTxDatapathInit()) && + (ICP_STATUS_SUCCESS == HssAccRxDatapathInit()) && + (ICP_STATUS_SUCCESS == HssAccTdmIOUnitErrorMhCbRegister + (HssAccTdmIOUnitErrorCallback) )) + { + HssAccVoiceBypassInit(); + + /* Reset all Error Callbacks for the component, + port Error Callbacks and service Errors callbacks */ + for (index =0; index < ICP_HSSACC_MAX_NUM_PORTS; index ++) + { + hssAccPortErrorCb[index][ICP_HSSACC_CHAN_TYPE_VOICE] = + HssAccPortErrorDummyClientCb; + hssAccPortErrorCtxt[index][ICP_HSSACC_CHAN_TYPE_VOICE] = + (icp_user_context_t)index; + hssAccPortErrorCb[index][ICP_HSSACC_CHAN_TYPE_HDLC] = + HssAccPortErrorDummyClientCb; + hssAccPortErrorCtxt[index][ICP_HSSACC_CHAN_TYPE_HDLC] = + (icp_user_context_t)index; + } + hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_VOICE] = + HssAccErrorDummyClientCb; + hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_HDLC] = + HssAccErrorDummyClientCb; + hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_VOICE] = + (icp_user_context_t)ICP_HSSACC_CHAN_TYPE_VOICE; + hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_HDLC] = + (icp_user_context_t)ICP_HSSACC_CHAN_TYPE_HDLC; + } + else + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - one or more " + "modules failed to initialise\n"); + + status = HssAccPortConfigShutdown(); + status = HssAccChannelConfigShutdown(); + status = HssAccQueuesShutdown(); + status = HssAccTxDatapathShutdown(); + status = HssAccRxDatapathShutdown(); + /* This will deregister the Callback */ + status = HssAccTdmIOUnitErrorMhCbRegister(NULL); + status = ICP_STATUS_FAIL; + } + } + /* Last Step enable notifications with the QMgr + for the Receive Side */ + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_STATUS_SUCCESS == HssAccRxQueuesNotificationEnable()) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccInit - Service has " + "successfully initialised\n"); + hssAccStaticErrorBitmask = 0; + serviceInitialised = ICP_TRUE; + } + else + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed notification enable\n"); + status = HssAccVoiceBypassShutdown(); + status = HssAccPortConfigShutdown(); + status = HssAccChannelConfigShutdown(); + status = HssAccQueuesShutdown(); + status = HssAccTxDatapathShutdown(); + status = HssAccRxDatapathShutdown(); + /* This will deregister the Callback */ + status = HssAccTdmIOUnitErrorMhCbRegister(NULL); + status = ICP_STATUS_FAIL; + } + } + /* Set the Timer interval for the TDM I/O Unit to enable the Unit */ + if (ICP_STATUS_SUCCESS == status) + { + /* Construct the message to configure the queue */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG, + 0, + 0, + 0, + ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_INTERVAL, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + if (ICP_STATUS_SUCCESS == + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG_RESPONSE, + &(hssAccServStats.timerStat), + NULL) ) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccInit - Timer Interval " + "Set\n"); + } + else + { + + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed Timer Interval Set\n"); + status = HssAccVoiceBypassShutdown(); + status = HssAccPortConfigShutdown(); + status = HssAccChannelConfigShutdown(); + status = HssAccQueuesShutdown(); + status = HssAccTxDatapathShutdown(); + status = HssAccRxDatapathShutdown(); + /* This will deregister the Callback */ + status = HssAccTdmIOUnitErrorMhCbRegister(NULL); + status = ICP_STATUS_FAIL; + } + } + + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + } + + + if (status != ICP_STATUS_SUCCESS) + { + /* report the error */ + ICP_HSSACC_REPORT_ERROR ("icp_HssAccInit - " + "failed to initialise HssAcc\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccInit\n"); + + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Initialises the HDLC service specific part of the TDM I/O Unit: + * max frame size and whether to generate interrupts for HDLC data or not + * + *****************************************************************************/ +icp_status_t +icp_HssAccHdlcInit(unsigned maxRxFrameSize, + icp_boolean_t intGenerationEnable) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccHdlcInit\n"); + + /* Check if component is initialised */ + if (ICP_TRUE != serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccHdlcInit - " + "component has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + else + { + if (0 == maxRxFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccHdlcInit - " + "Max Rx Frame Size cannot be 0\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccHdlcInit - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + + else + { + if (ICP_TRUE == intGenerationEnable) + { + hdlcIntEnabled = ICP_TRUE; + status = HssAccServiceIntGenUpdate(); + } + HssAccRxDatapathHdlcInit(maxRxFrameSize); + + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccHdlcInit - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccHdlcInit\n"); + + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Setup the Voice service on the TDM I/O unit. provides is with the + * max receive frame size and whether to generate interrupts for Voice + * traffic or not. + * + *****************************************************************************/ +icp_status_t +icp_HssAccVoiceInit(unsigned maxRxFrameSize, + icp_boolean_t intGenerationEnable) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccVoiceInit\n"); + + /* Check if component is already been initialised */ + if (ICP_TRUE != serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceInit - " + "component has not been initialised\n"); + + status = ICP_STATUS_FAIL; + } + else + { + if (0 == maxRxFrameSize) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceInit - " + "Max Rx Frame Size cannot be 0\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceInit - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + if (ICP_TRUE == intGenerationEnable) + { + voiceIntEnabled = ICP_TRUE; + status = HssAccServiceIntGenUpdate(); + } + HssAccRxDatapathVoiceInit(maxRxFrameSize); + + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceInit - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + } + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccVoiceInit\n"); + + return status; +} + + + + +/****************************************************************************** + * Abstract: Shutdown the HSS I/O Access Library including all its sub-modules + * + *****************************************************************************/ +icp_status_t +icp_HssAccShutdown (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccShutdown\n"); + + /* If the service hasnt already been initialised then + we dont need to do anything */ + if (ICP_FALSE == serviceInitialised ) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccShutdown - " + "the service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccShutdown - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + voiceIntEnabled = ICP_FALSE; + hdlcIntEnabled = ICP_FALSE; + status = HssAccServiceIntGenUpdate(); + /* Shutdown Tx and Rx datapath sub-components + Tx: buffers in the tx queues will be sent before being freed + Rx: buffers in the rx queue will be freed and not sent to the client + */ + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccPortConfigShutdown(); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccChannelConfigShutdown(); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccQueuesShutdown(); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccVoiceBypassShutdown(); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTxDatapathShutdown (); + } + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccRxDatapathShutdown (); + } + if (ICP_STATUS_SUCCESS == status) + { + /* This will deregister the Callback */ + status = HssAccTdmIOUnitErrorMhCbRegister(NULL); + } + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccShutdown - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + /* Destroy HssAcc Mutex */ + if (ICP_STATUS_SUCCESS == status) + { + status = ICP_HSSACC_MUTEX_DESTROY(); + } + serviceInitialised = ICP_FALSE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccShutdown\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: register data callbacks for a channel + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelCallbacksRegister ( + unsigned channelId, + icp_user_context_t userContext, + icp_hssacc_rx_callback_t rxCallback, + icp_hssacc_tx_done_callback_t txDoneCallback) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelCallbacksRegister\n"); + + /* If the service hasnt been initialised, report an error */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelCallbacksRegister - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelCallbacksRegister - " + "Channel Id is not valid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if ((NULL == rxCallback) || + (NULL == txDoneCallback)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelCallbacksRegister - " + "Callback function pointers invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + /* save the callbacks to an internal structure so that + the datapath can use them */ + if (ICP_STATUS_SUCCESS == status) + { + HssAccChannelRxCallbackRegister(channelId, rxCallback, userContext); + HssAccTxDatapathChanTxDoneCallbackRegister(channelId, + txDoneCallback, + userContext); + } + return status; + +} + + + + +/****************************************************************************** + * Abstract: register Error callbacks for a channel + *****************************************************************************/ +icp_status_t +icp_HssAccErrorCallbackRegister (icp_hssacc_channel_type_t channelType, + icp_user_context_t userContext, + icp_hssacc_error_callback_t errorCallback) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccErrorCallbackRegister\n"); + + /* If the service hasnt already been initialised then + we dont need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccErrorCallbackRegister - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if ((NULL == errorCallback) || + (ICP_HSSACC_ENUM_INVALID (channelType, + ICP_HSSACC_CHAN_TYPE_DELIMITER))) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccErrorCallbackRegister - " + "one or more parameters invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccErrorCb[channelType] = errorCallback; + hssAccErrorCtxt[channelType] = userContext; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccErrorCallbackRegister\n"); + return status; +} + + + + + +/****************************************************************************** + * Abstract: + * Service the datapath, Rx and Tx + * + *****************************************************************************/ +icp_status_t +icp_HssAccDataPathService (icp_hssacc_channel_type_t channelType) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccDataPathService\n"); +#ifndef NDEBUG + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccDataPathService - " + "service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_ENUM_INVALID(channelType, ICP_HSSACC_CHAN_TYPE_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccDataPathService - " + "invalid Type to service\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } +#endif + if (ICP_STATUS_SUCCESS == status) + { + /* Service Tx Direction */ + status = HssAccTxDatapathService(channelType); + } + if (ICP_STATUS_SUCCESS == status) + { + /* Service Rx Direction */ + status = HssAccRxDatapathService(channelType); + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccDataPathService\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * Retrive all the buffers in the TDM I/O unit associated with the + * specified channel. will call Rx and Tx sub-modules. If channelId is + * equal to ICP_HSSACC_MAX_NUM_CHANNELS then retrieve buffers from the + * rx free queues for any service which has all unitialized channels. + * + *****************************************************************************/ +icp_status_t +icp_HssAccAllBuffersRetrieve (unsigned channelId, + IX_OSAL_MBUF * * buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + IX_OSAL_MBUF * pEndChainBuffer = NULL; + IX_OSAL_MBUF * pTmpBuffer = NULL; + IX_OSAL_MBUF * pTmpEndChainBuffer = NULL; + icp_hssacc_channel_state_t channelState = ICP_HSSACC_CHANNEL_UNINITIALISED; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccAllBuffersRetrieve\n"); + + if (ICP_TRUE != serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + /* channelId == ICP_HSSACC_MAX_NUM_CHANNELS is allowed */ + if (ICP_HSSACC_MAX_NUM_CHANNELS < channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "Channel Id Invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (NULL == buffer) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "Buffer Pointer Invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + + if (ICP_HSSACC_MAX_NUM_CHANNELS != channelId) + { + /* Check that the channel is not enabled first */ + channelState = HssAccChannelConfigStateQuery(channelId); + + if (ICP_HSSACC_CHANNEL_ENABLED == channelState + || ICP_HSSACC_CHANNEL_DOWN_TRANSITION == channelState) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "Channel is enabled\n"); + status = ICP_STATUS_RESOURCE; + } + } + } + } + + + if (status == ICP_STATUS_SUCCESS) + { + + *buffer = NULL; + + if (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + if (ICP_STATUS_SUCCESS == status) + { + /* Retrieve Tx Datapath Buffers Chain containing all leftover + TxDones and submitted Tx buffers that werent transmitted */ + status = HssAccTxDatapathChannelBuffersRetrieve( + channelId, + buffer, + &pTmpEndChainBuffer); + } + + if (status == ICP_STATUS_SUCCESS) + { + /* Retrieve Rx Datapath Buffer Chain */ + status = HssAccRxDatapathChanBufsRetrieve(channelId, + &pTmpBuffer, + &pEndChainBuffer); + } + } + else + { + /* Retrieve Rx Free Q Buffer Chain(s) */ + status = HssAccRxFreeQsBufsRetrieve(&pTmpBuffer, + &pEndChainBuffer); + } + } + + + if (status == ICP_STATUS_SUCCESS) + { + if (*buffer != NULL) + { + if (pTmpBuffer != NULL) + { + /* Link two chains together */ + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pTmpEndChainBuffer) = + pTmpBuffer; + } + } + else if (pTmpBuffer != NULL) + { + /* Rx datapath or free queue buffers were retrieved so + operation succeeded */ + *buffer = pTmpBuffer; + } + + /* Notify Channel Config of success */ + if (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + HssAccChannelConfigBuffersClearedNotify(channelId); + } + } + + + if (ICP_TRUE == mutexLocked) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccAllBuffersRetrieve - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccAllBuffersRetrieve\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * saves the provided callback for the specified port and service. + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortErrorCallbackRegister ( + unsigned portId, + icp_hssacc_channel_type_t channelType, + icp_user_context_t userContext, + icp_hssacc_port_error_callback_t portErrorCallback) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortErrorCallbackRegister\n"); + + if (ICP_TRUE != serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortErrorCallbackRegister - " + "service is not initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_PORTS <= portId) || + ICP_HSSACC_ENUM_INVALID (channelType, + ICP_HSSACC_CHAN_TYPE_DELIMITER)) + { + ICP_HSSACC_REPORT_ERROR_2 ("icp_HssAccPortErrorCallbackRegister - " + "Invalid parameter portId %u for " + "service %u\n", + portId, + channelType); + status = ICP_STATUS_INVALID_PARAM; + } + + if (NULL == portErrorCallback) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccPortErrorCallbackRegister - " + "Invalid callback provided 0x%08X\n", + (uint32_t)portErrorCallback); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + hssAccPortErrorCb[portId][channelType] = portErrorCallback; + hssAccPortErrorCtxt[portId][channelType] = userContext; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortErrorCallbackRegister\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * display all stats within this Access module and the TDM I/O unit. + * + *****************************************************************************/ +void +icp_HssAccStatsShow (void) +{ + unsigned channelId = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_channel_type_t channelType = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccStatsShow\n"); + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_TRUE == serviceInitialised) + { + HssAccPortConfigStatsShow(); + HssAccQueuesConfigStatsShow(); + HssAccChannelConfigStatsShow(); + HssAccTsAllocStatsShow(); + HssAccBypassStatsShow(); + + while ((ICP_STATUS_SUCCESS == status ) && + (channelId < ICP_HSSACC_MAX_NUM_CHANNELS)) + { + status = icp_HssAccChannelStatsShow(channelId); + channelId ++; + } + while ((ICP_STATUS_SUCCESS == status ) && + (channelType < ICP_HSSACC_CHAN_TYPE_DELIMITER)) + { + HssAccRxDatapathReplenishStatsShow(channelType); + channelType ++; + } + HssAccServiceStatsShow(); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccStatsShow\n"); + +} + + + +/***************************************************************************** + * Abstract: + * Reset all internal stats. + * + *****************************************************************************/ +void +icp_HssAccStatsReset (void) +{ + unsigned channelId = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_channel_type_t channelType = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccStatsReset\n"); + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_TRUE == serviceInitialised) + { + HssAccPortConfigStatsReset(); + HssAccQueuesConfigStatsReset(); + HssAccChannelConfigStatsReset(); + HssAccTsAllocStatsReset(); + HssAccBypassStatsReset(); + + while ((ICP_STATUS_SUCCESS == status ) && + (channelId < ICP_HSSACC_MAX_NUM_CHANNELS)) + { + status = icp_HssAccChannelStatsReset(channelId); + channelId ++; + } + while ((ICP_STATUS_SUCCESS == status ) && + (channelType < ICP_HSSACC_CHAN_TYPE_DELIMITER)) + { + HssAccRxDatapathReplenishStatsReset(channelType); + channelType ++; + } + if (ICP_STATUS_SUCCESS == status) + { + /* Also reset here the Sw Error Stats from the TDM IO Unit */ + status = HssAccSwErrorStatsReset (); + } + HssAccServiceStatsReset(); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccStatsReset\n"); + +} + + + +/***************************************************************************** + * Abstract: + * display all stats relating to the specified channel + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelStatsShow (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelStatsShow\n"); + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsShow - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsShow - " + "channel number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + HssAccChannelConfigStateShow (channelId); + HssAccTxDatapathChanStatsShow(channelId); + HssAccRxDatapathChanStatsShow(channelId); + + + if (ICP_STATUS_SUCCESS != HssAccChannelTdmIOErrorStatsShow(channelId)) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccChannelStatsShow - Error " + "retrieving Stats from TDM I/O Unit\n"); + status = ICP_STATUS_RESOURCE; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelStatsShow\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * reset all the stats relating to the specified channel. + * + *****************************************************************************/ +icp_status_t +icp_HssAccChannelStatsReset (unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccChannelStatsReset\n"); + + /* If the service hasnt already been initialised then we + dont need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsReset - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsReset - " + "channel number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsReset - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + /* Reset the Datapath Stats for this channel */ + HssAccTxDatapathChanStatsReset(channelId); + HssAccRxDatapathChanStatsReset(channelId); + + if (ICP_STATUS_SUCCESS != HssAccChannelTdmIOErrorStatsReset(channelId)) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccChannelStatsShow - Error " + "retrieving Stats from TDM I/O Unit\n"); + status = ICP_STATUS_RESOURCE; + } + + } + if (mutexLocked == ICP_TRUE) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccChannelStatsReset - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccChannelStatsReset\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * show all the stats relating to the specified port, this includes + * all the channels associated to timeslots on this port. + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortStatsShow (unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned channelId = ICP_HSSACC_MAX_NUM_CHANNELS; + icp_hssacc_tdm_io_unit_channel_list_t listId = + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_PRIMARY; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortStatsShow\n"); + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortStatsShow - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortStatsShow - " + "port number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (ICP_STATUS_SUCCESS == status) + { + /* For each port, the channels to be processed are split + into 3 lists for the TDM I/O Unit. + Show the channels in each list */ + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Primary List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsShow(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + } + /* Repeat for the Secondary 0 list */ + if (ICP_STATUS_SUCCESS == status) + { + listId = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_0; + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Secondary 0 List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsShow(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + } + + /* Repeat for the Secondary 1 list */ + if (ICP_STATUS_SUCCESS == status) + { + listId = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_1; + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Secondary 1 List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsShow(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + + /* Also print out here the Sw Error Stats from the TDM IO Unit */ + status = HssAccSwErrorStatsShow (); + } + + if (ICP_STATUS_SUCCESS == status) + { + + /* And overall stats for Abt, Aln, FCS and Max pkt size errors */ + status = HssAccTdmIOErrorStatsShow (); + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortStatsShow\n"); + return status; + +} + + + + +/***************************************************************************** + * Abstract: + * reset all the stats relating to the specified port, this includes + * resting all the stats for channels on this port. + * + *****************************************************************************/ +icp_status_t +icp_HssAccPortStatsReset (unsigned portId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned channelId = ICP_HSSACC_MAX_NUM_CHANNELS; + icp_hssacc_tdm_io_unit_channel_list_t listId = + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_PRIMARY; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccPortStatsReset\n"); + + + /* If the service hasnt already been initialised then we dont + need to do anything */ + if (ICP_FALSE == serviceInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortStatsReset - " + "Service has not been initialised\n"); + status = ICP_STATUS_FAIL; + } + + /* Check Port Number */ + if (portId >= ICP_HSSACC_MAX_NUM_PORTS) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccPortStatsReset - " + "port number is invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* For each port, the channels to be processed are split + into 3 lists for the TDM I/O Unit. + Show the channels in each list */ + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Primary List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsReset(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + } + /* Repeat for the Secondary 0 list */ + if (ICP_STATUS_SUCCESS == status) + { + listId = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_0; + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Secondary 0 List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsReset(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + + } + + /* Repeat for the Secondary 1 list */ + if (ICP_STATUS_SUCCESS == status) + { + listId = ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_1; + channelId = HssAccChannelListLastPortChannelGet (portId, + listId); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Channels on the Secondary 1 List for port %u:\n", + portId, + 0, 0, 0, 0, 0); + while (ICP_HSSACC_MAX_NUM_CHANNELS > channelId) + { + icp_HssAccChannelStatsReset(channelId); + channelId = HssAccChannelListPrevChannelOnListGet(channelId); + } + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccPortStatsReset\n"); + return status; + +} + + + +/***************************************************************************** + * Abstract: + * return the number of channels supported by the TDM I/O unit. + * + *****************************************************************************/ +unsigned +icp_HssAccNumSupportedChannelsGet ( void ) +{ + return ICP_HSSACC_MAX_NUM_CHANNELS; +} + + + + +/***************************************************************************** + * Abstract: + * register the HSS I/O Access callback with the Message Handler. + * + *****************************************************************************/ +icp_status_t +HssAccTdmIOUnitErrorMhCbRegister (IxPiuMhCallback callback) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitErrorMhCbRegister\n"); + if (ICP_STATUS_SUCCESS != + ixPiuMhUnsolicitedCallbackRegister ( + IX_PIUMH_PIUID_PIU0, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_STATUS, + callback)) + { + + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOUnitErrorMhCbRegister - " + "Could not register callback\n"); + status = ICP_STATUS_FAIL; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitErrorMhCbRegister\n"); + + return status; +} + + +/***************************************************************************** + * Abstract: + * this is the callback that the Message Handler will call when it + * receives an error message from the TDM I/O unit. + * + *****************************************************************************/ +void +HssAccTdmIOUnitErrorCallback(IxPiuMhPiuId piuId, IxPiuMhMessage message) +{ + uint32_t localBitmask = 0; + uint32_t portBitmask = 0; + unsigned portId = ICP_HSSACC_MAX_NUM_PORTS; + icp_hssacc_port_error_t portError = ICP_HSSACC_PORT_ERROR_TX_LOS; + uint32_t errorOffset = 0; + icp_hssacc_error_t errorType = ICP_HSSACC_ERROR_DELIMITER; + icp_boolean_t bothServices = ICP_FALSE; + icp_hssacc_channel_type_t service = ICP_HSSACC_CHAN_TYPE_DELIMITER; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOUnitErrorCallback 0x%08X 0x%08X\n", + message.data[0], + message.data[1]); + + + if ((IX_PIUMH_PIUID_PIU0 != piuId) || + ((message.data[0] >> ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET) != + (ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_STATUS))) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOUnitErrorCallback - " + "Invalid parameters\n"); + } + else + { + /* First check if we have any port errors */ + localBitmask = + message.data[0] & ICP_HSSACC_TDM_IO_UNIT_ERR_ALL_PORT_MASK; + if (0 != localBitmask) + { + /* determine which port error triggered this message */ + portId = 0; + while (0 != localBitmask) + { + portBitmask = localBitmask & + ICP_HSSACC_TDM_IO_UNIT_ERR_SGLE_PORT_MASK; + if (0 != portBitmask) + { + while ((portBitmask & 1) != 1) + { + portBitmask >>= 1; + portError ++; + } + ICP_HSSACC_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccTdmIOUnitErrorCallback - " + "Error Reported on port %u\n", + portId); + /* use the client callbacks */ + hssAccPortErrorCb[portId][ICP_HSSACC_CHAN_TYPE_HDLC]( + hssAccPortErrorCtxt[portId][ICP_HSSACC_CHAN_TYPE_HDLC], + portError); + + hssAccPortErrorCb[portId][ICP_HSSACC_CHAN_TYPE_VOICE]( + hssAccPortErrorCtxt[portId][ICP_HSSACC_CHAN_TYPE_VOICE], + portError); + } + localBitmask >>= ICP_HSSACC_TDM_IO_UNIT_NEXT_PORT_SHIFT; + portId ++; + } + } + + + /* now check for a software error triggering this message; + compare the bitmask sent with our static one */ + localBitmask = message.data[1]; + if ((0 != localBitmask) && + (hssAccStaticErrorBitmask != localBitmask)) + { + while ((localBitmask & 1) == (hssAccStaticErrorBitmask & 1)) + { + localBitmask >>= 1; + hssAccStaticErrorBitmask >>= 1; + errorOffset ++; + } + switch (errorOffset) + { + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_MSG_OUT_FIFO_H: + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_MSG_OUT_FIFO_L: + errorType = ICP_HSSACC_ERROR_MESSAGE_FIFO_OVERFLOW; + bothServices = ICP_TRUE; + break; + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_FREE_UNDERF: + errorType = ICP_HSSACC_ERROR_RX_FREE_UNDERFLOW; + service = ICP_HSSACC_CHAN_TYPE_VOICE; + break; + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_FREE_UNDERF: + errorType = ICP_HSSACC_ERROR_RX_FREE_UNDERFLOW; + service = ICP_HSSACC_CHAN_TYPE_HDLC; + break; + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_INT_FIFO_OVERF: + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_Q_OVERF: + errorType = ICP_HSSACC_ERROR_RX_OVERFLOW; + service = ICP_HSSACC_CHAN_TYPE_VOICE; + break; + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_INT_FIFO_OVERF: + case ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_Q_OVERF: + errorType = ICP_HSSACC_ERROR_RX_OVERFLOW; + service = ICP_HSSACC_CHAN_TYPE_HDLC; + break; + default: + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOUnitErrorCallback - " + "Unknown Software Error " + "from TDM I/O Unit\n"); + status = ICP_STATUS_FAIL; + break; + + } + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTdmIOUnitErrorCallback - " + "Firmware Error Reported\n"); + if (ICP_TRUE == bothServices) + { + hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_HDLC]( + hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_HDLC], + errorType); + hssAccErrorCb[ICP_HSSACC_CHAN_TYPE_VOICE]( + hssAccErrorCtxt[ICP_HSSACC_CHAN_TYPE_VOICE], + errorType); + } + else + { + hssAccErrorCb[service](hssAccErrorCtxt[service], + errorType); + } + hssAccStaticErrorBitmask = message.data[1]; + } + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOUnitErrorCallback\n"); +} + + + +/***************************************************************************** + * Abstract: + * this is a dummy callback used in the event of the client never + * registering its own for a port error + * + *****************************************************************************/ +void HssAccPortErrorDummyClientCb (icp_user_context_t userContext, + icp_hssacc_port_error_t errorType) +{ + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccPortErrorDummyClientCb - received " + "notification of Port error %u for service %u\n", + errorType, + (unsigned)userContext); +} + + + +/***************************************************************************** + * Abstract: + * this is a dummy callback used in the event of the client never + * registering its own for a TDM I/O Unit firmware error. + * + *****************************************************************************/ +void HssAccErrorDummyClientCb (icp_user_context_t userContext, + icp_hssacc_error_t errorType) +{ + ICP_HSSACC_TRACE_2 (ICP_HSSACC_DEBUG, + "HssAccErrorDummyClientCb - " + "received notification of error %u for service %u\n", + errorType, + (unsigned)userContext); +} + + + + + + + +/***************************************************************************** + * Abstract: + * display all stats provided by the TDM I/O unit relating to detected + * firmware errors. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccSwErrorStatsShow (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + unsigned statValue = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccSwErrorStatsShow\n"); + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccSwErrorStatsShow - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + if (ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "TDM IO Unit Firmware Error Stats:\n", + 0, 0, 0, 0, 0, 0); + + /* Retrieve each Sw Error Count and print it */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_Q_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive Voice Q Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_Q_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive HDLC Q Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FIFO_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive Voice FIFO Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FIFO_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive HDLC FIFO Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FREE_Q_UNDERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive Voice Free Q Underflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FREE_Q_UNDERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Receive Voice HDLC Free Underflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_LP_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Msg Out FIFO Low Priority Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_HP_OVERFLOW, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Msg Out FIFO High Priority Overflows: %u\n", + statValue, + 0, 0, 0, 0, 0); + + } + + if (ICP_TRUE == mutexLocked) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccSwErrorStatsShow - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccSwErrorStatsShow\n"); + return status; +} + + +/***************************************************************************** + * Abstract: + * reset the firmware error stats in the TDM I/O Unit. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccSwErrorStatsReset (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t resetFlag = 1; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccSwErrorStatsReset\n"); + + /* Retrieve each Sw Error Count and print it */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_Q_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + + if ( ICP_STATUS_SUCCESS == status) + { + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_Q_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FIFO_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FIFO_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FREE_Q_UNDERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FREE_Q_UNDERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_LP_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ, + ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_HP_OVERFLOW, + resetFlag, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE, + &(hssAccServStats.swErrReset), + NULL); + } + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccSwErrorStatsReset\n"); + return status; +} + +/***************************************************************************** + * Abstract: + * display all error stats collected by the TDM I/O unit. + * + *****************************************************************************/ +icp_status_t +HssAccTdmIOErrorStatsShow (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + unsigned statValue = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTdmIOErrorStatsShow\n"); + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOErrorStatsShow - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "TDM IO Unit Global Error Stats:\n", + 0, 0, 0, 0, 0, 0); + + /* Retrieve each hardware error Count and print it */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ, + 0, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ_RESPONSE, + &(hssAccServStats.abtAlnRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Alignment Errors %u, Abort Errors %u\n", + statValue & ICP_HSSACC_TDM_IO_UNIT_SHORT1_MASK, + (statValue & ICP_HSSACC_TDM_IO_UNIT_SHORT0_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET, + 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ, + 0, 0, 0, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ_RESPONSE, + &(hssAccServStats.fcsMaxRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "FCS Errors %u, Max Frame Size Errors %u\n", + statValue & ICP_HSSACC_TDM_IO_UNIT_SHORT1_MASK, + (statValue & ICP_HSSACC_TDM_IO_UNIT_SHORT0_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET, + 0, 0, 0, 0); + } + + if (ICP_TRUE == mutexLocked) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccTdmIOErrorStatsShow - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTdmIOErrorStatsShow\n"); + return status; +} + + + + + +/***************************************************************************** + * Abstract: + * display all error stats collected by the TDM I/O Unit for the specified + * channel. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelTdmIOErrorStatsShow(unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + unsigned statValue = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelTdmIOErrorStatsShow\n"); + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccChannelTdmIOErrorStatsShow - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "TDM IO Unit channel Error Stats for channel %u:\n", + channelId, 0, 0, 0, 0, 0); + + + /* Retrieve Stats from the TDM I/O Unit */ + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_ABT_ALN, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Abort or Alignment: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_FCS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "FCS: %u\n", + statValue, + 0, 0, 0, 0, 0); + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_MAX_SIZE, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Max Size: %u\n", + statValue, + 0, 0, 0, 0, 0); + + +#ifndef NDEBUG + /* Retrieve Packet Rx and Tx stats */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_TX_PKTS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + } + + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Transmitted Packets: %u\n", + statValue, + 0, 0, 0, 0, 0); + + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, 0, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_RX_PKTS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + &statValue); + } + if ( ICP_STATUS_SUCCESS == status) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Received Packets: %u\n", + statValue, + 0, 0, 0, 0, 0); + + +#endif + } + + if (ICP_TRUE == mutexLocked) + { + /* release the HssAcc Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("HssAccChannelTdmIOErrorStatsShow - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelTdmIOErrorStatsShow\n"); + return status; +} + +/***************************************************************************** + * Abstract: + * get the TDM I/O unit to reset all error stats for the specified channel. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccChannelTdmIOErrorStatsReset(unsigned channelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t resetFlag = 1; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelTdmIOErrorStatsReset\n"); + + + + /* Retrieve Stats from the TDM I/O Unit */ + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_ABT_ALN, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_FCS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_MAX_SIZE, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + + } + + if ( ICP_STATUS_SUCCESS == status) + { + +#ifndef NDEBUG + /* Retrieve Packet Rx and Tx stats */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_TX_PKTS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + } + + if ( ICP_STATUS_SUCCESS == status) + { + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_STATS_READ, + channelId, resetFlag, + ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_RX_PKTS, 0, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE, + &(hssAccServStats.chanStatRead), + NULL); + +#endif + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelTdmIOErrorStatsReset\n"); + return status; +} + + + +/***************************************************************************** + * Abstract: + * reset all internal stats for this sub-module only. + * + *****************************************************************************/ +TDM_PRIVATE void +HssAccServiceStatsReset (void) +{ + memset (&hssAccServStats, 0, sizeof(icp_hssacc_service_stats_t)); +} + + + + +/***************************************************************************** + * Abstract: + * display all internal stats for this sub-module. + * + *****************************************************************************/ +TDM_PRIVATE void +HssAccServiceStatsShow (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccServiceStatsShow\n"); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM Service Statistics:\n" + "Service Timer Config Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.timerStat); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nInterrupt Generation Configuration Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.intStat); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nAbort and Alignment Error Stats Read Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.abtAlnRead); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nFCS and Max Size Error Stats Read Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.fcsMaxRead); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Stats Read Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.chanStatRead); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM IO Unit Firmware Error Stats Read Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.swErrRead); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM IO Unit Firmware Error Stats Reset Messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccServStats.swErrReset); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccServiceStatsShow\n"); + +} + + + +/***************************************************************************** + * Abstract: + * Updates the configuration of the int generation on the TDM I/O Unit + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccServiceIntGenUpdate (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint8_t voiceTxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED; + uint8_t voiceRxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED; + uint8_t hdlcTxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED; + uint8_t hdlcRxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED; + IxPiuMhMessage message; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccServiceIntGenUpdate\n"); + + if (ICP_TRUE == voiceIntEnabled) + { + voiceTxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED; + voiceRxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED; + } + + if (ICP_TRUE == hdlcIntEnabled) + { + hdlcTxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED; + hdlcRxEnabled = ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED; + } + + /* Construct the message to configure the interrupt generation */ + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG, + 0, 0, 0, + hdlcTxEnabled, hdlcRxEnabled, + voiceTxEnabled, voiceRxEnabled, + &message); + + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG_RESPONSE, + &(hssAccServStats.intStat), + NULL); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR ("HssAccServiceIntGenUpdate - " + "Failed to update Interrupt Gen " + "Config in TDM I/O Unit\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccServiceIntGenUpdate\n"); + return status; +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_symbols.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_symbols.c new file mode 100644 index 0000000..53e7855 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_symbols.c @@ -0,0 +1,121 @@ +/****************************************************************************** + * @file icp_hssacc_symbols.c + * + * @description Contents of this file provide the list of symbols to be + * exported by this module + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + + +#ifdef __linux + + +#include <linux/module.h> +#include "icp_hssacc.h" + +EXPORT_SYMBOL(icp_HssAccInit); +EXPORT_SYMBOL(icp_HssAccHdlcInit); +EXPORT_SYMBOL(icp_HssAccVoiceInit); +EXPORT_SYMBOL(icp_HssAccShutdown); +EXPORT_SYMBOL(icp_HssAccNumSupportedPortsGet); +EXPORT_SYMBOL(icp_HssAccPortConfig); +EXPORT_SYMBOL(icp_HssAccPortUp); +EXPORT_SYMBOL(icp_HssAccPortDown); +EXPORT_SYMBOL(icp_HssAccNumSupportedChannelsGet); +EXPORT_SYMBOL(icp_HssAccChannelAllocate); +EXPORT_SYMBOL(icp_HssAccChannelConfigure); +EXPORT_SYMBOL(icp_HssAccChannelHdlcServiceConfigure); +EXPORT_SYMBOL(icp_HssAccChannelVoiceServiceConfigure); +EXPORT_SYMBOL(icp_HssAccChannelCallbacksRegister); +EXPORT_SYMBOL(icp_HssAccErrorCallbackRegister); +EXPORT_SYMBOL(icp_HssAccPortErrorCallbackRegister); +EXPORT_SYMBOL(icp_HssAccNumSupportedGCTsGet); +EXPORT_SYMBOL(icp_HssAccNumSupportedVoiceBypassesGet); +EXPORT_SYMBOL(icp_HssAccVoiceBypassGctDownload); +EXPORT_SYMBOL(icp_HssAccVoiceBypassEnable); +EXPORT_SYMBOL(icp_HssAccVoiceBypassDisable); +EXPORT_SYMBOL(icp_HssAccChannelUp); +EXPORT_SYMBOL(icp_HssAccChannelDown); +EXPORT_SYMBOL(icp_HssAccChannelDelete); +EXPORT_SYMBOL(icp_HssAccTransmit); +EXPORT_SYMBOL(icp_HssAccReceive); +EXPORT_SYMBOL(icp_HssAccRxFreeReplenish); +EXPORT_SYMBOL(icp_HssAccTxDoneRetrieve); +EXPORT_SYMBOL(icp_HssAccAllBuffersRetrieve); +EXPORT_SYMBOL(icp_HssAccDataPathService); +EXPORT_SYMBOL(icp_HssAccChannelStatsShow); +EXPORT_SYMBOL(icp_HssAccChannelStatsReset); +EXPORT_SYMBOL(icp_HssAccPortStatsShow); +EXPORT_SYMBOL(icp_HssAccPortStatsReset); +EXPORT_SYMBOL(icp_HssAccStatsShow); +EXPORT_SYMBOL(icp_HssAccStatsReset); + +#include "icp_hssacc_queues_config.h" + +// hacky +EXPORT_SYMBOL(HssAccQueueIdGet); + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_timeslot_allocation.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_timeslot_allocation.c new file mode 100644 index 0000000..80a9d72 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_timeslot_allocation.c @@ -0,0 +1,665 @@ +/****************************************************************************** + * + * @file icp_hssacc_timeslot_allocation.c + * + * @description Content of this file is the implementation of the Timeslot + * allocation and de-allocation functionality used for channel Allocation + * and deletion. This platform specific implementation compliments the + * file icp_hssacc_common_timeslot_allocation.c containing the common + * sections of this module. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#include "IxOsal.h" + +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_timeslot_allocation.h" +#include "icp_hssacc_port_config.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_address_translate.h" + + + +#define ICP_HSSACC_OFFSET_HALF_WD_PER_LINE (16) +#define ICP_HSSACC_CHAN_OFFS_PER_WD (2) + +/* This Macro operates an endianness swap on half-words for + addressing purposes within the TDM I/O Unit channel offset + table */ +#define ICP_HSSACC_CHAN_OFFS_LOC_IN_TBL(chan) ((chan)^1) + +/* Stats */ +typedef struct icp_hssacc_ts_alloc_stats_s +{ + icp_hssacc_msg_with_resp_stats_t hssPortProvTableLoad; + icp_hssacc_msg_with_resp_stats_t chanOffsetTableLoad; + icp_hssacc_msg_with_resp_stats_t chanOffsetTableRead; + icp_hssacc_msg_with_resp_stats_t hssPortProvTableSwap; +} icp_hssacc_ts_alloc_stats_t; + + +TDM_PRIVATE icp_hssacc_ts_alloc_stats_t hssAccTsAllocStats; + +TDM_PRIVATE icp_boolean_t hssAccTsAllocated [ICP_HSSACC_MAX_NUM_PORTS]; + + +/** + * Function Definition: HssAccTsAllocSwapStatsGet + */ +icp_hssacc_msg_with_resp_stats_t * HssAccTsAllocSwapStatsGet(void) +{ + return &(hssAccTsAllocStats.hssPortProvTableSwap); +} + +/** + * Function Definition: HssAccTsAllocOffsetTableReadStatsGet + */ +icp_hssacc_msg_with_resp_stats_t * HssAccTsAllocOffsetTableReadStatsGet(void) +{ + return &(hssAccTsAllocStats.chanOffsetTableRead); +} + +/** + * Function Definition: HssAccTsAllocPlatformInit + */ +icp_status_t HssAccTsAllocPlatformInit (void) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned portIndex = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocPlatformInit\n"); + + for (portIndex = 0; portIndex < ICP_HSSACC_MAX_NUM_PORTS; portIndex ++) + { + hssAccTsAllocated[portIndex] = ICP_FALSE; + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocPlatformInit\n"); + return status; +} + + + +/** + * Function definition: HssAccTsAllocStatsReset + */ +void HssAccTsAllocStatsReset (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocStatsReset\n"); + memset (&hssAccTsAllocStats, + 0, + sizeof(icp_hssacc_ts_alloc_stats_t)); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocStatsReset\n"); +} + + + +#ifdef SW_SWAPPING +/** + * Function definition: HssAccTsAllocTableWordsSwap + * This function assumes that the size provided is a multiple + * of a word size. + */ +TDM_PRIVATE +void HssAccTsAllocTableWordsSwap (uint32_t * tableAddr, + uint32_t sizeInBytes) +{ + unsigned index = 0; + for (;index < (sizeInBytes/ICP_HSSACC_WORD_SIZE); index ++) + { + tableAddr[index] = IX_OSAL_SWAP_BE_SHARED_LONG(tableAddr[index]); + } +} +#endif + + + +/** + * Function definition: HssAccTsAllocOffsetTableLoad + */ + +TDM_PRIVATE icp_status_t +HssAccTsAllocOffsetTableLoad (unsigned portId, + uint32_t offsetTablePhysAddr, + uint8_t messageId, + uint8_t messageRespId, + icp_hssacc_msg_with_resp_stats_t * stats, + icp_boolean_t activeTableLoad) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + uint8_t activeShadow = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocOffsetTableLoad\n"); + + /* Translate Active/Shadow, only used for certain types of message + of no impact on others */ + if ( ICP_TRUE == activeTableLoad ) + { + activeShadow = 1; + } + + /* Create Message for TDM I/O Unit */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate (messageId, + 0, + portId, + activeShadow, + offsetTablePhysAddr, + &message); + /* Send the message */ + status = HssAccComTdmIOUnitMsgSendAndRecv(message, + messageRespId, + stats, + NULL); + + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR("HssAccTsAllocOffsetTableLoad - " + "Failed communication with TDM I/O Unit " + "for Timeslot Allocation\n"); + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocOffsetTableLoad\n"); + + return status; +} + + + + +/** + * Function definition: HssAccTsAllocDummyProvTableCreate + * This will create a table with a single channel enabled + * with all timeslots assigned + */ +void +HssAccTsAllocDummyProvTableCreate (uint32_t * provTable) +{ + unsigned index = 0; + for (index = 0; index < ICP_HSSACC_MAX_TIMESLOTS_PER_PORT; index++) + { + provTable[index] = + (ICP_HSSACC_TDM_IO_UNIT_TS_ENABLE << + ICP_HSSACC_TDM_IO_UNIT_TS_EN_BIT_OFFSET); + } +} + + +/***************************************************************************** + * Abstract: + * Builds a new channel offset table for the TDM I/O unit. Only the offsets + * of channels on the specified HSS port will be affected. + * Also constructs a new Timeslot provisioning table for the specified port. + * When both tables have been built, they are loaded into the TDM I/O unit. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocUpdate(unsigned portId, + const icp_hssacc_channel_config_t * hssChannelData) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + unsigned chanId = 0, hdmaChannelId = 0; + unsigned tableProvOffset[ICP_HSSACC_MAX_NUM_PORTS]; + uint32_t tableOffset = 0; + uint16_t *pTdmIoUnitOffsetTable = NULL; + uint32_t *pHdmaProvTable = NULL; + uint8_t tsIndex, indexOffset = 0; + icp_boolean_t noTsUsed = ICP_TRUE; + uint32_t hdmaProvTablePhysOffset = 0; + uint32_t tdmIoUnitOffsetTablePhysOffset = 0; + + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocUpdate - " + "Configuring timeslots on port %u\n", + portId); + + /* Get the base address of the channel offset tables */ + pTdmIoUnitOffsetTable = + (uint16_t *)HssAccTsAllocTdmIoUnitOffsetTableVirtAddrGet(); + + pHdmaProvTable = + (uint32_t *)HssAccTsAllocHdmaProvTableVirtAddrGet(); + + /* Clear the contents of the TDM I/O Unit channe offset table + and timeslot provisioning table */ + memset (pHdmaProvTable, 0, ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + memset (pTdmIoUnitOffsetTable, 0, ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ); + memset (tableProvOffset, 0, ICP_HSSACC_MAX_NUM_PORTS*sizeof(unsigned)); + /* + * The objective here is to pack the internal TDM I/O Unit memory channel + * usage such that the TDM I/O unit's internal memory doesn't become + * fragmented from adding/removing channels. This allows us to make maximum + * use of the total available memory. + * + * Two tables need to be updated: + * 1) the TDM I/O unit's offset table, which has a 1-to-1 mapping between + * MAX_NUM channels and their location in internal memory. Only + * channels on the specified port will be updated. The offset of each + * channel is relative to the port base address. + * 2) the TDM I/O Unit's timeslot proviosining table, which tracks the + * offsets of all channels active on that port. The channel ID(s) on a + * port differ from that of the TDM I/O unit (since we can't + * have MAX_NUM channels per port). For example, + * channel 5 (from the perspective of the access layer/TDM I/O unit) + * could have a channel ID of 0 on the port where it is active. + * + * Timeslot aggregation is also performed for all channels on the port. + */ + + /* The TDM I/O unit offset table has an entry for MAX_NUM channels */ + for (chanId = 0; chanId < ICP_HSSACC_MAX_NUM_CHANNELS; chanId++) + { + /* + * Only need to update the channels on the specified port, so skip any + * that are active on other ports, or inactive. + * This preserves the offsets for channels on other HSS ports. + */ + if (hssChannelData[chanId].size > 0) + { + /* Update the TDM I/O unit offset table for the active + channel (byte offset required)*/ + pTdmIoUnitOffsetTable[ICP_HSSACC_CHAN_OFFS_LOC_IN_TBL(chanId)] = + tableProvOffset[hssChannelData[chanId].portId]; + + if (hssChannelData[chanId].portId == portId) + { + noTsUsed = ICP_FALSE; + hssAccTsAllocated[portId] = ICP_TRUE; + + /* Calculate the HDMA timeslot index offset */ + indexOffset = hssChannelData[chanId].lineId * + ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + + + /* Enable the timeslots used by this channel */ + for (tsIndex = 0; + tsIndex < ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE; + tsIndex ++) + { + if (hssChannelData[chanId].timeslotMap & BIT_SET(tsIndex)) + { + ICP_HSSACC_TRACE_3 (ICP_HSSACC_DEBUG, + "HssAccTsAllocUpdate - Timeslot" + " %u is used by chan %u " + "on port %u\n", + tsIndex, + chanId, + hssChannelData[chanId].portId); + pHdmaProvTable[indexOffset + tsIndex] = + (ICP_HSSACC_TDM_IO_UNIT_TS_ENABLE << + ICP_HSSACC_TDM_IO_UNIT_TS_EN_BIT_OFFSET) | + (hdmaChannelId << ICP_HSSACC_TDM_IO_UNIT_CHAN_OFFSET); + } + } + + /* + * Must offset by 128 words in order to get to the first channel + * configuration word. + */ + indexOffset = ICP_HSSACC_MAX_TIMESLOTS_PER_PORT; + + /* Update the HDMA offset table */ + pHdmaProvTable[indexOffset + hdmaChannelId] = + tableOffset << ICP_HSSACC_TDM_IO_UNIT_CHAN_OFFSET; + + hdmaChannelId ++; + + /* Update the word offset by the size of the channel */ + tableOffset += hssChannelData[chanId].size; + } + tableProvOffset[hssChannelData[chanId].portId] += + hssChannelData[chanId].size*ICP_HSSACC_WORD_SIZE; + + } + } + + /* if no TS are used for this port, we need to allocate a dummy single + channel with all timeslots assigned to keep the TDM I/O Unit from + generating errors */ + if (noTsUsed) + { + HssAccTsAllocDummyProvTableCreate(pHdmaProvTable); + } +#ifdef SW_SWAPPING + HssAccTsAllocTableWordsSwap(pHdmaProvTable, + ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + + HssAccTsAllocTableWordsSwap((uint32_t*)pTdmIoUnitOffsetTable, + ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ); +#endif + + /* Flush the new tables to memory */ + IX_OSAL_CACHE_FLUSH (pHdmaProvTable, ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + IX_OSAL_CACHE_FLUSH (pTdmIoUnitOffsetTable, + ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ); + + /* Convert virtual addresses to Physical Offsets */ + hdmaProvTablePhysOffset = + HssAccVirtToPhysAddressTranslate(pHdmaProvTable); + tdmIoUnitOffsetTablePhysOffset = + HssAccVirtToPhysAddressTranslate((uint32_t*)pTdmIoUnitOffsetTable); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTsAllocUpdate - Update HDMA" + " provision table\n"); + + + /* Load the new HDMA offset table for this port */ + status = HssAccTsAllocOffsetTableLoad ( + portId, + hdmaProvTablePhysOffset, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD_RESPONSE, + &(hssAccTsAllocStats.hssPortProvTableLoad), + ICP_FALSE); + + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTsAllocUpdate - Update offset" + " table\n"); + + /* Load the new TDM I/O unit offset table */ + status = HssAccTsAllocOffsetTableLoad( + 0, + tdmIoUnitOffsetTablePhysOffset, + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD, + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD_RESPONSE, + &(hssAccTsAllocStats.chanOffsetTableLoad), + ICP_FALSE); + } + + + + if (ICP_STATUS_SUCCESS == status) + { + status = HssAccTsAllocTableSwap (portId); + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocUpdate\n"); + + return status; +} + + + +/** + * Function definition: HssAccTsAllocInitialAllocationUpdate + */ +icp_status_t +HssAccTsAllocInitialAllocationUpdate(unsigned portId) + +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t *pHdmaProvTable = NULL; + uint32_t hdmaProvTablePhysOffset = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocInitialAllocationUpdate\n"); + if (ICP_TRUE != hssAccTsAllocated[portId]) + { + + /* Get the base address of the channel offset tables */ + pHdmaProvTable = + (uint32_t *)HssAccTsAllocHdmaProvTableVirtAddrGet(); + + /* Clear the contents of the HDMA offset table */ + memset (pHdmaProvTable, 0, ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + + + HssAccTsAllocDummyProvTableCreate(pHdmaProvTable); + +#ifdef SW_SWAPPING + HssAccTsAllocTableWordsSwap(pHdmaProvTable, + ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + +#endif + /* Flush the new tables to memory */ + IX_OSAL_CACHE_FLUSH (pHdmaProvTable, + ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ); + + + /* Convert virtual addresses to Physical Offsets */ + hdmaProvTablePhysOffset = + HssAccVirtToPhysAddressTranslate(pHdmaProvTable); + + ICP_HSSACC_TRACE_0(ICP_HSSACC_DEBUG, + "HssAccTsAllocInitialAllocationUpdate - " + "Update Timeslot provisioning table\n"); + + + /* Load the new timeslot Provisioning table for this port */ + status = + HssAccTsAllocOffsetTableLoad ( + portId, + hdmaProvTablePhysOffset, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD, + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD_RESPONSE, + &(hssAccTsAllocStats.hssPortProvTableLoad), + ICP_TRUE); + + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocInitialAllocationUpdate\n"); + return status; +} + + + + + + + +/** + * Function definition: HssAccTsAllocOffsetTableShow + */ +TDM_PRIVATE void +HssAccTsAllocOffsetTableShow (icp_boolean_t readShadowTable) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t offsetTableWord = 0; + uint16_t offsetTableOffset = 0; + unsigned channelCount = 0; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocOffsetTableShow\n"); + + for (offsetTableOffset = 0; + offsetTableOffset < ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ; + offsetTableOffset += ICP_HSSACC_WORD_SIZE) + { + status = HssAccTsAllocOffsetTableWordRead (readShadowTable, + offsetTableOffset, + &offsetTableWord); + if (ICP_STATUS_SUCCESS == status) + { + if (0 == (offsetTableOffset % ICP_HSSACC_OFFSET_HALF_WD_PER_LINE)) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "%u: ", + channelCount, + 0, 0, 0, 0, 0); + } + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "0x%04X 0x%04X ", + (uint16_t)((offsetTableWord & + ICP_HSSACC_TDM_IO_UNIT_SHORT0_MASK) >> + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET), + (uint16_t)(offsetTableWord & + ICP_HSSACC_TDM_IO_UNIT_SHORT1_MASK), + 0, 0, 0, 0); + if ((ICP_HSSACC_OFFSET_HALF_WD_PER_LINE - ICP_HSSACC_WORD_SIZE) == + (offsetTableOffset % ICP_HSSACC_OFFSET_HALF_WD_PER_LINE)) + { + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n", 0, 0, 0, 0, 0, 0); + } + } + else + { + ICP_HSSACC_REPORT_ERROR ("HssAccTsAllocOffsetTableShow - " + "Failed to read " + "Channel Offset Table from TDM I/O Unit\n"); + break; + } + channelCount += ICP_HSSACC_CHAN_OFFS_PER_WD; + } + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n", 0, 0, 0, 0, 0, 0); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocOffsetTableShow\n"); +} + + +/** + * Function definition: HssAccTsAllocChanOffsetActiveTableShow + */ +void HssAccTsAllocChanOffsetActiveTableShow (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocChanOffsetActiveTableShow\n"); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM I/O Unit Channel Offset ACTIVE Table:\n", + 0, 0, 0, 0, 0, 0); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n----------------------------------------------\n", + 0, 0, 0, 0, 0, 0); + HssAccTsAllocOffsetTableShow (ICP_FALSE); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocChanOffsetActiveTableShow\n"); +} + + +/** + * Function definition: HssAccTsAllocChanOffsetShadowTableShow + */ +void HssAccTsAllocChanOffsetShadowTableShow (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocChanOffsetShadowTableShow\n"); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTDM I/O Unit Channel Offset SHADOW Table:\n", + 0, 0, 0, 0, 0, 0); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\n----------------------------------------\n", + 0, 0, 0, 0, 0, 0); + HssAccTsAllocOffsetTableShow (ICP_TRUE); + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocChanOffsetShadowTableShow\n"); +} + + + +/** + * Function definition: HssAccTsAllocStatsShow + */ +void HssAccTsAllocStatsShow (void) +{ + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTsAllocStatsShow\n"); + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nTimeslot Allocation Stats:\n", + 0, 0, 0, 0, 0, 0); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Stats for TDM I/O Unit channel Offset Table Load messages:\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow(hssAccTsAllocStats.chanOffsetTableLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Stats for Timeslot Provisioning Table Load messages:\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow(hssAccTsAllocStats.hssPortProvTableLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Stats for Timeslot Provisioning Table Swap messages:\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow(hssAccTsAllocStats.hssPortProvTableSwap); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "Stats for TDM I/O Unit channel Offset Table Read messages:\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow(hssAccTsAllocStats.chanOffsetTableRead); + + HssAccTsAllocChanOffsetActiveTableShow(); + HssAccTsAllocChanOffsetShadowTableShow(); + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTsAllocStatsShow\n"); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_tx_datapath.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_tx_datapath.c new file mode 100644 index 0000000..3f02636 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_tx_datapath.c @@ -0,0 +1,1023 @@ +/***************************************************************************** + * @file icp_hssacc_tx_datapath.c + * + * @description Contents of this file provide the implementation of the + * transmit functionality for the HSS I/O Access component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#include "IxOsal.h" + + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_address_translate.h" + +#include "icp_hssacc_rings.h" +#include "icp_hssacc_queues_config.h" +#include "icp_hssacc_tx_datapath.h" +#include "icp_hssacc_tdm_io_queue_entry.h" +#include "IxQMgr.h" + + +/* Mutex which controls access to transmit datapath path functions */ +TDM_PRIVATE IxOsalMutex hssAccTxMutex[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_hssacc_tx_done_callback_t +hssAccTxDoneChannelCallbacks[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_user_context_t +hssAccTxDoneUserContext[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE uint32_t +hssAccTxDatapathNumPendPkts[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t +hssAccTxDatapathLastSubmitSuccess[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t hssAccTxServiceInitialised = ICP_FALSE; + + +/* Stats */ +#ifndef NDEBUG +TDM_PRIVATE uint32_t hssAccTxNumPktsSubmissions[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t +hssAccTxNumPktsSuccessSubmissions[ICP_HSSACC_MAX_NUM_CHANNELS]; +TDM_PRIVATE uint32_t hssAccTxNumPktsDone[ICP_HSSACC_MAX_NUM_CHANNELS]; +#endif + + +/* + * Initialises the service mutex. + */ +#define ICP_HSSACC_TX_DP_MUTEX_INIT(channelId) \ + (ixOsalMutexInit(&hssAccTxMutex[channelId])) + +/* + * Locks the service mutex. + */ +#define ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId) \ + (ixOsalMutexLock(&hssAccTxMutex[channelId],ICP_HSSACC_MUTEX_TIMEOUT)) + +/* + * Unlocks the service mutex. + */ +#define ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId) \ + (ixOsalMutexUnlock(&hssAccTxMutex[channelId])) + +/* + * Destroys the service mutex. + */ +#define ICP_HSSACC_TX_DP_MUTEX_DESTROY(channelId) \ + (ixOsalMutexDestroy(&hssAccTxMutex[channelId])) + +/* + * Reset the stats for a channel + */ +#ifndef NDEBUG +#define ICP_HSSACC_TX_DP_CHAN_STATS_RESET(channelId) do { \ + hssAccTxNumPktsSuccessSubmissions[channelId] = 0; \ + hssAccTxNumPktsSubmissions[channelId] = 0; \ + hssAccTxNumPktsDone[channelId] =0; \ + } while(0); +#else +#define ICP_HSSACC_TX_DP_CHAN_STATS_RESET(channelId) do { \ + } while (0); +#endif + + +/* Data for the descriptor to mbuf mapping queue */ +TDM_PRIVATE uint32_t +hssAccDataPlaneTxDescRingData +[ICP_HSSACC_MAX_NUM_CHANNELS][ICP_HSSACC_TX_QUEUE_DEPTH]; + + +TDM_PRIVATE icp_hssacc_dataplane_ring_t +hssAccDataPlaneTxDescRing[ICP_HSSACC_MAX_NUM_CHANNELS]; + +TDM_PRIVATE icp_boolean_t hssAccDataPlaneTxBypass[ICP_HSSACC_MAX_NUM_CHANNELS]; + + +/***************************************************************************** + * Abstract: + * Resets the Tx Datapath internal data. + * + *****************************************************************************/ +TDM_PRIVATE icp_status_t +HssAccTxDatapathReset(void); + + + + +icp_status_t +HssAccTxDatapathInit(void) +{ + uint32_t index = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathInit\n"); + if (ICP_TRUE == hssAccTxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathInit - Tx Datapath sub-component" + " already initialised\n"); + status = ICP_STATUS_RESOURCE; + } + + if (ICP_STATUS_SUCCESS == status) + { + /* We support 1 client only per channel, to protect against corruption + we need 1 mutex per channel */ + for (index = 0; + index < ICP_HSSACC_MAX_NUM_CHANNELS; + index ++) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_INIT(index)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathInit - Mutex " + "Init Error for channel %d\n", + index); + status = ICP_STATUS_MUTEX; + break; + } + } + status = HssAccTxDatapathReset(); + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccTxServiceInitialised = ICP_TRUE; + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathInit\n"); + return status; +} + + +void +HssAccTxDatapathChanStatsReset(uint32_t channelId) +{ + if (ICP_STATUS_SUCCESS == ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_TX_DP_CHAN_STATS_RESET(channelId); + + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanStatsReset - " + "Mutex Unlock Error for channel %d\n", + channelId); + } + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanStatsReset - " + "Mutex Lock Error for channel %d\n", + channelId); + } +} + + +void +HssAccTxDatapathChanStatsShow(uint32_t channelId) +{ +#ifndef NDEBUG + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Tx Datapath Statistics\n", + 0, 0, 0, 0, 0, 0); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\t\t%d Packets Submitted\n" + "\t\t%d Packets Successfully Submitted\n" + "\t\t%d Packets Done and Recycled to Client\n", + hssAccTxNumPktsSubmissions[channelId], + hssAccTxNumPktsSuccessSubmissions[channelId], + hssAccTxNumPktsDone[channelId], 0, 0, 0); +#else + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nChannel Tx Datapath Statistics Not Supported in this Build\n", + 0, 0, 0, 0, 0, 0); +#endif +} + + +icp_status_t +HssAccTxDatapathShutdown(void) +{ + uint32_t index = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathShutdown\n"); + if (ICP_TRUE == hssAccTxServiceInitialised) + { + status = HssAccTxDatapathReset(); + if (ICP_STATUS_SUCCESS == status) + { + for (index = 0; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_DESTROY(index)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathShutdown - Mutex " + "Destroy Error for channel %d\n", + index); + status = ICP_STATUS_MUTEX; + break; + } + } + } + if (ICP_STATUS_SUCCESS == status) + { + hssAccTxServiceInitialised = ICP_FALSE; + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathShutdown\n"); + return status; +} + + +TDM_PRIVATE icp_status_t +HssAccTxDatapathReset(void) +{ + uint32_t index = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathReset\n"); + for (index = 0; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + if (ICP_STATUS_SUCCESS == ICP_HSSACC_TX_DP_MUTEX_LOCK(index)) + { + hssAccDataPlaneTxDescRing[index].content = + hssAccDataPlaneTxDescRingData[index]; + hssAccDataPlaneTxDescRing[index].size = ICP_HSSACC_TX_QUEUE_DEPTH; + hssAccDataPlaneTxDescRing[index].mask = + ICP_HSSACC_TX_QUEUE_DEPTH - 1; + + hssAccDataPlaneTxDescRing[index].tail = 0; + hssAccDataPlaneTxDescRing[index].head = 0; + hssAccDataPlaneTxBypass[index] = ICP_FALSE; + hssAccTxDatapathNumPendPkts[index] = 0; + hssAccTxDatapathLastSubmitSuccess[index] = ICP_FALSE; + ICP_HSSACC_TX_DP_CHAN_STATS_RESET(index); + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(index)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathReset - " + "Mutex Unlock Error for channel %d\n", + index); + status = ICP_STATUS_MUTEX; + break; + } + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathReset - " + "Mutex Lock Error for channel %d\n", + index); + status = ICP_STATUS_MUTEX; + break; + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathReset\n"); + return status; +} + + +icp_status_t +HssAccTxDatapathChanTypeUpdate (uint32_t channelId, + icp_hssacc_channel_type_t chanType) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathChanTypeUpdate\n"); + if (ICP_STATUS_SUCCESS == ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + if (ICP_HSSACC_CHAN_TYPE_HDLC == chanType) + { + hssAccDataPlaneTxDescRing[channelId].size = + ICP_HSSACC_HDLC_TX_QUEUE_DEPTH; + hssAccDataPlaneTxDescRing[channelId].mask = + ICP_HSSACC_HDLC_TX_QUEUE_DEPTH - 1; + } + else + { + hssAccDataPlaneTxDescRing[channelId].size = + ICP_HSSACC_VOICE_TX_QUEUE_DEPTH; + hssAccDataPlaneTxDescRing[channelId].mask = + ICP_HSSACC_VOICE_TX_QUEUE_DEPTH - 1; + } + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanTypeUpdate - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + else + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanTypeUpdate - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathChanTypeUpdate\n"); + return status; +} + +TDM_PRIVATE icp_status_t +HssAccTxDatapathBufferValidityCheck(const IX_OSAL_MBUF * buffer, + icp_hssacc_channel_type_t channelType) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathBufferValidityCheck\n"); + + if ((NULL != IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(buffer)) || + (NULL != IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(buffer))) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathBufferValidityCheck - " + "Buffer and Packet Chaining not supported " + "for Transmission\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if ( IX_OSAL_MBUF_PKT_LEN(buffer) != IX_OSAL_MBUF_MLEN(buffer)) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathBufferValidityCheck - " + "Buffer length and Packet Length in OS " + "Abstraction Layer Buffer must be equal\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (0 == IX_OSAL_MBUF_PKT_LEN(buffer)) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathBufferValidityCheck - " + "Buffer length cannot be 0\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (NULL == IX_OSAL_MBUF_MDATA(buffer)) + { + ICP_HSSACC_REPORT_ERROR("HssAccTxDatapathBufferValidityCheck - " + "Pointer to data cannot be NULL\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (ICP_HSSACC_CHAN_TYPE_VOICE == channelType) + { + /* voice buffers - check if length is not + modulo 4 (using bit comparison) */ + if (0 != (IX_OSAL_MBUF_PKT_LEN(buffer) & + (uint32_t) ICP_HSSACC_TX_VOICE_PACKET_LENGTH_CHECK_MASK)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathBufferValidityCheck - " + "Voice buffer length must be divisible " + "by 4 - buffer provided has " + "length %d\n", + IX_OSAL_MBUF_PKT_LEN(buffer)); + status = ICP_STATUS_INVALID_PARAM; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathBufferValidityCheck\n"); + return status; +} + + +TDM_PRIVATE void +HssAccTxDatapathBufferTdmSectionUpdate(uint32_t channelId, + IX_OSAL_MBUF * buffer) +{ + icp_hssacc_osal_mbuf_tdm_io_section_t * pBufferTdmSection = + (icp_hssacc_osal_mbuf_tdm_io_section_t*)&(buffer->ix_ne); + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathBufferTdmSectionUpdate\n"); + + /* Using the data in the normal section of the OSAL Buffer, + we fill the TDM I/O private section of the buffer */ + ICP_OSAL_MBUF_TDM_SECT_CHANNEL_ID(pBufferTdmSection) = channelId; + ICP_OSAL_MBUF_TDM_SECT_STATUS(pBufferTdmSection) = 0; + + ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_MSB(pBufferTdmSection) = + ICP_OSAL_MBUF_PKT_LEN_MSB(IX_OSAL_MBUF_PKT_LEN(buffer)); + + ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_LSB(pBufferTdmSection) = + ICP_OSAL_MBUF_PKT_LEN_LSB(IX_OSAL_MBUF_PKT_LEN(buffer)); + + ICP_OSAL_MBUF_TDM_SECT_DATA(pBufferTdmSection) = IX_OSAL_MBUF_MDATA(buffer); + ICP_OSAL_MBUF_TDM_SECT_PKT_LEN(pBufferTdmSection) = 0; + + ICP_OSAL_MBUF_TDM_SECT_NEXT_BUF(pBufferTdmSection) = NULL; + ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(pBufferTdmSection) = buffer; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathBufferTdmSectionUpdate\n"); +} + + + +/* This function requires the OSAL buffer to have been filled + with the correct data in the TDM I/O specific section */ +TDM_PRIVATE void +HssAccTxDatapathQueueEntryCreate(IX_OSAL_MBUF * buffer, + icp_hssacc_tdm_io_queue_entry_t * qEntry) +{ + /* initialise this pointer to the start of the TDM I/O Private section + of the OSAL buffer passed as a parameter */ + icp_hssacc_osal_mbuf_tdm_io_section_t * pBufferTdmSection = + (icp_hssacc_osal_mbuf_tdm_io_section_t*)&(buffer->ix_ne); + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathQueueEntryCreate\n"); + /* Create the first word of the Q Entry using the first word of the TDM I/O + Section of the buffer passed */ + qEntry->descriptor.word = + pBufferTdmSection->tdm_io_entry.descriptor.word; + + /* Endianness Swap done by translation function */ + ICP_TDM_IO_Q_ENTRY_DATA(qEntry) = + (void*)HssAccVirtToPhysAddressTranslateAndSwap( + ICP_OSAL_MBUF_TDM_SECT_DATA(pBufferTdmSection)); + + /* This field is not used for Tx */ + ICP_TDM_IO_Q_ENTRY_PKT_LEN(qEntry) = 0; + + ICP_TDM_IO_Q_ENTRY_OSAL_MBUF(qEntry) = + (IX_OSAL_MBUF*)HssAccVirtToPhysAddressTranslateAndSwap(buffer); + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathQueueEntryCreate\n"); +} + +icp_status_t +icp_HssAccTransmit (uint32_t channelId, + IX_OSAL_MBUF *buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + icp_hssacc_tdm_io_queue_entry_t qEntry; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccTransmit\n"); + +#ifndef NDEBUG + if (ICP_TRUE != hssAccTxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTransmit - Service not initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTransmit - invalid ChannelId\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else + { + hssAccTxNumPktsSubmissions[channelId] ++; + } + if (NULL == buffer) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTransmit - Invalid Buffer\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + +#endif + + + if (ICP_STATUS_SUCCESS == status) + { + /* Check the Buffer validity */ + status = + HssAccTxDatapathBufferValidityCheck(buffer, + HssAccChannelConfigTypeQuery( + channelId)); + } + if (ICP_STATUS_SUCCESS == status) + { + /* Lock the Datapath on Transmit */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTransmit - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + if (ICP_TRUE == hssAccDataPlaneTxBypass[channelId]) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTransmit - " + "Tx not allowed, Channel %d is bypassed\n", + channelId); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check the Channel Type and Queue Level. reject if above level and + previous submission was accepted */ + if ((ICP_HSSACC_CHAN_TYPE_VOICE == + HssAccChannelConfigTypeQuery(channelId)) && + (ICP_HSSACC_TX_Q_WATERMARK_LEVEL <= + hssAccTxDatapathNumPendPkts[channelId]) && + (ICP_TRUE == hssAccTxDatapathLastSubmitSuccess[channelId])) + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "icp_HssAccTransmit - " + "Regulating Tx Flow for channel %d\n", + channelId); + status = ICP_STATUS_OVERFLOW; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + HssAccDataEndiannessSwap(buffer); + HssAccTxDatapathBufferTdmSectionUpdate(channelId, + buffer); + /* Create the Queue Entry for the Q */ + HssAccTxDatapathQueueEntryCreate(buffer, + &qEntry); + /* Submit the Entry to the Queue */ + status = ixQMgrQWrite (HssAccQueueIdGet(channelId), + (IxQMgrQEntryType *)&qEntry); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Push the Buffer Ptr onto the Ring */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD(hssAccDataPlaneTxDescRing[channelId], + buffer); + hssAccTxDatapathNumPendPkts[channelId] ++; + hssAccTxDatapathLastSubmitSuccess[channelId] = ICP_TRUE; +#ifndef NDEBUG + hssAccTxNumPktsSuccessSubmissions[channelId] ++; +#endif + } + else + { + hssAccTxDatapathLastSubmitSuccess[channelId] = ICP_FALSE; + } + + /* Unlock the datapath */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTransmit - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccTransmit\n"); + return status; +} + + + +icp_status_t +icp_HssAccTxDoneRetrieve (uint32_t channelId, + IX_OSAL_MBUF **buffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t entry = 0; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccTxDoneRetrieve\n"); +#ifndef NDEBUG + if (ICP_TRUE != hssAccTxServiceInitialised) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTxDoneRetrieve - " + "Service not initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_HSSACC_MAX_NUM_CHANNELS <= channelId) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTxDoneRetrieve - " + "invalid ChannelId\n"); + status = ICP_STATUS_INVALID_PARAM; + } + if (NULL == buffer) + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccTxDoneRetrieve - " + "Invalid Buffer\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } +#endif + + if (ICP_STATUS_SUCCESS == status) + { + /* Lock the datapath for this Q */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTxDoneRetrieve - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + /* The Shadow counter allows us to keep track of the number of + transmissions completed by the TDM I/O Unit: real Tail - shadow Tail = + number of transmits completed by unit since last servicing. here we are + retrieving the oldest completed transmission so increment the shadow + counter by 1 */ + status = ixQMgrShadowAdvance(HssAccQueueIdGet(channelId), + IX_QMGR_Q_SHADOW_TAIL_ONLY, + 1); + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Get the Buffer Ptr from the Ring */ + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(hssAccDataPlaneTxDescRing[channelId], + entry); + *buffer = (IX_OSAL_MBUF*)entry; + hssAccTxDatapathNumPendPkts[channelId] --; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + + /* Unlock datapath */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccTxDoneRetrieve - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccTxDoneRetrieve\n"); + return status; +} + + + +icp_status_t +HssAccTxDatapathChanBypassStateSet(uint32_t channelId, + icp_boolean_t bypassed) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathChanBypassedSet\n"); + /* Lock the Tx Datapath Mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChanBypassSet - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + else + { + hssAccDataPlaneTxBypass[channelId] = bypassed; + + /* Unlock the mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDapapathChanBypassedSet - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathChanBypassedSet\n"); + return status; +} + + +void +HssAccTxDatapathChanTxDoneCallbackRegister( + uint32_t channelId, + icp_hssacc_tx_done_callback_t txDoneCallback, + icp_user_context_t userContext) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathChanTxDoneCallbackRegister\n"); + hssAccTxDoneChannelCallbacks[channelId] = txDoneCallback; + hssAccTxDoneUserContext[channelId] = userContext; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathChanTxDoneCallbackRegister\n"); +} + +/****************************************************************************** + * Abstract: + * Register rx callback and user context + * + ******************************************************************************/ +void +HssAccTxDatapathChanTxDoneCallbackDeregister(uint32_t channelId) +{ + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccChannelRxCallbackDeregister\n"); + + hssAccTxDoneChannelCallbacks[channelId] = NULL; + hssAccTxDoneUserContext[channelId] = 0; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccChannelRxCallbackDeregister\n"); +} + + + +/* Service all channels of the specified channel Type: find any completed + transmissions by the TDM I/O Unit and report them to the client */ +icp_status_t +HssAccTxDatapathService(icp_hssacc_channel_type_t channelType) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t index = 0; + uint32_t numEntries = 0; + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathService\n"); + + /* cycle through the channels for this service */ + for (; index < ICP_HSSACC_MAX_NUM_CHANNELS; index ++) + { + numEntries = 0; + /* check if servicing is required on TxDone and use the callback + if this is the case */ + if (channelType == HssAccChannelConfigTypeQuery(index)) + { + if (ICP_HSSACC_CHANNEL_ENABLED != + HssAccChannelConfigStateQuery(index)) + { + /* This channel has been configured for this service but it is + not enabled, Datapath functionality is not enabled yet */ + continue; + } + status = ixQMgrShadowDeltaGet(HssAccQueueIdGet(index), + IX_QMGR_Q_SHADOW_TAIL_ONLY, + &numEntries); + } + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccTxDatapathService - " + "Couldnt determine Queue level for " + "channel %d\n", + index); + break; + } + if (0 < numEntries) + { + if (NULL != hssAccTxDoneChannelCallbacks[index]) + { + hssAccTxDoneChannelCallbacks[index]( + hssAccTxDoneUserContext[index]); + } + else + { + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathService - " + "Channel %d has no TxDone callback\n", + index); + } + ICP_HSSACC_DP_TRACE_1 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathService - Channel %d Serviced\n", + index); + } + } + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathService\n"); + + return status; +} + + + +/* Retrieve all buffers left over on the specified channel, + channel must be disabled */ +icp_status_t +HssAccTxDatapathChannelBuffersRetrieve(uint32_t channelId, + IX_OSAL_MBUF * * startChainBuffer, + IX_OSAL_MBUF * * endChainBuffer) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t numEntries = 0; + uint32_t entry = 0; + IX_OSAL_MBUF * pCurrentBuffer = NULL; + icp_boolean_t mutexLocked = ICP_FALSE; + icp_boolean_t chainStarted = ICP_FALSE; + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccTxDatapathChannelBuffersRetrieve\n"); + + /* Lock the datapath for this Q */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_LOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChannelBuffersRetrieve - " + "Mutex Lock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Recycle Tx Done Buffers\n"); + + mutexLocked = ICP_TRUE; + status = ixQMgrShadowDeltaGet(HssAccQueueIdGet(channelId), + IX_QMGR_Q_SHADOW_TAIL_ONLY, + &numEntries); + + if ((ICP_STATUS_SUCCESS == status) && + (0 != numEntries)) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Update the QMgr for TxDone\n"); + status = ixQMgrShadowAdvance(HssAccQueueIdGet(channelId), + IX_QMGR_Q_SHADOW_TAIL_ONLY, + numEntries); + + if (ICP_STATUS_SUCCESS == status) + { + numEntries --; + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + hssAccDataPlaneTxDescRing[channelId], + entry); + + *startChainBuffer = (IX_OSAL_MBUF*)entry; + pCurrentBuffer = (IX_OSAL_MBUF*)entry; + chainStarted = ICP_TRUE; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + } + } + + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Create Chain with Tx Done Buffers\n"); + + for (; numEntries > 0; numEntries --) + { + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + hssAccDataPlaneTxDescRing[channelId], + entry); + + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pCurrentBuffer) = + (IX_OSAL_MBUF*)entry; + pCurrentBuffer = (IX_OSAL_MBUF*)entry; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Recycle Tx Pending Buffers\n"); + + status = ixQMgrQNumEntriesGet(HssAccQueueIdGet(channelId), + &numEntries); + } + if ((ICP_STATUS_SUCCESS == status) && + (0 != numEntries)) + { + /* Update Queue Head counter */ + status = ixQMgrQWriteRollback(HssAccQueueIdGet(channelId), + numEntries); + + } + if (ICP_STATUS_SUCCESS == status) + { + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_DEBUG, + "HssAccTxDatapathChannelBuffersRetrieve - " + "Append Chain with Tx Buffers\n"); + if ((ICP_FALSE == chainStarted) && + (0 != numEntries)) + { + numEntries --; + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + hssAccDataPlaneTxDescRing[channelId], + entry); + + *startChainBuffer = (IX_OSAL_MBUF*)entry; + pCurrentBuffer = (IX_OSAL_MBUF*)entry; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + for (; numEntries > 0; numEntries --) + { + ICP_HSSACC_DATAPLANE_RING_ENTRY_REM( + hssAccDataPlaneTxDescRing[channelId], + entry); + + IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(pCurrentBuffer) = + (IX_OSAL_MBUF*)entry; + pCurrentBuffer = (IX_OSAL_MBUF*)entry; +#ifndef NDEBUG + hssAccTxNumPktsDone[channelId] ++; +#endif + } + + *endChainBuffer = pCurrentBuffer; + hssAccTxDatapathNumPendPkts[channelId] = 0; + } + + /* Unlock datapath */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_TX_DP_MUTEX_UNLOCK(channelId)) + { + ICP_HSSACC_REPORT_ERROR_1("HssAccTxDatapathChannelBuffersRetrieve - " + "Mutex Unlock Error for channel %d\n", + channelId); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_DP_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccTxDatapathChannelBuffersRetrieve\n"); + return status; +} + + diff --git a/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_voice_bypass.c b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_voice_bypass.c new file mode 100644 index 0000000..591b00b --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/icp_hssacc_voice_bypass.c @@ -0,0 +1,776 @@ +/****************************************************************************** + * @file icp_hssacc_timeslot_switching.c + * + * @description Contents of this file provide the implementation of all + * Timeslot switching functionality as described the icp_hssacc.h header file + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#include "IxOsal.h" + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_trace.h" +#include "icp_hssacc_common.h" +#include "icp_hssacc_channel_config.h" +#include "icp_hssacc_voice_bypass.h" +#include "icp_hssacc_address_translate.h" +#include "icp_hssacc_tx_datapath.h" + + + +/* Stats */ +typedef struct icp_hssacc_bypass_stats_s +{ + icp_hssacc_msg_with_resp_stats_t gctLoad; + icp_hssacc_msg_with_resp_stats_t gainCfg; + icp_hssacc_msg_with_resp_stats_t bypassEnable; + icp_hssacc_msg_with_resp_stats_t bypassDisable; +} icp_hssacc_bypass_stats_t; + + + +/* Internal GCT info */ +typedef struct icp_hssacc_gct_internal_data_s +{ + icp_boolean_t configured; + unsigned numBypassUsing; +} icp_hssacc_gct_internal_data_t; + + + +/* Internal Timeslot switch info */ +typedef struct icp_hssacc_bypass_internal_data_s +{ + icp_boolean_t enabled; + unsigned srcChannelId; + unsigned destChannelId; + unsigned portId; + unsigned gctId; +} icp_hssacc_bypass_internal_data_t; + +TDM_PRIVATE icp_hssacc_gct_internal_data_t +hssAccGctData[ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS]; + +TDM_PRIVATE icp_hssacc_bypass_internal_data_t +hssAccBypassData[ICP_HSSACC_MAX_NUM_VOICE_BYPASSES]; + +TDM_PRIVATE icp_boolean_t channelSwitchModuleInitialised = ICP_FALSE; + +TDM_PRIVATE icp_hssacc_bypass_stats_t hssAccBypassStats; + + + +/****************************************************************************** + * Abstract: + * Initialise the Voice bypass module + * + *****************************************************************************/ +void +HssAccVoiceBypassInit(void) +{ + unsigned index = 0; + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccVoiceBypassInit\n"); + if (ICP_TRUE == channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR("HssAccVoiceBypassInit - module already " + "initialised\n"); + } + else + { + + for (;index < ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; index ++) + { + hssAccGctData[index].configured = ICP_FALSE; + hssAccGctData[index].numBypassUsing = 0; + } + + for (index = 0; index < ICP_HSSACC_MAX_NUM_VOICE_BYPASSES; index ++) + { + hssAccBypassData[index].enabled = ICP_FALSE; + hssAccBypassData[index].srcChannelId = ICP_HSSACC_MAX_NUM_CHANNELS; + hssAccBypassData[index].destChannelId = ICP_HSSACC_MAX_NUM_CHANNELS; + hssAccBypassData[index].portId = ICP_HSSACC_MAX_NUM_PORTS; + hssAccBypassData[index].gctId = ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; + } + + HssAccBypassStatsReset(); + + channelSwitchModuleInitialised = ICP_TRUE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccVoiceBypassInit\n"); + +} + + +/****************************************************************************** + * Abstract: + * Shutdown the Voice Bypass module. + * + *****************************************************************************/ +icp_status_t +HssAccVoiceBypassShutdown(void) +{ + unsigned index = 0; + icp_status_t status = ICP_STATUS_SUCCESS; + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering HssAccVoiceBypassShutdown\n"); + if (ICP_TRUE != channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR("HssAccVoiceBypassShutdown - module has not " + "already been initialised\n"); + status = ICP_STATUS_FAIL; + } + + for (index = 0; index < ICP_HSSACC_MAX_NUM_VOICE_BYPASSES; index ++) + { + if (ICP_TRUE == hssAccBypassData[index].enabled) + { + ICP_HSSACC_REPORT_ERROR_1 ("HssAccVoiceBypassShutdown - " + "Bypass %u is still enabled, can't" + " shutdown\n", + index); + status = ICP_STATUS_RESOURCE; + } + } + if (ICP_STATUS_SUCCESS == status) + { + for (index = 0;index < ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; index ++) + { + hssAccGctData[index].configured = ICP_FALSE; + hssAccGctData[index].numBypassUsing = 0; + } + channelSwitchModuleInitialised = ICP_FALSE; + } + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting HssAccVoiceBypassShutdown\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: + * Returns the number of supported Gain Control Tables. + * + *****************************************************************************/ +unsigned +icp_HssAccNumSupportedGCTsGet ( void ) +{ + return ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; +} + + +/****************************************************************************** + * Abstract: + * returns the number of Voice bypasses supported + * + *****************************************************************************/ +unsigned +icp_HssAccNumSupportedVoiceBypassesGet ( void ) +{ + return ICP_HSSACC_MAX_NUM_VOICE_BYPASSES; +} + +/****************************************************************************** + * Abstract: + * Download the provided Gain Control Table to the TDM I/O Unit. + * + *****************************************************************************/ +icp_status_t +icp_HssAccVoiceBypassGctDownload (unsigned voiceBypassGct, + uint8_t *gainCtrlTable) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + uint32_t physAddr = 0; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccVoiceBypassGctDownload " + "for Table %u\n", + voiceBypassGct); + + if (ICP_FALSE == channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((voiceBypassGct >= ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS)|| + (NULL == gainCtrlTable)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "invalid parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + else if (0 != + ((uint32_t)gainCtrlTable & ICP_HSSACC_DBLE_WD_ALIGN_MASK)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "invalid alignment for GCT memory " + "location\n"); + status = ICP_STATUS_INVALID_PARAM; + } + + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "failed to lock HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + else + { + mutexLocked = ICP_TRUE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Check if this Gain Control table has already been configured + and if it is already in use for a bypass, we only allow configuration + of the GCT if it is not in use by any bypass */ + if (0 != hssAccGctData[voiceBypassGct].numBypassUsing) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "GCT is currently in use by 1 " + "or more bypasses\n"); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Send Configuration to TDM I/O Unit and save it in + Access for Stats purposes */ + + + /* Convert the table base address to a physical address */ + physAddr = + HssAccVirtToPhysAddressTranslate(gainCtrlTable); + + /* Construct the message to load the table */ + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD, + 0, + 0, + voiceBypassGct, + physAddr, + &message); + /* Send the message to the TDM I/O Unit and wait for its reply */ + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD_RESPONSE, + &(hssAccBypassStats.gctLoad), + NULL); + + if (ICP_STATUS_SUCCESS == status) + { + hssAccGctData[voiceBypassGct].configured = ICP_TRUE; + } + else + { + ICP_HSSACC_REPORT_ERROR("icp_HssAccVoiceBypassGctDownload - " + "failed to set Table in TDM I/O Unit\n"); + } + + } + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassGctDownload - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccVoiceBypassGctDownload\n"); + return status; +} + + + + + +/****************************************************************************** + * Abstract: + * Enable the specified Voice bypass between the specified source and + * destination channels. + * + *****************************************************************************/ +icp_status_t +icp_HssAccVoiceBypassEnable (unsigned portId, + unsigned voiceBypassId, + unsigned voiceBypassGct, + unsigned srcChannelId, + unsigned destChannelId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + unsigned index = 0; + ICP_HSSACC_TRACE_2 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccVoiceBypassEnable for Table %u " + "on bypass %u\n", + voiceBypassGct, + voiceBypassId); + + if (ICP_FALSE == channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if ((portId >= ICP_HSSACC_MAX_NUM_PORTS) || + (voiceBypassId >= ICP_HSSACC_MAX_NUM_VOICE_BYPASSES) || + (voiceBypassGct >= ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - invalid " + "Bypass configuration parameter\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + if ((ICP_HSSACC_MAX_NUM_CHANNELS <= srcChannelId) || + (ICP_HSSACC_MAX_NUM_CHANNELS <= destChannelId)) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - Channels " + "selected for bypass are invalid\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + + if (ICP_TRUE == hssAccBypassData[voiceBypassId].enabled) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccVoiceBypassEnable - Selected " + "bypass (%u) is already enabled; it must " + "be disabled first before " + "reconfiguring\n", + voiceBypassId); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if (ICP_TRUE != hssAccGctData[voiceBypassGct].configured) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccVoiceBypassEnable - Selected " + "Gain Control Table (%u) is not " + "configured, need to configure it first\n", + voiceBypassGct); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + for (index = 0; index < ICP_HSSACC_MAX_NUM_VOICE_BYPASSES; index ++) + { + if ((hssAccBypassData[index].srcChannelId == srcChannelId) || + (hssAccBypassData[index].destChannelId == destChannelId)) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccVoiceBypassEnable - " + "One of the channels selected is " + "already used in a identical role " + "for bypass %u\n", + index); + status = ICP_STATUS_RESOURCE; + break; + } + } + } + + if (ICP_STATUS_SUCCESS == status) + { + if ( (ICP_FALSE == HssAccChannelConfigValidBypass(srcChannelId,portId)) || + (ICP_FALSE == HssAccChannelConfigValidBypass(destChannelId,portId))) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - Channel(s) " + "selected for bypass is(are) not " + "appropriate (Narrowband Enabled Channels " + "only on same port)\n"); + status = ICP_STATUS_RESOURCE; + } + } + + + if (ICP_STATUS_SUCCESS == status) + { + /* Link the Bypass to the Gain Control Table */ + + HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG, + portId, + voiceBypassId, + voiceBypassGct, + 0, + &message); + + + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG_RESPONSE, + &(hssAccBypassStats.gainCfg), + NULL); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_2("icp_HssAccVoiceBypassEnable - " + "Failed to link GCT %u with Voice " + "Bypass %u on the TDM I/O Unit\n", + voiceBypassGct, + voiceBypassId); + } + + + + if (ICP_STATUS_SUCCESS == status) + { + /* Configure the Bypass*/ + + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE, + portId, + voiceBypassId, + srcChannelId, + destChannelId, + 0, 0, 0, + &message); + + + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE_RESPONSE, + &(hssAccBypassStats.bypassEnable), + NULL); + + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccVoiceBypassEnable - " + "Failed to enable Voice " + "Bypass %u on the TDM I/O Unit\n", + voiceBypassId); + } + + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Save bypass config and send new channel state to tx */ + hssAccBypassData[voiceBypassId].enabled = ICP_TRUE; + hssAccBypassData[voiceBypassId].portId = portId; + hssAccBypassData[voiceBypassId].srcChannelId = srcChannelId; + hssAccBypassData[voiceBypassId].destChannelId = destChannelId; + hssAccBypassData[voiceBypassId].gctId = voiceBypassGct; + hssAccGctData[voiceBypassGct].numBypassUsing ++; + + /* Notify the Tx Datapath and config modules that this channel is + bypassed */ + HssAccTxDatapathChanBypassStateSet(destChannelId, + ICP_TRUE); + HssAccChannelBypassPairSet(srcChannelId, destChannelId); + } + } + + + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassEnable - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccVoiceBypassEnable\n"); + return status; +} + + + + +/****************************************************************************** + * Abstract: + * disable the specified Voice bypass. + * + *****************************************************************************/ +icp_status_t +icp_HssAccVoiceBypassDisable (unsigned voiceBypassId) +{ + icp_status_t status = ICP_STATUS_SUCCESS; + IxPiuMhMessage message; + icp_boolean_t mutexLocked = ICP_FALSE; + unsigned gctId = ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; + ICP_HSSACC_TRACE_1 (ICP_HSSACC_FN_ENTRY_EXIT, + "Entering icp_HssAccVoiceBypassDisable for Bypass %u\n", + voiceBypassId); + + if (ICP_FALSE == channelSwitchModuleInitialised) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassDisable - " + "Service is not Initialised\n"); + status = ICP_STATUS_FAIL; + } + + if (ICP_STATUS_SUCCESS == status) + { + if (voiceBypassId >= ICP_HSSACC_MAX_NUM_VOICE_BYPASSES) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassDisable - invalid " + "Bypass ID\n"); + status = ICP_STATUS_INVALID_PARAM; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Grab the HssAcc mutex */ + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_LOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassDisable - " + "failed to lock HssAcc Mutex\n"); + + status = ICP_STATUS_MUTEX; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + mutexLocked = ICP_TRUE; + + if (ICP_TRUE != hssAccBypassData[voiceBypassId].enabled) + { + ICP_HSSACC_REPORT_ERROR_1 ("icp_HssAccVoiceBypassDisable - Selected " + "bypass (%u) is not enabled\n", + voiceBypassId); + status = ICP_STATUS_RESOURCE; + } + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Configure the Bypass*/ + + HssAccComTdmIOUnitCmd8byteMsgCreate ( + ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE, + hssAccBypassData[voiceBypassId].portId, + voiceBypassId, + 0, + 0, 0, 0, 0, + &message); + + + status = + HssAccComTdmIOUnitMsgSendAndRecv( + message, + ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE_RESPONSE, + &(hssAccBypassStats.bypassDisable), + NULL); + if (ICP_STATUS_SUCCESS != status) + { + ICP_HSSACC_REPORT_ERROR_1("icp_HssAccVoiceBypassDisable - " + "Failed to disable Voice " + "Bypass %u on the TDM I/O Unit\n", + voiceBypassId); + } + + + } + + if (ICP_STATUS_SUCCESS == status) + { + /* Save bypass config and send new channel state to tx */ + hssAccBypassData[voiceBypassId].enabled = ICP_FALSE; + gctId = hssAccBypassData[voiceBypassId].gctId; + hssAccBypassData[voiceBypassId].portId = ICP_HSSACC_MAX_NUM_PORTS; + hssAccBypassData[voiceBypassId].gctId = + ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS; + hssAccGctData[gctId].numBypassUsing --; + + /* Notify the Tx Datapath module that this channel is + no longer bypassed */ + HssAccTxDatapathChanBypassStateSet( + hssAccBypassData[voiceBypassId].destChannelId, + ICP_FALSE); + + HssAccChannelBypassPairClear( + hssAccBypassData[voiceBypassId].srcChannelId, + hssAccBypassData[voiceBypassId].destChannelId); + + hssAccBypassData[voiceBypassId].srcChannelId = + ICP_HSSACC_MAX_NUM_CHANNELS; + hssAccBypassData[voiceBypassId].destChannelId = + ICP_HSSACC_MAX_NUM_CHANNELS; + } + + /* Free the HssAcc mutex */ + if (ICP_TRUE == mutexLocked) + { + if (ICP_STATUS_SUCCESS != ICP_HSSACC_MUTEX_UNLOCK()) + { + ICP_HSSACC_REPORT_ERROR ("icp_HssAccVoiceBypassDisable - " + "failed to release HssAcc Mutex\n"); + status = ICP_STATUS_MUTEX; + } + } + + + + ICP_HSSACC_TRACE_0 (ICP_HSSACC_FN_ENTRY_EXIT, + "Exiting icp_HssAccVoiceBypassDisable\n"); + return status; +} + + + +/****************************************************************************** + * Abstract: + * Display the stats collected by this sub-module. + * + * + *****************************************************************************/ +void +HssAccBypassStatsShow (void) +{ + + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nVoice Channel Bypass Configuration:\n" + "Gain Control Table Loading\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccBypassStats.gctLoad); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nBypass Gain Control Config messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccBypassStats.gainCfg); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nBypass Enable messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccBypassStats.bypassEnable); + ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, + "\nBypass Disable messaging\n", + 0, 0, 0, 0, 0, 0); + HssAccSingleMessageStatsShow (hssAccBypassStats.bypassDisable); + +} + +/****************************************************************************** + * Abstract: + * Reset the stats collected by this sub-module. + * + *****************************************************************************/ +void +HssAccBypassStatsReset (void) +{ + memset (&hssAccBypassStats, + 0, + sizeof(icp_hssacc_bypass_stats_t)); +} diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_address_translate.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_address_translate.h new file mode 100644 index 0000000..df0475d --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_address_translate.h @@ -0,0 +1,142 @@ +/****************************************************************************** + * @file icp_hssacc_address_translate.h + * + * @description Content of this file provides the prototypes for address + * translation functionality + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#ifndef ICP_HSSACC_ADDRESS_TRANSLATE_H +#define ICP_HSSACC_ADDRESS_TRANSLATE_H + +#include "icp.h" + + +/***************************************************************************** + * Abstract: + * Translate a Virtual address to a physical offset, includes Endianness + * Swapping if necessary. + * + *****************************************************************************/ +uint32_t +HssAccVirtToPhysAddressTranslateAndSwap(void* virtAddr); + + + +/***************************************************************************** + * Abstract: + * Translate a physical offset to a virtual address includes endianness + * swapping and platform specific bit manipulation where required. + * + *****************************************************************************/ +void * +HssAccPhysToVirtAddressSwapAndTranslate(uint32_t physAddr); + + +/***************************************************************************** + * Abstract: + * Translate a Virtual address to a physical offset. + * + *****************************************************************************/ +uint32_t +HssAccVirtToPhysAddressTranslate(void * const virtAddr); + + + +/***************************************************************************** + * Abstract: + * Translate a physical offset to a virtual address. + * + *****************************************************************************/ +void * +HssAccPhysToVirtAddressTranslate(const uint32_t physAddr); + + + +/***************************************************************************** + * Abstract: + * Allocate a chunk of memory for DMA communication with the TDM I/O Unit. + * returns the virtual address and the physical offset as an out parameter. + * virtual Address will be NULL if allocation failed and physAddr will be + * left un-touched. + * + *****************************************************************************/ +void * +HssAccDmaMemAllocate(uint32_t sizeBytes, + uint32_t * physAddr); + + + + +/***************************************************************************** + * Abstract: + * Swap Endianness on the data of an OSAL Buffer + * + *****************************************************************************/ +void +HssAccDataEndiannessSwap(IX_OSAL_MBUF * const buffer); + +#endif /* ICP_HSSACC_ADDRESS_TRANSLATE_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_config.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_config.h new file mode 100644 index 0000000..c355b94 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_config.h @@ -0,0 +1,269 @@ +/******************************************************************************* + * + * @file icp_hssacc_channel_config.h + * + * @description Content of this file is the Prototype definition of the API for + * the Channel Configuration module and all related Data structures shared + * by this module. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + + +#ifndef ICP_HSSACCCHANNELCONFIG_H +#define ICP_HSSACCCHANNELCONFIG_H + +#include "icp.h" +#include "icp_hssacc.h" +#include "icp_hssacc_port_config.h" + + +#define BIT_SET(index) (1 << index) + + +/* + * ---------------------------------------------------------------------------- + * Enumerated types + * ---------------------------------------------------------------------------- + */ + +/* Enum for the various states a channel can be in */ +typedef enum +{ + ICP_HSSACC_CHANNEL_UNINITIALISED = 0, + ICP_HSSACC_CHANNEL_ALLOCATED, + ICP_HSSACC_CHANNEL_CONFIGURED, + ICP_HSSACC_CHANNEL_SERVICE_CONFIGURED, + ICP_HSSACC_CHANNEL_DOWN, + ICP_HSSACC_CHANNEL_ENABLED, + ICP_HSSACC_CHANNEL_DOWN_TRANSITION +} icp_hssacc_channel_state_t; + + + +/* + Definition of the structure containing all Channel + configuration Data +*/ +typedef struct icp_hssacc_channel_config_s +{ + icp_hssacc_channel_state_t state; /* Current state of the channel */ + icp_hssacc_channel_type_t type; /* Voice or data */ + unsigned size; /* Size of the channel in timeslots */ + unsigned portId; /* HSS port number for the channel */ + icp_hssacc_line_t lineId; /* TDM line number for the channel */ + uint32_t timeslotMap; /* Timeslots reserved for the channel */ + uint32_t sdcCtrlReg; /* Common channel settings */ + uint32_t rxCfg; /* HDLC Rx settings */ + uint32_t txCfg; /* HDLC Tx settings */ + icp_boolean_t dataPolarity; /* polarity of the data */ + icp_hssacc_bit_endian_t bitEndian; /* specifies endianness of the chan */ + icp_boolean_t byteSwap; /* byteSwapping on/off */ + icp_hssacc_robbed_bit_value_t rBitValue; /* value 0/1 of robbed bit */ + icp_hssacc_robbed_bit_location_t rBitLocation; + /* location of the robbed bit in the byte */ + icp_hssacc_bit_robbing_t bitRobbing; /* bit robbing used or not */ + + /* HDLC specific */ + icp_hssacc_hdlc_sof_flag_type_t sofFlagType; /* start of frame */ + icp_hssacc_hdlc_idle_pattern_t hdlcTxIdlePattern; /* idle pattern to Tx */ + icp_hssacc_hdlc_idle_pattern_t hdlcRxIdlePattern; /* expected idle on rx */ + icp_hssacc_hdlc_crc_bit_width_t hdlcCrcBitWidth; /* CRC size */ + uint32_t hdlcMaxFrSize; /* maximum frame size on rx */ + + /* VOICE specific */ + uint32_t voiceSampleSize; /* size of voice samples */ + uint8_t voiceIdlePattern; /* voice silence pattern */ + icp_hssacc_channel_voice_tx_idle_action_t txIdleAction; + /* tx silence or repeat last frame */ + + unsigned numBypasses; /* channel can be involved in up to 2 bypasses, + one as source, one as destination */ +} icp_hssacc_channel_config_t; + +/* ---------------------------------------------------------------------------- + * Function declarations + * ---------------------------------------------------------------------------- + */ +/***************************************************************************** + * Abstract: + * Initialise the Channel Configuration module + * + *****************************************************************************/ +icp_status_t +HssAccChannelConfigInit(void); + + +/***************************************************************************** + * Abstract: + * shutdown the Channel Configuration module + * + *****************************************************************************/ +icp_status_t +HssAccChannelConfigShutdown(void); + + + +/***************************************************************************** + * Abstract: + * Reset the internal stats gathered by this module + * + *****************************************************************************/ +void +HssAccChannelConfigStatsReset (void); + + + +/***************************************************************************** + * Abstract: + * display all stats gathered by this module. + * + *****************************************************************************/ +void +HssAccChannelConfigStatsShow (void); + + + +/***************************************************************************** + * Abstract: + * display the state of the specified channel + * + *****************************************************************************/ +void +HssAccChannelConfigStateShow (unsigned channelId); + + +/***************************************************************************** + * Abstract: + * check whether it is valid to configure a bypass on the specified + * channel. + * + *****************************************************************************/ +icp_boolean_t +HssAccChannelConfigValidBypass(const unsigned channelId, + const unsigned portId); + + +/***************************************************************************** + * Abstract: + * set the 2 specified channels as part of a bypass + * + *****************************************************************************/ +void +HssAccChannelBypassPairSet(unsigned srcChannelId, + unsigned destChannelId); + + +/***************************************************************************** + * Abstract: + * clear the 2 specified channels from any bypass connection + * + *****************************************************************************/ +void +HssAccChannelBypassPairClear(unsigned srcChannelId, + unsigned destChannelId); + + +/***************************************************************************** + * Abstract: + * query the service to which the specified channel is associated, Voice + * or HDLC. + * + *****************************************************************************/ +icp_hssacc_channel_type_t +HssAccChannelConfigTypeQuery (unsigned channelId); + + + +/***************************************************************************** + * Abstract: + * query the current state of the specified channel. + * + *****************************************************************************/ +icp_hssacc_channel_state_t +HssAccChannelConfigStateQuery (unsigned channelId); + + + +/***************************************************************************** + * Abstract: + * notify the Channel Configuration module that all buffers associated + * with this channel have been retrieved. + * + *****************************************************************************/ +void +HssAccChannelConfigBuffersClearedNotify (unsigned channelId); + + + +/***************************************************************************** + * Abstract: + * query whether there are any channels allocated on the specified port. + * + *****************************************************************************/ +icp_boolean_t +HssAccChannelConfigUsedChansOnPortFind (const unsigned portId); +#endif /* ICP_HSSACCCHANNELCONFIG_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_list.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_list.h new file mode 100644 index 0000000..df939fc --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_channel_list.h @@ -0,0 +1,137 @@ +/****************************************************************************** + * @file icp_hssacc_channel_list.h + * + * @description Content of this file includes the prototypes for channel + * list manipulations + * + * @ingroup icp_HssAcc + * + * @revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ +#ifndef ICP_HSSACC_CHANNEL_LIST_H +#define ICP_HSSACC_CHANNEL_LIST_H + + +#include "icp.h" + +/***************************************************************************** + * Abstract + * Reset All the channels lists + * + *****************************************************************************/ +void HssAccChannelListsReset (void); + + +/***************************************************************************** + * Abstract + * Add a channel to one of the lists for processing. + * + *****************************************************************************/ +icp_status_t HssAccChannelListAdd (unsigned hssPortId, + unsigned chanId, + unsigned chanSize); + + + + +/***************************************************************************** + * Abstract + * Remove the specified channel from processing lists. + * + *****************************************************************************/ +icp_status_t HssAccChannelListRemove (unsigned hssPortId, + unsigned chanId, + unsigned chanSize); + + +/***************************************************************************** + * Abstract + * Retrieve the ID of the last channel being processed on a specific port + * and a specific list + * + *****************************************************************************/ +unsigned +HssAccChannelListLastPortChannelGet (unsigned portId, + icp_hssacc_channel_list_t listId); + +/***************************************************************************** + * Abstract + * Retrieve the prev channel to processed in the list this channel + * belongs to. + * + *****************************************************************************/ +unsigned +HssAccChannelListPrevChannelOnListGet(unsigned channelId); + + +/***************************************************************************** + * Abstract + * Reset the messaging stats for Channel List management. + * + *****************************************************************************/ +void +HssAccChannelListsStatsReset (void); + + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_common.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_common.h new file mode 100644 index 0000000..c839e53 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_common.h @@ -0,0 +1,978 @@ +/****************************************************************************** + * @file icp_hssacc_common.h + * + * @description this file contains value definitions and function prototypes + * that are common accross all the HSS Access component + * + * @revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * Copyright(c) 2010,2011,2012 Avencall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + *****************************************************************************/ + + +#ifndef ICP_HSSACCCOMMON_H +#define ICP_HSSACCCOMMON_H + +#include "IxOsal.h" +#include "icp.h" +#include "IxPiuMh.h" +#include "IxPiuDl.h" +#include "icp_hssacc.h" + + +#if !defined(TDM_PRIVATE) +#define TDM_PRIVATE static +#else +#define TDM_PRIVATE +#endif +#ifdef IXP23XX +#define ICP_HSSACC_MAX_NUM_CHANNELS (128) +#endif +#ifdef TOLAPAI +#define ICP_HSSACC_MAX_NUM_CHANNELS (128) +#endif + + +/* + * This macro represents an invalid Channel + */ +#define ICP_HSSACC_INVALID_CHAN ICP_HSSACC_MAX_NUM_CHANNELS + + + +#ifdef TOLAPAI +#define ICP_HSSACC_MAX_NUM_PORTS 3 +#else +#ifdef IXP23XX +#define ICP_HSSACC_MAX_NUM_PORTS 4 +#endif +#endif + +#define ICP_HSSACC_MAX_NUM_VOICE_BYPASS_GCTS 4 + +#define ICP_HSSACC_MAX_NUM_VOICE_BYPASSES 4 + +/* ---------------------------------------------------------------------------- + * Externs + * ---------------------------------------------------------------------------- + */ +/* Mutex which controls access to control path functions */ +extern IxOsalMutex hssAccControlPathMutex; + + +/* ---------------------------------------------------------------------------- + * Defines and Macros. + * ---------------------------------------------------------------------------- + */ +/* + * Timeout value in ms + */ +#define ICP_HSSACC_MUTEX_TIMEOUT 10 + +/* + * Initialises the service mutex. + */ +#define ICP_HSSACC_MUTEX_INIT() (ixOsalMutexInit(&hssAccControlPathMutex)) + +/* + * Locks the service mutex. + */ +#define ICP_HSSACC_MUTEX_LOCK() (ixOsalMutexLock( \ + &hssAccControlPathMutex,\ + ICP_HSSACC_MUTEX_TIMEOUT)) + +/* + * Unlocks the service mutex. + */ +#define ICP_HSSACC_MUTEX_UNLOCK() (ixOsalMutexUnlock(&hssAccControlPathMutex)) + +/* + * Destroys the service mutex. + */ +#define ICP_HSSACC_MUTEX_DESTROY() (\ + ixOsalMutexDestroy(&hssAccControlPathMutex)) + +/* + * The bit offset for byte 0 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET (24) + +/* + * The byte mask for byte 0 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE0_MASK (0xFF << \ + ICP_HSSACC_TDM_IO_UNIT_BYTE0_OFFSET) + +/* + * The bit offset for byte 1 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET (16) + +/* + * The byte mask for byte 1 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE1_MASK (0xFF << \ + ICP_HSSACC_TDM_IO_UNIT_BYTE1_OFFSET) + +/* + * The bit offset for byte 2 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET (8) + +/* + * The byte mask for byte 2 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE2_MASK (0xFF << \ + ICP_HSSACC_TDM_IO_UNIT_BYTE2_OFFSET) + +/* + * The bit offset for byte 3 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET (0) + +/* + * The byte mask for byte 3 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_BYTE3_MASK (0xFF << \ + ICP_HSSACC_TDM_IO_UNIT_BYTE3_OFFSET) + + + +/* + * The byte offset for Short 0 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET (16) + +/* + * The byte mask for short 0 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_SHORT0_MASK (0xFFFF << \ + ICP_HSSACC_TDM_IO_UNIT_SHORT0_OFFSET) + +/* + * The byte offset for Short 1 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_SHORT1_OFFSET 0 + +/* + * The byte mask for Short 1 in a TDM I/O Unit message + */ +#define ICP_HSSACC_TDM_IO_UNIT_SHORT1_MASK (0xFFFF << \ + ICP_HSSACC_TDM_IO_UNIT_SHORT1_OFFSET) + + +/* + * The size of a word in bytes + */ +#define ICP_HSSACC_WORD_SIZE 4 + + +/* Mask to determine whether an address is aligned on a double + word boundary or not */ +#define ICP_HSSACC_DBLE_WD_ALIGN_MASK 0x7 + + +/* + * Mechanism to validate the upper (MAX) and lower (0) bounds + * of a positive enumeration + * + * param int [in] VALUE - the integer value to test + * param int [in] MAX - the maximum value to test against + * + * This macro returns TRUE if the bounds are invalid and FALSE if + * they are okay. NOTE: MAX will be an invalid value, so check >= + * + */ +#define ICP_HSSACC_ENUM_INVALID(VALUE, MAX) ((((VALUE) < 0) || \ + ((VALUE) >= (MAX))) ? \ + TRUE : FALSE) + + +/* + * TDM I/O Unit message commands + */ +/* + * HDMA configuration commands + */ + +/* + * Port configuration commands + */ +#define ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD (0x20) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE (0x21) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_ENABLE +#define ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE (0x22) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_DISABLE +#define ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD (0x23) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP (0x24) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP_DONE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_PROV_TABLE_SWAP +#define ICP_HSSACC_TDM_IO_UNIT_PORT_ERROR_READ (0x25) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_ERROR_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_ERROR_READ +#define ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_READ (0x26) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_CFG_TABLE_READ +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_LOAD (0x27) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_READ (0x28) +#define ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_PORT_TS_REMAP_TABLE_READ +#endif + +/* + * Queue configuration commands + */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG (0x40) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_PORT_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG (0x41) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_CHAN_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG (0x42) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_CFG +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG (0x43) +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_VOICE_CHAN_CFG +#define ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE (0x44) +#define ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_NEXT_CHAN_WRITE +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR (0x45) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_CHAN_RX_MAX_SIZE_WR +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE (0x46) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_ENABLE +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE (0x47) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_CHAN_FLOW_DISABLE +#define ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ (0x48) +#define ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_ABT_ALN_ERR_READ +#define ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ (0x49) +#define ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_FCS_MAX_ERR_READ +#define ICP_HSSACC_TDM_IO_UNIT_STATS_READ (0x4A) +#define ICP_HSSACC_TDM_IO_UNIT_STATS_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_STATS_READ +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE (0x4B) +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_BYPASS_ENABLE +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE (0x4C) +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_BYPASS_DISABLE +#define ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD (0x4D) +#define ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_GCT_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG (0x4E) +#define ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_BYPASS_GAIN_CFG +#define ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG (0x4F) +#define ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_TX_CHAN_Q_ADDR_CFG + + +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG (0xA0) +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_TX_Q_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG (0xA1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_CFG +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG (0xA2) +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_CFG +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG (0xA3) +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_TX_Q_HEAD_CTR_CFG +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG (0xA4) +#define ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_TX_Q_TAIL_CTR_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG (0xA5) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_READER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG (0xA6) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_Q_WRITER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG (0xA7) +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_READER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG (0xA8) +#define ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_VOICE_RX_Q_WRITER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG (0xA9) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_INT_CFG +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG (0xAA) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_CFG +#define ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD (0xAB) +#define ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_LOAD +#define ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ (0xAC) +#define ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_OFFS_TABLE_READ + + +#define ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_STATUS (0x80) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ (0x81) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ_RESPONSE \ + ICP_HSSACC_TDM_IO_UNIT_HSS_SW_ERROR_READ + + +/* interval in TDM I/O Unit cycles at which the TDM I/O Unit is to + service the Software Queues */ +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_INTERVAL (133000) +#else +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TIMER_INTERVAL (100000) +#endif +#endif + +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_MAX_TRANSACTION_SIZE_WRDS (14) +#else +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_MAX_TRANSACTION_SIZE_WRDS (9) +#endif +#endif + +#define ICP_HSSACC_TDM_IO_UNIT_HSS_INT_DISABLED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_INT_ENABLED (1) + +/* Channel Stats codes for Stat Read TDM I/O Unit message */ + +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_ABT_ALN (0) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_MAX_SIZE (1) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_FCS (2) +#ifndef NDEBUG +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_RX_PKTS (3) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_STAT_TX_PKTS (4) +#endif + +#ifdef IXP23XX +/* LUT defines used in the creation of the timeslot allocation + tables to be sent to the TDM I/O Unit */ +#define ICP_HSSACC_TDM_IO_UNIT_WORDS_PER_LUT (8) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_WORD_FULL_ASSIGNMENT (0x55555555) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_WORD_T1_ASSIGNMENT (0x5555) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_E1_SIZE_WRDS (2) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_DMVIP_SIZE_WRDS (4) +#define ICP_HSSACC_TDM_IO_UNIT_LUT_QMVIP_SIZE_WRDS (8) +#endif + + +/* Provision Table defines */ +#define ICP_HSSACC_TDM_IO_UNIT_PROV_TABLE_SZ (0x400) +#define ICP_HSSACC_TDM_IO_UNIT_TS_ENABLE (1) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_TS_EN_BIT_OFFSET (23) +#define ICP_HSSACC_TDM_IO_UNIT_OFFSET_TABLE_SZ (0x200) + +/* Queue List configuration */ +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_ADD_FLAG (0) +#define ICP_HSSACC_TDM_IO_UNIT_CHAN_DEL_FLAG (1) + +/* When adding/removing channels on a linked list for + * a port, these values are used to indicate whether the list is + * a Tx list or an Rx list + */ +#define IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_TX (0) +#define IX_HSSACC_TDM_IO_UNIT_LIST_INDICATOR_RX (1) + +/* Defines for specifying the data flow direction which we are + enabling/disabling for this channel */ +#define ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_NEITHER (0) +#define ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_TX_ONLY (1) +#define ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_RX_ONLY (2) +#define ICP_HSSACC_TDM_IO_UNIT_FLOW_DIR_BOTH (3) + + +/* Queue Configuration parameters for QMgr component */ +#define ICP_HSSACC_VOICE_RX_WATERMARK (1) +#define ICP_HSSACC_HDLC_RX_WATERMARK (1) +#define ICP_HSSACC_TX_WATERMARK (1) + + +/* SDC Control Register Offset and Masks */ +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_VOICE (2) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_HDLC (0) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_ROBBING_OFFSET (14) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_OFFSET (12) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VAL_OFFSET (9) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_INVERT_OFFSET (8) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CHAN_TYPE_OFFSET (6) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_REVERSE_OFFSET (5) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_SWAP_OFFSET (4) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_NO_REVERSE (0) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_REVERSE (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_NO_SWAP (0) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BYTE_SWAP (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_INVERT_ON (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_BIT_INVERT_OFF (0) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_ONE_BIT_ON (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_OFF (0) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VALUE_ZERO (0) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_VALUE_ONE (1) + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_ZERO (1) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RBIT_LOC_SEVEN (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_IDLE_FLAG (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_IDLE_ONES (1) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_32_BIT_CRC (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_16_BIT_CRC (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_SHARED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_ONE (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_SOF_TWO (2) + + + + +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_MSB_MASK (0xFF00) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_MSB_OFFSET (8) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_CTRL_LSB_MASK (0xFF) + + +/* HDLC TX & RX CFG Registers Offsets */ +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_IM_OFFSET (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_FCS_OFFSET (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_SF_OFFSET (3) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_TX_CFG_POSTBF_OFFSET (5) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_IM_OFFSET (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_FCS_OFFSET (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_RX_CFG_PREBF_OFFSET (3) + +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CFG_BIT_FLIP (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDLC_CFG_NO_BIT_FLIP (0) + + + + +/* HDMA Register Offset Definitions */ +/* Port Configuration Register Common Section */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FT_OFFSET (30) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FS_OFFSET (28) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FE_OFFSET (27) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_DE_OFFSET (26) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_OFFSET (25) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FR_OFFSET (24) +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_OFFSET (23) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_RATE_OFFSET (21) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_DP_OFFSET (20) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_BITEND_OFFSET (19) +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_REFF_OFFSET (17) +#endif + +/* Port Configuration Register Tx Section */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_OD_OFFSET (18) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_EN_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_TX_PCR_LB_OFFSET (15) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KTYPE_OFFSET (13) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_UTYPE_OFFSET (11) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_FB_OFFSET (10) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KEND_OFFSET (9) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_56KSEL_OFFSET (8) + + +/* Port Configuration Register Rx Section */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_RX_PCR_LB_OFFSET (16) + + +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_LB_ON (1) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_LB_OFF (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_INPUT (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CLKDIR_OUTPUT (1) +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_INT (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_PCR_CS_EXT_REF (1) +#endif + + +/* Frame Configuration Register */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FBIT_OFFSET (31) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFFSET (7) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_OFFSET (6) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_INT_OFFSET (5) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_OFFSET (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_T1_IN_TS (23) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_TS (31) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_T1_IN_BITS (193) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_BITS (256) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_DUAL_MVIP_IN_BITS \ + (ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_BITS * 2) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_QUAD_MVIP_IN_BITS \ + (ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_FRAME_SIZE_E1_IN_BITS * 4) + +/* The HSS co-processor register values to be added to OFFSET in the + * case of TX and data in the HSSFCR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_TX_ADD_CLK_RATE (0x13) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_TX_ADD_HALF_CLK_RATE (0x11) + +/* value to be added to OFFSET in the case of FBIT being set in the FCR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_OFFSET_FBIT_ADDITION (7) + + +/* Image Configuration Register */ +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_VOICE_CHANNELISATION_OFFSET (20) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PINGPONG_OFFSET (19) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PHO_OFFSET (8) +/* Ping Pong */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_PING_PONG_ENABLED (1) +/* Voice channelisation. */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_VCH_ENABLED (0) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PID_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_ICR_PBA_OFFSET (0) + +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_0 (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_1 (3) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_2 (5) +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_RX_PBA_3 (7) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_0 (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_1 (2) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_2 (4) +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_TX_PBA_3 (6) +#endif + +/*The port image depth as a power of 2. + The port image depth is always 32*4 = 128 no matter + how many timeslots are assigned*/ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_HDMA_PID_SHIFT (7) + +/* CLK CR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_MAIN_OFFSET (22) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_DENOM_OFFSET (0) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CLKCR_NUM_OFFSET (12) + +#ifdef IXP23XX +/* HCR */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_SUB_FRAME_DELTA_OFFSET (32) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_HCR_FRAME_BASE_OFFSET (8) + +/* VCR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_VCR_FRAME_BASE_OFFSET (8) +#endif + +/* CWR */ +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW2_ENABLE_OFFSET (31) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW2_ADDRESS_OFFSET (24) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW1_ENABLE_OFFSET (23) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_TX_CW1_ADDRESS_OFFSET (16) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW2_ENABLE_OFFSET (15) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW2_ADDRESS_OFFSET (8) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW1_ENABLE_OFFSET (7) +#define ICP_HSSACC_TDM_IO_UNIT_HDMA_CWR_RX_CW1_ADDRESS_OFFSET (0) + +/* + Context wakeup Enabling. +*/ +/* 1 means on. 0 means off */ +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW1_ENABLED (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW1_ENABLED (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW1_DISABLED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW1_DISABLED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW2_ENABLED (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW2_ENABLED (1) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_TX_CW2_DISABLED (0) +#define ICP_HSSACC_TDM_IO_UNIT_HSS_RX_CW2_DISABLED (0) + + + +/* TDM IO UNIT Software Error codes and Bitmask offsets */ +#define ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_Q_OVERFLOW (0x2) +#define ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_Q_OVERFLOW (0x3) +#define ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FIFO_OVERFLOW (0x4) +#define ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FIFO_OVERFLOW (0x5) +#define ICP_HSSACC_TDM_IO_UNIT_RX_VOICE_FREE_Q_UNDERFLOW (0x6) +#define ICP_HSSACC_TDM_IO_UNIT_RX_HDLC_FREE_Q_UNDERFLOW (0x7) +#define ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_LP_OVERFLOW (0xa) +#define ICP_HSSACC_TDM_IO_UNIT_MSG_OUT_FIFO_HP_OVERFLOW (0xb) + +/* + * Error Bitmask offset definitions + */ +#ifdef TOLAPAI +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_RX_PARITY (5) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_TX_PARITY (4) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_RX_FLOW (3) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_TX_FLOW (2) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_RX_LOSS (1) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_PORT_TX_LOSS (0) + + +#ifdef IXP23XX +#define ICP_HSSACC_TDM_IO_UNIT_ERR_ALL_PORT_MASK (0xFFFFFF) +#else +#define ICP_HSSACC_TDM_IO_UNIT_ERR_ALL_PORT_MASK (0x3FFFF) +#endif +#define ICP_HSSACC_TDM_IO_UNIT_ERR_SGLE_PORT_MASK (0x3F) +#define ICP_HSSACC_TDM_IO_UNIT_NEXT_PORT_SHIFT (6) + +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_MSG_OUT_FIFO_H (23) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_FREE_UNDERF (19) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_FREE_UNDERF (18) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_INT_FIFO_OVERF (17) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_INT_FIFO_OVERF (16) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_MSG_OUT_FIFO_L (3) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_H_Q_OVERF (2) +#define ICP_HSSACC_TDM_IO_UNIT_ERR_BITMSK_RX_V_Q_OVERF (1) + + +/* + * The maximum number of timeslots available on a TDM trunk. + */ +#define ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE (32) +#define ICP_HSSACC_TIMESLOTS_PER_T1_LINE (24) + + +/* + * The number of TDM trunks per HSS port. + */ +#define ICP_HSSACC_MAX_TDM_LINES_PER_PORT (4) + +/* + * The maximum number of timeslots available on a HSS port. + */ +#define ICP_HSSACC_MAX_TIMESLOTS_PER_PORT (\ + ICP_HSSACC_MAX_TIMESLOTS_PER_TDM_LINE * \ + ICP_HSSACC_MAX_TDM_LINES_PER_PORT) + + + +/* System Clock divider definitions for the TDM I/O Unit HDMA coprocessor */ +#ifdef IXP23XX +#define ICP_HSSACC_HDMA_SYSCLK_1544KHZ { 64,147,197 } +#define ICP_HSSACC_HDMA_SYSCLK_2048KHZ { 48, 52, 63 } +#define ICP_HSSACC_HDMA_SYSCLK_8192KHZ { 12, 52,255 } +#else +#ifdef TOLAPAI +#define ICP_HSSACC_HDMA_SYSCLK_1544KHZ { 43,28,192 } +#define ICP_HSSACC_HDMA_SYSCLK_2048KHZ { 32, 135, 255 } +#define ICP_HSSACC_HDMA_SYSCLK_8192KHZ { 8, 135,1023 } +#endif +#endif + + + +/* ---------------------------------------------------------------------------- + * Application Specific Duals + * ---------------------------------------------------------------------------- + */ +#define ICP_HSSACC_TDM_IO_UNIT_CPP_COPROC (0x09) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_COPROC (0x02) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RD_HDLC_INST (0x09) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_WR_HDLC_INST (0x0C) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_RD_VOICE_INST (0x12) +#define ICP_HSSACC_TDM_IO_UNIT_SDC_WR_VOICE_INST (0x02) +#define ICP_HSSACC_TDM_IO_UNIT_CPP_RD_WORD_INST (0x0C) +#define ICP_HSSACC_TDM_IO_UNIT_CPP_WR_WORD_INST (0x08) + +/* ---------------------------------------------------------------------------- + * Structure definitions + * ---------------------------------------------------------------------------- + */ +/* + * structure of stats for TDM I/O Unit messages with responses + */ +typedef struct icp_hssacc_msg_with_resp_stats_s +{ + uint32_t numTdmIOUnitMessagesSent; + uint32_t numTdmIOUnitRespReceived; + uint32_t numTdmIOUnitTimeoutErrs; + uint32_t numTdmIOUnitInvalidResp; +} icp_hssacc_msg_with_resp_stats_t; + + +/* This is a set of identifiers for the + * channel linked lists + */ +typedef enum icp_hssacc_channel_list_s +{ + ICP_HSSACC_CHANNEL_LIST_PRIMARY = 0, + ICP_HSSACC_CHANNEL_LIST_SECONDARY_0, + ICP_HSSACC_CHANNEL_LIST_SECONDARY_1, + ICP_HSSACC_CHANNEL_LIST_DELIMITER +} icp_hssacc_channel_list_t; + + +/* + This is the list of all the channel lists used by the + HSS I/O Access library +*/ +typedef enum icp_hssacc_tdm_io_unit_channel_list_s +{ + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_PRIMARY = 0, + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_0, + ICP_HSSACC_TDM_IO_UNIT_LIST_TX_SECONDARY_1, + ICP_HSSACC_TDM_IO_UNIT_LIST_RX_PRIMARY, + ICP_HSSACC_TDM_IO_UNIT_LIST_RX_SECONDARY_0, + ICP_HSSACC_TDM_IO_UNIT_LIST_RX_SECONDARY_1, + ICP_HSSACC_TDM_IO_UNIT_LIST_DELIMITER +} icp_hssacc_tdm_io_unit_channel_list_t; + + +/***************************************************************************** + * Abstract + * HssAcc Receive queue reader counters. + * Used by the HssAcc component to access + * counters written solely by the TDM I/O unit. + * + * + *****************************************************************************/ +typedef struct icp_hssacc_rx_q_read_counters_s +{ + uint32_t rxFreeTail; + uint32_t rxHead; +} __attribute__((packed)) icp_hssacc_rx_q_read_counters_t; + + +/***************************************************************************** + * Abstract + * HssAcc queue reader counters. Used by the HssAcc component to access + * counters written solely by the TDM I/O unit. + * + * Purpose + * Should be used by the access layer to read the counters written by the + * TDM I/O unit. + * + * Fields + * txTail - an array of 1-byte counters for each Tx queue. + * voiceRxCounters.rxFreeTail - a 4-byte counter for the voice Rx free + * tail counter. Only the lower 2 bytes + * are used. + * voiceRxCounters.rxHead - a 4-byte counter for the voice Rx head + * counter. Only the lower 2 bytes are used. + * hdlcRxCounters.rxFreeTail - a 4-byte counter for the HDLC Rx free + * tail counter. Only the lower 2 bytes + * are used. + * hdlcRxCounters.rxHead - a 4-byte counter for the HDLC Rx head + * counter. Only the lower 2 bytes are used. + * + *****************************************************************************/ +typedef struct icp_hssacc_queue_reader_counters_s +{ + /* The tail counters for each of the Tx queues */ + uint8_t txTail[ICP_HSSACC_MAX_NUM_CHANNELS]; + + /* The voice Rx free tail and rx head counters */ + icp_hssacc_rx_q_read_counters_t voiceRxCounters; + + /* The HDLC Rx free tail and rx head counters */ + icp_hssacc_rx_q_read_counters_t hdlcRxCounters; +} __attribute__((packed,aligned(4))) icp_hssacc_queue_reader_counters_t; + + + +/***************************************************************************** + * Abstract + * HssAcc Receive queue writer counters. + * These counters are read by the TDM I/O unit + * and written by HssAcc. + * + *****************************************************************************/ +typedef struct icp_hssacc_rx_q_write_counters_s +{ + uint32_t rxFreeHead; + uint32_t rxTail; +} __attribute__((packed)) icp_hssacc_rx_q_write_counters_t; + + + +/***************************************************************************** + * Abstract + * HssAcc queue writer counters. These counters are read by the TDM I/O unit + * and written by HssAcc. + * + * Purpose + * Should be used by the access layer to update the counters read by the + * TDM I/O unit. + * + * Fields + * txHeadCounters - an array of 1-byte counters for each Tx queue. + * voiceRxCounters.rxFreeHead - a 4-byte counter for the voice Rx free + * head counter. Only the lower 2 bytes + * are used. + * voiceRxCounters.rxTail - a 4-byte counter for the voice Rx tail + * counter. Only the lower 2 bytes are used. + * hdlcRxCounters.rxFreeHead - a 4-byte counter for the HDLC Rx free + * head counter. Only the lower 2 bytes + * are used. + * hdlcRxCounters.rxTail - a 4-byte counter for the HDLC Rx tail + * counter. Only the lower 2 bytes are used. + * + *****************************************************************************/ +typedef struct icp_hssacc_queue_write_counters_s +{ + /* The head counters for all the Tx queues */ + uint8_t txHead[ICP_HSSACC_MAX_NUM_CHANNELS]; + + /* The voice Rx free head and rx tail counters */ + icp_hssacc_rx_q_write_counters_t voiceRxCounters; + + /* The HDLC Rx free head and rx tail counters */ + icp_hssacc_rx_q_write_counters_t hdlcRxCounters; +} __attribute__((packed,aligned(4))) icp_hssacc_queue_write_counters_t; + + + +/* ---------------------------------------------------------------------------- + * Function declarations + * ---------------------------------------------------------------------------- + */ + +/***************************************************************************** + * Abstract: + * Constructs a 2 word TDM I/O Unit message out of 4 individual bytes + * values and a full word value. + * + * + * Side Effects: + * The message will be written into pMessage->data[0] & pMessage->data[1]. + * + * Assumptions: + * None. + * + *****************************************************************************/ +void +HssAccComTdmIOUnitCmd4byte1wordMsgCreate ( + uint32_t byte0, + uint32_t byte1, + uint32_t byte2, + uint32_t byte3, + uint32_t word, + IxPiuMhMessage *pMessage); + + +/***************************************************************************** + * Abstract: + * Constructs a 2 word TDM I/O Unit message out of 8 individual byte values. + * + * Side Effects: + * The message will be written into pMessage->data[0] & pMessage->data[1]. + * + * Assumptions: + * None. + * + *****************************************************************************/ +void +HssAccComTdmIOUnitCmd8byteMsgCreate ( + uint32_t byte0, + uint32_t byte1, + uint32_t byte2, + uint32_t byte3, + uint32_t byte4, + uint32_t byte5, + uint32_t byte6, + uint32_t byte7, + IxPiuMhMessage *pMessage); + + +/***************************************************************************** + * Abstract: + * Submits a message to the TDM I/O Unit, waits for a response and verifies + * that the correct response was received. if responseWord is NULL then + * we are not expecting anything more than an ACK. + * + * + *****************************************************************************/ +icp_status_t +HssAccComTdmIOUnitMsgSendAndRecv( + IxPiuMhMessage message, + uint8_t response, + icp_hssacc_msg_with_resp_stats_t * stats, + uint32_t * responseWord); + +/***************************************************************************** + * Abstract: + * Displays Communication Stats relating to a single TDM I/O message + * + * + *****************************************************************************/ +void HssAccSingleMessageStatsShow (icp_hssacc_msg_with_resp_stats_t stat); + +#endif /* ICP_HSSACCCOMMON_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_config.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_config.h new file mode 100644 index 0000000..407ccae --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_config.h @@ -0,0 +1,297 @@ +/****************************************************************************** + * @file icp_hssacc_port_config.h + * + * @description this contains the data structure definitions and function + * prototypes necessary for port configuration + * + * @ingroup icp_HssAcc + * + * @revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#ifndef ICP_HSSACCPORTCONFIG_H +#define ICP_HSSACCPORTCONFIG_H + +#include "icp_hssacc.h" +#include "icp_hssacc_common.h" + + +/* Default Frame Pulse Widths for the TDM ports + Valid Range for Frame Pulse Width is 1 to 8 */ +#define ICP_HSSACC_RX_DFLT_FRM_PULSE_WIDTH 1 +#define ICP_HSSACC_TX_DFLT_FRM_PULSE_WIDTH 1 + +/* Enum for the enabled state of a port */ +typedef enum +{ + ICP_HSSACC_PORT_UNCONFIGURED = 0 , + ICP_HSSACC_PORT_CONFIGURED, + /* config written to memory but not to TDM I/O Unit */ + ICP_HSSACC_PORT_ENABLED + /* config written to TDM I/O Unit, port enabled */ +} icp_hssacc_port_state_t; + +/* + * Enum for each of the TDM lines on a HSS port + */ +typedef enum +{ + ICP_HSSACC_LINE_0 = 0, + ICP_HSSACC_LINE_1, + ICP_HSSACC_LINE_2, + ICP_HSSACC_LINE_3, + ICP_HSSACC_LINE_DELIMITER +} icp_hssacc_line_t; + + +/* + icp_hssacc_data_rate_t is used to specify the GCI setting of either + full line rate or half line rate +*/ +typedef enum + { + ICP_HSSACC_DATA_RATE_EQUALS_CLK_RATE = 0, + ICP_HSSACC_DATA_RATE_HALF_CLK_RATE, + ICP_HSSACC_DATA_RATE_TYPE_DELIMITER + } icp_hssacc_data_rate_t; + + +/* list of settings for the Frame Config Register MVIP ON/OFF bit */ +typedef enum +{ + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_OFF = 0, + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_ON, + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SWITCH_DELIMITER +} icp_hssacc_hdma_mvip_switch_t; + + +/* list of settings for the Frame Config Register MVIP mode bit */ +typedef enum +{ + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_DUAL = 0, + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_QUAD, + ICP_HSSACC_TDM_IO_UNIT_HDMA_FCR_MVIP_SETTING_DELIMITER +} icp_hssacc_hdma_mvip_setting_t; + +/* + icp_hssacc_port_additional_internal_config_t is used to specify the + additional port configuration information that is not provided through + the HSS I/O Access API + */ +typedef struct icp_hssacc_port_additional_internal_config_s +{ + icp_hssacc_data_rate_t dataRate; + uint32_t frmPulseWidth; +} icp_hssacc_port_additional_internal_config_t; + +/* + combines the API provided port configuration data and the + internal only configuration +*/ +typedef struct icp_hssacc_port_full_config_s +{ + icp_hssacc_port_config_t cfg; /* Port config from API */ + icp_hssacc_port_additional_internal_config_t addCfg; + /* addtional config params needed internally */ +} icp_hssacc_port_full_config_t; + + + +/* + data structure containing all port registers + in the format required by the TDM I/O Unit +*/ +typedef struct icp_hssacc_hdma_port_config_s +{ +#ifdef IXP23XX + uint32_t tx_LUT[ICP_HSSACC_TDM_IO_UNIT_WORDS_PER_LUT]; + /* tx LUT for TDM slot assignments */ + uint32_t rx_LUT[ICP_HSSACC_TDM_IO_UNIT_WORDS_PER_LUT]; + /* rx LUT for TDM slot assignments */ +#endif + uint32_t tx_pcr; + uint32_t rx_pcr; + uint32_t tx_fcr; + uint32_t rx_fcr; + uint32_t tx_icr; +#ifdef IXP23XX + uint32_t tx_vcr; + uint32_t tx_hcr; +#endif + uint32_t rx_icr; +#ifdef IXP23XX + uint32_t rx_vcr; + uint32_t rx_hcr; +#endif + uint32_t clkcr; + uint32_t cwr; +} icp_hssacc_hdma_port_config_t; + + + +/* + internal data structure containing all information + related to port configuration +*/ +typedef struct icp_hssacc_port_internal_config_s +{ + icp_hssacc_port_state_t state; + icp_hssacc_port_full_config_t rx; + icp_hssacc_port_full_config_t tx; + icp_hssacc_hdma_port_config_t * hdmaPortCfgTableVirtAddr; + /* Virtual address of HDMA port cfg table*/ + icp_hssacc_clk_speed_t clkSpeed; +} icp_hssacc_port_internal_config_t; + + + +/* ---------------------------------------------------------------------------- + * Function declarations + * ---------------------------------------------------------------------------- + */ + +/***************************************************************************** + * Abstract: + * sub-module initialisation function + * + *****************************************************************************/ +icp_status_t +HssAccPortConfigInit(void); + + +/***************************************************************************** + * Abstract: + * sub-module shutdown function. + * + *****************************************************************************/ +icp_status_t +HssAccPortConfigShutdown(void); + + +/***************************************************************************** + * Abstract: + * Check the line, first and last TS position are compatible with the + * current port config. + * + *****************************************************************************/ +icp_status_t +HssAccPortLineValidCheck (unsigned portId, + icp_hssacc_line_t lineId, + unsigned firstTsPos, + unsigned lastTsPos); + + + +/***************************************************************************** + * Abstract: + * Retrieve the current state of the port (configgured/disabled/enabled). + * + *****************************************************************************/ +icp_hssacc_port_state_t +HssAccPortStateGet (unsigned portId); + + + + +/***************************************************************************** + * Abstract: + * reset the internal stats of this sub-module + * + *****************************************************************************/ +void +HssAccPortConfigStatsReset (void); + + + +/***************************************************************************** + * Abstract: + * print out the stats of this sub-module + * + *****************************************************************************/ +void +HssAccPortConfigStatsShow (void); + + + +/***************************************************************************** + * Abstract: + * check the validity of the specified Tx clk mode depending on + * the platform + * + *****************************************************************************/ +icp_boolean_t +HssAccPortConfigTxClkModeInvalid(icp_hssacc_clk_mode_t clkMode); + + + +/***************************************************************************** + * Abstract: + * check the validity of the specified Rx clk mode depending on + * the platform + * + *****************************************************************************/ +icp_boolean_t +HssAccPortConfigRxClkModeInvalid(icp_hssacc_clk_mode_t clkMode); + +#endif /* ICP_HSSACCPORTCONFIG_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_hdma_reg_mgr.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_hdma_reg_mgr.h new file mode 100644 index 0000000..0d77dbe --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_port_hdma_reg_mgr.h @@ -0,0 +1,160 @@ +/******************************************************************************* + * + * @file icp_hssacc_port_hdma_reg_mgr.h + * + * @description Content of this file is the prototype definitions for the Port + * HDMA Register creation module + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#ifndef ICP_HSSACC_PORT_HDMA_REG_MGR_H +#define ICP_HSSACC_PORT_HDMA_REG_MGR_H + + +#include "icp_hssacc.h" + + +/* icp_hssacc_hdma_reg_trans_t is used to specify register types of Tx or Rx */ +typedef enum +{ + ICP_HSSACC_HDMA_RX_REG_TYPE = 0, + /* Rx type register for the HSS Port Config registers */ + ICP_HSSACC_HDMA_TX_REG_TYPE, + /* Tx type register for the HSS Port Config registers */ + ICP_HSSACC_HDMA_REG_TYPE_DELIMITER + /* Delimiter for array sizes */ +} icp_hssacc_hdma_reg_trans_t; + + + +/***************************************************************************** + * Abstract: + * Create the Port Config Register Value for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrPCRCreate (icp_hssacc_hdma_reg_trans_t type, + const icp_hssacc_port_full_config_t *portConfig, + uint32_t *pcr); + + + +/***************************************************************************** + * Abstract: + * Create the Frame Config Register value for the TDM I/O Unit + * + *****************************************************************************/ +icp_status_t +HssAccHdmaMgrFCRCreate (icp_hssacc_hdma_reg_trans_t type, + icp_hssacc_clk_speed_t clkSpeed, + const icp_hssacc_port_full_config_t *portConfig, + uint32_t *fcr); + +/***************************************************************************** + * Abstract: + * Create the Image Config Register Value for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrICRCreate (icp_hssacc_hdma_reg_trans_t type, + unsigned hssPortId, + uint32_t *icr); + + + +/***************************************************************************** + * Abstract: + * Create the Clock Config Register Value for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrClkCRCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *clkCR); + + +/***************************************************************************** + * Abstract: + * Create the Context Wakeup Register for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrCWRCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *cwr); + + +#ifdef IXP23XX +/***************************************************************************** + * Abstract: + * create the Voice Config Regsiter Values for the TDM I/O Unit. + * + *****************************************************************************/ +void +HssAccHdmaMgrVCRCreate (uint32_t *vcr); +#endif + + +#endif /* ICP_HSSACC_PORT_HDMA_REG_MGR_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_queues_config.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_queues_config.h new file mode 100644 index 0000000..936b091 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_queues_config.h @@ -0,0 +1,275 @@ +/******************************************************************************* + * + * @file icp_hssacc_queues_config.h + * + * @description Content of this file is the prototype defintions and data + * structure definitions for the Queue configuration module + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ +#ifndef ICP_HSSACCQUEUESCONFIG_H +#define ICP_HSSACCQUEUESCONFIG_H + +#include "IxQMgr.h" +#include "icp_hssacc_common.h" +#define ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_WORDS (1) +#define ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_BYTES \ + (ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_WORDS * \ + ICP_HSSACC_WORD_SIZE) + +/* The size of the queue descriptor. This is common to all queues */ +#define ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS (4) +#define ICP_HSSACC_QUEUE_DESC_SIZE_IN_BYTES \ + (ICP_HSSACC_QUEUE_DESC_SIZE_IN_WORDS * \ + ICP_HSSACC_WORD_SIZE) + +/* + * HssAcc transmit queue settings + */ + +#define ICP_HSSACC_TX_QUEUE_DEPTH_POW_2 (7) +#define ICP_HSSACC_TX_QUEUE_DEPTH (1 << ICP_HSSACC_TX_QUEUE_DEPTH_POW_2) + +#define ICP_HSSACC_HDLC_TX_QUEUE_DEPTH_POW_2 (ICP_HSSACC_TX_QUEUE_DEPTH_POW_2) +#define ICP_HSSACC_HDLC_TX_QUEUE_DEPTH (ICP_HSSACC_TX_QUEUE_DEPTH) + +#define ICP_HSSACC_VOICE_TX_QUEUE_DEPTH_POW_2 (4) +#define ICP_HSSACC_VOICE_TX_QUEUE_DEPTH \ + (1 << ICP_HSSACC_VOICE_TX_QUEUE_DEPTH_POW_2) + +/* The maximum number of bytes required to accomodate one TX queue */ +#define ICP_HSSACC_TX_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_TX_QUEUE_DEPTH) * \ + ICP_HSSACC_QUEUE_DESC_SIZE_IN_BYTES ) + + +/* + * HssAcc HDLC receive queue settings + */ +/* The depth of the HDLC RX queue */ +#define ICP_HSSACC_HDLC_RX_QUEUE_DEPTH_POW_2 (11) +#define ICP_HSSACC_HDLC_RX_QUEUE_DEPTH \ + (1 << ICP_HSSACC_HDLC_RX_QUEUE_DEPTH_POW_2) + +/* The total number of bytes required to accomodate the HDLC RX queue */ +#define ICP_HSSACC_HDLC_RX_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_HDLC_RX_QUEUE_DEPTH) * \ + ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_BYTES ) + + +/* + * HssAcc HDLC receive free queue settings + */ +/* The depth of the HDLC RX free queue 2048*/ +#define ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH_POW_2 \ + (ICP_HSSACC_HDLC_RX_QUEUE_DEPTH_POW_2) + +#define ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH \ + (1 << ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH_POW_2) + +/* The total number of bytes required to accomodate the HDLC RX free queue */ +#define ICP_HSSACC_HDLC_RX_FREE_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_HDLC_RX_FREE_QUEUE_DEPTH) * \ + ICP_HSSACC_QUEUE_DESC_SIZE_IN_BYTES ) + + +/* + * HssAcc Voice receive queue settings + */ +/* The depth of the voice RX queue */ +#define ICP_HSSACC_VOICE_RX_QUEUE_DEPTH_POW_2 (11) +#define ICP_HSSACC_VOICE_RX_QUEUE_DEPTH \ + (1 << ICP_HSSACC_VOICE_RX_QUEUE_DEPTH_POW_2) + +/* The total number of bytes required to accomodate the voice RX queue */ +#define ICP_HSSACC_VOICE_RX_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_VOICE_RX_QUEUE_DEPTH) * \ + ICP_HSSACC_RX_QUEUE_ENTRY_SIZE_IN_BYTES ) + + +/* + * HssAcc Voice receive free queue settings + */ +/* The depth of the voice RX free queue, as a power of 2 */ +#define ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH_POW_2 \ + (ICP_HSSACC_VOICE_RX_QUEUE_DEPTH_POW_2) + +#define ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH \ + (1 << ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH_POW_2) + +/* The total number of bytes required to accomodate the voice RX free queue */ +#define ICP_HSSACC_VOICE_RX_FREE_QUEUE_SIZE_IN_BYTES \ + ((ICP_HSSACC_VOICE_RX_FREE_QUEUE_DEPTH) * \ + ICP_HSSACC_QUEUE_DESC_SIZE_IN_BYTES ) + + +/* + List of IDs for Receive Queues used with the TDM I/O Unit +*/ + +typedef enum icp_hssacc_receive_queues_e + { + ICP_HSSACC_VOICE_RX_Q = ICP_HSSACC_MAX_NUM_CHANNELS, + ICP_HSSACC_VOICE_RX_FREE_Q, + ICP_HSSACC_HDLC_RX_Q, + ICP_HSSACC_HDLC_RX_FREE_Q + } icp_hssacc_receive_queues_t; + + +#define ICP_HSSACC_NUM_RECEIVE_QS (4) + + + +/* Stats */ +typedef struct icp_hssacc_queues_config_stats_s +{ + icp_hssacc_msg_with_resp_stats_t txQCfg; + icp_hssacc_msg_with_resp_stats_t txChanQAddrCfg; + icp_hssacc_msg_with_resp_stats_t hdlcRxQCfg; + icp_hssacc_msg_with_resp_stats_t voiceRxQCfg; + icp_hssacc_msg_with_resp_stats_t txQHeadCfg; + icp_hssacc_msg_with_resp_stats_t txQTailCfg; + icp_hssacc_msg_with_resp_stats_t voiceRxQReaderCfg; + icp_hssacc_msg_with_resp_stats_t voiceRxQWriterCfg; + icp_hssacc_msg_with_resp_stats_t hdlcRxQReaderCfg; + icp_hssacc_msg_with_resp_stats_t hdlcRxQWriterCfg; +} icp_hssacc_queues_config_stats_t; + + + +/* ---------------------------------------------------------------------------- + * Function declarations + * ---------------------------------------------------------------------------- + */ +/***************************************************************************** + * Abstract: + * Initialise all the queues used between the access layer and the + * TDM I/O Unit + * + *****************************************************************************/ +icp_status_t +HssAccQueuesInit(void); + + +/***************************************************************************** + * Abstract: + * shutdown all the queues used between the access layer and the + * TDM I/O Unit + * + *****************************************************************************/ +icp_status_t +HssAccQueuesShutdown(void); + + +/***************************************************************************** + * Abstract: + * Voice and HDLC channels use queues of different sizes so when a + * channel gets allocated for a specific service we need to make sure + * the size is correct and up to date. + * + *****************************************************************************/ +icp_status_t +HssAccQueueConfigQSizeUpdate(uint32_t channelId, + icp_hssacc_channel_type_t type); + + +/***************************************************************************** + * Abstract: + * Reset this modules stats. + * + *****************************************************************************/ +void +HssAccQueuesConfigStatsReset (void); + + +/***************************************************************************** + * Abstract: + * Display all the stats inherent to this module. + * + *****************************************************************************/ +void +HssAccQueuesConfigStatsShow (void); + + +/***************************************************************************** + * Abstract: + * Retrieve the QMgr queue Id using the internal ID (channel number for + * Tx or rx queue ID) + * + *****************************************************************************/ +IxQMgrQId +HssAccQueueIdGet (uint32_t qIndexId); + +/***************************************************************************** + * Abstract: + * enables the callbacks within the QMgr component. + * + *****************************************************************************/ +icp_status_t +HssAccRxQueuesNotificationEnable(void); + + +#endif /* ICP_HSSACCQUEUESCONFIG_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rings.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rings.h new file mode 100644 index 0000000..c272757 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rings.h @@ -0,0 +1,170 @@ +/****************************************************************************** + * @file icp_hssacc_rings.h + * + * @description Content of the file provides Ring creation and manipulation + * functionality + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + *****************************************************************************/ + +#ifndef ICP_HSSACC_RINGS_H +#define ICP_HSSACC_RINGS_H + +/* Tx & Rx s/w ring routines */ +typedef struct icp_hssacc_dataplane_ring_s +{ + volatile uint32_t *content; + uint32_t size; + uint32_t mask; + volatile uint32_t tail; + volatile uint32_t head; +} icp_hssacc_dataplane_ring_t; + +/** + * @def IX_HSSACC_DATAPLANE_RING_ENTRY_ADD + * @brief puts an entry at the head of the sw ring and increments head + * counter + */ +#define ICP_HSSACC_DATAPLANE_RING_ENTRY_ADD(ring,entry) do { \ + icp_hssacc_dataplane_ring_t *pRing = &(ring); \ + pRing->content[pRing->head & pRing->mask] = ((uint32_t)(entry)); \ + pRing->head++; \ + } while (0) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_ENTRY_REM + * @brief gets an entry from the tail of the sw ring and decrements tail + * counter + */ +#define ICP_HSSACC_DATAPLANE_RING_ENTRY_REM(ring,entry) do { \ + icp_hssacc_dataplane_ring_t *pRing = &(ring); \ + entry = pRing->content[pRing->tail & pRing->mask]; \ + pRing->tail++; \ + } while (0) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_TAIL_ENTRY_GET + * @brief Get the entry at the tail of a sw Ring + */ +#define ICP_HSSACC_DATAPLANE_RING_TAIL_ENTRY_GET(ring) \ + (ring).content[ICP_HSSACC_DATAPLANE_RING_TAIL(ring)] + +/** + * @def ICP_HSSACC_DATAPLANE_RING_TAIL + * @brief Get the Tail pointer of a ring + */ +#define ICP_HSSACC_DATAPLANE_RING_TAIL(ring) \ + ((ring).tail & (ring).mask) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_TAIL_INCR + * @brief Increment the Tail pointer of a ring + */ +#define ICP_HSSACC_DATAPLANE_RING_TAIL_INCR(ring) (ring).tail++ + +/** + * @def ICP_HSSACC_DATAPLANE_RING_HEAD_ENTRY_GET + * @brief Get the entry at the head of a sw ring + */ +#define ICP_HSSACC_DATAPLANE_RING_HEAD_ENTRY_GET(ring) \ + (ring).content[ICP_HSSACC_DATAPLANE_RING_HEAD(ring)] + +/** + * @def ICP_HSSACC_DATAPLANE_RING_HEAD + * @brief Get the Head pointer of a sw ring + */ +#define ICP_HSSACC_DATAPLANE_RING_HEAD(ring) \ + ((ring).head & (ring).mask) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_HEAD_INCR + * @brief Increment the Head pointer of a sw ring + */ +#define ICP_HSSACC_DATAPLANE_RING_HEAD_INCR(ring) do { \ + (ring).head++; } while(0) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_NUM_ENTRIES_GET + * @brief gets the number of entries currently in the sw ring + */ +#define ICP_HSSACC_DATAPLANE_RING_NUM_ENTRIES_GET(ring) \ + ((ring).head - (ring).tail) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_FULL + * @brief tests whether the sw ring is full + */ +#define ICP_HSSACC_DATAPLANE_RING_FULL(ring) \ + (((ring).head - (ring).tail) == (ring).size) + +/** + * @def ICP_HSSACC_DATAPLANE_RING_EMPTY + * @brief tests whether the sw ring is empty + */ +#define ICP_HSSACC_DATAPLANE_RING_EMPTY(ring) \ + ((ring).head == (ring).tail) + + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rx_datapath.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rx_datapath.h new file mode 100644 index 0000000..62d18d3 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_rx_datapath.h @@ -0,0 +1,216 @@ +/****************************************************************************** + * @file icp_hssacc_rx_datapath.h + * + * @description Content of this file provides the function prototypes for the + * HSS I/O Access receive functionality + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + *****************************************************************************/ + +#ifndef ICP_HSSACC_RX_DP_H +#define ICP_HSSACC_RX_DP_H + +#include "IxOsal.h" +#include "icp.h" +#include "icp_hssacc.h" +#include "IxQMgr.h" + +#define ICP_HSSACC_RX_DP_CHAN_DESC_PTR_RING_SZ (256) + +/* Definition of watermark level for pre-emptive Voice traffic flow regulation, + this watermark is tuned following performance testing, at this point +it is assumed that flow regulation should begin early to prevent Speech latency +build-up. */ +#define ICP_HSSACC_RX_Q_WATERMARK_LEVEL (2) + + +void +HssAccRxQServiceCallback(IxQMgrQId qId, + IxQMgrCallbackId cbId); + +/****************************************************************************** + * Abstract: + * Initialise Rx datapath global variables + * + ******************************************************************************/ +icp_status_t +HssAccRxDatapathInit(void); + +/****************************************************************************** + * Abstract: + * Shut down Rx datapath Module. + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathShutdown(void); + + +/****************************************************************************** + * Abstract: + * Register rx callback and user context + * + ******************************************************************************/ +void +HssAccChannelRxCallbackRegister(uint32_t channelId, + icp_hssacc_rx_callback_t rxCallback, + icp_user_context_t userContext); + +/****************************************************************************** + * Abstract: + * Deregister rx callback and user context + * + ******************************************************************************/ +void +HssAccChannelRxCallbackDeregister(uint32_t channelId); + +/****************************************************************************** + * Abstract: + * Set max frame size for HDLC, must be done at init + * + *****************************************************************************/ +void +HssAccRxDatapathHdlcInit(uint32_t maxRxFrameSize); + +/****************************************************************************** + * Abstract: + * Set max frame size for voice, must be done at init + * + *****************************************************************************/ +void +HssAccRxDatapathVoiceInit(uint32_t maxRxFrameSize); + +/****************************************************************************** + * Abstract: + * Function to run the Q Mgr processing function and call + * associated callbacks + * + ******************************************************************************/ +icp_status_t +HssAccRxDatapathService(icp_hssacc_channel_type_t channelType); + + + +/****************************************************************************** + * Abstract: + * Retrieve all buffers in an Rx Free Queue if there are no initialized + * channels for the corresponding service + * + *****************************************************************************/ +icp_status_t +HssAccRxFreeQsBufsRetrieve(IX_OSAL_MBUF * * ppStartChainBuffer, + IX_OSAL_MBUF * * ppEndChainBuffer); + +/****************************************************************************** + * Abstract: + * Retrieve all buffers in a chain from Rx Ring for a specified channel + * + *****************************************************************************/ +icp_status_t +HssAccRxDatapathChanBufsRetrieve(uint32_t channelId, + IX_OSAL_MBUF * * startChainBuffer, + IX_OSAL_MBUF * * endChainBuffer); + +/****************************************************************************** + * Abstract: + * Print out the per-channel statistics + * + ******************************************************************************/ +void +HssAccRxDatapathChanStatsShow(uint32_t channelId); + + +/****************************************************************************** + * Abstract: + * Function to print out stats on replenishing + * + ******************************************************************************/ +void +HssAccRxDatapathReplenishStatsShow(icp_hssacc_channel_type_t serviceType); + +/****************************************************************************** + * Abstract: + * Reset the per-channel statistics + ******************************************************************************/ +void +HssAccRxDatapathChanStatsReset(uint32_t channelId); + + +/****************************************************************************** + * Abstract: + * Function to reset stats on replenishing + * + *****************************************************************************/ +void +HssAccRxDatapathReplenishStatsReset(icp_hssacc_channel_type_t serviceType); + + +/****************************************************************************** + * Abstract: + * Return the Max Rx Sample/Frame size configured for the specified Service + * + *****************************************************************************/ +uint32_t +HssAccRxDatapathMaxServiceFrameSizeGet(icp_hssacc_channel_type_t servType); +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tdm_io_queue_entry.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tdm_io_queue_entry.h new file mode 100644 index 0000000..a6a286a --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tdm_io_queue_entry.h @@ -0,0 +1,193 @@ +/****************************************************************************** + * @file icp_hssacc_tdm_io_queue_entry.h + * + * @description Content of this file contains the definition and access + * macros for the TDM I/O Queue Entry format + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + *****************************************************************************/ + +#ifndef ICP_HSSACC_TDM_IO_QUEUE_ENTRY_H +#define ICP_HSSACC_TDM_IO_QUEUE_ENTRY_H + + +/***************************************************************************** + * Definition of the Channel descriptor format + * + *****************************************************************************/ +typedef struct icp_hssacc_chan_desc_s +{ + /* In order to handle both Little and Big Endianness correctly, + this data struct contains the Length split into MSB and LSB fields. */ + uint8_t currBufLength_LSB; + uint8_t currBufLength_MSB; + uint8_t status; + uint8_t channelId; +} icp_hssacc_chan_desc_t; + +/***************************************************************************** + * Definition of the Queue Entry format for Tx and RxFree Queues + * + *****************************************************************************/ +typedef struct icp_hssacc_tdm_io_queue_entry_s +{ + /* this union allows us to manipulate and move around the entire data + struct as a single word,thus saving instructions for copies */ + union { + icp_hssacc_chan_desc_t strct; + uint32_t word; + } descriptor; + void * currBufData; + uint32_t packetLengthBytes; + IX_OSAL_MBUF * currBuf; +} icp_hssacc_tdm_io_queue_entry_t; + + + + +/***************************************************************************** + * Definition of the TDM I/O private section of the OSAL Buffer + * + *****************************************************************************/ +typedef struct icp_hssacc_osal_mbuf_tdm_io_section_s +{ + icp_hssacc_tdm_io_queue_entry_t tdm_io_entry; + IX_OSAL_MBUF * pNextBuf; + uint32_t reserved[3]; +} icp_hssacc_osal_mbuf_tdm_io_section_t; + + + +/***************************************************************************** + * Macros for accessing the different fields of a Queue Entry + * + *****************************************************************************/ + +#define ICP_TDM_IO_Q_ENTRY_CHANNEL_ID(entryPtr) \ + ((entryPtr)->descriptor.strct.channelId) + +#define ICP_TDM_IO_Q_ENTRY_STATUS(entryPtr) (entryPtr->descriptor.strct.status) + +#define ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_MSB(entryPtr) \ + ((entryPtr)->descriptor.strct.currBufLength_MSB) + +#define ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_LSB(entryPtr) \ + ((entryPtr)->descriptor.strct.currBufLength_LSB) + +#define ICP_TDM_IO_Q_ENTRY_DATA(entryPtr) ((entryPtr)->currBufData) + +#define ICP_TDM_IO_Q_ENTRY_PKT_LEN(entryPtr) ((entryPtr)->packetLengthBytes) + +#define ICP_TDM_IO_Q_ENTRY_OSAL_MBUF(entryPtr) ((entryPtr)->currBuf) + + + +/***************************************************************************** + * Macros for accessing the different fields of the TDM I/O Unit private section + * of the OSAL Buffer + * + *****************************************************************************/ + +#define ICP_OSAL_MBUF_TDM_SECT_CHANNEL_ID(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_CHANNEL_ID((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_STATUS(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_STATUS((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_MSB(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_MSB((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_CURR_BUF_LEN_LSB(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_CURR_BUF_LEN_LSB((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_DATA(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_DATA((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_PKT_LEN(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_PKT_LEN((&((mbufPtr)->tdm_io_entry)))) + +#define ICP_OSAL_MBUF_TDM_SECT_NEXT_BUF(mbufPtr) \ + ((mbufPtr)->pNextBuf) + +#define ICP_OSAL_MBUF_TDM_SECT_OSAL_MBUF_START(mbufPtr) \ + (ICP_TDM_IO_Q_ENTRY_OSAL_MBUF((&((mbufPtr)->tdm_io_entry)))) + + +/***************************************************************************** + * Macros for handling the Packet Length field. these are used to manipulate + * the endianness of the field. + * + *****************************************************************************/ +#define ICP_OSAL_MBUF_TDM_SECT_LEN_MASK 0xFF +#define ICP_OSAL_MBUF_TDM_SECT_LEN_MSB_OFFSET 8 + +/* These macros will return as a byte number the MSB and LSB + respectively of a 2 byte packet length field */ +#define ICP_OSAL_MBUF_PKT_LEN_MSB(len) ((len >> ICP_OSAL_MBUF_TDM_SECT_LEN_MSB_OFFSET) & ICP_OSAL_MBUF_TDM_SECT_LEN_MASK) + +#define ICP_OSAL_MBUF_PKT_LEN_LSB(len) (len & ICP_OSAL_MBUF_TDM_SECT_LEN_MASK) + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_timeslot_allocation.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_timeslot_allocation.h new file mode 100644 index 0000000..815e289 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_timeslot_allocation.h @@ -0,0 +1,260 @@ +/******************************************************************************* + * + * @file icp_hssacc_timeslot_allocation.h + * + * @description Content of this file provides the main internal API for the + * timeslot allocation module used as part of channel Allocation and Deletion + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#ifndef ICP_HSSACC_TIMESLOT_ALLOCATION_H +#define ICP_HSSACC_TIMESLOT_ALLOCATION_H + + + +#include "icp_hssacc_channel_config.h" + + +/***************************************************************************** + * Abstract + * Platform specific initialisation for this sub-module. + * + *****************************************************************************/ +icp_status_t HssAccTsAllocPlatformInit (void); + + + +/***************************************************************************** + * Abstract + * Initialisation of the sub-module. + * + *****************************************************************************/ +icp_status_t HssAccTsAllocInit (void); + + +/***************************************************************************** + * Abstract + * Shutdown this sub-module. + * + *****************************************************************************/ +void HssAccTsAllocShutdown (void); + +/***************************************************************************** + * Abstract + * Remove the allocation of timeslots associated with the specified + * channel. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocDelete (unsigned channelId, + icp_hssacc_channel_config_t * hssChannelData); + + +/***************************************************************************** + * Abstract + * Update the Timeslot provisioning table for the specified port. will + * also update the offset table for all ports. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocUpdate(unsigned portId, + const icp_hssacc_channel_config_t * hssChannelData); + + +/***************************************************************************** + * Abstract + * Setup an initial Timeslot allocation for correct behaviour of the + * specified port with no channels configured on it. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocInitialAllocationUpdate(unsigned portId); + + + + +#ifdef IXP23XX +/***************************************************************************** + * Abstract + * Create the Timeslot Look-up Table for the TDM I/O unit. + * + *****************************************************************************/ +icp_status_t +HssAccTxAllocLUTCreate (icp_hssacc_clk_speed_t clkSpeed, + uint32_t *pHssLUT); +#endif + +/***************************************************************************** + * Abstract + * Swap the Timeslot provisioning tables within the TDM I/O Unit. + * + *****************************************************************************/ +icp_status_t HssAccTsAllocTableSwap (unsigned hssPortId); + + + + +/***************************************************************************** + * Abstract + * returns the address of the Memory block allocated for the + * Timeslot provisioning Table. + * + *****************************************************************************/ +void * HssAccTsAllocHdmaProvTableVirtAddrGet (void); + + +/***************************************************************************** + * Abstract + * Returns the address of the memory block allocated for the timeslot + * offset table. + * + *****************************************************************************/ +void * HssAccTsAllocTdmIoUnitOffsetTableVirtAddrGet (void); + + +/***************************************************************************** + * Abstract + * Return a pointer to the stats for Swap message. + * + *****************************************************************************/ +icp_hssacc_msg_with_resp_stats_t * HssAccTsAllocSwapStatsGet(void); + + +/***************************************************************************** + * Abstract + * return a pointer to the stats for the Offset Table read message. + * + *****************************************************************************/ +icp_hssacc_msg_with_resp_stats_t * HssAccTsAllocOffsetTableReadStatsGet(void); + + + +/***************************************************************************** + * Abstract + * Read one word of the specified table. + * + *****************************************************************************/ +icp_status_t +HssAccTsAllocOffsetTableWordRead (icp_boolean_t readShadowTable, + uint16_t tableOffset, + uint32_t *tableWord); + + + + +/***************************************************************************** + * Abstract: + * Verify that all of the timeslots requested are not already in use. + * + *****************************************************************************/ +icp_boolean_t +HssAccTsAvailableVerify(unsigned portId, icp_hssacc_line_t lineId, + uint32_t tsMap); + + + +/***************************************************************************** + * Abstract: + * Register the timeslots specified for the specified channel. + * + *****************************************************************************/ +void +HssAccTsRegister(unsigned channelId, + unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap); + + +/***************************************************************************** + * Abstract: + * Unregister any timeslots associated with the specified channel. + * + *****************************************************************************/ +void +HssAccTsUnregister(unsigned portId, + icp_hssacc_line_t lineId, + uint32_t tsMap); + +/***************************************************************************** + * Abstract + * Display all the stats collecting within this module. + * + *****************************************************************************/ +void HssAccTsAllocStatsShow (void); + + +/***************************************************************************** + * Abstract + * Reset The stats for the Timeslot allocation module. + * + *****************************************************************************/ +void HssAccTsAllocStatsReset (void); + + + + +#endif /* #ifndef ICP_HSSACC_TIMESLOT_ALLOCATION_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_trace.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_trace.h new file mode 100644 index 0000000..703f6e2 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_trace.h @@ -0,0 +1,339 @@ +/******************************************************************************* + * + * @file icp_hssacc_trace.h + * + * @description Content of this file provides Trace functionality for the + * component + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + + +#ifndef ICP_HSSACC_TRACE_H +#define ICP_HSSACC_TRACE_H + + +/* ---------------------------------------------------------------------------- + * Includes + * ---------------------------------------------------------------------------- + */ +#include "IxOsal.h" + + +/* + * ---------------------------------------------------------------------------- + * Enumerated types + * ---------------------------------------------------------------------------- + */ + +/***************************************************************************** + * Enumeration defining HssAcc trace levels. + *****************************************************************************/ +typedef enum icp_hssacc_trace_level_e +{ + ICP_HSSACC_TRACE_OFF = 0, /**< NO TRACE */ + ICP_HSSACC_DEBUG = 1, /**< Select traces of interest */ + ICP_HSSACC_FN_ENTRY_EXIT = 2 /**< ALL function entry/exit traces + and all traces of interest */ +} icp_hssacc_trace_level_t; + + +/* ---------------------------------------------------------------------------- + * Defines and Macros. + * ---------------------------------------------------------------------------- + */ + +/***************************************************************************** + * The trace level for the HSS Acc Control path and Datapath blocks + * + * Description: + * This macro turns the debug trace on or off, depending on whether the + * code is compiled for debug or release. + * There are 3 levels allowed in the current compilation setup: + * if NDEBUG is not defined and DEBUG is not defined, then selected tracing + * will be done for the control path and the datapath tracing will be off. + * if NDEBUG is not defined and DEBUG is defined then all function + * entry/exits are on as well selected tracing for control and data paths. + * if NDEBUG is defined ALL tracing is off. + * + *****************************************************************************/ + +#ifdef DEBUG +#define ICP_HSSACC_TRACE_LEVEL ICP_HSSACC_FN_ENTRY_EXIT +#define ICP_HSSACC_DP_TRACE_LEVEL ICP_HSSACC_FN_ENTRY_EXIT +#else +#define ICP_HSSACC_TRACE_LEVEL ICP_HSSACC_TRACE_OFF +#define ICP_HSSACC_DP_TRACE_LEVEL ICP_HSSACC_TRACE_OFF +#endif + + + + + +/***************************************************************************** + * Mechanism for reporting HssAcc software errors + * + *****************************************************************************/ +#define ICP_HSSACC_REPORT_ERROR(STR) \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, \ + IX_OSAL_LOG_DEV_STDERR, \ + STR, 0, 0, 0, 0, 0, 0); + +/***************************************************************************** + * Mechanism for reporting HssAcc software errors with 1 argument + * + *****************************************************************************/ +#define ICP_HSSACC_REPORT_ERROR_1(STR,ARG1) \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, \ + IX_OSAL_LOG_DEV_STDERR, \ + STR, ARG1, 0, 0, 0, 0, 0); + +/***************************************************************************** + * Mechanism for reporting HssAcc software errors with 2 arguments + * + *****************************************************************************/ +#define ICP_HSSACC_REPORT_ERROR_2(STR,ARG1,ARG2) \ + ixOsalLog (IX_OSAL_LOG_LVL_ERROR, \ + IX_OSAL_LOG_DEV_STDERR, \ + STR, ARG1, ARG2, 0, 0, 0, 0); + + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with no arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_0(LEVEL, STR) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, 0, 0, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_0(LEVEL, STR) do { /* nothing */ } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with one argument + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_1(LEVEL, STR, ARG1) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, 0, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_1(LEVEL, STR, ARG1) do { /* nothing */ } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with two arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_2(LEVEL, STR, ARG1, ARG2) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, ARG2, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_2(LEVEL, STR, ARG1, ARG2) do { } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with three arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + * + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_3(LEVEL, STR, ARG1, ARG2, ARG3) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, ARG2, ARG3, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_3(LEVEL, STR, ARG1, ARG2, ARG3) do { } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc component, with four arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + * + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_TRACE_4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \ + { \ + if (LEVEL <= ICP_HSSACC_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, ARG2, ARG3, ARG4, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_TRACE_4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) do { } while(0) +#endif + + +/***************************************************************************** + * Mechanism for tracing debug for the HSS Acc Datapath block component, + * with no arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_DP_TRACE_0(LEVEL, STR) \ + { \ + if (LEVEL <= ICP_HSSACC_DP_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, 0, 0, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_DP_TRACE_0(LEVEL, STR) do { /* nothing */ } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc Datapath component, + * with one argument + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_DP_TRACE_1(LEVEL, STR, ARG1) \ + { \ + if (LEVEL <= ICP_HSSACC_DP_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, 0, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_DP_TRACE_1(LEVEL, STR, ARG1) do { /* nothing */ } while(0) +#endif + +/***************************************************************************** + * Mechanism for tracing debug for the HssAcc Datapath component, + * with two arguments + * + * Note: + * This macro executes only in debug versions of the code. It does nothing + * in release code. + *****************************************************************************/ +#ifndef NDEBUG + #define ICP_HSSACC_DP_TRACE_2(LEVEL, STR, ARG1, ARG2) \ + { \ + if (LEVEL <= ICP_HSSACC_DP_TRACE_LEVEL) \ + { \ + ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, \ + IX_OSAL_LOG_DEV_STDOUT, \ + STR, ARG1, ARG2, 0, 0, 0, 0); \ + } \ + } +#else + #define ICP_HSSACC_DP_TRACE_2(LEVEL, STR, ARG1, ARG2) do { } while(0) +#endif + + +#endif /* ICP_HSSACC_TRACE_H */ diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tx_datapath.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tx_datapath.h new file mode 100644 index 0000000..4c6c722 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_tx_datapath.h @@ -0,0 +1,191 @@ +/******************************************************************************* + * + * @file icp_hssacc_tx_datapath.h + * + * @description Content of this file provides the internal API for the Transmit + * datapath module. + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#ifndef ICP_HSSACC_TX_DATAPATH_H +#define ICP_HSSACC_TX_DATAPATH_H + +#include "icp_hssacc.h" + +/* Definition of watermark level for pre-emptive Voice traffic flow regulation, + this watermark is tuned following performance testing, at this point +it is assumed that flow regulation should begin early to prevent Speech latency +build-up. */ +#define ICP_HSSACC_TX_Q_WATERMARK_LEVEL (4) + +/* Voice packet length should be modulo 4. A pre-transmit voice buffer check +will bitwise AND the voice packet length with this value. */ +#define ICP_HSSACC_TX_VOICE_PACKET_LENGTH_CHECK_MASK (0x00000003) + + +/***************************************************************************** + * Abstract: + * Initialises this subcomponent (mutex...) and Resets the Tx Datapath + * internal data. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathInit(void); + + +/***************************************************************************** + * Abstract: + * Destroys all allocated memory and mutexes for this component. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathShutdown(void); + +/***************************************************************************** + * Abstract: + * updates the Type for specified channel, + * will potentially trigger a resizing of the Queue associated with this + * channel. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathChanTypeUpdate (uint32_t channelId, + icp_hssacc_channel_type_t chanType); + + +/***************************************************************************** + * Abstract: + * Set or unset the channel as bypassed, will allow the component to prevent + * or allow Tx. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathChanBypassStateSet(uint32_t channelId, + icp_boolean_t bypassed); + + +/***************************************************************************** + * Abstract: + * Register the Tx Done callback + * + *****************************************************************************/ +void +HssAccTxDatapathChanTxDoneCallbackRegister( + uint32_t channelId, + icp_hssacc_tx_done_callback_t txDoneCallback, + icp_user_context_t userContext); + +/***************************************************************************** + * Abstract: + * Deregister the Tx Done callback + * + *****************************************************************************/ +void +HssAccTxDatapathChanTxDoneCallbackDeregister(uint32_t channelId); + + +/***************************************************************************** + * Abstract: + * Triggers the servicing of all the Tx Queues, this will trigger TxDone + * callbacks when appropriate for each queue of type channelType. + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathService(icp_hssacc_channel_type_t channelType); + + + +/***************************************************************************** + * Abstract: + * Retrieve all buffers in the transmit path for specified channel + * + *****************************************************************************/ +icp_status_t +HssAccTxDatapathChannelBuffersRetrieve(uint32_t channelId, + IX_OSAL_MBUF * * startChainBuffer, + IX_OSAL_MBUF * * endChainBuffer); + + +/***************************************************************************** + * Abstract: + * Reset the stats for specified channel + * + *****************************************************************************/ +void +HssAccTxDatapathChanStatsReset(uint32_t channelId); + + + +/***************************************************************************** + * Abstract: + * Print out the stats for the specified channel + * + *****************************************************************************/ +void +HssAccTxDatapathChanStatsShow(uint32_t channelId); + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_voice_bypass.h b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_voice_bypass.h new file mode 100644 index 0000000..e59fec7 --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/include/icp_hssacc_voice_bypass.h @@ -0,0 +1,115 @@ +/******************************************************************************* + * + * @file icp_hssacc_voice_bypass.h + * + * @description Content of this file provides the internal API for the Voice + * bypass module + * + * @ingroup icp_HssAcc + * + * @Revision 1.0 + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * + * + ******************************************************************************/ + +#ifndef ICP_HSSACC_VOICE_BYPASS_H +#define ICP_HSSACC_VOICE_BYPASS_H + +#include "icp.h" + +/***************************************************************************** + * Abstract + * This function initialises the internals of the Voice Bypass + * sub-module. it can only be called once. + * + *****************************************************************************/ +void +HssAccVoiceBypassInit(void); + + +/***************************************************************************** + * Abstract + * This function shuts down the Voice Bypass submodule. the module + * must have been initialised beforehand. + * + *****************************************************************************/ +icp_status_t +HssAccVoiceBypassShutdown(void); + +/***************************************************************************** + * Abstract + * This function displays the internal gathered by this sub-module. + * + *****************************************************************************/ +void +HssAccBypassStatsShow (void); + + +/***************************************************************************** + * Abstract + * This function resets all the internal stats relating to this sub-module. + * + *****************************************************************************/ +void +HssAccBypassStatsReset (void); + +#endif diff --git a/Acceleration/library/icp_telephony/tdm_io_access/linux_2.6_kernel_space.mk b/Acceleration/library/icp_telephony/tdm_io_access/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..325733d --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_io_access/linux_2.6_kernel_space.mk @@ -0,0 +1,76 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# +################### + +#specific include directories in kernel space +INCLUDES+= -I $(ICP_OSAL_DIR)/platforms/EP805XX/include \ + -I $(ICP_OSAL_DIR)/platforms/EP805XX/os/linux/include \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/core \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ddk \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/ioMem \ + -I $(ICP_OSAL_DIR)/common/os/linux/include/modules/bufferMgt + + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -DTOLAPAI -D__tolapai -DEP805XX -D__ep805xx -DIX_HW_COHERENT_MEMORY=1 +EXTRA_LDFLAGS+=-whole-archive + |