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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Avencall
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
static const u32 wl_cntl_tbl[2][4] = {
/* Not ECC */ {
[DDR_400] = 0xb90,
[DDR_533] = 0xb60,
[DDR_667] = 0xb60,
[DDR_800] = 0xb48,
},
/* ECC */ {
[DDR_400] = 0xb60,
[DDR_533] = 0xb40,
[DDR_667] = 0xb40,
[DDR_800] = 0xb30,
}
};
static const u32 wdll_misc_val = 0x1200802;
static void wl_rcven_calibrate(struct mem_controller *mch)
{
u32 data32;
/* Reset VOX Mode */
u32 ddriomc0 = read32(BAR+DDRIOMC0) | 0xb << DDRIOMC0_DQVOXADJ |
1 << DDRIOMC0_DDRVOXCTL1 | 1 << DDRIOMC0_DDRVOXCTL0;
write32(BAR+DDRIOMC0, ddriomc0);
mdelay(50);
/* Reset DRRTC00, which is sticky, to its default value */
write32(BAR+DRRTC00, 0x06060606);
write32(BAR+WDLL_MISC, wdll_misc_val);
u32 wl_cntl_val = wl_cntl_tbl[mch->ecc][mch->timing.speed];
write32(BAR+WL_CNTL0, wl_cntl_val | 1 << WL_CNTL_WDLL_CLKG); /* 2: WDLL_CLKG */
write32(BAR+WL_CNTL1, wl_cntl_val | 1 << WL_CNTL_WDLL_CLKG);
write32(BAR+WL_CNTL2, wl_cntl_val | 1 << WL_CNTL_WDLL_CLKG);
write32(BAR+WL_CNTL3, wl_cntl_val | 1 << WL_CNTL_WDLL_CLKG);
write32(BAR+WL_CNTL4, wl_cntl_val);
ddriomc0 &= ~(1 << DDRIOMC0_DDRVOXCTL1);
write32(BAR+DDRIOMC0, ddriomc0);
mdelay(50);
write32(BAR+DQSFAIL0, 0);
write8(BAR+DQSFAIL1, 0);
write32(BAR+DCALADDR, 0x10008);
write32(BAR+DCALCSR, 0x8802001C);
while((data32 = read32(BAR+DCALCSR)) & 0x80000000);
if (data32 & 0x40000000)
die("receive enable failed!\n");
data32 = read32(BAR+DRRTC00);
u8 rcven = (u8)data32;
rcven = MAX(rcven, (u8)(data32>>8));
rcven = MAX(rcven, (u8)(data32>>16));
rcven = MAX(rcven, (u8)(data32>>24));
data32 = read32(BAR+DRRTC01);
rcven = MAX(rcven, (u8)(data32));
rcven = MAX(rcven, (u8)(data32>>8));
rcven = MAX(rcven, (u8)(data32>>16));
rcven = MAX(rcven, (u8)(data32>>24));
if (mch->ecc) {
u8 drrtc02 = read8(BAR+DRRTC02);
rcven = MAX(rcven, drrtc02);
}
unsigned prgrpd = (rcven + 0x1f) >> 5; /* ceil and take 3 MSB */
data32 = (pci_read_config32(PCI_DEV(0,0,0), DRT1) & ~1) | ((prgrpd>>3) & 1);
pci_write_config32(PCI_DEV(0,0,0), DRT1, data32);
data32 = (pci_read_config32(PCI_DEV(0,0,0), DRT0) & ~7) | (prgrpd & 7);
pci_write_config32(PCI_DEV(0,0,0), DRT0, data32);
printk(BIOS_SPEW, "Finished RCVEN calibration and write levelization\n");
for (i = 0; i < 5; i++)
printk(BIOS_DEBUG, "WL_CNTL%d=%08x\n",
i, read32(BAR+WL_CNTL0+(i*4)));
}
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