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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Arastra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include "pc80/udelay_io.c"
#include <console/console.h>
#include "southbridge/intel/i3100/early_smbus.h"
#include "southbridge/intel/i3100/early_lpc.c"
#include "northbridge/intel/i3100/raminit_ep80579.h"
#include "superio/intel/i3100/i3100.h"
#include "superio/intel/i3100/early_serial.c"
#include "cpu/x86/bist.h"
#include <lib.h>
#include <spd.h>
#include "lib/generic_sdram.c"
/* RCBA registers */
#define RCBA 0xF0
#define DEFAULT_RCBA 0xFEA00000
#define RCBA_HPTC 0x3404 /* 32 bit */
#define RCBA_GCS 0x3410 /* 32 bit */
#define RCBA_D31IR 0x3140 /* 16 bit */
#define RCBA_D30IR 0x3142 /* 16 bit */
#define RCBA_D29IR 0x3144 /* 16 bit */
#define RCBA_D28IR 0x3146 /* 16 bit */
#define TRUXTON_DEBUG_PCI 0
static void early_config(void)
{
u32 gcs;
/* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
/* Disable watchdog */
gcs = read32(DEFAULT_RCBA + RCBA_GCS);
gcs |= (1 << 5); /* No reset */
write32(DEFAULT_RCBA + RCBA_GCS, gcs);
/* Enable HPET */
write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
/* Improve interrupt routing
* D31:F2 SATA INTB# -> PIRQD
* D31:F3 SMBUS INTB# -> PIRQD
* D31:F4 CHAP INTD# -> PIRQA
* D29:F0 USB1#1 INTA# -> PIRQH
* D29:F1 USB1#2 INTB# -> PIRQD
* D29:F7 USB2 INTA# -> PIRQH
* D28:F0 PCIe Port 1 INTA# -> PIRQE
*/
write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
}
#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
void main(unsigned long bist)
{
const struct mem_controller mch[] = {
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x00, 0),
.channel0 = { DIMM2, DIMM3 },
}
};
if (bist == 0) {
/* Skip this if there was a built in self test failure */
if (memory_initialized()) {
/* Reboot doesn't work right now, so if we're rebooting
* force a HARD reboot by using the 0xe into CF9h
*/
printk(BIOS_INFO, "Detected soft reboot: Issuing HARD reboot.\n");
outb(0xe, 0xCF9);
udelay(1);
printk(BIOS_INFO, "HARD reboot slow to respond! Re-issue HARD Reboot!\n");
outb(0xe, 0xCF9);
printk(BIOS_ERR, "Reboot failed!\n");
for (;;) asm("hlt");
}
}
/* Set up the console */
i3100_enable_superio();
i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
console_init();
/* Prevent the TCO timer from rebooting us */
i3100_halt_tco_timer();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
enable_smbus();
#if TRUXTON_DEBUG_PCI
dump_pci_devices();
#endif
PRINT_SPD_DUMP();
sdram_initialize(ARRAY_SIZE(mch), mch);
#if TRUXTON_DEBUG_PCI
dump_pci_devices();
dump_pci_device(PCI_DEV(0, 0x00, 0));
PRINT_DCAL_DUMP();
#endif
#if CONFIG_DEBUG_RAM_SETUP
#include <northbridge/intel/i3100/ep80579.h>
int tolm=0;
ram_check(0x00000000, 0x0009FFFF);
/* Skip VGA and CAR region */
tolm=(pci_read_config16(mch->f0, TOLM)<<16);
ram_check(0x000D0000, tolm);
#endif
early_config();
}
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