add Coreboot test reports

author: Bastien Ligneul <bligneul@avencall.com> 2012-06-07 11:23:02 +0200
committer: Bastien Ligneul <bligneul@avencall.com> 2012-06-07 11:23:36 +0200
commit: 1a84216de7a77f164424ce2815ea8c9b8b87d8e5 (patch)
tree: fab962b668a28e4dfa68b817eabd9a14c48c5089 /coreboot-pirq-tests
parent: 0608d1fa132f06e4cdd26a2c2cfc20315bcec194 (diff)
4 files changed, 1703 insertions, 3 deletions
diff --git a/coreboot-pirq-tests/946f413/screenlog.1 b/coreboot-pirq-tests/47c9a04/screenlog.1
index 93e7397..93e7397 100644
--- a/coreboot-pirq-tests/946f413/screenlog.1
+++ b/coreboot-pirq-tests/47c9a04/screenlog.1
diff --git a/coreboot-pirq-tests/README b/coreboot-pirq-tests/README
index 7836c67..8913f40 100644
--- a/coreboot-pirq-tests/README
+++ b/coreboot-pirq-tests/README
@@ -13,6 +13,7 @@ C-a H
 $ cd ~/coreboot
 
 make oldconfig
+make clean
 make
 
 cd
@@ -33,9 +34,7 @@ Si "Verify OK"
 //Éteindre la carte
 //Débrancher le Dédiprog SF 100
 
-Aller dans le dossier xioh-acceptance/coreboot-pirq-tests/"versiontest"
-
-screen (puis entrée)
+cd xioh-acceptance/coreboot-pirq-tests/"versiontest"
 
 sudo minicom -D /dev/ttyS0
 
diff --git a/coreboot-pirq-tests/f5dc42c-iasl20100528/coreboot.rom b/coreboot-pirq-tests/f5dc42c-iasl20100528/coreboot.rom
new file mode 100644
index 0000000..b475ead
--- /dev/null
+++ b/coreboot-pirq-tests/f5dc42c-iasl20100528/coreboot.rom
diff --git a/coreboot-pirq-tests/f5dc42c-iasl20100528/screenlog.0 b/coreboot-pirq-tests/f5dc42c-iasl20100528/screenlog.0
new file mode 100644
index 0000000..db4975d
--- /dev/null
+++ b/coreboot-pirq-tests/f5dc42c-iasl20100528/screenlog.0
@@ -0,0 +1,1701 @@
+
+bastien@bastien:~/xioh-acceptance/coreboot-pirq-tests/f5dc42c-iasl20100528$ 
+bastien@bastien:~/xioh-acceptance/coreboot-pirq-tests/f5dc42c-iasl20100528$ 
+bastien@bastien:~/xioh-acceptance/coreboot-pirq-tests/f5dc42c-iasl20100528$ cd ~ 
+/coreboot
+bastien@bastien:~/coreboot$ make oldcio[K[Konfig
+*
+* coreboot Configuration
+*
+*
+* General setup
+*
+Expert mode (EXPERT) [N/y/?] n
+Local version string (LOCALVERSION) [] 
+CBFS prefix to use (CBFS_PREFIX) [fallback] fallback
+Compiler
+> 1. GCC (COMPILER_GCC)
+  2. LLVM/clang (COMPILER_LLVM_CLANG)
+choice[1-2?]: 1
+Build with scan-build for static analysis (SCANBUILD_ENABLE) [N/y/?] n
+ccache (CCACHE) [N/y/?] n
+Compress ramstage with LZMA (COMPRESS_RAMSTAGE) [Y/n/?] y
+*
+* Mainboard
+*
+Mainboard vendor
+  1. Abit (VENDOR_ABIT)
+  2. Advansus (VENDOR_ADVANSUS)
+  3. Advantech (VENDOR_ADVANTECH)
+  4. AMD (VENDOR_AMD)
+  5. Arima (VENDOR_ARIMA)
+  6. Artec Group (VENDOR_ARTEC_GROUP)
+  7. ASI (VENDOR_ASI)
+  8. ASROCK (VENDOR_ASROCK)
+  9. ASUS (VENDOR_ASUS)
+  10. A-Trend (VENDOR_A_TREND)
+  11. Avencall (VENDOR_AVENCALL)
+  12. AXUS (VENDOR_AXUS)
+  13. AZZA (VENDOR_AZZA)
+  14. BCOM (VENDOR_BCOM)
+  15. Biostar (VENDOR_BIOSTAR)
+  16. Broadcom (VENDOR_BROADCOM)
+  17. Compaq (VENDOR_COMPAQ)
+  18. Dell (VENDOR_DELL)
+  19. DIGITAL-LOGIC (VENDOR_DIGITAL_LOGIC)
+  20. EagleLion (VENDOR_EAGLELION)
+  21. ECS (VENDOR_ECS)
+  22. Emulation (VENDOR_EMULATION)
+  23. Getac (VENDOR_GETAC)
+  24. GIGABYTE (VENDOR_GIGABYTE)
+  25. HP (VENDOR_HP)
+  26. iBase (VENDOR_IBASE)
+  27. IBM (VENDOR_IBM)
+  28. IEI (VENDOR_IEI)
+> 29. Intel (VENDOR_INTEL)
+  30. iWave (VENDOR_IWAVE)
+  31. IWILL (VENDOR_IWILL)
+  32. Jetway (VENDOR_JETWAY)
+  33. Kontron (VENDOR_KONTRON)
+  34. Lanner (VENDOR_LANNER)
+  35. Lenovo (VENDOR_LENOVO)
+  36. Lippert (VENDOR_LIPPERT)
+  37. Mitac (VENDOR_MITAC)
+  38. MSI (VENDOR_MSI)
+  39. NEC (VENDOR_NEC)
+  40. Newisys (VENDOR_NEWISYS)
+  41. Nokia (VENDOR_NOKIA)
+  42. NVIDIA (VENDOR_NVIDIA)
+  43. PC Engines (VENDOR_PC_ENGINES)
+  44. RCA (VENDOR_RCA)
+  45. Roda (VENDOR_RODA)
+  46. Siemens (VENDOR_SIEMENS)
+  47. Soyo (VENDOR_SOYO)
+  48. Sun (VENDOR_SUNW)
+  49. Supermicro (VENDOR_SUPERMICRO)
+  50. Technexion (VENDOR_TECHNEXION)
+  51. Technologic (VENDOR_TECHNOLOGIC)
+  52. TeleVideo (VENDOR_TELEVIDEO)
+  53. Thomson (VENDOR_THOMSON)
+  54. Traverse Technologies (VENDOR_TRAVERSE)
+  55. Tyan (VENDOR_TYAN)
+  56. VIA (VENDOR_VIA)
+  57. Win Enterprises (VENDOR_WINENT)
+  58. Wyse (VENDOR_WYSE)
+choice[1-58]: 29
+Mainboard model
+  1. D810E2CB (BOARD_INTEL_D810E2CB)
+  2. D945GCLF (BOARD_INTEL_D945GCLF)
+  3. EagleHeights (BOARD_INTEL_EAGLEHEIGHTS)
+  4. Jarrell (SE7520JR2) (BOARD_INTEL_JARRELL)
+  5. 3100 devkit (Mt. Arvon) (BOARD_INTEL_MTARVON)
+> 6. EP80579 devkit (Truxton) (BOARD_INTEL_TRUXTON)
+  7. XE7501devkit (BOARD_INTEL_XE7501DEVKIT)
+choice[1-7]: 6
+ROM chip size
+  1. 128 KB (COREBOOT_ROMSIZE_KB_128)
+  2. 256 KB (COREBOOT_ROMSIZE_KB_256)
+  3. 512 KB (COREBOOT_ROMSIZE_KB_512)
+  4. 1024 KB (1 MB) (COREBOOT_ROMSIZE_KB_1024)
+> 5. 2048 KB (2 MB) (COREBOOT_ROMSIZE_KB_2048)
+  6. 4096 KB (4 MB) (COREBOOT_ROMSIZE_KB_4096)
+choice[1-6?]: 5
+*
+* Architecture (x86)
+*
+*
+* Chipset
+*
+*
+* CPU
+*
+*
+* Northbridge
+*
+*
+* Southbridge
+*
+*
+* Super I/O
+*
+*
+* Devices
+*
+Setup bridges on path to VGA adapter (VGA_BRIDGE_SETUP) [Y/n/?] y
+Run VGA option ROMs (VGA_ROM_RUN) [Y/n/?] y
+Run non-VGA option ROMs (PCI_ROM_RUN) [Y/n/?] y
+  Option ROM execution type
+  > 1. Native mode (PCI_OPTION_ROM_RUN_REALMODE)
+    2. Secure mode (PCI_OPTION_ROM_RUN_YABEL)
+  choice[1-2]: 1
+*
+* Embedded Controllers
+*
+*
+* Generic Drivers
+*
+Oxford OXPCIe952 (DRIVERS_OXFORD_OXPCIE) [N/y/?] n
+Silicon Image SIL3114 (DRIVERS_SIL_3114) [N/y/?] n
+*
+* Console
+*
+Serial port console output (CONSOLE_SERIAL8250) [Y/n/?] y
+Serial port
+> 1. COM1/ttyS0, I/O port 0x3f8 (CONSOLE_SERIAL_COM1)
+  2. COM2/ttyS1, I/O port 0x2f8 (CONSOLE_SERIAL_COM2)
+  3. COM3/ttyS2, I/O port 0x3e8 (CONSOLE_SERIAL_COM3)
+  4. COM4/ttyS3, I/O port 0x2e8 (CONSOLE_SERIAL_COM4)
+choice[1-4]: 1
+Baud rate
+> 1. 115200 (CONSOLE_SERIAL_115200)
+  2. 57600 (CONSOLE_SERIAL_57600)
+  3. 38400 (CONSOLE_SERIAL_38400)
+  4. 19200 (CONSOLE_SERIAL_19200)
+  5. 9600 (CONSOLE_SERIAL_9600)
+choice[1-5]: 1
+Use onboard VGA as primary video device (ONBOARD_VGA_IS_PRIMARY) [N/y/?] n
+Network console over NE2000 compatible Ethernet adapter (CONSOLE_NE2K) [N/y/?] n
+Maximum console log level
+> 1. 8: SPEW (MAXIMUM_CONSOLE_LOGLEVEL_8)
+  2. 7: DEBUG (MAXIMUM_CONSOLE_LOGLEVEL_7)
+  3. 6: INFO (MAXIMUM_CONSOLE_LOGLEVEL_6)
+  4. 5: NOTICE (MAXIMUM_CONSOLE_LOGLEVEL_5)
+  5. 4: WARNING (MAXIMUM_CONSOLE_LOGLEVEL_4)
+  6. 3: ERR (MAXIMUM_CONSOLE_LOGLEVEL_3)
+  7. 2: CRIT (MAXIMUM_CONSOLE_LOGLEVEL_2)
+  8. 1: ALERT (MAXIMUM_CONSOLE_LOGLEVEL_1)
+  9. 0: EMERG (MAXIMUM_CONSOLE_LOGLEVEL_0)
+choice[1-9]: 1
+Default console log level
+> 1. 8: SPEW (DEFAULT_CONSOLE_LOGLEVEL_8)
+  2. 7: DEBUG (DEFAULT_CONSOLE_LOGLEVEL_7)
+  3. 6: INFO (DEFAULT_CONSOLE_LOGLEVEL_6)
+  4. 5: NOTICE (DEFAULT_CONSOLE_LOGLEVEL_5)
+  5. 4: WARNING (DEFAULT_CONSOLE_LOGLEVEL_4)
+  6. 3: ERR (DEFAULT_CONSOLE_LOGLEVEL_3)
+  7. 2: CRIT (DEFAULT_CONSOLE_LOGLEVEL_2)
+  8. 1: ALERT (DEFAULT_CONSOLE_LOGLEVEL_1)
+  9. 0: EMERG (DEFAULT_CONSOLE_LOGLEVEL_0)
+choice[1-9]: 1
+Don't show any POST codes (NO_POST) [N/y] n
+  Show POST codes on the debug console (CONSOLE_POST) [N/y/?] n
+*
+* System tables
+*
+Write 'high' tables to avoid being overwritten in F segment (WRITE_HIGH_TABLES) [Y/n] y
+Generate Multiboot tables (for GRUB2) (MULTIBOOT) [Y/n] y
+Generate ACPI tables (GENERATE_ACPI_TABLES) [Y/?] y
+*
+* Payload
+*
+Add a payload
+  1. None (PAYLOAD_NONE)
+  2. An ELF executable payload (PAYLOAD_ELF)
+> 3. SeaBIOS (PAYLOAD_SEABIOS)
+  4. FILO (PAYLOAD_FILO)
+choice[1-4]: 3
+SeaBIOS version
+> 1. stable (SEABIOS_STABLE)
+  2. master (SEABIOS_MASTER)
+choice[1-2]: 1
+Use LZMA compression for payloads (COMPRESSED_PAYLOAD_LZMA) [Y/n/?] y
+*
+* VGA BIOS
+*
+Add a VGA BIOS image (VGA_BIOS) [N/y/?] n
+*
+* Debugging
+*
+GDB debugging support (GDB_STUB) [Y/n/?] y
+Output verbose RAM init debug messages (DEBUG_RAM_SETUP) [N/y/?] n
+Output verbose malloc debug messages (DEBUG_MALLOC) [N/y/?] n
+Enable debug messages for option ROM execution (REALMODE_DEBUG) [N/y/?] n
+Built-in low-level shell (LLSHELL) [N/y/?] n
+*
+* Deprecated
+*
+PS/2 keyboard init (DRIVERS_PS2_KEYBOARD) [Y/n/?] y
+#
+# configuration written to .config
+#
+bastien@bastien:~/coreboot$ make clean
+  Working around no -fwhole-program
+bastien@bastien:~/coreboot$ make
+/home/bastien/coreboot/util/crossgcc/xgcc/bin/i386-elf-as: error while loading shared libraries: libz.so.1: cannot open shared object file: No such file or directory
+/home/bastien/coreboot/util/crossgcc/xgcc/bin/i386-elf-as: error while loading shared libraries: libz.so.1: cannot open shared object file: No such file or directory
+    CC         lib/memset.romstage.o
+    CC         lib/memcpy.romstage.o
+    CC         lib/memcmp.romstage.o
+    CC         lib/cbfs.romstage.o
+    CC         lib/lzma.romstage.o
+    CC         lib/ramtest.romstage.o
+    CC         lib/uart8250.romstage.o
+    CC         console/vtxprintf.romstage.o
+    GEN        build.h
+    CC         console/console.romstage.o
+    CC         console/post.romstage.o
+    CC         console/die.romstage.o
+    CC         romstage.inc
+    POST       romstage.inc
+    GEN        crt0.S
+    CC         mainboard/intel/truxton/crt0.s
+    CC         mainboard/intel/truxton/crt0.romstage.o
+    CC         arch/x86/lib/romstage_console.romstage.o
+    CC         arch/x86/lib/cbfs_and_run.romstage.o
+    CC         southbridge/intel/i3100/early_smbus.romstage.o
+    CC         southbridge/intel/i3100/smbus.romstage.o
+    CC         northbridge/intel/i3100/raminit_ep80579.romstage.o
+    LINK       coreboot
+    OBJCOPY    coreboot.bootblock
+    CC         arch/x86/lib/c_start.ramstage.o
+    CC         console/uart8250_console.driver.o
+    CC         southbridge/intel/i3100/i3100.driver.o
+    CC         southbridge/intel/i3100/uhci.driver.o
+    CC         southbridge/intel/i3100/lpc.driver.o
+    CC         southbridge/intel/i3100/sata.driver.o
+    CC         southbridge/intel/i3100/ehci.driver.o
+    CC         southbridge/intel/i3100/smbus.driver.o
+    CC         southbridge/intel/i3100/pci.driver.o
+    CC         northbridge/intel/i3100/northbridge.driver.o
+    CC         northbridge/intel/i3100/pciexp_porta.driver.o
+    CC         northbridge/intel/i3100/pciexp_porta_ep80579.driver.o
+    CC         cpu/intel/ep80579/ep80579_init.driver.o
+    SCONFIG    mainboard/intel/truxton/devicetree.cb
+    CC         mainboard/intel/truxton/static.ramstage.o
+    CC         lib/memset.ramstage.o
+    CC         lib/memcpy.ramstage.o
+    CC         lib/memcmp.ramstage.o
+    CC         lib/memmove.ramstage.o
+    CC         lib/malloc.ramstage.o
+    CC         lib/delay.ramstage.o
+    CC         lib/fallback_boot.ramstage.o
+    CC         lib/compute_ip_checksum.ramstage.o
+    CC         lib/version.ramstage.o
+    CC         lib/cbfs.ramstage.o
+    CC         lib/lzma.ramstage.o
+    CC         lib/gcc.ramstage.o
+    CC         lib/clog2.ramstage.o
+    CC         lib/cbmem.ramstage.o
+    CC         lib/uart8250.ramstage.o
+    CC         boot/hardwaremain.ramstage.o
+    CC         boot/selfboot.ramstage.o
+    CC         console/printk.ramstage.o
+    CC         console/console.ramstage.o
+    CC         console/vtxprintf.ramstage.o
+    CC         console/vsprintf.ramstage.o
+    CC         console/post.ramstage.o
+    CC         console/die.ramstage.o
+    CC         devices/device.ramstage.o
+    CC         devices/root_device.ramstage.o
+    CC         devices/device_util.ramstage.o
+    CC         devices/pci_device.ramstage.o
+    CC         devices/pcix_device.ramstage.o
+    CC         devices/pciexp_device.ramstage.o
+    CC         devices/agp_device.ramstage.o
+    CC         devices/cardbus_device.ramstage.o
+    CC         devices/pnp_device.ramstage.o
+    CC         devices/pci_ops.ramstage.o
+    CC         devices/smbus_ops.ramstage.o
+    CC         devices/pci_rom.ramstage.o
+    CC         mainboard/intel/truxton/mainboard.ramstage.o
+    CC         mainboard/intel/truxton/acpi_tables.ramstage.o
+    IASL       build/mainboard/intel/truxton/dsdt.ramstage.o
+
+Intel ACPI Component Architecture
+ASL Optimizing Compiler version 20100528 [Jul  2 2010]
+Copyright (c) 2000 - 2010 Intel Corporation
+Supports ACPI Specification Revision 4.0a
+
+ASL Input:  dsdt.ramstage.asl - 1006 lines, 21645 bytes, 430 keywords
+AML Output: dsdt.ramstage.aml - 4289 bytes, 211 named objects, 219 executable opcodes
+
+Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 149 Optimizations
+    CC         mainboard/intel/truxton/fadt.ramstage.o
+    CC         pc80/mc146818rtc.ramstage.o
+    CC         pc80/isa-dma.ramstage.o
+    CC         pc80/i8259.ramstage.o
+    CC         pc80/keyboard.ramstage.o
+    CC         devices/oprom/x86.ramstage.o
+    CC         devices/oprom/x86_asm.ramstage.o
+    CC         devices/oprom/x86_interrupts.ramstage.o
+    CC         arch/x86/boot/boot.ramstage.o
+    CC         arch/x86/boot/coreboot_table.ramstage.o
+    CC         arch/x86/boot/multiboot.ramstage.o
+    CC         arch/x86/boot/gdt.ramstage.o
+    CC         arch/x86/boot/tables.ramstage.o
+    CC         arch/x86/boot/acpi.ramstage.o
+    CC         arch/x86/boot/acpigen.ramstage.o
+    CC         arch/x86/lib/cpu.ramstage.o
+    CC         arch/x86/lib/pci_ops_conf1.ramstage.o
+    CC         arch/x86/lib/pci_ops_conf2.ramstage.o
+    CC         arch/x86/lib/pci_ops_mmconf.ramstage.o
+    CC         arch/x86/lib/pci_ops_auto.ramstage.o
+    CC         arch/x86/lib/exception.ramstage.o
+    CC         arch/x86/lib/ioapic.ramstage.o
+    CC         pc80/vga/vga_io.ramstage.o
+    CC         southbridge/intel/i3100/reset.ramstage.o
+    CC         southbridge/intel/i3100/pciexp_portb.ramstage.o
+    CC         superio/intel/i3100/superio.ramstage.o
+    CC         superio/smsc/smscsuperio/superio.ramstage.o
+    CC         cpu/intel/ep80579/ep80579.ramstage.o
+    CC         cpu/x86/tsc/delay_tsc.ramstage.o
+    CC         cpu/x86/mtrr/mtrr.ramstage.o
+    CC         cpu/x86/lapic/lapic.ramstage.o
+    CC         cpu/x86/lapic/lapic_cpu_init.ramstage.o
+    CC         cpu/x86/lapic/secondary.ramstage.o
+    CC         cpu/x86/cache/cache.ramstage.o
+    CC         cpu/intel/microcode/microcode.ramstage.o
+    AR         coreboot.a
+    CC         coreboot_ram.o
+    CC         coreboot_ram
+    GIT        SeaBIOS 1efb10b9ea30c45a8c9c6230234fefa10d2886ed
+Switched to branch 'master'
+Deleted branch coreboot (was 1efb10b).
+Switched to a new branch 'coreboot'
+    CONFIG     SeaBIOS 1efb10b9ea30c45a8c9c6230234fefa10d2886ed
+  Build default config
+#
+# configuration written to /home/bastien/coreboot/payloads/external/SeaBIOS/seabios/.config
+#
+    MAKE       SeaBIOS 1efb10b9ea30c45a8c9c6230234fefa10d2886ed
+  Build Kconfig config file
+/home/bastien/coreboot/payloads/external/SeaBIOS/seabios/.config:75:warning: override: reassigning to symbol COREBOOT
+/home/bastien/coreboot/payloads/external/SeaBIOS/seabios/.config:76:warning: override: reassigning to symbol DEBUG_SERIAL
+#
+# configuration written to /home/bastien/coreboot/payloads/external/SeaBIOS/seabios/.config
+#
+  Compiling whole program out/ccode.16.s
+  Compiling to assembler out/asm-offsets.s
+  Generating offset file out/asm-offsets.h
+  Compiling (16bit) out/code16.o
+  Compiling whole program out/ccode32flat.o
+  Compiling whole program out/code32seg.o
+  Building ld scripts (version "pre-0.6.2-20120531_150337-bastien")
+Fixed space: 0xe05b-0x10000  total: 8101  slack: 16  Percent slack: 0.2%
+16bit size:           39328
+32bit segmented size: 2217
+32bit flat size:      13863
+32bit flat init size: 40416
+  Linking out/rom16.o
+  Stripping out/rom16.strip.o
+  Linking out/rom32seg.o
+  Stripping out/rom32seg.strip.o
+  Linking out/rom.o
+  Prepping out/bios.bin
+Total size: 97148  Fixed: 55420  Free: 33924 (used 74.1% of 128KiB rom)
+    CBFS       coreboot.rom
+    PAYLOAD    SeaBIOS (internal, compression: LZMA)
+    CBFSPRINT  coreboot.rom
+
+coreboot.rom: 2048 kB, bootblocksize 65536, romsize 2097152, offset 0x0
+Alignment: 64 bytes
+
+Name                           Offset     Type         Size
+fallback/coreboot_ram          0x0        stage        38700
+fallback/payload               0x9780     payload      48584
+(empty)                        0x15580    null         1944120
+bastien@bastien:~/coreboot$ cd
+bastien@bastien:~$ cp coreboot/build/coreboot.rom xioh-acceptance/coreboot-pirq- 
+tests/M[C[C[C[C[C[C[C[C[C[C[C[C[C[Cd[K
+
+[KM[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[Cmake cleanoldconfig[1Pcd ~/corebootls[Ksgit commitadd ..commitlss[K[Kcd ~/corebootmake oldconfig[4Pclean[K[2Pcdp coreboot/build/coreboot.rom xioh-acceptance/coreboot-pirq-t
+tests/f5dc42c-iasl20100528
+bastien@bastien:~$ cd xioh-acceptance/coreboot-pirq-tests/"versiontest"[K[K[K[K[K[K[K[K[K[K[K[K[Kf5dc42c-iasl20100528
+bastien@bastien:~/xioh-acceptance/coreboot-pirq-tests/f5dc42c-iasl20100528$ scp  
+coreboot.rom no@192.168.44.2:
+
+coreboot.rom                                    0%    0     0.0KB/s   --:-- ETA
+coreboot.rom                                  100% 2048KB   2.0MB/s   00:00    
+bastien@bastien:~/xioh-acceptance/coreboot-pirq-tests/f5dc42c-iasl20100528$ ssh  
+no@192.168.44.2
+Last login: Thu May 31 14:40:08 2012 from 192.168.44.1
+]0;~
+[32mno@botskath [33m~[0m
+$ dpcmd -v -ucoreboot.rom
+DpCmd 6.0.2.01 Engine Version:  
+Last Built on Sep 30 2011
+
+
+By reading the chip ID, the chip applies to [ 25VF016B 25VF016B ]
+25VF016B parameters to be applied by default
+25VF016B chip size is 2097152 bytes.
+
+
+Loading file, please wait ...(coreboot.rom)
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+Auto Sequences, please wait ...
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+Automatic program OK
+
+Checksum(file): 1E534089
+Checksum(Written part of file): 1E534089
+Verifying, please wait ...
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elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed  9.765s elapsed
+Operation completed. 
+9.859 seconds elapsed.
+
+Error: Verify Failed
+]0;~
+[32mno@botskath [33m~[0m
+$ dpcmd -v -ucoreboot.rom
+DpCmd 6.0.2.01 Engine Version:  
+Last Built on Sep 30 2011
+
+
+By reading the chip ID, the chip applies to [ 25VF016B 25VF016B ]
+25VF016B parameters to be applied by default
+25VF016B chip size is 2097152 bytes.
+
+
+Loading file, please wait ...(coreboot.rom)
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+Automatic program OK
+
+Checksum(file): 1E534089
+Checksum(Written part of file): 1E534089
+Verifying, please wait ...
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elapsed  9.797s elapsed  9.797s elapsed  9.797s elapsed  9.797s elapsed  9.797s elapsed  9.797s elapsed  9.797s elapsed  9.797s elapsed  9.797s elapsed
+Verify OK
+]0;~
+[32mno@botskath [33m~[0m
+$ 
+
+coreboot-4.0-r6637 Thu May 31 15:03:27 CEST 2012 starting...
+SMBus controller enabled
+1 DDR2 SRRAM modules found
+Chosen DRAM speed: DDR2-667 5-5-5
+SKU 1 (with QuickAssist)
+Starting RCVEN calibration and write levelization
+i=0 inc_rcven=01
+good_count=0 delta_rcven=46 inc_rcven=1
+i=1 inc_rcven=01
+i=2 inc_rcven=00
+i=3 inc_rcven=00
+i=4 inc_rcven=00
+i=5 inc_rcven=01
+[23;80H [24;1Hi=6 inc_rcven=01
+[23;80H [24;1Hi=7 inc_rcven=01
+[23;80H [24;1Hi=8 inc_rcven=01
+[23;80H [24;1Hi=9 inc_rcven=01
+[23;80H [24;1Hi=10 inc_rcven=01
+[23;80H [24;1Hi=11 inc_rcven=01
+[23;80H [24;1Hi=12 inc_rcven=01
+[23;80H [24;1Hi=13 inc_rcven=01
+[23;80H [24;1Hi=14 inc_rcven=01
+[23;80H [24;1Hi=15 inc_rcven=01
+[23;80H [24;1Hi=16 inc_rcven=01
+[23;80H [24;1Hi=17 inc_rcven=01
+[23;80H [24;1Hi=18 inc_rcven=01
+[23;80H [24;1Hi=19 inc_rcven=01
+[23;80H [24;1Hgood_count=18 delta_rcven=44 inc_rcven=1
+[23;80H [24;1HFinished RCVEN calibration and write levelization
+[23;80H [24;1HWL_CNTL0=00000922
+[23;80H [24;1HWL_CNTL1=00000922
+[23;80H [24;1HWL_CNTL2=00000922
+[23;80H [24;1HWL_CNTL3=00000922
+[23;80H [24;1HWL_CNTL4=00000920
+[23;80H [24;1HSDRAM initialized
+[23;80H [24;1HEnd of romstage
+[23;80H [24;1HLoading image.
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HStage: loading fallback/coreboot_ram @ 0x100000 (245760 bytes), entry @ 0x10000[24;80H
+[23;80H0[24;1HStage: done loading.
+[23;80H [24;1HJumping to image.
+[23;80H [24;1Hcoreboot-4.0-r6637 Thu May 31 15:03:27 CEST 2012 booting...
+[23;80H [24;1Hclocks_per_usec: 601
+[23;80H [24;1HEnumerating buses...
+[23;80H [24;1HShow all devs...Before device enumeration.
+[23;80H [24;1HRoot Device: enabled 1
+[23;80H [24;1HPCI_DOMAIN: 0000: enabled 1
+[23;80H [24;1HPCI: 00:00.0: enabled 1
+[23;80H [24;1HPCI: 00:00.1: enabled 1
+[23;80H [24;1HPCI: 00:01.0: enabled 1
+[23;80H [24;1HPCI: 00:02.0: enabled 1
+[23;80H [24;1HPCI: 00:03.0: enabled 1
+[23;80H [24;1HPCI: 00:04.0: enabled 1
+[23;80H [24;1HPCI: 00:08.0: enabled 0
+[23;80H [24;1HPCI: 00:0d.0: enabled 0
+[23;80H [24;1HPCI: 00:0d.1: enabled 0
+[23;80H [24;1HPCI: 00:1d.0: enabled 1
+[23;80H [24;1HPCI: 00:1d.7: enabled 1
+[23;80H [24;1HPCI: 00:1f.0: enabled 1
+[23;80H [24;1HPNP: 004e.4: enabled 1
+[23;80H [24;1HPNP: 004e.5: enabled 1
+[23;80H [24;1HPNP: 002e.0: enabled 0
+[23;80H [24;1HPNP: 002e.3: enabled 0
+[23;80H [24;1HPNP: 002e.4: enabled 0
+[23;80H [24;1HPNP: 002e.5: enabled 0
+[23;80H [24;1HPNP: 002e.7: enabled 1
+[23;80H [24;1HPNP: 002e.a: enabled 0
+[23;80H [24;1HPCI: 00:1f.2: enabled 1
+[23;80H [24;1HPCI: 00:1f.3: enabled 1
+[23;80H [24;1HPCI: 00:1f.4: enabled 1
+[23;80H [24;1HAPIC_CLUSTER: 0: enabled 1
+[23;80H [24;1HAPIC: 00: enabled 1
+[23;80H [24;1HCompare with tree...
+[23;80H [24;1HRoot Device: enabled 1
+[23;80H [24;1H PCI_DOMAIN: 0000: enabled 1
+[23;80H [24;1H  PCI: 00:00.0: enabled 1
+[23;80H [24;1H  PCI: 00:00.1: enabled 1
+[23;80H [24;1H  PCI: 00:01.0: enabled 1
+[23;80H [24;1H  PCI: 00:02.0: enabled 1
+[23;80H [24;1H  PCI: 00:03.0: enabled 1
+[23;80H [24;1H  PCI: 00:04.0: enabled 1
+[23;80H [24;1H  PCI: 00:08.0: enabled 0
+[23;80H [24;1H  PCI: 00:0d.0: enabled 0
+[23;80H [24;1H  PCI: 00:0d.1: enabled 0
+[23;80H [24;1H  PCI: 00:1d.0: enabled 1
+[23;80H [24;1H  PCI: 00:1d.7: enabled 1
+[23;80H [24;1H  PCI: 00:1f.0: enabled 1
+[23;80H [24;1H   PNP: 004e.4: enabled 1
+[23;80H [24;1H   PNP: 004e.5: enabled 1
+[23;80H [24;1H   PNP: 002e.0: enabled 0
+[23;80H [24;1H   PNP: 002e.3: enabled 0
+[23;80H [24;1H   PNP: 002e.4: enabled 0
+[23;80H [24;1H   PNP: 002e.5: enabled 0
+[23;80H [24;1H   PNP: 002e.7: enabled 1
+[23;80H [24;1H   PNP: 002e.a: enabled 0
+[23;80H [24;1H  PCI: 00:1f.2: enabled 1
+[23;80H [24;1H  PCI: 00:1f.3: enabled 1
+[23;80H [24;1H  PCI: 00:1f.4: enabled 1
+[23;80H [24;1H APIC_CLUSTER: 0: enabled 1
+[23;80H [24;1H  APIC: 00: enabled 1
+[23;80H [24;1Hscan_static_bus for Root Device
+[23;80H [24;1HPCI_DOMAIN: 0000 enabled
+[23;80H [24;1HAPIC_CLUSTER: 0 enabled
+[23;80H [24;1HPCI_DOMAIN: 0000 scanning...
+[23;80H [24;1HPCI: pci_scan_bus for bus 00
+[23;80H [24;1HPCI: 00:00.0 [8086/5020] enabled
+[23;80H [24;1HPCI: 00:00.1 [8086/5021] enabled
+[23;80H [24;1HPCI: 00:01.0 [8086/5023] enabled
+[23;80H [24;1HPCI: 00:02.0 [8086/5024] bus ops
+[23;80H [24;1HPCI: 00:02.0 [8086/5024] enabled
+[23;80H [24;1HPCI: 00:03.0 [8086/5025] bus ops
+[23;80H [24;1HPCI: 00:03.0 [8086/5025] enabled
+[23;80H [24;1HCapability: type 0x01 @ 0xdc
+[23;80H [24;1HCapability: type 0x01 @ 0xdc
+[23;80H [24;1HPCI: 00:04.0 [8086/5037] enabled
+[23;80H [24;1HPCI: 00:08.0 [8086/5026] disabled
+[23;80H [24;1HPCI: 00:0a.0 [8086/5038] enabled
+[23;80H [24;1HPCI: 00:1d.0 [8086/5033] ops
+[23;80H [24;1HPCI: 00:1d.0 [8086/5033] enabled
+[23;80H [24;1HPCI: 00:1d.7 [8086/5035] ops
+[23;80H [24;1HPCI: 00:1d.7 [8086/5035] enabled
+[23;80H [24;1HPCI: 00:1f.0 [8086/5031] bus ops
+[23;80H [24;1HPCI: 00:1f.0 [8086/5031] enabled
+[23;80H [24;1HPCI: 00:1f.2 [8086/5028] ops
+[23;80H [24;1HPCI: 00:1f.2 [8086/5028] enabled
+[23;80H [24;1HPCI: 00:1f.3 [8086/5032] bus ops
+[23;80H [24;1HPCI: 00:1f.3 [8086/5032] enabled
+[23;80H [24;1HPCI: 00:1f.4 [8086/5036] enabled
+[23;80H [24;1Hpcie porta 0x76: 1001
+[23;80H [24;1Hdo_pci_scan_bridge for PCI: 00:02.0
+[23;80H [24;1HPCI: pci_scan_bus for bus 01
+[23;80H [24;1HPCI: Using configuration type 1
+[23;80H [24;1HPCI: pci_scan_bus returning with max=001
+[23;80H [24;1Hdo_pci_scan_bridge returns max 1
+[23;80H [24;1Hpcie porta 0x76: 1001
+[23;80H [24;1Hdo_pci_scan_bridge for PCI: 00:03.0
+[23;80H [24;1HPCI: pci_scan_bus for bus 02
+[23;80H [24;1HPCI: pci_scan_bus returning with max=002
+[23;80H [24;1Hdo_pci_scan_bridge returns max 2
+[23;80H [24;1Hdo_pci_scan_bridge for PCI: 00:04.0
+[23;80H [24;1HPCI: pci_scan_bus for bus 03
+[23;80H [24;1HPCI: 03:00.0 [8086/5041] enabled
+[23;80H [24;1HPCI: 03:01.0 [8086/5045] enabled
+[23;80H [24;1HPCI: 03:02.0 [8086/5049] enabled
+[23;80H [24;1HPCI: 03:03.0 [8086/503e] enabled
+[23;80H [24;1HPCI: 03:04.0 [8086/5039] enabled
+[23;80H [24;1HPCI: 03:05.0 [8086/503a] enabled
+[23;80H [24;1HPCI: 03:06.0 [8086/503b] enabled
+[23;80H [24;1HPCI: 03:07.0 [8086/503c] enabled
+[23;80H [24;1HPCI: 03:08.0 [8086/503d] enabled
+[23;80H [24;1HPCI: 03:09.0 [8086/502d] enabled
+[23;80H [24;1HPCI: 03:0a.0 [8086/503f] enabled
+[23;80H [24;1HPCI: 03:0b.0 [8086/504c] enabled
+[23;80H [24;1HPCI: 03:0c.0 [8086/5030] enabled
+[23;80H [24;1HPCI: pci_scan_bus returning with max=003
+[23;80H [24;1Hdo_pci_scan_bridge returns max 3
+[23;80H [24;1Hscan_static_bus for PCI: 00:1f.0
+[23;80H [24;1HPNP: 004e.4 enabled
+[23;80H [24;1HPNP: 004e.5 enabled
+[23;80H [24;1HFound SMSC Super I/O (ID=0xff, rev=0xff)
+[23;80H [24;1HPNP: 002e.0 disabled
+[23;80H [24;1HPNP: 002e.3 disabled
+[23;80H [24;1HPNP: 002e.4 disabled
+[23;80H [24;1HPNP: 002e.5 disabled
+[23;80H [24;1HPNP: 002e.7 enabled
+[23;80H [24;1HPNP: 002e.a disabled
+[23;80H [24;1Hscan_static_bus for PCI: 00:1f.0 done
+[23;80H [24;1Hscan_static_bus for PCI: 00:1f.3
+[23;80H [24;1Hscan_static_bus for PCI: 00:1f.3 done
+[23;80H [24;1HPCI: pci_scan_bus returning with max=003
+[23;80H [24;1Hscan_static_bus for Root Device done
+[23;80H [24;1Hdone
+[23;80H [24;1HAllocating resources...
+[23;80H [24;1HReading resources...
+[23;80H [24;1HRoot Device read_resources bus 0 link: 0
+[23;80H [24;1HPCI_DOMAIN: 0000 read_resources bus 0 link: 0
+[23;80H [24;1HPCI: 00:02.0 read_resources bus 1 link: 0
+[23;80H [24;1HPCI: 00:02.0 read_resources bus 1 link: 0 done
+[23;80H [24;1HPCI: 00:03.0 read_resources bus 2 link: 0
+[23;80H [24;1HPCI: 00:03.0 read_resources bus 2 link: 0 done
+[23;80H [24;1HPCI: 00:04.0 read_resources bus 3 link: 0
+[23;80H [24;1HPCI: 00:04.0 read_resources bus 3 link: 0 done
+[23;80H [24;1HPCI: 00:1f.0 read_resources bus 0 link: 0
+[23;80H [24;1HPNP: 002e.7 missing read_resources
+[23;80H [24;1HPCI: 00:1f.0 read_resources bus 0 link: 0 done
+[23;80H [24;1HPCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
+[23;80H [24;1HAPIC_CLUSTER: 0 read_resources bus 0 link: 0
+[23;80H [24;1HAPIC: 00 missing read_resources
+[23;80H [24;1HAPIC_CLUSTER: 0 read_resources bus 0 link: 0 done
+[23;80H [24;1HRoot Device read_resources bus 0 link: 0 done
+[23;80H [24;1HDone reading resources.
+[23;80H [24;1HShow resources in subtree (Root Device)...After reading.
+[23;80H [24;1H Root Device child on link 0 PCI_DOMAIN: 0000
+[23;80H [24;1H  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
+[23;80H [24;1H  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 4[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:00.0
+[23;80H [24;1H   PCI: 00:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:00.1
+[23;80H [24;1H   PCI: 00:01.0
+[23;80H [24;1H   PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:02.0
+[23;80H [24;1H   PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit fffffffff flags 8[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:03.0
+[23;80H [24;1H   PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit fffffffff flags 8[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:04.0 child on link 0 PCI: 03:00.0
+[23;80H [24;1H   PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit fffffffff flags 8[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:00.0
+[23;80H [24;1H    PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff fla[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:01.0
+[23;80H [24;1H    PCI: 03:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff fla[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:01.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:02.0
+[23;80H [24;1H    PCI: 03:02.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff fla[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:02.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:03.0
+[23;80H [24;1H    PCI: 03:03.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:04.0
+[23;80H [24;1H    PCI: 03:04.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
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+[23;80H [24;1H    PCI: 03:05.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
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+[23;80H [24;1H    PCI: 03:06.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
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+[23;80H [24;1H    PCI: 03:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
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+[23;80H0[24;1H   PCI: 00:08.0
+[23;80H [24;1H   PCI: 00:0a.0
+[23;80H [24;1H   PCI: 00:0a.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:0a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:0a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H8[24;1H   PCI: 00:0a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:0d.0
+[23;80H [24;1H   PCI: 00:0d.1
+[23;80H [24;1H   PCI: 00:1d.0
+[23;80H [24;1H   PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1d.7
+[23;80H [24;1H   PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.0 child on link 0 PNP: 004e.4
+[23;80H [24;1H   PCI: 00:1f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 ind[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 ind[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H8[24;1H   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H3[24;1H   PCI: 00:1f.0 resource base 0 size 4000 align 14 gran 14 limit ffffc000 flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 004e.4
+[23;80H [24;1H    PNP: 004e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c000010[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 004e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 004e.5
+[23;80H [24;1H    PNP: 004e.5 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c000010[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 004e.5 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 002e.0
+[23;80H [24;1H    PNP: 002e.3
+[23;80H [24;1H    PNP: 002e.4
+[23;80H [24;1H    PNP: 002e.5
+[23;80H [24;1H    PNP: 002e.7
+[23;80H [24;1H    PNP: 002e.7 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 i[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 002e.7 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 i[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H2[24;1H    PNP: 002e.7 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 002e.7 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H2[24;1H    PNP: 002e.a
+[23;80H [24;1H   PCI: 00:1f.2
+[23;80H [24;1H   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 inde[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde[24;80H[24;80H[24;80H[24;80H
+[23;80H8[24;1H   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 inde[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 ind[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:1f.3
+[23;80H [24;1H   PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.4
+[23;80H [24;1H   PCI: 00:1f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H  APIC_CLUSTER: 0 child on link 0 APIC: 00
+[23;80H [24;1H   APIC: 00
+[23;80H [24;1HPCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: [24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ff[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ff[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ff[24;80H[24;80H
+[23;80Hf[24;1HPCI: 03:00.0 14 *  [0x0 - 0x1f] io
+[23;80H [24;1HPCI: 03:01.0 14 *  [0x20 - 0x3f] io
+[23;80H [24;1HPCI: 03:02.0 14 *  [0x40 - 0x5f] io
+[23;80H [24;1HPCI: 00:04.0 compute_resources_io: base: 60 size: 1000 align: 12 gran: 12 limit[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:04.0 1c *  [0x0 - 0xfff] io
+[23;80H [24;1HPCI: 00:1f.0 40 *  [0x1000 - 0x107f] io
+[23;80H [24;1HPCI: 00:1f.0 48 *  [0x1080 - 0x10bf] io
+[23;80H [24;1HPCI: 00:1d.0 20 *  [0x10c0 - 0x10df] io
+[23;80H [24;1HPCI: 00:1f.3 20 *  [0x10e0 - 0x10ff] io
+[23;80H [24;1HPCI: 00:1f.2 20 *  [0x1400 - 0x140f] io
+[23;80H [24;1HPCI: 00:1f.2 10 *  [0x1410 - 0x1417] io
+[23;80H [24;1HPCI: 00:1f.2 18 *  [0x1418 - 0x141f] io
+[23;80H [24;1HPCI: 00:1f.2 14 *  [0x1420 - 0x1423] io
+[23;80H [24;1HPCI: 00:1f.2 1c *  [0x1424 - 0x1427] io
+[23;80H [24;1HPCI_DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12 gran: 0 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limi[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limi[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limi[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limi[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limi[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limi[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 03:08.0 14 *  [0x0 - 0x1ffffff] mem
+[23;80H [24;1HPCI: 03:0a.0 18 *  [0x2000000 - 0x203ffff] mem
+[23;80H [24;1HPCI: 03:00.0 10 *  [0x2040000 - 0x205ffff] mem
+[23;80H [24;1HPCI: 03:01.0 10 *  [0x2060000 - 0x207ffff] mem
+[23;80H [24;1HPCI: 03:02.0 10 *  [0x2080000 - 0x209ffff] mem
+[23;80H [24;1HPCI: 03:09.0 14 *  [0x20a0000 - 0x20a3fff] mem
+[23;80H [24;1HPCI: 03:09.0 18 *  [0x20a4000 - 0x20a7fff] mem
+[23;80H [24;1HPCI: 03:0a.0 10 *  [0x20a8000 - 0x20abfff] mem
+[23;80H [24;1HPCI: 03:09.0 10 *  [0x20ac000 - 0x20adfff] mem
+[23;80H [24;1HPCI: 03:0c.0 10 *  [0x20ae000 - 0x20affff] mem
+[23;80H [24;1HPCI: 03:03.0 10 *  [0x20b0000 - 0x20b0fff] mem
+[23;80H [24;1HPCI: 03:04.0 10 *  [0x20b1000 - 0x20b1fff] mem
+[23;80H [24;1HPCI: 03:05.0 10 *  [0x20b2000 - 0x20b2fff] mem
+[23;80H [24;1HPCI: 03:06.0 10 *  [0x20b3000 - 0x20b3fff] mem
+[23;80H [24;1HPCI: 03:07.0 10 *  [0x20b4000 - 0x20b4fff] mem
+[23;80H [24;1HPCI: 03:08.0 10 *  [0x20b5000 - 0x20b5fff] mem
+[23;80H [24;1HPCI: 03:09.0 1c *  [0x20b6000 - 0x20b6fff] mem
+[23;80H [24;1HPCI: 03:0a.0 14 *  [0x20b7000 - 0x20b7fff] mem
+[23;80H [24;1HPCI: 03:0b.0 10 *  [0x20b8000 - 0x20b8fff] mem
+[23;80H [24;1HPCI: 03:0b.0 14 *  [0x20b9000 - 0x20b9fff] mem
+[23;80H [24;1HPCI: 00:04.0 compute_resources_mem: base: 20ba000 size: 2100000 align: 25 gran:[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:04.0 20 *  [0x0 - 0x20fffff] mem
+[23;80H [24;1HPCI: 00:1f.0 f0 *  [0x2100000 - 0x2103fff] mem
+[23;80H [24;1HPCI: 00:0a.0 10 *  [0x2104000 - 0x2105fff] mem
+[23;80H [24;1HPCI: 00:00.0 14 *  [0x2106000 - 0x2106fff] mem
+[23;80H [24;1HPCI: 00:01.0 10 *  [0x2107000 - 0x2107fff] mem
+[23;80H [24;1HPCI: 00:0a.0 14 *  [0x2108000 - 0x2108fff] mem
+[23;80H [24;1HPCI: 00:0a.0 18 *  [0x2109000 - 0x2109fff] mem
+[23;80H [24;1HPCI: 00:0a.0 1c *  [0x210a000 - 0x210afff] mem
+[23;80H [24;1HPCI: 00:1f.4 10 *  [0x210b000 - 0x210bfff] mem
+[23;80H [24;1HPCI: 00:1d.7 10 *  [0x210c000 - 0x210c3ff] mem
+[23;80H [24;1HPCI: 00:1f.2 24 *  [0x210c400 - 0x210c7ff] mem
+[23;80H [24;1HPCI_DOMAIN: 0000 compute_resources_mem: base: 210c800 size: 210c800 align: 25 g[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1Havoid_fixed_resources: PCI_DOMAIN: 0000
+[23;80H [24;1Havoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
+[23;80H [24;1Havoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffc000
+[23;80H [24;1Hconstrain_resources: PCI_DOMAIN: 0000
+[23;80H [24;1Hconstrain_resources: PCI: 00:00.0
+[23;80H [24;1Hconstrain_resources: PCI: 00:00.1
+[23;80H [24;1Hconstrain_resources: PCI: 00:01.0
+[23;80H [24;1Hconstrain_resources: PCI: 00:02.0
+[23;80H [24;1Hconstrain_resources: PCI: 00:03.0
+[23;80H [24;1Hconstrain_resources: PCI: 00:04.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:00.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:01.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:02.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:03.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:04.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:05.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:06.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:07.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:08.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:09.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:0a.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:0b.0
+[23;80H [24;1Hconstrain_resources: PCI: 03:0c.0
+[23;80H [24;1Hconstrain_resources: PCI: 00:0a.0
+[23;80H [24;1Hconstrain_resources: PCI: 00:1d.0
+[23;80H [24;1Hconstrain_resources: PCI: 00:1d.7
+[23;80H [24;1Hconstrain_resources: PCI: 00:1f.0
+[23;80H [24;1Hconstrain_resources: PNP: 004e.4
+[23;80H [24;1Hconstrain_resources: PNP: 004e.5
+[23;80H [24;1Hconstrain_resources: PNP: 002e.7
+[23;80H [24;1Hskipping PNP: 002e.7@60 fixed resource, size=0!
+[23;80H [24;1Hskipping PNP: 002e.7@62 fixed resource, size=0!
+[23;80H [24;1Hskipping PNP: 002e.7@70 fixed resource, size=0!
+[23;80H [24;1Hskipping PNP: 002e.7@72 fixed resource, size=0!
+[23;80H [24;1Hconstrain_resources: PCI: 00:1f.2
+[23;80H [24;1Hconstrain_resources: PCI: 00:1f.3
+[23;80H [24;1Hconstrain_resources: PCI: 00:1f.4
+[23;80H [24;1Havoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
+[23;80H [24;1H[24;9Hlim->base 00001000 lim->limit 0000ffff
+[23;80H [24;1Havoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffc000
+[23;80H [24;1H[24;9Hlim->base 00000000 lim->limit febfffff
+[23;80H [24;1HSetting resources...
+[23;80H [24;1HPCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12 gran:0 lim[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HAssigned: PCI: 00:04.0 1c *  [0x1000 - 0x1fff] io
+[23;80H [24;1HAssigned: PCI: 00:1f.0 40 *  [0x2000 - 0x207f] io
+[23;80H [24;1HAssigned: PCI: 00:1f.0 48 *  [0x2080 - 0x20bf] io
+[23;80H [24;1HAssigned: PCI: 00:1d.0 20 *  [0x20c0 - 0x20df] io
+[23;80H [24;1HAssigned: PCI: 00:1f.3 20 *  [0x20e0 - 0x20ff] io
+[23;80H [24;1HAssigned: PCI: 00:1f.2 20 *  [0x2400 - 0x240f] io
+[23;80H [24;1HAssigned: PCI: 00:1f.2 10 *  [0x2410 - 0x2417] io
+[23;80H [24;1HAssigned: PCI: 00:1f.2 18 *  [0x2418 - 0x241f] io
+[23;80H [24;1HAssigned: PCI: 00:1f.2 14 *  [0x2420 - 0x2423] io
+[23;80H [24;1HAssigned: PCI: 00:1f.2 1c *  [0x2424 - 0x2427] io
+[23;80H [24;1HPCI_DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428 align: 12 gr[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:02.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:fff[24;80H
+[23;80Hf[24;1HPCI: 00:02.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 [24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:03.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:fff[24;80H
+[23;80Hf[24;1HPCI: 00:03.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 [24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HAssigned: PCI: 03:00.0 14 *  [0x1000 - 0x101f] io
+[23;80H [24;1HAssigned: PCI: 03:01.0 14 *  [0x1020 - 0x103f] io
+[23;80H [24;1HAssigned: PCI: 03:02.0 14 *  [0x1040 - 0x105f] io
+[23;80H [24;1HPCI: 00:04.0 allocate_resources_io: next_base: 1060 size: 1000 align: 12 gran: [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:210c800 align:25 gr[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HAssigned: PCI: 00:04.0 20 *  [0xfc000000 - 0xfe0fffff] mem
+[23;80H [24;1HAssigned: PCI: 00:1f.0 f0 *  [0xfe100000 - 0xfe103fff] mem
+[23;80H [24;1HAssigned: PCI: 00:0a.0 10 *  [0xfe104000 - 0xfe105fff] mem
+[23;80H [24;1HAssigned: PCI: 00:00.0 14 *  [0xfe106000 - 0xfe106fff] mem
+[23;80H [24;1HAssigned: PCI: 00:01.0 10 *  [0xfe107000 - 0xfe107fff] mem
+[23;80H [24;1HAssigned: PCI: 00:0a.0 14 *  [0xfe108000 - 0xfe108fff] mem
+[23;80H [24;1HAssigned: PCI: 00:0a.0 18 *  [0xfe109000 - 0xfe109fff] mem
+[23;80H [24;1HAssigned: PCI: 00:0a.0 1c *  [0xfe10a000 - 0xfe10afff] mem
+[23;80H [24;1HAssigned: PCI: 00:1f.4 10 *  [0xfe10b000 - 0xfe10bfff] mem
+[23;80H [24;1HAssigned: PCI: 00:1d.7 10 *  [0xfe10c000 - 0xfe10c3ff] mem
+[23;80H [24;1HAssigned: PCI: 00:1f.2 24 *  [0xfe10c400 - 0xfe10c7ff] mem
+[23;80H [24;1HPCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe10c800 size: 210c800 alig[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:02.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:02.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:02.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limi[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:02.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:03.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:03.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:03.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limi[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:03.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:04.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HPCI: 00:04.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HPCI: 00:04.0 allocate_resources_mem: base:fc000000 size:2100000 align:25 gran:2[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hf[24;1HAssigned: PCI: 03:08.0 14 *  [0xfc000000 - 0xfdffffff] mem
+[23;80H [24;1HAssigned: PCI: 03:0a.0 18 *  [0xfe000000 - 0xfe03ffff] mem
+[23;80H [24;1HAssigned: PCI: 03:00.0 10 *  [0xfe040000 - 0xfe05ffff] mem
+[23;80H [24;1HAssigned: PCI: 03:01.0 10 *  [0xfe060000 - 0xfe07ffff] mem
+[23;80H [24;1HAssigned: PCI: 03:02.0 10 *  [0xfe080000 - 0xfe09ffff] mem
+[23;80H [24;1HAssigned: PCI: 03:09.0 14 *  [0xfe0a0000 - 0xfe0a3fff] mem
+[23;80H [24;1HAssigned: PCI: 03:09.0 18 *  [0xfe0a4000 - 0xfe0a7fff] mem
+[23;80H [24;1HAssigned: PCI: 03:0a.0 10 *  [0xfe0a8000 - 0xfe0abfff] mem
+[23;80H [24;1HAssigned: PCI: 03:09.0 10 *  [0xfe0ac000 - 0xfe0adfff] mem
+[23;80H [24;1HAssigned: PCI: 03:0c.0 10 *  [0xfe0ae000 - 0xfe0affff] mem
+[23;80H [24;1HAssigned: PCI: 03:03.0 10 *  [0xfe0b0000 - 0xfe0b0fff] mem
+[23;80H [24;1HAssigned: PCI: 03:04.0 10 *  [0xfe0b1000 - 0xfe0b1fff] mem
+[23;80H [24;1HAssigned: PCI: 03:05.0 10 *  [0xfe0b2000 - 0xfe0b2fff] mem
+[23;80H [24;1HAssigned: PCI: 03:06.0 10 *  [0xfe0b3000 - 0xfe0b3fff] mem
+[23;80H [24;1HAssigned: PCI: 03:07.0 10 *  [0xfe0b4000 - 0xfe0b4fff] mem
+[23;80H [24;1HAssigned: PCI: 03:08.0 10 *  [0xfe0b5000 - 0xfe0b5fff] mem
+[23;80H [24;1HAssigned: PCI: 03:09.0 1c *  [0xfe0b6000 - 0xfe0b6fff] mem
+[23;80H [24;1HAssigned: PCI: 03:0a.0 14 *  [0xfe0b7000 - 0xfe0b7fff] mem
+[23;80H [24;1HAssigned: PCI: 03:0b.0 10 *  [0xfe0b8000 - 0xfe0b8fff] mem
+[23;80H [24;1HAssigned: PCI: 03:0b.0 14 *  [0xfe0b9000 - 0xfe0b9fff] mem
+[23;80H [24;1HPCI: 00:04.0 allocate_resources_mem: next_base: fe0ba000 size: 2100000 align: 2[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80He[24;1HRoot Device assign_resources, bus 0 link: 0
+[23;80H [24;1HPCI mem marker = fc000000
+[23;80H [24;1HPCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
+[23;80H [24;1HPCI: 00:00.0 14 <- [0x00fe106000 - 0x00fe106fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 00:01.0 10 <- [0x00fe107000 - 0x00fe107fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus [24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Ho[24;1HPCI: 00:02.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hm[24;1HPCI: 00:02.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hm[24;1HPCI: 00:03.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus [24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Ho[24;1HPCI: 00:03.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hm[24;1HPCI: 00:03.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hm[24;1HPCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus [24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Ho[24;1HPCI: 00:04.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hm[24;1HPCI: 00:04.0 20 <- [0x00fc000000 - 0x00fe0fffff] size 0x02100000 gran 0x14 bus [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hm[24;1HPCI: 00:04.0 assign_resources, bus 3 link: 0
+[23;80H [24;1HPCI: 03:00.0 10 <- [0x00fe040000 - 0x00fe05ffff] size 0x00020000 gran 0x11 mem
+[23;80H [24;1HPCI: 03:00.0 14 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
+[23;80H [24;1HPCI: 03:01.0 10 <- [0x00fe060000 - 0x00fe07ffff] size 0x00020000 gran 0x11 mem
+[23;80H [24;1HPCI: 03:01.0 14 <- [0x0000001020 - 0x000000103f] size 0x00000020 gran 0x05 io
+[23;80H [24;1HPCI: 03:02.0 10 <- [0x00fe080000 - 0x00fe09ffff] size 0x00020000 gran 0x11 mem
+[23;80H [24;1HPCI: 03:02.0 14 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
+[23;80H [24;1HPCI: 03:03.0 10 <- [0x00fe0b0000 - 0x00fe0b0fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:04.0 10 <- [0x00fe0b1000 - 0x00fe0b1fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:05.0 10 <- [0x00fe0b2000 - 0x00fe0b2fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:06.0 10 <- [0x00fe0b3000 - 0x00fe0b3fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:07.0 10 <- [0x00fe0b4000 - 0x00fe0b4fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:08.0 10 <- [0x00fe0b5000 - 0x00fe0b5fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:08.0 14 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 mem
+[23;80H [24;1HPCI: 03:09.0 10 <- [0x00fe0ac000 - 0x00fe0adfff] size 0x00002000 gran 0x0d mem
+[23;80H [24;1HPCI: 03:09.0 14 <- [0x00fe0a0000 - 0x00fe0a3fff] size 0x00004000 gran 0x0e mem
+[23;80H [24;1HPCI: 03:09.0 18 <- [0x00fe0a4000 - 0x00fe0a7fff] size 0x00004000 gran 0x0e mem
+[23;80H [24;1HPCI: 03:09.0 1c <- [0x00fe0b6000 - 0x00fe0b6fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:0a.0 10 <- [0x00fe0a8000 - 0x00fe0abfff] size 0x00004000 gran 0x0e mem
+[23;80H [24;1HPCI: 03:0a.0 14 <- [0x00fe0b7000 - 0x00fe0b7fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:0a.0 18 <- [0x00fe000000 - 0x00fe03ffff] size 0x00040000 gran 0x12 mem
+[23;80H [24;1HPCI: 03:0b.0 10 <- [0x00fe0b8000 - 0x00fe0b8fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:0b.0 14 <- [0x00fe0b9000 - 0x00fe0b9fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 03:0c.0 10 <- [0x00fe0ae000 - 0x00fe0affff] size 0x00002000 gran 0x0d mem
+[23;80H [24;1HPCI: 00:04.0 assign_resources, bus 3 link: 0
+[23;80H [24;1HPCI: 00:0a.0 10 <- [0x00fe104000 - 0x00fe105fff] size 0x00002000 gran 0x0d mem
+[23;80H [24;1HPCI: 00:0a.0 14 <- [0x00fe108000 - 0x00fe108fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 00:0a.0 18 <- [0x00fe109000 - 0x00fe109fff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 00:0a.0 1c <- [0x00fe10a000 - 0x00fe10afff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI: 00:1d.0 20 <- [0x00000020c0 - 0x00000020df] size 0x00000020 gran 0x05 io
+[23;80H [24;1HPCI: 00:1d.7 10 <- [0x00fe10c000 - 0x00fe10c3ff] size 0x00000400 gran 0x0a mem
+[23;80H [24;1HPCI: 00:1f.0 40 <- [0x0000002000 - 0x000000207f] size 0x00000080 gran 0x07 io
+[23;80H [24;1HPCI: 00:1f.0 48 <- [0x0000002080 - 0x00000020bf] size 0x00000040 gran 0x06 io
+[23;80H [24;1HPCI: 00:1f.0 f0 <- [0x00fe100000 - 0x00fe103fff] size 0x00004000 gran 0x0e mem
+[23;80H [24;1HPCI: 00:1f.0 assign_resources, bus 0 link: 0
+[23;80H [24;1HPNP: 004e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
+[23;80H [24;1HPNP: 004e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
+[23;80H [24;1HPNP: 004e.5 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
+[23;80H [24;1HPNP: 004e.5 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
+[23;80H [24;1HPNP: 002e.7 missing set_resources
+[23;80H [24;1HPCI: 00:1f.0 assign_resources, bus 0 link: 0
+[23;80H [24;1HPCI: 00:1f.2 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03 io
+[23;80H [24;1HPCI: 00:1f.2 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02 io
+[23;80H [24;1HPCI: 00:1f.2 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03 io
+[23;80H [24;1HPCI: 00:1f.2 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02 io
+[23;80H [24;1HPCI: 00:1f.2 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04 io
+[23;80H [24;1HPCI: 00:1f.2 24 <- [0x00fe10c400 - 0x00fe10c7ff] size 0x00000400 gran 0x0a mem
+[23;80H [24;1HPCI: 00:1f.3 20 <- [0x00000020e0 - 0x00000020ff] size 0x00000020 gran 0x05 io
+[23;80H [24;1HPCI: 00:1f.4 10 <- [0x00fe10b000 - 0x00fe10bfff] size 0x00001000 gran 0x0c mem
+[23;80H [24;1HPCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
+[23;80H [24;1HRoot Device assign_resources, bus 0 link: 0
+[23;80H [24;1HDone setting resources.
+[23;80H [24;1HShow resources in subtree (Root Device)...After assigning values.
+[23;80H [24;1H Root Device child on link 0 PCI_DOMAIN: 0000
+[23;80H [24;1H  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
+[23;80H [24;1H  PCI_DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff flag[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H  PCI_DOMAIN: 0000 resource base fc000000 size 210c800 align 25 gran 0 limit fe[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H3[24;1H  PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 fla[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:00.0
+[23;80H [24;1H   PCI: 00:00.0 resource base fe106000 size 1000 align 12 gran 12 limit febffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:00.1
+[23;80H [24;1H   PCI: 00:01.0
+[23;80H [24;1H   PCI: 00:01.0 resource base fe107000 size 1000 align 12 gran 12 limit febffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:02.0
+[23;80H [24;1H   PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 600[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:03.0
+[23;80H [24;1H   PCI: 00:03.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 600[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:04.0 child on link 0 PCI: 03:00.0
+[23;80H [24;1H   PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags [24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:04.0 resource base febfffff size 0 align 20 gran 20 limit febfffff f[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:04.0 resource base fc000000 size 2100000 align 25 gran 20 limit febf[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:00.0
+[23;80H [24;1H    PCI: 03:00.0 resource base fe040000 size 20000 align 17 gran 17 limit febff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:00.0 resource base 1000 size 20 align 5 gran 5 limit ffff flags 600[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:01.0
+[23;80H [24;1H    PCI: 03:01.0 resource base fe060000 size 20000 align 17 gran 17 limit febff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:01.0 resource base 1020 size 20 align 5 gran 5 limit ffff flags 600[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:02.0
+[23;80H [24;1H    PCI: 03:02.0 resource base fe080000 size 20000 align 17 gran 17 limit febff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:02.0 resource base 1040 size 20 align 5 gran 5 limit ffff flags 600[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:03.0
+[23;80H [24;1H    PCI: 03:03.0 resource base fe0b0000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:04.0
+[23;80H [24;1H    PCI: 03:04.0 resource base fe0b1000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:05.0
+[23;80H [24;1H    PCI: 03:05.0 resource base fe0b2000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:06.0
+[23;80H [24;1H    PCI: 03:06.0 resource base fe0b3000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:07.0
+[23;80H [24;1H    PCI: 03:07.0 resource base fe0b4000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:08.0
+[23;80H [24;1H    PCI: 03:08.0 resource base fe0b5000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:08.0 resource base fc000000 size 2000000 align 25 gran 25 limit feb[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:09.0
+[23;80H [24;1H    PCI: 03:09.0 resource base fe0ac000 size 2000 align 13 gran 13 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:09.0 resource base fe0a0000 size 4000 align 14 gran 14 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:09.0 resource base fe0a4000 size 4000 align 14 gran 14 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H8[24;1H    PCI: 03:09.0 resource base fe0b6000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H    PCI: 03:0a.0
+[23;80H [24;1H    PCI: 03:0a.0 resource base fe0a8000 size 4000 align 14 gran 14 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:0a.0 resource base fe0b7000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:0a.0 resource base fe000000 size 40000 align 18 gran 18 limit febff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H8[24;1H    PCI: 03:0b.0
+[23;80H [24;1H    PCI: 03:0b.0 resource base fe0b8000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PCI: 03:0b.0 resource base fe0b9000 size 1000 align 12 gran 12 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H    PCI: 03:0c.0
+[23;80H [24;1H    PCI: 03:0c.0 resource base fe0ae000 size 2000 align 13 gran 13 limit febfff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:08.0
+[23;80H [24;1H   PCI: 00:0a.0
+[23;80H [24;1H   PCI: 00:0a.0 resource base fe104000 size 2000 align 13 gran 13 limit febffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:0a.0 resource base fe108000 size 1000 align 12 gran 12 limit febffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:0a.0 resource base fe109000 size 1000 align 12 gran 12 limit febffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H8[24;1H   PCI: 00:0a.0 resource base fe10a000 size 1000 align 12 gran 12 limit febffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:0d.0
+[23;80H [24;1H   PCI: 00:0d.1
+[23;80H [24;1H   PCI: 00:1d.0
+[23;80H [24;1H   PCI: 00:1d.0 resource base 20c0 size 20 align 5 gran 5 limit ffff flags 6000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1d.7
+[23;80H [24;1H   PCI: 00:1d.7 resource base fe10c000 size 400 align 10 gran 10 limit febfffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.0 child on link 0 PNP: 004e.4
+[23;80H [24;1H   PCI: 00:1f.0 resource base 2000 size 80 align 7 gran 7 limit ffff flags 6000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.0 resource base 2080 size 40 align 6 gran 6 limit ffff flags 6000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H8[24;1H   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H3[24;1H   PCI: 00:1f.0 resource base fe100000 size 4000 align 14 gran 14 limit febffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 004e.4
+[23;80H [24;1H    PNP: 004e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e000010[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 004e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 004e.5
+[23;80H [24;1H    PNP: 004e.5 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e000010[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 004e.5 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 002e.0
+[23;80H [24;1H    PNP: 002e.3
+[23;80H [24;1H    PNP: 002e.4
+[23;80H [24;1H    PNP: 002e.5
+[23;80H [24;1H    PNP: 002e.7
+[23;80H [24;1H    PNP: 002e.7 resource base 60 size 0 align 0 gran 0 limit 0 flags c0000100 i[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 002e.7 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 i[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H2[24;1H    PNP: 002e.7 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H    PNP: 002e.7 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 in[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H2[24;1H    PNP: 002e.a
+[23;80H [24;1H   PCI: 00:1f.2
+[23;80H [24;1H   PCI: 00:1f.2 resource base 2410 size 8 align 3 gran 3 limit ffff flags 60000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.2 resource base 2420 size 4 align 2 gran 2 limit ffff flags 60000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:1f.2 resource base 2418 size 8 align 3 gran 3 limit ffff flags 60000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H8[24;1H   PCI: 00:1f.2 resource base 2424 size 4 align 2 gran 2 limit ffff flags 60000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80Hc[24;1H   PCI: 00:1f.2 resource base 2400 size 10 align 4 gran 4 limit ffff flags 6000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.2 resource base fe10c400 size 400 align 10 gran 10 limit febfffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H4[24;1H   PCI: 00:1f.3
+[23;80H [24;1H   PCI: 00:1f.3 resource base 20e0 size 20 align 5 gran 5 limit ffff flags 6000[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H   PCI: 00:1f.4
+[23;80H [24;1H   PCI: 00:1f.4 resource base fe10b000 size 1000 align 12 gran 12 limit febffff[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1H  APIC_CLUSTER: 0 child on link 0 APIC: 00
+[23;80H [24;1H   APIC: 00
+[23;80H [24;1HDone allocating resources.
+[23;80H [24;1HEnabling resources...
+[23;80H [24;1HPCI: 00:00.0 subsystem <- 8086/2680
+[23;80H [24;1HOuais
+[23;80H [24;1HPCI: 00:00.0 cmd <- 06
+[23;80H [24;1HPCI: 00:00.1 subsystem <- 8086/2680
+[23;80H [24;1HOuais
+[23;80H [24;1HPCI: 00:00.1 cmd <- 00
+[23;80H [24;1HPCI: 00:01.0 subsystem <- 8086/2680
+[23;80H [24;1HOuais
+[23;80H [24;1HPCI: 00:01.0 cmd <- 06
+[23;80H [24;1HPCI: 00:02.0 cmd <- 00
+[23;80H [24;1HPCI: 00:03.0 cmd <- 00
+[23;80H [24;1HPCI: 00:04.0 bridge ctrl <- 0003
+[23;80H [24;1HPCI: 00:04.0 cmd <- 07
+[23;80H [24;1HPCI: 00:0a.0 cmd <- 02
+[23;80H [24;1HPCI: 00:1d.0 subsystem <- 8086/2680
+[23;80H [24;1HOuais
+[23;80H [24;1HSleeping for a bit... OK
+[23;80H [24;1HPCI: 00:1d.0 cmd <- 01
+[23;80H [24;1HPCI: 00:1d.7 subsystem <- 8086/2680
+[23;80H [24;1HSetting subsystem IDs
+[23;80H [24;1HDone
+[23;80H [24;1HOuais
+[23;80H [24;1HPCI: 00:1d.7 cmd <- 02
+[23;80H [24;1HPCI: 00:1f.0 cmd <- 07
+[23;80H [24;1HPCI: 00:1f.2 subsystem <- 8086/2680
+[23;80H [24;1HOuais
+[23;80H [24;1HPCI: 00:1f.2 cmd <- 03
+[23;80H [24;1HPCI: 00:1f.3 subsystem <- 8086/2680
+[23;80H [24;1HOuais
+[23;80H [24;1HPCI: 00:1f.3 cmd <- 01
+[23;80H [24;1HPCI: 00:1f.4 subsystem <- 8086/2680
+[23;80H [24;1HOuais
+[23;80H [24;1HPCI: 00:1f.4 cmd <- 02
+[23;80H [24;1HPCI: 03:00.0 cmd <- 03
+[23;80H [24;1HPCI: 03:01.0 cmd <- 03
+[23;80H [24;1HPCI: 03:02.0 cmd <- 03
+[23;80H [24;1HPCI: 03:03.0 cmd <- 02
+[23;80H [24;1HPCI: 03:04.0 cmd <- 02
+[23;80H [24;1HPCI: 03:05.0 cmd <- 02
+[23;80H [24;1HPCI: 03:06.0 cmd <- 02
+[23;80H [24;1HPCI: 03:07.0 cmd <- 02
+[23;80H [24;1HPCI: 03:08.0 cmd <- 02
+[23;80H [24;1HPCI: 03:09.0 cmd <- 02
+[23;80H [24;1HPCI: 03:0a.0 cmd <- 06
+[23;80H [24;1HPCI: 03:0b.0 cmd <- 02
+[23;80H [24;1HPCI: 03:0c.0 cmd <- 02
+[23;80H [24;1Hdone.
+[23;80H [24;1HInitializing devices...
+[23;80H [24;1HRoot Device init
+[23;80H [24;1HAPIC_CLUSTER: 0 init
+[23;80H [24;1Hstart_eip=0x0000b000, offset=0x00100000, code_size=0x0000005b
+[23;80H [24;1HInitializing CPU #0
+[23;80H [24;1HCPU: vendor Intel device 10650
+[23;80H [24;1HCPU: family 06, model 15, stepping 00
+[23;80H [24;1HEnabling cache
+[23;80H [24;1H
+[23;80H [24;1HSetting fixed MTRRs(0-88) Type: UC
+[23;80H [24;1HSetting fixed MTRRs(0-16) Type: WB
+[23;80H [24;1HSetting fixed MTRRs(24-88) Type: WB
+[23;80H [24;1HDONE fixed MTRRs
+[23;80H [24;1Hcall enable_fixed_mtrr()
+[23;80H [24;1HSetting variable MTRR 0, base:    0MB, range:  512MB, type WB
+[23;80H [24;1HADDRESS_MASK_HIGH=0xf
+[23;80H [24;1HZero-sized MTRR range @0KB
+[23;80H [24;1HDONE variable MTRRs
+[23;80H [24;1HClear out the extra MTRR's
+[23;80H [24;1Hcall enable_var_mtrr()
+[23;80H [24;1HLeave x86_setup_var_mtrrs
+[23;80H [24;1H
+[23;80H [24;1HMTRR check
+[23;80H [24;1HFixed MTRRs   : Enabled
+[23;80H [24;1HVariable MTRRs: Enabled
+[23;80H [24;1H
+[23;80H [24;1Hmicrocode_info: sig = 0x00010650 pf=0x00000010 rev = 0x00000000
+[23;80H [24;1HSetting up local apic... apic_id: 0x00 done.
+[23;80H [24;1HCPU #0 initialized
+[23;80H [24;1HAll AP CPUs stopped
+[23;80H [24;1HPCI: 00:00.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5020.rom
+[23;80H [24;1HPCI: 00:00.1 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5021.rom
+[23;80H [24;1HPCI: 00:01.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5023.rom
+[23;80H [24;1HPCI: 00:02.0 init
+[23;80H [24;1Hconfigure PCIe port as "Slot Implemented"
+[23;80H [24;1HPCI: 00:03.0 init
+[23;80H [24;1Hconfigure PCIe port as "Slot Implemented"
+[23;80H [24;1HPCI: 00:0a.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5038.rom
+[23;80H [24;1HPCI: 00:1d.0 init
+[23;80H [24;1HPCI: 00:1d.7 init
+[23;80H [24;1HPCI: 00:1f.0 init
+[23;80H [24;1HIOAPIC: Initializing IOAPIC at 0xfec00000
+[23;80H [24;1HIOAPIC: Bootstrap Processor Local APIC = 0x00
+[23;80H [24;1HIOAPIC: 39 interrupts
+[23;80H [24;1HIOAPIC: Enabling interrupts on FSB
+[23;80H [24;1HIOAPIC: reg 0x00000000 value 0x00000000 0x00000700
+[23;80H [24;1HIOAPIC: reg 0x00000001 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000002 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000003 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000004 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000005 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000006 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000007 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000008 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000009 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000000a value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000000b value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000000c value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000000d value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000000e value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000000f value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000010 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000011 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000012 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000013 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000014 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000015 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000016 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000017 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000018 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000019 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000001a value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000001b value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000001c value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000001d value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000001e value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x0000001f value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000020 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000021 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000022 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000023 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000024 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000025 value 0x00000000 0x00010000
+[23;80H [24;1HIOAPIC: reg 0x00000026 value 0x00000000 0x00010000
+[23;80H [24;1Hset power off after power fail
+[23;80H [24;1HNMI sources disabled.
+[23;80H [24;1HRTC Init
+[23;80H [24;1HPCI: 00:1f.2 init
+[23;80H [24;1HSATA init (Legacy mode)
+[23;80H [24;1HSATA Enabled
+[23;80H [24;1HPCI: 00:1f.4 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5036.rom
+[23;80H [24;1HPCI: 03:00.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5041.rom
+[23;80H [24;1HPCI: 03:01.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5045.rom
+[23;80H [24;1HPCI: 03:02.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5049.rom
+[23;80H [24;1HPCI: 03:03.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,503e.rom
+[23;80H [24;1HPCI: 03:04.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5039.rom
+[23;80H [24;1HPCI: 03:05.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,503a.rom
+[23;80H [24;1HPCI: 03:06.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,503b.rom
+[23;80H [24;1HPCI: 03:07.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,503c.rom
+[23;80H [24;1HPCI: 03:08.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,503d.rom
+[23;80H [24;1HPCI: 03:09.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,502d.rom
+[23;80H [24;1HPCI: 03:0a.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,503f.rom
+[23;80H [24;1HPCI: 03:0b.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,504c.rom
+[23;80H [24;1HPCI: 03:0c.0 init
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HCBFS: follow chain: ffe09780 + 38 + bdc8 + align -> ffe15580
+[23;80H [24;1HCheck 
+[23;80H [24;1HCBFS: follow chain: ffe15580 + 28 + 1daa38 + align -> ffff0000
+[23;80H [24;1HCBFS:  Could not find file pci8086,5030.rom
+[23;80H [24;1HPNP: 004e.4 init
+[23;80H [24;1HPNP: 004e.5 init
+[23;80H [24;1HDevices initialized
+[23;80H [24;1HShow all devs...After init.
+[23;80H [24;1HRoot Device: enabled 1
+[23;80H [24;1HPCI_DOMAIN: 0000: enabled 1
+[23;80H [24;1HPCI: 00:00.0: enabled 1
+[23;80H [24;1HPCI: 00:00.1: enabled 1
+[23;80H [24;1HPCI: 00:01.0: enabled 1
+[23;80H [24;1HPCI: 00:02.0: enabled 1
+[23;80H [24;1HPCI: 00:03.0: enabled 1
+[23;80H [24;1HPCI: 00:04.0: enabled 1
+[23;80H [24;1HPCI: 00:08.0: enabled 0
+[23;80H [24;1HPCI: 00:0d.0: enabled 0
+[23;80H [24;1HPCI: 00:0d.1: enabled 0
+[23;80H [24;1HPCI: 00:1d.0: enabled 1
+[23;80H [24;1HPCI: 00:1d.7: enabled 1
+[23;80H [24;1HPCI: 00:1f.0: enabled 1
+[23;80H [24;1HPNP: 004e.4: enabled 1
+[23;80H [24;1HPNP: 004e.5: enabled 1
+[23;80H [24;1HPNP: 002e.0: enabled 0
+[23;80H [24;1HPNP: 002e.3: enabled 0
+[23;80H [24;1HPNP: 002e.4: enabled 0
+[23;80H [24;1HPNP: 002e.5: enabled 0
+[23;80H [24;1HPNP: 002e.7: enabled 1
+[23;80H [24;1HPNP: 002e.a: enabled 0
+[23;80H [24;1HPCI: 00:1f.2: enabled 1
+[23;80H [24;1HPCI: 00:1f.3: enabled 1
+[23;80H [24;1HPCI: 00:1f.4: enabled 1
+[23;80H [24;1HAPIC_CLUSTER: 0: enabled 1
+[23;80H [24;1HAPIC: 00: enabled 1
+[23;80H [24;1HPCI: 00:0a.0: enabled 1
+[23;80H [24;1HPCI: 03:00.0: enabled 1
+[23;80H [24;1HPCI: 03:01.0: enabled 1
+[23;80H [24;1HPCI: 03:02.0: enabled 1
+[23;80H [24;1HPCI: 03:03.0: enabled 1
+[23;80H [24;1HPCI: 03:04.0: enabled 1
+[23;80H [24;1HPCI: 03:05.0: enabled 1
+[23;80H [24;1HPCI: 03:06.0: enabled 1
+[23;80H [24;1HPCI: 03:07.0: enabled 1
+[23;80H [24;1HPCI: 03:08.0: enabled 1
+[23;80H [24;1HPCI: 03:09.0: enabled 1
+[23;80H [24;1HPCI: 03:0a.0: enabled 1
+[23;80H [24;1HPCI: 03:0b.0: enabled 1
+[23;80H [24;1HPCI: 03:0c.0: enabled 1
+[23;80H [24;1HInitializing CBMEM area to 0x1fff0000 (65536 bytes)
+[23;80H [24;1HAdding CBMEM entry as no. 1
+[23;80H [24;1HMoving GDT to 1fff0200...ok
+[23;80H [24;1HHigh Tables Base is 1fff0000.
+[23;80H [24;1HAdding CBMEM entry as no. 2
+[23;80H [24;1HACPI: Writing ACPI tables at 1fff0400.
+[23;80H [24;1HACPI:    * HPET
+[23;80H [24;1HACPI: added table 1/32, length now 40
+[23;80H [24;1HACPI:    * MADT
+[23;80H [24;1HACPI: added table 2/32, length now 44
+[23;80H [24;1HACPI:    * MCFG
+[23;80H [24;1HACPI: added table 3/32, length now 48
+[23;80H [24;1HACPI:     * FACS
+[23;80H [24;1HACPI:     * DSDT @ 1fff0600 Length 10c1
+[23;80H [24;1HACPI:     * FADT
+[23;80H [24;1HACPI: added table 4/32, length now 52
+[23;80H [24;1HACPI: done.
+[23;80H [24;1HACPI tables: 5072 bytes.
+[23;80H [24;1HAdding CBMEM entry as no. 3
+[23;80H [24;1HWriting high table forward entry at 0x00000500
+[23;80H [24;1HWrote coreboot table at: 00000500 - 00000518  checksum 1fdf
+[23;80H [24;1HNew low_table_end: 0x00000518
+[23;80H [24;1HNow going to write high coreboot table at 0x1fffc000
+[23;80H [24;1Hrom_table_end = 0x1fffc000
+[23;80H [24;1HAdjust low_table_end from 0x00000518 to 0x00001000 
+[23;80H [24;1HAdjust rom_table_end from 0x1fffc000 to 0x20000000 
+[23;80H [24;1HAdding high table area
+[23;80H [24;1Hcoreboot memory table:
+[23;80H [24;1H 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+[23;80H [24;1H 1. 0000000000001000-000000000009ffff: RAM
+[23;80H [24;1H 2. 00000000000c0000-000000001ffeffff: RAM
+[23;80H [24;1H 3. 000000001fff0000-000000001fffffff: CONFIGURATION TABLES
+[23;80H [24;1HWrote coreboot table at: 1fffc000 - 1fffc1ac  checksum 9df1
+[23;80H [24;1Hcoreboot table: 428 bytes.
+[23;80H [24;1HMultiboot Information structure has been written.
+[23;80H [24;1H 0. FREE SPACE 1fffe000 00002000
+[23;80H [24;1H 1. GDT        1fff0200 00000200
+[23;80H [24;1H 2. ACPI       1fff0400 0000bc00
+[23;80H [24;1H 3. COREBOOT   1fffc000 00002000
+[23;80H [24;1HCheck CBFS header at fffeffe0
+[23;80H [24;1Hmagic is 4f524243
+[23;80H [24;1HFound CBFS header at fffeffe0
+[23;80H [24;1HCheck fallback/coreboot_ram
+[23;80H [24;1HCBFS: follow chain: ffe00000 + 38 + 972c + align -> ffe09780
+[23;80H [24;1HCheck fallback/payload
+[23;80H [24;1HGot a payload
+[23;80H [24;1HLoading segment from rom address 0xffe097b8
+[23;80H [24;1H  data (compression=1)
+[23;80H [24;1H  New segment dstaddr 0xe8484 memsize 0x17b7c srcaddr 0xffe097f0 filesize 0xbd9[24;80H
+[23;80H0[24;1H  (cleaned up) New segment addr 0xe8484 size 0x17b7c offset 0xffe097f0 filesize[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1HLoading segment from rom address 0xffe097d4
+[23;80H [24;1H  Entry Point 0x000fc8de
+[23;80H [24;1HLoading Segment: addr: 0x00000000000e8484 memsz: 0x0000000000017b7c filesz: 0x0[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1Hlb: [0x0000000000100000, 0x000000000013c000)
+[23;80H [24;1HPost relocation: addr: 0x00000000000e8484 memsz: 0x0000000000017b7c filesz: 0x0[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H[24;80H
+[23;80H0[24;1Husing LZMA
+[23;80H [24;1H[ 0x000e8484, 00100000, 0x00100000) <- ffe097f0
+[23;80H [24;1Hdest 000e8484, end 00100000, bouncebuffer 1ff78000
+[23;80H [24;1HLoaded segments
+[23;80H [24;1HJumping to boot code at fc8de
+[23;80H [24;1Hentry    = 0x000fc8de
+[23;80H [24;1Hlb_start = 0x00100000
+[23;80H [24;1Hlb_size  = 0x0003c000
+[23;80H [24;1Hadjust   = 0x1feb4000
+[23;80H [24;1Hbuffer   = 0x1ff78000
+[23;80H [24;1H     elf_boot_notes = 0x00112664
+[23;80H [24;1Hadjusted_boot_notes = 0x1ffc6664
+[23;80H [24;1HStart bios (version pre-0.6.2-20120531_150337-bastien)
+[23;80H [24;1HFound mainboard Intel Truxton
+[23;80H [24;1HFound CBFS header at 0xfffeffe0
+[23;80H [24;1HRam Size=0x1fff0000 (0x0000000000000000 high)
+[23;80H [24;1HRelocating init from 0x000e89b0 to 0x1ffd6100 (size 40404)
+[23;80H [24;1HCPU Mhz=600
+[23;80H [24;1HFound 1 cpu(s) max supported 1 cpu(s)
+[23;80H [24;1HCopying ACPI RSDP from 0x1fff0400 to 0x000fdc10
+[23;80H [24;1HSMBIOS ptr=0x000fdbf0 table=0x1ffefef0
+[23;80H [24;1HScan for VGA option rom
+[23;80H [24;1HNo support for 64bit EHCI
+[23;80H [24;1HUHCI init on dev 00:1d.0 (io=20c0)
+[23;80H [24;1HAll threads complete.
+[23;80H [24;1HWARNING - Timeout at i8042_flush:68!
+[23;80H [24;1HAll threads complete.
+[23;80H [24;1HFound 0 lpt ports
+[23;80H [24;1HFound 2 serial ports
+[23;80H [24;1HATA controller 0 at 2410/2420/0 (irq 0 dev fa)
+[23;80H [24;1HAll threads complete.
+[23;80H [24;1HATA controller 1 at 2418/2424/0 (irq 0 dev fa)
+[23;80H [24;1Hata1-0: ST3500418AS ATA-8 Hard-Disk (465 GiBytes)
+[23;80H [24;1HSearching bootorder for: /pci@i0cf8/*@1f,2/drive@1/disk@0
+[23;80H [24;1HAll threads complete.
+[23;80H [24;1HScan for option roms
+[23;80H [24;1HPress F12 for boot menu.
+[23;80H [24;1H
+[23;80H [24;1Hdrive 0x000fdba0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=976773168
+[23;80H [24;1HReturned 61440 bytes of ZoneHigh
+[23;80H [24;1He820 map has 5 items:
+[23;80H [24;1H  0: 0000000000000000 - 000000000009fc00 = 1
+[23;80H [24;1H  1: 000000000009fc00 - 00000000000a0000 = 2
+[23;80H [24;1H  2: 00000000000f0000 - 0000000000100000 = 2
+[23;80H [24;1H  3: 0000000000100000 - 000000001ffef000 = 1
+[23;80H [24;1H  4: 000000001ffef000 - 0000000020000000 = 2
+[23;80H [24;1Henter handle_19:
+[23;80H [24;1H  NULL
+[23;80H [24;1HBooting from Hard Disk...
+[23;80H [24;1HBooting from 0000:7c00
+[23;80H [24;1HPress `ESC' to enter the menu... 4   
+Press `ESC' to enter the menu... 3   
+Press `ESC' to enter the menu... 2   
+Press `ESC' to enter the menu... 1   
+Press `ESC' to enter the menu... 0   [1;1H
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K
+[K[1;1H[K  Booting 'Debian GNU/Linux, kernel 2.6.32-5-686'
+
+root  (hd0,0)
+ Filesystem type is ext2fs, partition type 0x83
+kernel  /vmlinuz-2.6.32-5-686 root=/dev/mapper/data-system ro 
+   [Linux-bzImage, setup=0x3600, size=0x22e540]
+initrd  /initrd.img-2.6.32-5-686
+   [Linux-initrd @ 0x1f6bb000, 0x92353d bytes]
+
+ls -tr
+lol
+setup.log.full
+setup.log
+xivo.rom
+coreboot-raminit_new-debug-1321276694.rom
+coreboot-xivo-debug-1321280629.rom
+random1
+random2
+coreboot-raminit_new-debug-seabios-1321628785.rom
+coreboot-raminit_new-debug-seabios-new_dsdt-ipxe-1330076393.rom
+coreboot-raminit_new-debug-seabios-new_dsdt-ipxe-no_quickassist-1330096817.rom
+coreboot-raminit_new-debug-seabios-new_dsdt-ipxe-no_quickassist-debug_ipxe-1330097980.rom
+coreboot-raminit_new-debug-seabios-new_dsdt-ipxe-no_quickassist-debug_ipxe-1330098465.rom
+coreboot-raminit_new-debug-seabios-new_dsdt-ipxe-no_quickassist-debug_ipxe-1330098874.rom
+coreboot-raminit_new-debug-seabios-new_dsdt-1328722979.rom
+coreboot-raminit_new-debug-seabios-new_dsdt-ipxe-1336558603.rom
+coreboot.rom
+]0;~
+[32mno@botskath [33m~[0m
+$ 
+[20@(reverse-i-search)`':[Cd': dpcmd -v -ucoreboot.rom[1@p[C[C[C[1@c[C[C[C
+[23P$[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[C[K[K[K[K[K[K[K[K[K[K[K[K[Kucoreboot-raminit_new-debug-seabios-new_dsdt-ipxe-1330076393.rom
+DpCmd 6.0.2.01 Engine Version:  
+Last Built on Sep 30 2011
+
+
+By reading the chip ID, the chip applies to [ 25VF016B 25VF016B ]
+25VF016B parameters to be applied by default
+25VF016B chip size is 2097152 bytes.
+
+
+Loading file, please wait ...(coreboot-raminit_new-debug-seabios-new_dsdt-ipxe-1330076393.rom)
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+Auto Sequences, please wait ...
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+Automatic program OK
+
+Checksum(file): 1DCD5E58
+Checksum(Written part of file): 1DCD5E58
+Verifying, please wait ...
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+Operation completed. 
+9.376 seconds elapsed.
+
+Error: Verify Failed
+]0;~
+[32mno@botskath [33m~[0m
+$ dpcmd -v -ucoreboot-raminit_new-debug-seabios-new_dsdt-ipxe-1330076393.rom
+DpCmd 6.0.2.01 Engine Version:  
+Last Built on Sep 30 2011
+
+
+By reading the chip ID, the chip applies to [ 25VF016B 25VF016B ]
+25VF016B parameters to be applied by default
+25VF016B chip size is 2097152 bytes.
+
+
+Loading file, please wait ...(coreboot-raminit_new-debug-seabios-new_dsdt-ipxe-1330076393.rom)
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+Automatic program OK
+
+Checksum(file): 1DCD5E58
+Checksum(Written part of file): 1DCD5E58
+Verifying, please wait ...
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+Verify OK
+]0;~
+[32mno@botskath [33m~[0m
+$ man minicom
+No manual entry for minicom
+]0;~
+[32mno@botskath [33m~[0m
+$ 
+\ No newline at end of file
author	Bastien Ligneul <bligneul@avencall.com>	2012-06-07 11:23:02 +0200
committer	Bastien Ligneul <bligneul@avencall.com>	2012-06-07 11:23:36 +0200
commit	1a84216de7a77f164424ce2815ea8c9b8b87d8e5 (patch)
tree	fab962b668a28e4dfa68b817eabd9a14c48c5089 /coreboot-pirq-tests
parent	0608d1fa132f06e4cdd26a2c2cfc20315bcec194 (diff)