x86/{cpu,trap}: implement lockless checkpoint reset IPIs

These inter-processor interrupts will be used by the upcoming llsync module
implementing lockless synchronization.

5 files changed, 30 insertions, 0 deletions

diff --git a/arch/x86/machine/cpu.c b/arch/x86/machine/cpu.c
index 4190a65f..8dfb2714 100644
--- a/arch/x86/machine/cpu.c
+++ b/arch/x86/machine/cpu.c
@@ -596,3 +596,13 @@ cpu_halt_intr(struct trap_frame *frame)
 
     cpu_halt();
 }
+
+void
+cpu_llsync_reset_intr(struct trap_frame *frame)
+{
+    (void)frame;
+
+    lapic_eoi();
+
+    /* Not implemented yet */
+}
diff --git a/arch/x86/machine/cpu.h b/arch/x86/machine/cpu.h
index 205036e3..9acd746a 100644
--- a/arch/x86/machine/cpu.h
+++ b/arch/x86/machine/cpu.h
@@ -93,6 +93,7 @@
 #include <kern/param.h>
 #include <kern/stddef.h>
 #include <kern/stdint.h>
+#include <machine/lapic.h>
 #include <machine/pit.h>
 
 /*
@@ -593,6 +594,20 @@ void cpu_ap_setup(void);
  */
 void cpu_ap_sync(void);
 
+/*
+ * Request a remote processor to reset its checkpoint.
+ */
+static inline void
+cpu_send_llsync_reset(unsigned int cpu)
+{
+    lapic_ipi_send(cpu, TRAP_LLSYNC_RESET);
+}
+
+/*
+ * Interrupt handler for checkpoint reset requests.
+ */
+void cpu_llsync_reset_intr(struct trap_frame *frame);
+
 #endif /* __ASSEMBLER__ */
 
 #endif /* _X86_CPU_H */
diff --git a/arch/x86/machine/trap.c b/arch/x86/machine/trap.c
index b8d154ac..983f99e2 100644
--- a/arch/x86/machine/trap.c
+++ b/arch/x86/machine/trap.c
@@ -76,6 +76,7 @@ void trap_isr_machine_check(void);
 void trap_isr_simd_fp_exception(void);
 void trap_isr_pic_int7(void);
 void trap_isr_pic_int15(void);
+void trap_isr_llsync_reset(void);
 void trap_isr_reschedule(void);
 void trap_isr_pmap_update(void);
 void trap_isr_cpu_halt(void);
@@ -203,6 +204,8 @@ trap_setup(void)
                  trap_isr_pic_int15, pic_intr_spurious);
 
     /* System defined traps */
+    trap_install(TRAP_LLSYNC_RESET, TRAP_HF_NOPREEMPT,
+                 trap_isr_llsync_reset, cpu_llsync_reset_intr);
     trap_install(TRAP_RESCHEDULE, TRAP_HF_NOPREEMPT,
                  trap_isr_reschedule, tcb_reschedule_intr);
     trap_install(TRAP_PMAP_UPDATE, TRAP_HF_NOPREEMPT,
diff --git a/arch/x86/machine/trap.h b/arch/x86/machine/trap.h
index 89520245..0e15c452 100644
--- a/arch/x86/machine/trap.h
+++ b/arch/x86/machine/trap.h
@@ -53,6 +53,7 @@
  *
  * The local APIC assigns one priority every 16 vectors.
  */
+#define TRAP_LLSYNC_RESET   237
 #define TRAP_RESCHEDULE     238
 #define TRAP_PMAP_UPDATE    239
 #define TRAP_CPU_HALT       240
diff --git a/arch/x86/machine/trap_asm.S b/arch/x86/machine/trap_asm.S
index 535ede30..b80a15c6 100644
--- a/arch/x86/machine/trap_asm.S
+++ b/arch/x86/machine/trap_asm.S
@@ -157,6 +157,7 @@ TRAP(TRAP_PIC_BASE + 7, pic_int7)
 TRAP(TRAP_PIC_BASE + 15, pic_int15)
 
 /* System defined traps */
+TRAP(TRAP_LLSYNC_RESET, llsync_reset)
 TRAP(TRAP_RESCHEDULE, reschedule)
 TRAP(TRAP_PMAP_UPDATE, pmap_update)
 TRAP(TRAP_CPU_HALT, cpu_halt)