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authorRichard Braun <rbraun@sceen.net>2018-01-05 16:12:25 +0100
committerRichard Braun <rbraun@sceen.net>2018-01-05 16:12:25 +0100
commit897447864c8e67203ceb0998f4d02e4aa41a635c (patch)
tree89b57ca21f08cd3d9525d277ce26c8c8d747c0ff /src/cpu_asm.S
parent5ad6a354a9a5ba37a57a743ddf3c0659e73e29a9 (diff)
cpu: discuss the stack on interrupt handling
Diffstat (limited to 'src/cpu_asm.S')
-rw-r--r--src/cpu_asm.S17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/cpu_asm.S b/src/cpu_asm.S
index 321f5b2..e14fb1f 100644
--- a/src/cpu_asm.S
+++ b/src/cpu_asm.S
@@ -128,6 +128,23 @@ name: \
pushl $(vector); \
jmp cpu_intr_common
+/*
+ * This is the first common low level entry point for all exceptions and
+ * interrupts. When reached, the stack contains the registers automatically
+ * pushed by the processor, an error code and the vector. It's important
+ * to note that the stack pointer still points to the stack of the thread
+ * running when the interrupt occurs. Actually, in this implementation,
+ * the entire interrupt handler borrows the stack of the interrupted thread.
+ *
+ * This is dangerous because the stack must then be large enough for both
+ * the largest call chain of the interrupted thread as well as the largest
+ * call chain of any interrupt handler. On some implementations, especially
+ * those with very demanding real-time constraints, interrupt handling may
+ * nest to avoid waiting for the current interrupt to be serviced before
+ * starting handling a higher priority one, leading to even larger stack
+ * needs. This is why many operating systems dedicate a separate stack for
+ * interrupt handling.
+ */
cpu_intr_common:
CPU_INTR_STORE_REGISTERS
push %esp /* push the address of the interrupt frame */