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The axg TDM HW does not depend on a selected set of rates.
The hardware itself, just takes an input clock and work with it, regardless
of its rate. In this way, the rates TDM can take are continuous.
What might force the use of specific rate are the PLL available as clock
and/or the codecs facing the TDM HW. Either way, this constraint does not
belong in the TDM interface driver.
Allow any rate as far as TDM is concerned by setting
SNDRV_PCM_RATE_CONTINUOUS with an interval it has been tested with.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patch.msgid.link/20240920-asoc-axg-iface-continuous-v1-1-6075d7db0e61@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add support for 705.6kHz and 768kHz sample rates
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patch.msgid.link/20240628123256.2019224-1-jbrunet@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Some devices may need the clocks running, even while paused.
Add support for this use case.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20240426152946.3078805-5-jbrunet@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The TDM HW on the axg SoC families and derivatives actually supports
384kHz sampling rate.
Update the fifo and tdm interface constraints accordingly.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20230907090910.13546-1-jbrunet@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The content of SND_SOC_DAIFMT_FORMAT_MASK is a number, not a bitfield,
so the test to check if the format is i2s is wrong. Because of this the
clock setting may be wrong. For example, the sample clock gets inverted
in DSP B mode, when it should not.
Fix the lrclk invert helper function
Fixes: 1a11d88f499c ("ASoC: meson: add tdm formatter base driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add Amlogic's axg TDM interface driver. This driver manages the format
and clocks provided on the pads.
On this SoC, each stream direction provides 4 serial lanes. This makes
a maximum of 8 channels in i2s modes and 128 channels in DSP modes.
While each lanes operate on the same slot number (same bit clock), they
may have different TDM masks. This requires to provide a function to let
the card set the 4 masks, in lieu of the usual set_tdm_slots() callback
of the dai driver.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add Amlogic's axg TDM core driver. On this SoC, tdm is bit more
complex than usual, mainly because the different TDM input decoders can
be attached to any of TDM pad interface, including the output pads.
For the this, TDM on this SoC is modeled like this:
- TDM interface provides the DAIs the codecs will be attached to.
The main responsibility of this driver is to manage the pad format
and the TDM clock rates.
- TDM Formatters: These are the entities which are actually dealing with
the TDM signal. TDMOUT produce a TDM signal from the audio sample
provided by FRDDR using the clocks provided the TDM interface. TDMIN
feeds TODDR with audio sample using the clocks and TDM signal provided
by the TDM Interface.
- TDM Streams: This provides the link between 1 DAI stream of the TDM
interface and one (or more) TDM formatters.
This driver provides the TDM formatter and TDM stream operations.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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