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2025-05-12ACPICA: Update copyright yearSaket Dumbre
ACPICA commit 45253be18b3f37d46cd0072aa3f8a0a21a70e0a4 Changes needed by acpisrc to update copyright year when building for release. Link: https://github.com/acpica/acpica/commit/45253be1 Signed-off-by: Saket Dumbre <saket.dumbre@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-05-12ACPICA: actbl2.h: ACPI 6.5: RAS2: Rename structure and field names of the ↵Shiju Jose
RAS2 table ACPICA commit 2c8a38f747de9d977491a494faf0dfaf799b777b Rename the structure and field names of the RAS2 table to shorten them and avoid long lines in the ACPI RAS2 drivers. 1. struct acpi_ras2_shared_memory to struct acpi_ras2_shmem 2. In struct acpi_ras2_shared_memory: fields, - set_capabilities[16] to set_caps[16] - num_parameter_blocks to num_param_blks - set_capabilities_status to set_caps_status 3. struct acpi_ras2_patrol_scrub_parameter to struct acpi_ras2_patrol_scrub_param 4. In struct acpi_ras2_patrol_scrub_parameter: fields, - patrol_scrub_command to command - requested_address_range to req_addr_range - actual_address_range to actl_addr_range Link: https://github.com/acpica/acpica/commit/2c8a38f7 Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/1942053.CQOukoFCf9@rjwysocki.net
2025-05-12ACPICA: actbl2.h: ERDT: Add typedef and other definitionsTony Luck
ACPICA commit dddd9270531d74af523afa68515d8aae6a18bbe0 The ERDT table (and its many subtables) enumerate capabilities and methods for Intel Resource Director Technology to monitor and control L3 cache allocation and memory bandwidth by CPU cores and IO devices. Structure defined in the Intel Resource Director Technology (RDT) Architecture specification downloadable from www.intel.com/sdm Link: https://github.com/acpica/acpica/commit/dddd9270 Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3296755.5fSG56mABF@rjwysocki.net
2025-05-12ACPICA: infrastructure: Add new DMT_BUF types and shorten a long nameTony Luck
ACPICA commit b8713f71b4023a0396fe61503bbbf5226e5eed1b Some ERDT subtables have 11 and 24 byte reserved fields. Add the ACPI_DMT_BUF11 and ACPI_DMT_BUF24 types to describe these reserved fields in struct acpi_dmtable_info structures. Shorten the ACPI_SUBTABLE_HEADER_16 name to ACPI_SUBTBL_HDR Link: https://github.com/acpica/acpica/commit/b8713f71 Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3643286.iIbC2pHGDl@rjwysocki.net
2025-05-12ACPICA: MRRM: Some cleanupsTony Luck
ACPICA commit 022e2e4169841f429dbda677a4780830bf4c2177 1) Added source specification to MRRM table comment in actbl2.h 2) Shorten typedef from ACPI_TABLE_MRRM_MEM_RANGE_ENTRY to struct acpi_mrrm_mem_range_entry 3) Add new typedefs to source/tools/acpisrc/astable.c 4) Fix cut and paste errors in acpi_dm_table_info_mrrm0[] definition 5) Fix indent and source code style errors in actbl2.h 6) The base/length fields in the memory range structure are system memory addresses, not "MMIO". Update the acpi_dm_table_info_mrrm0[] strings. 7) Add main/sub table comments to acpi_dm_dump_mrrm() and dt_compile_mrrm() Link: https://github.com/acpica/acpica/commit/022e2e41 Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/2018955.PYKUYFuaPT@rjwysocki.net
2025-05-12ACPICA: actbl2: Add definitions for RIMTSunil V L
ACPICA commit 73c32bc89cad64ab19c1231a202361e917e6823c RISC-V IO Mapping Table (RIMT) is a new static table defined for RISC-V to communicate IOMMU information to the OS. The specification for RIMT is available at [1]. Add structure definitions for RIMT. Link: https://github.com/riscv-non-isa/riscv-acpi-rimt [1] Link: https://github.com/acpica/acpica/commit/73c32bc8 Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/10665648.nUPlyArG6x@rjwysocki.net
2025-05-12ACPICA: actbl2.h: MRRM: Add typedef and other definitionsTony Luck
ACPICA commit 04fd53b2647b9f6f98cfca551383689cb3b59362 The MRRM table describes association between physical address ranges and "region numbers". Structure defined in the Intel Resource Director Technology (RDT) Architecture specification downloadable from www.intel.com/sdm Link: https://github.com/acpica/acpica/commit/04fd53b2 Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/3372188.44csPzL39Z@rjwysocki.net
2025-04-28ACPICA: Drop stale comment about the header file contentSudeep Holla
ACPICA commit 48e7c4cd893270dab8d05e6d75fbf23d0fcbb267 Commit a025731aec31 ("Restructure ACPI table files") restructed the header files and moved lots of tables that are in the ACPI specification to actbl2.h(e.g.: APIC/MADT, PCCT, PPTT, ..etc). This restructure made the comment stating this header file contains tables that are not in the ACPI specification incorrect. From that commit onwards it has remained as stale. Let us get rid of it as it might be misleading. Link: https://github.com/acpica/acpica/commit/48e7c4cd Reported-by: Sahil Kaushal <sahil.kaushal@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/6168200.lOV4Wx5bFT@rjwysocki.net
2024-11-05ACPICA: IORT: Update for revision E.fNicolin Chen
ACPICA commit c4f5c083d24df9ddd71d5782c0988408cf0fc1ab The IORT spec, Issue E.f (April 2024), adds a new CANWBS bit to the Memory Access Flag field in the Memory Access Properties table, mainly for a PCI Root Complex. This CANWBS defines the coherency of memory accesses to be not marked IOWB cacheable/shareable. Its value further implies the coherency impact from a pair of mismatched memory attributes (e.g. in a nested translation case): 0x0: Use of mismatched memory attributes for accesses made by this device may lead to a loss of coherency. 0x1: Coherency of accesses made by this device to locations in Conventional memory are ensured as follows, even if the memory attributes for the accesses presented by the device or provided by the SMMU are different from Inner and Outer Write-back cacheable, Shareable. Link: https://github.com/acpica/acpica/commit/c4f5c083 Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Acked-by: Hanjun Guo <guohanjun@huawei.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/2-v4-9e99b76f3518+3a8-smmuv3_nesting_jgg@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
2024-08-29ACPICA: MPAM: Correct the typo in struct acpi_mpam_msc_node memberPunit Agrawal
ACPICA commit 3da3f7d776d17e9bfbb15de88317de8d7397ce38 A member of the struct acpi_mpam_msc_node that represents a Memory System Controller node structure - num_resource_nodes has a typo. Fix the typo No functional change. Link: https://github.com/acpica/acpica/commit/3da3f7d7 Signed-off-by: Punit Agrawal <punit.agrawal@bytedance.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-06-17x86/acpi: Add support for CPU offlining for ACPI MADT wakeup methodKirill A. Shutemov
MADT Multiprocessor Wakeup structure version 1 brings support for CPU offlining: BIOS provides a reset vector where the CPU has to jump to for offlining itself. The new TEST mailbox command can be used to test whether the CPU offlined itself which means the BIOS has control over the CPU and can online it again via the ACPI MADT wakeup method. Add CPU offlining support for the ACPI MADT wakeup method by implementing custom cpu_die(), play_dead() and stop_this_cpu() SMP operations. CPU offlining makes it possible to hand over secondary CPUs over kexec, not limiting the second kernel to a single CPU. The change conforms to the approved ACPI spec change proposal. See the Link. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Kai Huang <kai.huang@intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Tested-by: Tao Liu <ltao@redhat.com> Link: https://lore.kernel.org/all/13356251.uLZWGnKmhe@kreacher Link: https://lore.kernel.org/r/20240614095904.1345461-19-kirill.shutemov@linux.intel.com
2024-06-17x86/acpi: Rename fields in the acpi_madt_multiproc_wakeup structureKirill A. Shutemov
In order to support MADT wakeup structure version 1, provide more appropriate names for the fields in the structure. Rename 'mailbox_version' to 'version'. This field signifies the version of the structure and the related protocols, rather than the version of the mailbox. This field has not been utilized in the code thus far. Rename 'base_address' to 'mailbox_address' to clarify the kind of address it represents. In version 1, the structure includes the reset vector address. Clear and distinct naming helps to prevent any confusion. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Kai Huang <kai.huang@intel.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Tested-by: Tao Liu <ltao@redhat.com> Link: https://lore.kernel.org/r/20240614095904.1345461-15-kirill.shutemov@linux.intel.com
2024-05-13Merge branches 'acpi-scan' and 'acpi-tables'Rafael J. Wysocki
Merge ACPI device enumeration changes and ACPI data-only tables support updates for 6.10: - Rearrange fields in several structures to effectively eliminate computations from container_of() in some cases (Andy Shevchenko). - Do some assorted cleanups of the ACPI device enumeration code (Andy Shevchenko). - Make the ACPI device enumeration code skip devices with _STA values clearly identified by the specification as invalid (Rafael Wysocki). - Rework the handling of the NHLT table to simplify and clarify it and drop some obsolete pieces (Cezary Rojewski). * acpi-scan: ACPI: scan: Avoid enumerating devices with clearly invalid _STA values ACPI: scan: Introduce typedef:s for struct acpi_hotplug_context members ACPI: scan: Use standard error checking pattern ACPI: scan: Move misleading comment to acpi_dma_configure_id() ACPI: scan: Use list_first_entry_or_null() in acpi_device_hid() ACPI: bus: Don't use "proxy" headers ACPI: bus: Make container_of() no-op where it makes sense * acpi-tables: ACPI: NHLT: Streamline struct naming ACPI: NHLT: Drop redundant types ACPI: NHLT: Introduce API for the table ACPI: NHLT: Reintroduce types the table consists of
2024-04-30ACPICA: AEST: Add support for the AEST V2 tableRuidong Tian
ACPICA commit ebb49799c78891cbe370f1264844664a3d8b6f35 AEST V2 was published[1], add V2 support based on AEST V1. [1]: https://developer.arm.com/documentation/den0085/latest/ Link: https://github.com/acpica/acpica/commit/ebb4979 Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-04-12ACPICA: ACPI 6.5: RAS2: Add support for RAS2 tableShiju Jose
ACPICA commit c581606cf49b7574d29c02b1a3bc144650375e32 Add support for ACPI RAS2 feature table(RAS2) defined in the ACPI 6.5 Specification & upwards revision, section 5.2.21. The RAS2 table provides interfaces for platform RAS features. RAS2 offers the same services as RASF, but is more scalable than the latter. RAS2 supports independent RAS controls and capabilities for a given RAS feature for multiple instances of the same component in a given system. The platform can support either RAS2 or RASF but not both. Link: https://github.com/acpica/acpica/commit/c581606c Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-03-27ACPI: NHLT: Streamline struct namingCezary Rojewski
Few recently introduced structs are named 'nhlt2' instead of 'nhlt' to avoid naming conflicts. With duplicate types gone, the conflicts are no more. Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-03-27ACPI: NHLT: Drop redundant typesCezary Rojewski
ACPICA commit 0c7379eae2a0342bfc36d6b7db0bb90ad13a5a3e There are no users for the duplicated NHLT table components. Link: https://github.com/acpica/acpica/pull/890 Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-03-27ACPI: NHLT: Reintroduce types the table consists ofCezary Rojewski
ACPICA commit 32260f5ce519e854546ce907fc0cc449e1fe51fe Non HDAudio Link Table (NHLT) is designed to separate hardware-related description (registers) from AudioDSP firmware-related one i.e.: pipelines and modules that together make up the audio stream on Intel DSPs. This task is important as same set of hardware registers can be used with different topologies and vice versa, same topology could be utilized with different set of hardware. As the hardware registers description is directly tied to specific platform, intention is to have such description part of low-level firmware e.g.: BIOS. The initial design has been provided in early Sky Lake (SKL) days. The audio architecture goes by the name cAVS. SKL is a representative of cAVS 1.5. The table helps describe endpoint capabilities ever since. While Raptor Lake (RPL) is the last of cAVS architecture - cAVS 2.5 to be precise - its successor, the ACE architecture which begun with Meteor Lake (MTL) inherited the design for all I2S and PDM configurations. These two configurations are the primary targets for NHLT table. Due to naming conflicts with existing code, several structs are named 'nhlt2' rather than 'nhlt'. Follow up changes clean this up once existing code has no users and is removed. Link: https://github.com/acpica/acpica/pull/912 Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-01-09ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handlingLorenzo Pieralisi
ACPICA commit c5d2010744b1bf7efba0bd04a8a9c200ef8fb610 Add new flags and related fields to the MADT GICC/GICR/ITS structures according to the code first ECR: https://bugzilla.tianocore.org/show_bug.cgi?id=4557 Update the MADT template to the latest MADT revision. Link: https://github.com/acpica/acpica/commit/c5d20107 Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-01-09ACPICA: MADT: Add GICC online capable bit handlingLorenzo Pieralisi
ACPICA commit 16f0befdeddf25756f317907798192bbaa417e5e Implement code to handle the GICC online capable bit management added into ACPI v6.5. Link: https://github.com/acpica/acpica/commit/16f0befd Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-07-10ACPICA: RHCT: Add flags, CMO and MMU nodesSunil V L
ACPICA commit 2eded5a6a13d892b7dc3be6096e7b1e8d4407600 Update RHCT table with below details. 1) Add additional structure to describe the Cache Management Operation (CMO) related information. 2) Add structure to describe MMU type. 3) Convert the current reserved field to flags and define a flag to indicate timer capability. This codefirst ECR is approved by UEFI forum and will be part of next ACPI spec version. Link: https://github.com/acpica/acpica/commit/2eded5a6 Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-07-10ACPICA: MADT: Add RISC-V external interrupt controllersSunil V L
ACPICA commit 8c048cee4ea7b9ded8db3e1b3b9c14e21e084a2c This adds 3 different external interrupt controller definitions in MADT for RISC-V. 1) RISC-V PLIC is a platform interrupt controller for handling wired interrupt in a RISC-V systems. 2) RISC-V IMSIC is MSI interrupt controller to support MSI interrupts. 3) RISC-V APLIC has dual functionality. First it can act like PLIC and direct all wired interrupts to the CPU which doesn't have MSI controller. Second, when the CPU has MSI controller (IMSIC), it will act as a converter from wired interrupts to MSI. Update the existing RINTC structure also to support these external interrupt controllers. This codefirst ECR is approved by UEFI forum and will be part of next ACPI spec version. Link: https://github.com/acpica/acpica/commit/8c048cee Signed-off-by: Haibo, Xu <haibo1.xu@intel.com> Co-developed-by: Haibo, Xu <haibo1.xu@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: acpi_madt_oem_data: Fix flexible array member definitionKees Cook
ACPICA commit e7f6d8c1b7f79eb4b9b07f1bc09c549a2acbd6e8 Use ACPI_FLEX_ARRAY() helper to define flexible array member alone in a struct. Fixes issue #812. No binary changes appear in the .text nor .data sections. Link: https://github.com/acpica/acpica/commit/e7f6d8c1 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: struct acpi_nfit_interleave: Replace 1-element array with flexible arrayKees Cook
ACPICA commit e66decc6fca36b59194b0947d87d6a9bec078bc3 Similar to "Replace one-element array with flexible-array", replace the 1-element array with a proper flexible array member as defined by C99. This allows the code to operate without tripping compile-time and run- time bounds checkers (e.g. via __builtin_object_size(), -fsanitize=bounds, and/or -fstrict-flex-arrays=3). Unlike struct acpi_nfit_flush_address and struct acpi_nfit_smbios, which had their sizeof() uses adjusted in code, struct acpi_nfit_interleave did not. This appears to have been a bug. After this change, there is a binary difference in acpi_dm_dump_nfit() since the size of the structure now has the correct size, as the prior result was including the trailing U32: - mov $0x14,%ebp + mov $0x10,%ebp Link: https://github.com/acpica/acpica/commit/e66decc6 Signed-off-by: Bob Moore <robert.moore@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Tested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: actbl2: Replace 1-element arrays with flexible arraysKees Cook
ACPICA commit 44f1af0664599e87bebc3a1260692baa27b2f264 Similar to "Replace one-element array with flexible-array", replace the 1-element array with a proper flexible array member as defined by C99. This allows the code to operate without tripping compile-time and run- time bounds checkers (e.g. via __builtin_object_size(), -fsanitize=bounds, and/or -fstrict-flex-arrays=3). The sizeof() uses with struct acpi_nfit_flush_address and struct acpi_nfit_smbios have been adjusted to drop the open-coded subtraction of the trailing single element. The result is no binary differences in .text nor .data sections. Link: https://github.com/acpica/acpica/commit/44f1af06 Signed-off-by: Bob Moore <robert.moore@intel.com> Co-developed-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: Add structure definitions for RISC-V RHCTSunil V L
ACPICA commit 82afd0434e79f74b96a6be88115ddc8343a1ba40 RISC-V Hart Capabilities Table (RHCT) is a new static table. The ECR to add RHCT is approved by the UEFI forum and will be available in the next version of the ACPI spec. Link: https://github.com/acpica/acpica/commit/82afd043 Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: MADT: Add RISC-V INTC interrupt controllerSunil V L
ACPICA commit bd6d1ae1e13abe78e149c8b61b4bc7bc7feab015 The ECR to add RISC-V INTC interrupt controller is approved by the UEFI forum and will be available in the next revision of the ACPI specification. Link: https://github.com/acpica/acpica/commit/bd6d1ae1 Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: Update all copyrights/signons to 2023Bob Moore
ACPICA commit 25bddd1824b1e450829468a64bbdcb38074ba3d2 Copyright updates to 2023. Link: https://github.com/acpica/acpica/commit/25bddd18 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: Add support for Arm's MPAM ACPI table version 2Hesham Almatary
ACPICA commit 005e24bcaa6e4c7db327b4f81fb63b2715aac7e6 Complies with ACPI for Memory System Resource Partitioning and Monitoring 2.0 [1]. Document number: DEN0065, as of December 2022. Support for all types of MPAM resources. No support yet for: 1) MPAM PCC Interface Type 2) The optional Resource-specific data per MSC node, introduced in v2 of the MPAM ACPI spec. [1] https://developer.arm.com/documentation/den0065/latest Link: https://github.com/acpica/acpica/commit/005e24bc Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: ACPI 6.5: MADT: add support for trace buffer extension in GICCXiongfeng Wang
ACPICA commit 1363e35dc6976143d118588b5124d72017365588 Link: https://github.com/acpica/acpica/commit/1363e35d Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-04-06ACPICA: Headers: Delete bogus node_array array of pointers from AEST tableJessica Clarke
ACPICA commit f0c4a06f1dfc4886d4e0c2aa30bc57b10c5a8c53 Like many tables, this is a header followed by multiple subtables of varying self-identifying types, and ACPICA does not normally add a field for the subtables, instead relying on pointer arithmetic past the end of the first header struct, since indexing a flexible array member is meaningless for variable-length entries. If we really wanted a field for this, we could use a u8 flexible array member, but it contradicts the current style. Using void *, however, is categorically wrong, as ACPI tables never contain native C-language pointers. Link: https://github.com/acpica/acpica/commit/f0c4a06f Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-10-28ACPICA: Finish support for the CDAT tableBob Moore
ACPICA commit 8ac4e5116f59d6f9ba2fbeb9ce22ab58237a278f Finish support for the CDAT table, in both the data table compiler and the disassembler. Link: https://github.com/acpica/acpica/commit/8ac4e511 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-10-28ACPICA: IORT: Update for revision E.eRobin Murphy
ACPICA commit 54b54732c5fc9e0384bcfd531f3c10d3a7b628b5 The latest IORT update makes one small addition to SMMUv3 nodes to describe MSI support independently of wired GSIV support. Link: https://github.com/acpica/acpica/commit/54b54732 Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-10-28ACPICA: iASL: Add CCEL table to both compiler/disassemblerKuppuswamy Sathyanarayanan
ACPICA commit 10e4763f155eac0c60295a7e364b0316fc52c4f1 Link: https://github.com/acpica/acpica/commit/10e4763f Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-10-28ACPICA: MADT: Add loong_arch-specific APICs supportHuacai Chen
ACPICA commit 1dc530059a3e6202e941e6a9478cf30f092bfb47 loong_arch-specific interrupt controllers (similar to APIC) are added in the next revision of ACPI Specification (current revision is 6.4), which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC), HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC (PCHMSI). This patch add their definition. ACPI changes of loong_arch-specific interrupt controllers have already been approved in the ECRs, and will be public in the next revision of ACPI Specification. Link: https://github.com/acpica/acpica/commit/1dc53005 Link: https://mantis.uefi.org/mantis/view.php?id=2203 Link: https://mantis.uefi.org/mantis/view.php?id=2313 Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: IORT: Updates for revision E.dShameer Kolothum
ACPICA commit 87a2e39b8abdfedfb86b0a105708e37e895becd9 IORT revision is now updated to E.d (ARM DEN 0049E.d) and contains a few additions like, -Added descriptor in the root complex node for specifying PASID width supported by the root complex. -Updated RMR node Flags field. -Introduced memory access attributes in the RMR node. Please note that IORT Rev E.c is deprecated and not supported. Link: https://github.com/acpica/acpica/commit/87a2e39b Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: iASL/MADT: Add OEM-defined subtableBob Moore
ACPICA commit 4450b89b596a2b54b0cdfe2357b49a63445c2e03 Adds support for the "reserved for OEM use" subtable (types 0x80 to 0xFF). Link: https://github.com/acpica/acpica/commit/4450b89b Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: Add support for ARM Performance Monitoring Unit Table.Besar Wicaksono
ACPICA commit 002165ecc0a3dc703bb24c789aaa02fdada01675 The specification of this table is described in "ARM Performance Monitoring Unit Architecture 1.0 Platform Design Document" ARM DEN0117. This patch adds the necessary types and support for compiling/disassembling APMT. Link: https://github.com/acpica/acpica/commit/002165ec Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: Headers: Replace zero-length array with flexible-array memberGustavo A. R. Silva
ACPICA commit 98835f452c698b015d4da999944405ecb90da670 There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use “flexible array members”[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2]. [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://www.kernel.org/doc/html/v5.16/process/deprecated.html#zero-length-and-one-element-arrays Link: https://github.com/acpica/acpica/commit/98835f45 Link: https://github.com/KSPP/linux/issues/78 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: Removed some tabs and // commentsBob Moore
ACPICA commit 0914618b553d6f3366e568409cebf2656891ca69 Automated cleanup; No functional changes. Link: https://github.com/acpica/acpica/commit/0914618b Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: Update copyright notices to the year 2022Bob Moore
ACPICA commit 738d7b0726e6c0458ef93c0a01c0377490888d1e Affects all source modules and utility signons. Link: https://github.com/acpica/acpica/commit/738d7b07 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: iASL: NHLT: Rename linux specific strucures to device_infoPiotr Maziarz
ACPICA commit 68c7e542075319d57129467872fcbe98906f2b2c Those structures aren't used by Linux drivers, and in other NHLT related tools they are called device_info. Link: https://github.com/acpica/acpica/commit/68c7e542 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: iASL: NHLT: Fix parsing undocumented bytes at the end of Endpoint ↵Piotr Maziarz
Descriptor ACPICA commit 961221a76814ffa0ecc92219ddf857579b0f7d54 Undocumented bytes at the end of Endpoint Descriptor can be present independently of Linux-specific structures. Their size can also vary. Link: https://github.com/acpica/acpica/commit/961221a7 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-04-13ACPICA: iASL: NHLT: Treat Terminator as specific_configPiotr Maziarz
ACPICA commit 23a659e190cf3ed0edd46cddf12bbbcfeaa09396 specific_config has 4 bytes of size and then an amount of bytes specified by size. All of the terminators that I've seen had a size equal to 4, but theoretically it can vary. Link: https://github.com/acpica/acpica/commit/23a659e1 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-12-27ACPICA: iASL/NHLT table: "Specific Data" field supportBob Moore
ACPICA commit 26f8c721fb01e4a26eec8c85dffcbe950d5e61a9 Add support for optional "Specific Data" field for the optional Linux-specific structure that appears at the end of an Endpoint Descriptor. Link: https://github.com/acpica/acpica/commit/26f8c721 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-12-27ACPICA: iASL: Add suppport for AGDI tableIlkka Koskinen
ACPICA commit cf36a6d658ca5aa8c329c2edfc3322c095ffd844 Add support for Arm Generic Diagnostic Dump and Reset Interface, which is described by "ACPI for Arm Components 1.1 Platform Design Document" ARM DEN0093. Add the necessary types in the ACPICA header files and support for compiling and decompiling the table. Link: https://github.com/acpica/acpica/commit/cf36a6d6 Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-12-27ACPICA: iASL: Add TDEL table to both compiler/disassemblerBob Moore
ACPICA commit 403f9965aba7ff9d2ed5b41bbffdd2a1ed0f596f Added struct acpi_pcc_info to acpi_src. Link: https://github.com/acpica/acpica/commit/403f9965 Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-12-27ACPICA: Fix AEST Processor generic resource substructure data field byte lengthShuuichirou Ishii
ACPICA commit 13b9327761955f6e1e5dbf748b3112940c0dc539 The byte length of the Data field in the AEST Processor generic resource substructure defined in ACPI for the Armv8 RAS Extensions 1.1 is 4Byte. However, it is defined as a pointer type, and on a 64-bit machine, it is interpreted as 8 bytes. Therefore, it is changed from a pointer type unsigned integer 1 byte to an unsigned integer 4 bytes. Link: https://github.com/acpica/acpica/commit/13b93277 Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-12-27ACPICA: iASL/Disassembler: Additional support for NHLT tableBob Moore
ACPICA commit 0420852ffc520b81960e877852703b739c16025c Added support for Vendor-defined microphone arrays and SNR (signal-to-noise) extension. Link: https://github.com/acpica/acpica/commit/0420852f Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-11-02Merge branches 'acpi-x86', 'acpi-resources', 'acpi-scan' and 'acpi-misc'Rafael J. Wysocki
Merge x86-specific ACPI updates, ACPI resources management updates, one ACPI device enumeration update and miscellaneous ACPI updates for 5.16-rc1: - Avoid flushing caches before entering C3 type of idle states on AMD processors (Deepak Sharma). - Avoid enumerating CPUs that are not present and not online-capable according to the platform firmware (Mario Limonciello). - Add DMI-based mechanism to quirk IRQ overrides and use it for two platforms (Hui Wang). - Change the configuration of unused ACPI device objects to reflect the D3cold power state after enumerating devices (Rafael Wysocki). - Update MAINTAINERS information regarding ACPI (Rafael Wysocki). - Fix typo in ACPI Kconfig (Masanari Iid). - Use sysfs_emit() instead of snprintf() in some places (Qing Wang). * acpi-x86: x86: ACPI: cstate: Optimize C3 entry on AMD CPUs x86/ACPI: Don't add CPUs that are not online capable ACPICA: Add support for MADT online enabled bit * acpi-resources: ACPI: resources: Add one more Medion model in IRQ override quirk ACPI: resources: Add DMI-based legacy IRQ override quirk * acpi-scan: ACPI: scan: Release PM resources blocked by unused objects * acpi-misc: ACPI: replace snprintf() in "show" functions with sysfs_emit() ACPI: Update information in MAINTAINERS ACPI: Kconfig: Fix a typo in Kconfig
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